drivers/usb/host/xhci-mem.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/usb.h>
  24 #include <linux/pci.h>
  25 #include <linux/slab.h>
  26 #include <linux/dmapool.h>
  27
  28 #include "xhci.h"
  29
  30 /*
  31  * Allocates a generic ring segment from the ring pool, sets the dma address,
  32  * initializes the segment to zero, and sets the private next pointer to NULL.
  33  *
  34  * Section 4.11.1.1:
  35  * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  36  */
  37 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
  38 {
  39         struct xhci_segment *seg;
  40         dma_addr_t      dma;
  41
  42         seg = kzalloc(sizeof *seg, flags);
  43         if (!seg)
  44                 return NULL;
  45         xhci_dbg(xhci, "Allocating priv segment structure at %p\n", seg);
  46
  47         seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
  48         if (!seg->trbs) {
  49                 kfree(seg);
  50                 return NULL;
  51         }
  52         xhci_dbg(xhci, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n",
  53                         seg->trbs, (unsigned long long)dma);
  54
  55         memset(seg->trbs, 0, SEGMENT_SIZE);
  56         seg->dma = dma;
  57         seg->next = NULL;
  58
  59         return seg;
  60 }
  61
  62 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
  63 {
  64         if (!seg)
  65                 return;
  66         if (seg->trbs) {
  67                 xhci_dbg(xhci, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n",
  68                                 seg->trbs, (unsigned long long)seg->dma);
  69                 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
  70                 seg->trbs = NULL;
  71         }
  72         xhci_dbg(xhci, "Freeing priv segment structure at %p\n", seg);
  73         kfree(seg);
  74 }
  75
  76 /*
  77  * Make the prev segment point to the next segment.
  78  *
  79  * Change the last TRB in the prev segment to be a Link TRB which points to the
  80  * DMA address of the next segment.  The caller needs to set any Link TRB
  81  * related flags, such as End TRB, Toggle Cycle, and no snoop.
  82  */
  83 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
  84                 struct xhci_segment *next, bool link_trbs)
  85 {
  86         u32 val;
  87
  88         if (!prev || !next)
  89                 return;
  90         prev->next = next;
  91         if (link_trbs) {
  92                 prev->trbs[TRBS_PER_SEGMENT-1].link.
  93                         segment_ptr = cpu_to_le64(next->dma);
  94
  95                 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
  96                 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
  97                 val &= ~TRB_TYPE_BITMASK;
  98                 val |= TRB_TYPE(TRB_LINK);
  99                 /* Always set the chain bit with 0.95 hardware */
 100                 if (xhci_link_trb_quirk(xhci))
 101                         val |= TRB_CHAIN;
 102                 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
 103         }
 104         xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
 105                         (unsigned long long)prev->dma,
 106                         (unsigned long long)next->dma);
 107 }
 108
 109 /* XXX: Do we need the hcd structure in all these functions? */
 110 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
 111 {
 112         struct xhci_segment *seg;
 113         struct xhci_segment *first_seg;
 114
 115         if (!ring || !ring->first_seg)
 116                 return;
 117         first_seg = ring->first_seg;
 118         seg = first_seg->next;
 119         xhci_dbg(xhci, "Freeing ring at %p\n", ring);
 120         while (seg != first_seg) {
 121                 struct xhci_segment *next = seg->next;
 122                 xhci_segment_free(xhci, seg);
 123                 seg = next;
 124         }
 125         xhci_segment_free(xhci, first_seg);
 126         ring->first_seg = NULL;
 127         kfree(ring);
 128 }
 129
 130 static void xhci_initialize_ring_info(struct xhci_ring *ring)
 131 {
 132         /* The ring is empty, so the enqueue pointer == dequeue pointer */
 133         ring->enqueue = ring->first_seg->trbs;
 134         ring->enq_seg = ring->first_seg;
 135         ring->dequeue = ring->enqueue;
 136         ring->deq_seg = ring->first_seg;
 137         /* The ring is initialized to 0. The producer must write 1 to the cycle
 138          * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
 139          * compare CCS to the cycle bit to check ownership, so CCS = 1.
 140          */
 141         ring->cycle_state = 1;
 142         /* Not necessary for new rings, but needed for re-initialized rings */
 143         ring->enq_updates = 0;
 144         ring->deq_updates = 0;
 145 }
 146
 147 /**
 148  * Create a new ring with zero or more segments.
 149  *
 150  * Link each segment together into a ring.
 151  * Set the end flag and the cycle toggle bit on the last segment.
 152  * See section 4.9.1 and figures 15 and 16.
 153  */
 154 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
 155                 unsigned int num_segs, bool link_trbs, gfp_t flags)
 156 {
 157         struct xhci_ring        *ring;
 158         struct xhci_segment     *prev;
 159
 160         ring = kzalloc(sizeof *(ring), flags);
 161         xhci_dbg(xhci, "Allocating ring at %p\n", ring);
 162         if (!ring)
 163                 return NULL;
 164
 165         INIT_LIST_HEAD(&ring->td_list);
 166         if (num_segs == 0)
 167                 return ring;
 168
 169         ring->first_seg = xhci_segment_alloc(xhci, flags);
 170         if (!ring->first_seg)
 171                 goto fail;
 172         num_segs--;
 173
 174         prev = ring->first_seg;
 175         while (num_segs > 0) {
 176                 struct xhci_segment     *next;
 177
 178                 next = xhci_segment_alloc(xhci, flags);
 179                 if (!next)
 180                         goto fail;
 181                 xhci_link_segments(xhci, prev, next, link_trbs);
 182
 183                 prev = next;
 184                 num_segs--;
 185         }
 186         xhci_link_segments(xhci, prev, ring->first_seg, link_trbs);
 187
 188         if (link_trbs) {
 189                 /* See section 4.9.2.1 and 6.4.4.1 */
 190                 prev->trbs[TRBS_PER_SEGMENT-1].link.
 191                         control |= cpu_to_le32(LINK_TOGGLE);
 192                 xhci_dbg(xhci, "Wrote link toggle flag to"
 193                                 " segment %p (virtual), 0x%llx (DMA)\n",
 194                                 prev, (unsigned long long)prev->dma);
 195         }
 196         xhci_initialize_ring_info(ring);
 197         return ring;
 198
 199 fail:
 200         xhci_ring_free(xhci, ring);
 201         return NULL;
 202 }
 203
 204 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
 205                 struct xhci_virt_device *virt_dev,
 206                 unsigned int ep_index)
 207 {
 208         int rings_cached;
 209
 210         rings_cached = virt_dev->num_rings_cached;
 211         if (rings_cached < XHCI_MAX_RINGS_CACHED) {
 212                 virt_dev->num_rings_cached++;
 213                 rings_cached = virt_dev->num_rings_cached;
 214                 virt_dev->ring_cache[rings_cached] =
 215                         virt_dev->eps[ep_index].ring;
 216                 xhci_dbg(xhci, "Cached old ring, "
 217                                 "%d ring%s cached\n",
 218                                 rings_cached,
 219                                 (rings_cached > 1) ? "s" : "");
 220         } else {
 221                 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
 222                 xhci_dbg(xhci, "Ring cache full (%d rings), "
 223                                 "freeing ring\n",
 224                                 virt_dev->num_rings_cached);
 225         }
 226         virt_dev->eps[ep_index].ring = NULL;
 227 }
 228
 229 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
 230  * pointers to the beginning of the ring.
 231  */
 232 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
 233                 struct xhci_ring *ring)
 234 {
 235         struct xhci_segment     *seg = ring->first_seg;
 236         do {
 237                 memset(seg->trbs, 0,
 238                                 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
 239                 /* All endpoint rings have link TRBs */
 240                 xhci_link_segments(xhci, seg, seg->next, 1);
 241                 seg = seg->next;
 242         } while (seg != ring->first_seg);
 243         xhci_initialize_ring_info(ring);
 244         /* td list should be empty since all URBs have been cancelled,
 245          * but just in case...
 246          */
 247         INIT_LIST_HEAD(&ring->td_list);
 248 }
 249
 250 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
 251
 252 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
 253                                                     int type, gfp_t flags)
 254 {
 255         struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
 256         if (!ctx)
 257                 return NULL;
 258
 259         BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
 260         ctx->type = type;
 261         ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
 262         if (type == XHCI_CTX_TYPE_INPUT)
 263                 ctx->size += CTX_SIZE(xhci->hcc_params);
 264
 265         ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
 266         memset(ctx->bytes, 0, ctx->size);
 267         return ctx;
 268 }
 269
 270 static void xhci_free_container_ctx(struct xhci_hcd *xhci,
 271                              struct xhci_container_ctx *ctx)
 272 {
 273         if (!ctx)
 274                 return;
 275         dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
 276         kfree(ctx);
 277 }
 278
 279 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
 280                                               struct xhci_container_ctx *ctx)
 281 {
 282         BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
 283         return (struct xhci_input_control_ctx *)ctx->bytes;
 284 }
 285
 286 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
 287                                         struct xhci_container_ctx *ctx)
 288 {
 289         if (ctx->type == XHCI_CTX_TYPE_DEVICE)
 290                 return (struct xhci_slot_ctx *)ctx->bytes;
 291
 292         return (struct xhci_slot_ctx *)
 293                 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
 294 }
 295
 296 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
 297                                     struct xhci_container_ctx *ctx,
 298                                     unsigned int ep_index)
 299 {
 300         /* increment ep index by offset of start of ep ctx array */
 301         ep_index++;
 302         if (ctx->type == XHCI_CTX_TYPE_INPUT)
 303                 ep_index++;
 304
 305         return (struct xhci_ep_ctx *)
 306                 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
 307 }
 308
 309
 310 /***************** Streams structures manipulation *************************/
 311
 312 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
 313                 unsigned int num_stream_ctxs,
 314                 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
 315 {
 316         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 317
 318         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 319                 pci_free_consistent(pdev,
 320                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 321                                 stream_ctx, dma);
 322         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 323                 return dma_pool_free(xhci->small_streams_pool,
 324                                 stream_ctx, dma);
 325         else
 326                 return dma_pool_free(xhci->medium_streams_pool,
 327                                 stream_ctx, dma);
 328 }
 329
 330 /*
 331  * The stream context array for each endpoint with bulk streams enabled can
 332  * vary in size, based on:
 333  *  - how many streams the endpoint supports,
 334  *  - the maximum primary stream array size the host controller supports,
 335  *  - and how many streams the device driver asks for.
 336  *
 337  * The stream context array must be a power of 2, and can be as small as
 338  * 64 bytes or as large as 1MB.
 339  */
 340 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
 341                 unsigned int num_stream_ctxs, dma_addr_t *dma,
 342                 gfp_t mem_flags)
 343 {
 344         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 345
 346         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 347                 return pci_alloc_consistent(pdev,
 348                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 349                                 dma);
 350         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 351                 return dma_pool_alloc(xhci->small_streams_pool,
 352                                 mem_flags, dma);
 353         else
 354                 return dma_pool_alloc(xhci->medium_streams_pool,
 355                                 mem_flags, dma);
 356 }
 357
 358 struct xhci_ring *xhci_dma_to_transfer_ring(
 359                 struct xhci_virt_ep *ep,
 360                 u64 address)
 361 {
 362         if (ep->ep_state & EP_HAS_STREAMS)
 363                 return radix_tree_lookup(&ep->stream_info->trb_address_map,
 364                                 address >> SEGMENT_SHIFT);
 365         return ep->ring;
 366 }
 367
 368 /* Only use this when you know stream_info is valid */
 369 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 370 static struct xhci_ring *dma_to_stream_ring(
 371                 struct xhci_stream_info *stream_info,
 372                 u64 address)
 373 {
 374         return radix_tree_lookup(&stream_info->trb_address_map,
 375                         address >> SEGMENT_SHIFT);
 376 }
 377 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 378
 379 struct xhci_ring *xhci_stream_id_to_ring(
 380                 struct xhci_virt_device *dev,
 381                 unsigned int ep_index,
 382                 unsigned int stream_id)
 383 {
 384         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 385
 386         if (stream_id == 0)
 387                 return ep->ring;
 388         if (!ep->stream_info)
 389                 return NULL;
 390
 391         if (stream_id > ep->stream_info->num_streams)
 392                 return NULL;
 393         return ep->stream_info->stream_rings[stream_id];
 394 }
 395
 396 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 397 static int xhci_test_radix_tree(struct xhci_hcd *xhci,
 398                 unsigned int num_streams,
 399                 struct xhci_stream_info *stream_info)
 400 {
 401         u32 cur_stream;
 402         struct xhci_ring *cur_ring;
 403         u64 addr;
 404
 405         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 406                 struct xhci_ring *mapped_ring;
 407                 int trb_size = sizeof(union xhci_trb);
 408
 409                 cur_ring = stream_info->stream_rings[cur_stream];
 410                 for (addr = cur_ring->first_seg->dma;
 411                                 addr < cur_ring->first_seg->dma + SEGMENT_SIZE;
 412                                 addr += trb_size) {
 413                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 414                         if (cur_ring != mapped_ring) {
 415                                 xhci_warn(xhci, "WARN: DMA address 0x%08llx "
 416                                                 "didn't map to stream ID %u; "
 417                                                 "mapped to ring %p\n",
 418                                                 (unsigned long long) addr,
 419                                                 cur_stream,
 420                                                 mapped_ring);
 421                                 return -EINVAL;
 422                         }
 423                 }
 424                 /* One TRB after the end of the ring segment shouldn't return a
 425                  * pointer to the current ring (although it may be a part of a
 426                  * different ring).
 427                  */
 428                 mapped_ring = dma_to_stream_ring(stream_info, addr);
 429                 if (mapped_ring != cur_ring) {
 430                         /* One TRB before should also fail */
 431                         addr = cur_ring->first_seg->dma - trb_size;
 432                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 433                 }
 434                 if (mapped_ring == cur_ring) {
 435                         xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
 436                                         "mapped to valid stream ID %u; "
 437                                         "mapped ring = %p\n",
 438                                         (unsigned long long) addr,
 439                                         cur_stream,
 440                                         mapped_ring);
 441                         return -EINVAL;
 442                 }
 443         }
 444         return 0;
 445 }
 446 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 447
 448 /*
 449  * Change an endpoint's internal structure so it supports stream IDs.  The
 450  * number of requested streams includes stream 0, which cannot be used by device
 451  * drivers.
 452  *
 453  * The number of stream contexts in the stream context array may be bigger than
 454  * the number of streams the driver wants to use.  This is because the number of
 455  * stream context array entries must be a power of two.
 456  *
 457  * We need a radix tree for mapping physical addresses of TRBs to which stream
 458  * ID they belong to.  We need to do this because the host controller won't tell
 459  * us which stream ring the TRB came from.  We could store the stream ID in an
 460  * event data TRB, but that doesn't help us for the cancellation case, since the
 461  * endpoint may stop before it reaches that event data TRB.
 462  *
 463  * The radix tree maps the upper portion of the TRB DMA address to a ring
 464  * segment that has the same upper portion of DMA addresses.  For example, say I
 465  * have segments of size 1KB, that are always 64-byte aligned.  A segment may
 466  * start at 0x10c91000 and end at 0x10c913f0.  If I use the upper 10 bits, the
 467  * key to the stream ID is 0x43244.  I can use the DMA address of the TRB to
 468  * pass the radix tree a key to get the right stream ID:
 469  *
 470  *      0x10c90fff >> 10 = 0x43243
 471  *      0x10c912c0 >> 10 = 0x43244
 472  *      0x10c91400 >> 10 = 0x43245
 473  *
 474  * Obviously, only those TRBs with DMA addresses that are within the segment
 475  * will make the radix tree return the stream ID for that ring.
 476  *
 477  * Caveats for the radix tree:
 478  *
 479  * The radix tree uses an unsigned long as a key pair.  On 32-bit systems, an
 480  * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
 481  * 64-bits.  Since we only request 32-bit DMA addresses, we can use that as the
 482  * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
 483  * PCI DMA addresses on a 64-bit system).  There might be a problem on 32-bit
 484  * extended systems (where the DMA address can be bigger than 32-bits),
 485  * if we allow the PCI dma mask to be bigger than 32-bits.  So don't do that.
 486  */
 487 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
 488                 unsigned int num_stream_ctxs,
 489                 unsigned int num_streams, gfp_t mem_flags)
 490 {
 491         struct xhci_stream_info *stream_info;
 492         u32 cur_stream;
 493         struct xhci_ring *cur_ring;
 494         unsigned long key;
 495         u64 addr;
 496         int ret;
 497
 498         xhci_dbg(xhci, "Allocating %u streams and %u "
 499                         "stream context array entries.\n",
 500                         num_streams, num_stream_ctxs);
 501         if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
 502                 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
 503                 return NULL;
 504         }
 505         xhci->cmd_ring_reserved_trbs++;
 506
 507         stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
 508         if (!stream_info)
 509                 goto cleanup_trbs;
 510
 511         stream_info->num_streams = num_streams;
 512         stream_info->num_stream_ctxs = num_stream_ctxs;
 513
 514         /* Initialize the array of virtual pointers to stream rings. */
 515         stream_info->stream_rings = kzalloc(
 516                         sizeof(struct xhci_ring *)*num_streams,
 517                         mem_flags);
 518         if (!stream_info->stream_rings)
 519                 goto cleanup_info;
 520
 521         /* Initialize the array of DMA addresses for stream rings for the HW. */
 522         stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
 523                         num_stream_ctxs, &stream_info->ctx_array_dma,
 524                         mem_flags);
 525         if (!stream_info->stream_ctx_array)
 526                 goto cleanup_ctx;
 527         memset(stream_info->stream_ctx_array, 0,
 528                         sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
 529
 530         /* Allocate everything needed to free the stream rings later */
 531         stream_info->free_streams_command =
 532                 xhci_alloc_command(xhci, true, true, mem_flags);
 533         if (!stream_info->free_streams_command)
 534                 goto cleanup_ctx;
 535
 536         INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
 537
 538         /* Allocate rings for all the streams that the driver will use,
 539          * and add their segment DMA addresses to the radix tree.
 540          * Stream 0 is reserved.
 541          */
 542         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 543                 stream_info->stream_rings[cur_stream] =
 544                         xhci_ring_alloc(xhci, 1, true, mem_flags);
 545                 cur_ring = stream_info->stream_rings[cur_stream];
 546                 if (!cur_ring)
 547                         goto cleanup_rings;
 548                 cur_ring->stream_id = cur_stream;
 549                 /* Set deq ptr, cycle bit, and stream context type */
 550                 addr = cur_ring->first_seg->dma |
 551                         SCT_FOR_CTX(SCT_PRI_TR) |
 552                         cur_ring->cycle_state;
 553                 stream_info->stream_ctx_array[cur_stream].
 554                         stream_ring = cpu_to_le64(addr);
 555                 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
 556                                 cur_stream, (unsigned long long) addr);
 557
 558                 key = (unsigned long)
 559                         (cur_ring->first_seg->dma >> SEGMENT_SHIFT);
 560                 ret = radix_tree_insert(&stream_info->trb_address_map,
 561                                 key, cur_ring);
 562                 if (ret) {
 563                         xhci_ring_free(xhci, cur_ring);
 564                         stream_info->stream_rings[cur_stream] = NULL;
 565                         goto cleanup_rings;
 566                 }
 567         }
 568         /* Leave the other unused stream ring pointers in the stream context
 569          * array initialized to zero.  This will cause the xHC to give us an
 570          * error if the device asks for a stream ID we don't have setup (if it
 571          * was any other way, the host controller would assume the ring is
 572          * "empty" and wait forever for data to be queued to that stream ID).
 573          */
 574 #if XHCI_DEBUG
 575         /* Do a little test on the radix tree to make sure it returns the
 576          * correct values.
 577          */
 578         if (xhci_test_radix_tree(xhci, num_streams, stream_info))
 579                 goto cleanup_rings;
 580 #endif
 581
 582         return stream_info;
 583
 584 cleanup_rings:
 585         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 586                 cur_ring = stream_info->stream_rings[cur_stream];
 587                 if (cur_ring) {
 588                         addr = cur_ring->first_seg->dma;
 589                         radix_tree_delete(&stream_info->trb_address_map,
 590                                         addr >> SEGMENT_SHIFT);
 591                         xhci_ring_free(xhci, cur_ring);
 592                         stream_info->stream_rings[cur_stream] = NULL;
 593                 }
 594         }
 595         xhci_free_command(xhci, stream_info->free_streams_command);
 596 cleanup_ctx:
 597         kfree(stream_info->stream_rings);
 598 cleanup_info:
 599         kfree(stream_info);
 600 cleanup_trbs:
 601         xhci->cmd_ring_reserved_trbs--;
 602         return NULL;
 603 }
 604 /*
 605  * Sets the MaxPStreams field and the Linear Stream Array field.
 606  * Sets the dequeue pointer to the stream context array.
 607  */
 608 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
 609                 struct xhci_ep_ctx *ep_ctx,
 610                 struct xhci_stream_info *stream_info)
 611 {
 612         u32 max_primary_streams;
 613         /* MaxPStreams is the number of stream context array entries, not the
 614          * number we're actually using.  Must be in 2^(MaxPstreams + 1) format.
 615          * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
 616          */
 617         max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
 618         xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
 619                         1 << (max_primary_streams + 1));
 620         ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
 621         ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
 622                                        | EP_HAS_LSA);
 623         ep_ctx->deq  = cpu_to_le64(stream_info->ctx_array_dma);
 624 }
 625
 626 /*
 627  * Sets the MaxPStreams field and the Linear Stream Array field to 0.
 628  * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
 629  * not at the beginning of the ring).
 630  */
 631 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
 632                 struct xhci_ep_ctx *ep_ctx,
 633                 struct xhci_virt_ep *ep)
 634 {
 635         dma_addr_t addr;
 636         ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
 637         addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
 638         ep_ctx->deq  = cpu_to_le64(addr | ep->ring->cycle_state);
 639 }
 640
 641 /* Frees all stream contexts associated with the endpoint,
 642  *
 643  * Caller should fix the endpoint context streams fields.
 644  */
 645 void xhci_free_stream_info(struct xhci_hcd *xhci,
 646                 struct xhci_stream_info *stream_info)
 647 {
 648         int cur_stream;
 649         struct xhci_ring *cur_ring;
 650         dma_addr_t addr;
 651
 652         if (!stream_info)
 653                 return;
 654
 655         for (cur_stream = 1; cur_stream < stream_info->num_streams;
 656                         cur_stream++) {
 657                 cur_ring = stream_info->stream_rings[cur_stream];
 658                 if (cur_ring) {
 659                         addr = cur_ring->first_seg->dma;
 660                         radix_tree_delete(&stream_info->trb_address_map,
 661                                         addr >> SEGMENT_SHIFT);
 662                         xhci_ring_free(xhci, cur_ring);
 663                         stream_info->stream_rings[cur_stream] = NULL;
 664                 }
 665         }
 666         xhci_free_command(xhci, stream_info->free_streams_command);
 667         xhci->cmd_ring_reserved_trbs--;
 668         if (stream_info->stream_ctx_array)
 669                 xhci_free_stream_ctx(xhci,
 670                                 stream_info->num_stream_ctxs,
 671                                 stream_info->stream_ctx_array,
 672                                 stream_info->ctx_array_dma);
 673
 674         if (stream_info)
 675                 kfree(stream_info->stream_rings);
 676         kfree(stream_info);
 677 }
 678
 679
 680 /***************** Device context manipulation *************************/
 681
 682 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
 683                 struct xhci_virt_ep *ep)
 684 {
 685         init_timer(&ep->stop_cmd_timer);
 686         ep->stop_cmd_timer.data = (unsigned long) ep;
 687         ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
 688         ep->xhci = xhci;
 689 }
 690
 691 /* All the xhci_tds in the ring's TD list should be freed at this point */
 692 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
 693 {
 694         struct xhci_virt_device *dev;
 695         int i;
 696
 697         /* Slot ID 0 is reserved */
 698         if (slot_id == 0 || !xhci->devs[slot_id])
 699                 return;
 700
 701         dev = xhci->devs[slot_id];
 702         xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
 703         if (!dev)
 704                 return;
 705
 706         for (i = 0; i < 31; ++i) {
 707                 if (dev->eps[i].ring)
 708                         xhci_ring_free(xhci, dev->eps[i].ring);
 709                 if (dev->eps[i].stream_info)
 710                         xhci_free_stream_info(xhci,
 711                                         dev->eps[i].stream_info);
 712         }
 713
 714         if (dev->ring_cache) {
 715                 for (i = 0; i < dev->num_rings_cached; i++)
 716                         xhci_ring_free(xhci, dev->ring_cache[i]);
 717                 kfree(dev->ring_cache);
 718         }
 719
 720         if (dev->in_ctx)
 721                 xhci_free_container_ctx(xhci, dev->in_ctx);
 722         if (dev->out_ctx)
 723                 xhci_free_container_ctx(xhci, dev->out_ctx);
 724
 725         kfree(xhci->devs[slot_id]);
 726         xhci->devs[slot_id] = NULL;
 727 }
 728
 729 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
 730                 struct usb_device *udev, gfp_t flags)
 731 {
 732         struct xhci_virt_device *dev;
 733         int i;
 734
 735         /* Slot ID 0 is reserved */
 736         if (slot_id == 0 || xhci->devs[slot_id]) {
 737                 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
 738                 return 0;
 739         }
 740
 741         xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
 742         if (!xhci->devs[slot_id])
 743                 return 0;
 744         dev = xhci->devs[slot_id];
 745
 746         /* Allocate the (output) device context that will be used in the HC. */
 747         dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
 748         if (!dev->out_ctx)
 749                 goto fail;
 750
 751         xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
 752                         (unsigned long long)dev->out_ctx->dma);
 753
 754         /* Allocate the (input) device context for address device command */
 755         dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
 756         if (!dev->in_ctx)
 757                 goto fail;
 758
 759         xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
 760                         (unsigned long long)dev->in_ctx->dma);
 761
 762         /* Initialize the cancellation list and watchdog timers for each ep */
 763         for (i = 0; i < 31; i++) {
 764                 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
 765                 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
 766         }
 767
 768         /* Allocate endpoint 0 ring */
 769         dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, flags);
 770         if (!dev->eps[0].ring)
 771                 goto fail;
 772
 773         /* Allocate pointers to the ring cache */
 774         dev->ring_cache = kzalloc(
 775                         sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
 776                         flags);
 777         if (!dev->ring_cache)
 778                 goto fail;
 779         dev->num_rings_cached = 0;
 780
 781         init_completion(&dev->cmd_completion);
 782         INIT_LIST_HEAD(&dev->cmd_list);
 783         dev->udev = udev;
 784
 785         /* Point to output device context in dcbaa. */
 786         xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
 787         xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
 788                  slot_id,
 789                  &xhci->dcbaa->dev_context_ptrs[slot_id],
 790                  (unsigned long long) le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
 791
 792         return 1;
 793 fail:
 794         xhci_free_virt_device(xhci, slot_id);
 795         return 0;
 796 }
 797
 798 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
 799                 struct usb_device *udev)
 800 {
 801         struct xhci_virt_device *virt_dev;
 802         struct xhci_ep_ctx      *ep0_ctx;
 803         struct xhci_ring        *ep_ring;
 804
 805         virt_dev = xhci->devs[udev->slot_id];
 806         ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
 807         ep_ring = virt_dev->eps[0].ring;
 808         /*
 809          * FIXME we don't keep track of the dequeue pointer very well after a
 810          * Set TR dequeue pointer, so we're setting the dequeue pointer of the
 811          * host to our enqueue pointer.  This should only be called after a
 812          * configured device has reset, so all control transfers should have
 813          * been completed or cancelled before the reset.
 814          */
 815         ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
 816                                                         ep_ring->enqueue)
 817                                    | ep_ring->cycle_state);
 818 }
 819
 820 /*
 821  * The xHCI roothub may have ports of differing speeds in any order in the port
 822  * status registers.  xhci->port_array provides an array of the port speed for
 823  * each offset into the port status registers.
 824  *
 825  * The xHCI hardware wants to know the roothub port number that the USB device
 826  * is attached to (or the roothub port its ancestor hub is attached to).  All we
 827  * know is the index of that port under either the USB 2.0 or the USB 3.0
 828  * roothub, but that doesn't give us the real index into the HW port status
 829  * registers.  Scan through the xHCI roothub port array, looking for the Nth
 830  * entry of the correct port speed.  Return the port number of that entry.
 831  */
 832 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
 833                 struct usb_device *udev)
 834 {
 835         struct usb_device *top_dev;
 836         unsigned int num_similar_speed_ports;
 837         unsigned int faked_port_num;
 838         int i;
 839
 840         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
 841                         top_dev = top_dev->parent)
 842                 /* Found device below root hub */;
 843         faked_port_num = top_dev->portnum;
 844         for (i = 0, num_similar_speed_ports = 0;
 845                         i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
 846                 u8 port_speed = xhci->port_array[i];
 847
 848                 /*
 849                  * Skip ports that don't have known speeds, or have duplicate
 850                  * Extended Capabilities port speed entries.
 851                  */
 852                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
 853                         continue;
 854
 855                 /*
 856                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
 857                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
 858                  * matches the device speed, it's a similar speed port.
 859                  */
 860                 if ((port_speed == 0x03) == (udev->speed == USB_SPEED_SUPER))
 861                         num_similar_speed_ports++;
 862                 if (num_similar_speed_ports == faked_port_num)
 863                         /* Roothub ports are numbered from 1 to N */
 864                         return i+1;
 865         }
 866         return 0;
 867 }
 868
 869 /* Setup an xHCI virtual device for a Set Address command */
 870 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
 871 {
 872         struct xhci_virt_device *dev;
 873         struct xhci_ep_ctx      *ep0_ctx;
 874         struct xhci_slot_ctx    *slot_ctx;
 875         struct xhci_input_control_ctx *ctrl_ctx;
 876         u32                     port_num;
 877         struct usb_device *top_dev;
 878
 879         dev = xhci->devs[udev->slot_id];
 880         /* Slot ID 0 is reserved */
 881         if (udev->slot_id == 0 || !dev) {
 882                 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
 883                                 udev->slot_id);
 884                 return -EINVAL;
 885         }
 886         ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
 887         ctrl_ctx = xhci_get_input_control_ctx(xhci, dev->in_ctx);
 888         slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
 889
 890         /* 2) New slot context and endpoint 0 context are valid*/
 891         ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
 892
 893         /* 3) Only the control endpoint is valid - one endpoint context */
 894         slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | (u32) udev->route);
 895         switch (udev->speed) {
 896         case USB_SPEED_SUPER:
 897                 slot_ctx->dev_info |= cpu_to_le32((u32) SLOT_SPEED_SS);
 898                 break;
 899         case USB_SPEED_HIGH:
 900                 slot_ctx->dev_info |= cpu_to_le32((u32) SLOT_SPEED_HS);
 901                 break;
 902         case USB_SPEED_FULL:
 903                 slot_ctx->dev_info |= cpu_to_le32((u32) SLOT_SPEED_FS);
 904                 break;
 905         case USB_SPEED_LOW:
 906                 slot_ctx->dev_info |= cpu_to_le32((u32) SLOT_SPEED_LS);
 907                 break;
 908         case USB_SPEED_WIRELESS:
 909                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
 910                 return -EINVAL;
 911                 break;
 912         default:
 913                 /* Speed was set earlier, this shouldn't happen. */
 914                 BUG();
 915         }
 916         /* Find the root hub port this device is under */
 917         port_num = xhci_find_real_port_number(xhci, udev);
 918         if (!port_num)
 919                 return -EINVAL;
 920         slot_ctx->dev_info2 |= cpu_to_le32((u32) ROOT_HUB_PORT(port_num));
 921         /* Set the port number in the virtual_device to the faked port number */
 922         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
 923                         top_dev = top_dev->parent)
 924                 /* Found device below root hub */;
 925         dev->port = top_dev->portnum;
 926         xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
 927         xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->port);
 928
 929         /* Is this a LS/FS device under an external HS hub? */
 930         if (udev->tt && udev->tt->hub->parent) {
 931                 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
 932                                                 (udev->ttport << 8));
 933                 if (udev->tt->multi)
 934                         slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
 935         }
 936         xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
 937         xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
 938
 939         /* Step 4 - ring already allocated */
 940         /* Step 5 */
 941         ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
 942         /*
 943          * XXX: Not sure about wireless USB devices.
 944          */
 945         switch (udev->speed) {
 946         case USB_SPEED_SUPER:
 947                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
 948                 break;
 949         case USB_SPEED_HIGH:
 950         /* USB core guesses at a 64-byte max packet first for FS devices */
 951         case USB_SPEED_FULL:
 952                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
 953                 break;
 954         case USB_SPEED_LOW:
 955                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
 956                 break;
 957         case USB_SPEED_WIRELESS:
 958                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
 959                 return -EINVAL;
 960                 break;
 961         default:
 962                 /* New speed? */
 963                 BUG();
 964         }
 965         /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
 966         ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
 967
 968         ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
 969                                    dev->eps[0].ring->cycle_state);
 970
 971         /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
 972
 973         return 0;
 974 }
 975
 976 /*
 977  * Convert interval expressed as 2^(bInterval - 1) == interval into
 978  * straight exponent value 2^n == interval.
 979  *
 980  */
 981 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
 982                 struct usb_host_endpoint *ep)
 983 {
 984         unsigned int interval;
 985
 986         interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
 987         if (interval != ep->desc.bInterval - 1)
 988                 dev_warn(&udev->dev,
 989                          "ep %#x - rounding interval to %d microframes\n",
 990                          ep->desc.bEndpointAddress,
 991                          1 << interval);
 992
 993         return interval;
 994 }
 995
 996 /*
 997  * Convert bInterval expressed in frames (in 1-255 range) to exponent of
 998  * microframes, rounded down to nearest power of 2.
 999  */
1000 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1001                 struct usb_host_endpoint *ep)
1002 {
1003         unsigned int interval;
1004
1005         interval = fls(8 * ep->desc.bInterval) - 1;
1006         interval = clamp_val(interval, 3, 10);
1007         if ((1 << interval) != 8 * ep->desc.bInterval)
1008                 dev_warn(&udev->dev,
1009                          "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1010                          ep->desc.bEndpointAddress,
1011                          1 << interval,
1012                          8 * ep->desc.bInterval);
1013
1014         return interval;
1015 }
1016
1017 /* Return the polling or NAK interval.
1018  *
1019  * The polling interval is expressed in "microframes".  If xHCI's Interval field
1020  * is set to N, it will service the endpoint every 2^(Interval)*125us.
1021  *
1022  * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1023  * is set to 0.
1024  */
1025 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1026                 struct usb_host_endpoint *ep)
1027 {
1028         unsigned int interval = 0;
1029
1030         switch (udev->speed) {
1031         case USB_SPEED_HIGH:
1032                 /* Max NAK rate */
1033                 if (usb_endpoint_xfer_control(&ep->desc) ||
1034                     usb_endpoint_xfer_bulk(&ep->desc)) {
1035                         interval = ep->desc.bInterval;
1036                         break;
1037                 }
1038                 /* Fall through - SS and HS isoc/int have same decoding */
1039
1040         case USB_SPEED_SUPER:
1041                 if (usb_endpoint_xfer_int(&ep->desc) ||
1042                     usb_endpoint_xfer_isoc(&ep->desc)) {
1043                         interval = xhci_parse_exponent_interval(udev, ep);
1044                 }
1045                 break;
1046
1047         case USB_SPEED_FULL:
1048                 if (usb_endpoint_xfer_int(&ep->desc)) {
1049                         interval = xhci_parse_exponent_interval(udev, ep);
1050                         break;
1051                 }
1052                 /*
1053                  * Fall through for isochronous endpoint interval decoding
1054                  * since it uses the same rules as low speed interrupt
1055                  * endpoints.
1056                  */
1057
1058         case USB_SPEED_LOW:
1059                 if (usb_endpoint_xfer_int(&ep->desc) ||
1060                     usb_endpoint_xfer_isoc(&ep->desc)) {
1061
1062                         interval = xhci_parse_frame_interval(udev, ep);
1063                 }
1064                 break;
1065
1066         default:
1067                 BUG();
1068         }
1069         return EP_INTERVAL(interval);
1070 }
1071
1072 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1073  * High speed endpoint descriptors can define "the number of additional
1074  * transaction opportunities per microframe", but that goes in the Max Burst
1075  * endpoint context field.
1076  */
1077 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1078                 struct usb_host_endpoint *ep)
1079 {
1080         if (udev->speed != USB_SPEED_SUPER ||
1081                         !usb_endpoint_xfer_isoc(&ep->desc))
1082                 return 0;
1083         return ep->ss_ep_comp.bmAttributes;
1084 }
1085
1086 static u32 xhci_get_endpoint_type(struct usb_device *udev,
1087                 struct usb_host_endpoint *ep)
1088 {
1089         int in;
1090         u32 type;
1091
1092         in = usb_endpoint_dir_in(&ep->desc);
1093         if (usb_endpoint_xfer_control(&ep->desc)) {
1094                 type = EP_TYPE(CTRL_EP);
1095         } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
1096                 if (in)
1097                         type = EP_TYPE(BULK_IN_EP);
1098                 else
1099                         type = EP_TYPE(BULK_OUT_EP);
1100         } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
1101                 if (in)
1102                         type = EP_TYPE(ISOC_IN_EP);
1103                 else
1104                         type = EP_TYPE(ISOC_OUT_EP);
1105         } else if (usb_endpoint_xfer_int(&ep->desc)) {
1106                 if (in)
1107                         type = EP_TYPE(INT_IN_EP);
1108                 else
1109                         type = EP_TYPE(INT_OUT_EP);
1110         } else {
1111                 BUG();
1112         }
1113         return type;
1114 }
1115
1116 /* Return the maximum endpoint service interval time (ESIT) payload.
1117  * Basically, this is the maxpacket size, multiplied by the burst size
1118  * and mult size.
1119  */
1120 static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1121                 struct usb_device *udev,
1122                 struct usb_host_endpoint *ep)
1123 {
1124         int max_burst;
1125         int max_packet;
1126
1127         /* Only applies for interrupt or isochronous endpoints */
1128         if (usb_endpoint_xfer_control(&ep->desc) ||
1129                         usb_endpoint_xfer_bulk(&ep->desc))
1130                 return 0;
1131
1132         if (udev->speed == USB_SPEED_SUPER)
1133                 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1134
1135         max_packet = GET_MAX_PACKET(le16_to_cpu(ep->desc.wMaxPacketSize));
1136         max_burst = (le16_to_cpu(ep->desc.wMaxPacketSize) & 0x1800) >> 11;
1137         /* A 0 in max burst means 1 transfer per ESIT */
1138         return max_packet * (max_burst + 1);
1139 }
1140
1141 /* Set up an endpoint with one ring segment.  Do not allocate stream rings.
1142  * Drivers will have to call usb_alloc_streams() to do that.
1143  */
1144 int xhci_endpoint_init(struct xhci_hcd *xhci,
1145                 struct xhci_virt_device *virt_dev,
1146                 struct usb_device *udev,
1147                 struct usb_host_endpoint *ep,
1148                 gfp_t mem_flags)
1149 {
1150         unsigned int ep_index;
1151         struct xhci_ep_ctx *ep_ctx;
1152         struct xhci_ring *ep_ring;
1153         unsigned int max_packet;
1154         unsigned int max_burst;
1155         u32 max_esit_payload;
1156
1157         ep_index = xhci_get_endpoint_index(&ep->desc);
1158         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1159
1160         /* Set up the endpoint ring */
1161         /*
1162          * Isochronous endpoint ring needs bigger size because one isoc URB
1163          * carries multiple packets and it will insert multiple tds to the
1164          * ring.
1165          * This should be replaced with dynamic ring resizing in the future.
1166          */
1167         if (usb_endpoint_xfer_isoc(&ep->desc))
1168                 virt_dev->eps[ep_index].new_ring =
1169                         xhci_ring_alloc(xhci, 8, true, mem_flags);
1170         else
1171                 virt_dev->eps[ep_index].new_ring =
1172                         xhci_ring_alloc(xhci, 1, true, mem_flags);
1173         if (!virt_dev->eps[ep_index].new_ring) {
1174                 /* Attempt to use the ring cache */
1175                 if (virt_dev->num_rings_cached == 0)
1176                         return -ENOMEM;
1177                 virt_dev->eps[ep_index].new_ring =
1178                         virt_dev->ring_cache[virt_dev->num_rings_cached];
1179                 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1180                 virt_dev->num_rings_cached--;
1181                 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring);
1182         }
1183         virt_dev->eps[ep_index].skip = false;
1184         ep_ring = virt_dev->eps[ep_index].new_ring;
1185         ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
1186
1187         ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
1188                                       | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
1189
1190         /* FIXME dig Mult and streams info out of ep companion desc */
1191
1192         /* Allow 3 retries for everything but isoc;
1193          * error count = 0 means infinite retries.
1194          */
1195         if (!usb_endpoint_xfer_isoc(&ep->desc))
1196                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
1197         else
1198                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(1));
1199
1200         ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
1201
1202         /* Set the max packet size and max burst */
1203         switch (udev->speed) {
1204         case USB_SPEED_SUPER:
1205                 max_packet = le16_to_cpu(ep->desc.wMaxPacketSize);
1206                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1207                 /* dig out max burst from ep companion desc */
1208                 max_packet = ep->ss_ep_comp.bMaxBurst;
1209                 if (!max_packet)
1210                         xhci_warn(xhci, "WARN no SS endpoint bMaxBurst\n");
1211                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_packet));
1212                 break;
1213         case USB_SPEED_HIGH:
1214                 /* bits 11:12 specify the number of additional transaction
1215                  * opportunities per microframe (USB 2.0, section 9.6.6)
1216                  */
1217                 if (usb_endpoint_xfer_isoc(&ep->desc) ||
1218                                 usb_endpoint_xfer_int(&ep->desc)) {
1219                         max_burst = (le16_to_cpu(ep->desc.wMaxPacketSize)
1220                                      & 0x1800) >> 11;
1221                         ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_burst));
1222                 }
1223                 /* Fall through */
1224         case USB_SPEED_FULL:
1225         case USB_SPEED_LOW:
1226                 max_packet = GET_MAX_PACKET(le16_to_cpu(ep->desc.wMaxPacketSize));
1227                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1228                 break;
1229         default:
1230                 BUG();
1231         }
1232         max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
1233         ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
1234
1235         /*
1236          * XXX no idea how to calculate the average TRB buffer length for bulk
1237          * endpoints, as the driver gives us no clue how big each scatter gather
1238          * list entry (or buffer) is going to be.
1239          *
1240          * For isochronous and interrupt endpoints, we set it to the max
1241          * available, until we have new API in the USB core to allow drivers to
1242          * declare how much bandwidth they actually need.
1243          *
1244          * Normally, it would be calculated by taking the total of the buffer
1245          * lengths in the TD and then dividing by the number of TRBs in a TD,
1246          * including link TRBs, No-op TRBs, and Event data TRBs.  Since we don't
1247          * use Event Data TRBs, and we don't chain in a link TRB on short
1248          * transfers, we're basically dividing by 1.
1249          */
1250         ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
1251
1252         /* FIXME Debug endpoint context */
1253         return 0;
1254 }
1255
1256 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1257                 struct xhci_virt_device *virt_dev,
1258                 struct usb_host_endpoint *ep)
1259 {
1260         unsigned int ep_index;
1261         struct xhci_ep_ctx *ep_ctx;
1262
1263         ep_index = xhci_get_endpoint_index(&ep->desc);
1264         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1265
1266         ep_ctx->ep_info = 0;
1267         ep_ctx->ep_info2 = 0;
1268         ep_ctx->deq = 0;
1269         ep_ctx->tx_info = 0;
1270         /* Don't free the endpoint ring until the set interface or configuration
1271          * request succeeds.
1272          */
1273 }
1274
1275 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1276  * Useful when you want to change one particular aspect of the endpoint and then
1277  * issue a configure endpoint command.
1278  */
1279 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1280                 struct xhci_container_ctx *in_ctx,
1281                 struct xhci_container_ctx *out_ctx,
1282                 unsigned int ep_index)
1283 {
1284         struct xhci_ep_ctx *out_ep_ctx;
1285         struct xhci_ep_ctx *in_ep_ctx;
1286
1287         out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1288         in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1289
1290         in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1291         in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1292         in_ep_ctx->deq = out_ep_ctx->deq;
1293         in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1294 }
1295
1296 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1297  * Useful when you want to change one particular aspect of the endpoint and then
1298  * issue a configure endpoint command.  Only the context entries field matters,
1299  * but we'll copy the whole thing anyway.
1300  */
1301 void xhci_slot_copy(struct xhci_hcd *xhci,
1302                 struct xhci_container_ctx *in_ctx,
1303                 struct xhci_container_ctx *out_ctx)
1304 {
1305         struct xhci_slot_ctx *in_slot_ctx;
1306         struct xhci_slot_ctx *out_slot_ctx;
1307
1308         in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1309         out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1310
1311         in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1312         in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1313         in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1314         in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1315 }
1316
1317 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1318 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1319 {
1320         int i;
1321         struct device *dev = xhci_to_hcd(xhci)->self.controller;
1322         int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1323
1324         xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
1325
1326         if (!num_sp)
1327                 return 0;
1328
1329         xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1330         if (!xhci->scratchpad)
1331                 goto fail_sp;
1332
1333         xhci->scratchpad->sp_array =
1334                 pci_alloc_consistent(to_pci_dev(dev),
1335                                      num_sp * sizeof(u64),
1336                                      &xhci->scratchpad->sp_dma);
1337         if (!xhci->scratchpad->sp_array)
1338                 goto fail_sp2;
1339
1340         xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1341         if (!xhci->scratchpad->sp_buffers)
1342                 goto fail_sp3;
1343
1344         xhci->scratchpad->sp_dma_buffers =
1345                 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1346
1347         if (!xhci->scratchpad->sp_dma_buffers)
1348                 goto fail_sp4;
1349
1350         xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1351         for (i = 0; i < num_sp; i++) {
1352                 dma_addr_t dma;
1353                 void *buf = pci_alloc_consistent(to_pci_dev(dev),
1354                                                  xhci->page_size, &dma);
1355                 if (!buf)
1356                         goto fail_sp5;
1357
1358                 xhci->scratchpad->sp_array[i] = dma;
1359                 xhci->scratchpad->sp_buffers[i] = buf;
1360                 xhci->scratchpad->sp_dma_buffers[i] = dma;
1361         }
1362
1363         return 0;
1364
1365  fail_sp5:
1366         for (i = i - 1; i >= 0; i--) {
1367                 pci_free_consistent(to_pci_dev(dev), xhci->page_size,
1368                                     xhci->scratchpad->sp_buffers[i],
1369                                     xhci->scratchpad->sp_dma_buffers[i]);
1370         }
1371         kfree(xhci->scratchpad->sp_dma_buffers);
1372
1373  fail_sp4:
1374         kfree(xhci->scratchpad->sp_buffers);
1375
1376  fail_sp3:
1377         pci_free_consistent(to_pci_dev(dev), num_sp * sizeof(u64),
1378                             xhci->scratchpad->sp_array,
1379                             xhci->scratchpad->sp_dma);
1380
1381  fail_sp2:
1382         kfree(xhci->scratchpad);
1383         xhci->scratchpad = NULL;
1384
1385  fail_sp:
1386         return -ENOMEM;
1387 }
1388
1389 static void scratchpad_free(struct xhci_hcd *xhci)
1390 {
1391         int num_sp;
1392         int i;
1393         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1394
1395         if (!xhci->scratchpad)
1396                 return;
1397
1398         num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1399
1400         for (i = 0; i < num_sp; i++) {
1401                 pci_free_consistent(pdev, xhci->page_size,
1402                                     xhci->scratchpad->sp_buffers[i],
1403                                     xhci->scratchpad->sp_dma_buffers[i]);
1404         }
1405         kfree(xhci->scratchpad->sp_dma_buffers);
1406         kfree(xhci->scratchpad->sp_buffers);
1407         pci_free_consistent(pdev, num_sp * sizeof(u64),
1408                             xhci->scratchpad->sp_array,
1409                             xhci->scratchpad->sp_dma);
1410         kfree(xhci->scratchpad);
1411         xhci->scratchpad = NULL;
1412 }
1413
1414 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1415                 bool allocate_in_ctx, bool allocate_completion,
1416                 gfp_t mem_flags)
1417 {
1418         struct xhci_command *command;
1419
1420         command = kzalloc(sizeof(*command), mem_flags);
1421         if (!command)
1422                 return NULL;
1423
1424         if (allocate_in_ctx) {
1425                 command->in_ctx =
1426                         xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1427                                         mem_flags);
1428                 if (!command->in_ctx) {
1429                         kfree(command);
1430                         return NULL;
1431                 }
1432         }
1433
1434         if (allocate_completion) {
1435                 command->completion =
1436                         kzalloc(sizeof(struct completion), mem_flags);
1437                 if (!command->completion) {
1438                         xhci_free_container_ctx(xhci, command->in_ctx);
1439                         kfree(command);
1440                         return NULL;
1441                 }
1442                 init_completion(command->completion);
1443         }
1444
1445         command->status = 0;
1446         INIT_LIST_HEAD(&command->cmd_list);
1447         return command;
1448 }
1449
1450 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
1451 {
1452         int last;
1453
1454         if (!urb_priv)
1455                 return;
1456
1457         last = urb_priv->length - 1;
1458         if (last >= 0) {
1459                 int     i;
1460                 for (i = 0; i <= last; i++)
1461                         kfree(urb_priv->td[i]);
1462         }
1463         kfree(urb_priv);
1464 }
1465
1466 void xhci_free_command(struct xhci_hcd *xhci,
1467                 struct xhci_command *command)
1468 {
1469         xhci_free_container_ctx(xhci,
1470                         command->in_ctx);
1471         kfree(command->completion);
1472         kfree(command);
1473 }
1474
1475 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1476 {
1477         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1478         int size;
1479         int i;
1480
1481         /* Free the Event Ring Segment Table and the actual Event Ring */
1482         if (xhci->ir_set) {
1483                 xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
1484                 xhci_write_64(xhci, 0, &xhci->ir_set->erst_base);
1485                 xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue);
1486         }
1487         size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1488         if (xhci->erst.entries)
1489                 pci_free_consistent(pdev, size,
1490                                 xhci->erst.entries, xhci->erst.erst_dma_addr);
1491         xhci->erst.entries = NULL;
1492         xhci_dbg(xhci, "Freed ERST\n");
1493         if (xhci->event_ring)
1494                 xhci_ring_free(xhci, xhci->event_ring);
1495         xhci->event_ring = NULL;
1496         xhci_dbg(xhci, "Freed event ring\n");
1497
1498         xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
1499         if (xhci->cmd_ring)
1500                 xhci_ring_free(xhci, xhci->cmd_ring);
1501         xhci->cmd_ring = NULL;
1502         xhci_dbg(xhci, "Freed command ring\n");
1503
1504         for (i = 1; i < MAX_HC_SLOTS; ++i)
1505                 xhci_free_virt_device(xhci, i);
1506
1507         if (xhci->segment_pool)
1508                 dma_pool_destroy(xhci->segment_pool);
1509         xhci->segment_pool = NULL;
1510         xhci_dbg(xhci, "Freed segment pool\n");
1511
1512         if (xhci->device_pool)
1513                 dma_pool_destroy(xhci->device_pool);
1514         xhci->device_pool = NULL;
1515         xhci_dbg(xhci, "Freed device context pool\n");
1516
1517         if (xhci->small_streams_pool)
1518                 dma_pool_destroy(xhci->small_streams_pool);
1519         xhci->small_streams_pool = NULL;
1520         xhci_dbg(xhci, "Freed small stream array pool\n");
1521
1522         if (xhci->medium_streams_pool)
1523                 dma_pool_destroy(xhci->medium_streams_pool);
1524         xhci->medium_streams_pool = NULL;
1525         xhci_dbg(xhci, "Freed medium stream array pool\n");
1526
1527         xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
1528         if (xhci->dcbaa)
1529                 pci_free_consistent(pdev, sizeof(*xhci->dcbaa),
1530                                 xhci->dcbaa, xhci->dcbaa->dma);
1531         xhci->dcbaa = NULL;
1532
1533         scratchpad_free(xhci);
1534
1535         xhci->num_usb2_ports = 0;
1536         xhci->num_usb3_ports = 0;
1537         kfree(xhci->usb2_ports);
1538         kfree(xhci->usb3_ports);
1539         kfree(xhci->port_array);
1540
1541         xhci->page_size = 0;
1542         xhci->page_shift = 0;
1543         xhci->bus_state[0].bus_suspended = 0;
1544         xhci->bus_state[1].bus_suspended = 0;
1545 }
1546
1547 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1548                 struct xhci_segment *input_seg,
1549                 union xhci_trb *start_trb,
1550                 union xhci_trb *end_trb,
1551                 dma_addr_t input_dma,
1552                 struct xhci_segment *result_seg,
1553                 char *test_name, int test_number)
1554 {
1555         unsigned long long start_dma;
1556         unsigned long long end_dma;
1557         struct xhci_segment *seg;
1558
1559         start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1560         end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1561
1562         seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
1563         if (seg != result_seg) {
1564                 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1565                                 test_name, test_number);
1566                 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1567                                 "input DMA 0x%llx\n",
1568                                 input_seg,
1569                                 (unsigned long long) input_dma);
1570                 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1571                                 "ending TRB %p (0x%llx DMA)\n",
1572                                 start_trb, start_dma,
1573                                 end_trb, end_dma);
1574                 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1575                                 result_seg, seg);
1576                 return -1;
1577         }
1578         return 0;
1579 }
1580
1581 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1582 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
1583 {
1584         struct {
1585                 dma_addr_t              input_dma;
1586                 struct xhci_segment     *result_seg;
1587         } simple_test_vector [] = {
1588                 /* A zeroed DMA field should fail */
1589                 { 0, NULL },
1590                 /* One TRB before the ring start should fail */
1591                 { xhci->event_ring->first_seg->dma - 16, NULL },
1592                 /* One byte before the ring start should fail */
1593                 { xhci->event_ring->first_seg->dma - 1, NULL },
1594                 /* Starting TRB should succeed */
1595                 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1596                 /* Ending TRB should succeed */
1597                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1598                         xhci->event_ring->first_seg },
1599                 /* One byte after the ring end should fail */
1600                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1601                 /* One TRB after the ring end should fail */
1602                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1603                 /* An address of all ones should fail */
1604                 { (dma_addr_t) (~0), NULL },
1605         };
1606         struct {
1607                 struct xhci_segment     *input_seg;
1608                 union xhci_trb          *start_trb;
1609                 union xhci_trb          *end_trb;
1610                 dma_addr_t              input_dma;
1611                 struct xhci_segment     *result_seg;
1612         } complex_test_vector [] = {
1613                 /* Test feeding a valid DMA address from a different ring */
1614                 {       .input_seg = xhci->event_ring->first_seg,
1615                         .start_trb = xhci->event_ring->first_seg->trbs,
1616                         .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1617                         .input_dma = xhci->cmd_ring->first_seg->dma,
1618                         .result_seg = NULL,
1619                 },
1620                 /* Test feeding a valid end TRB from a different ring */
1621                 {       .input_seg = xhci->event_ring->first_seg,
1622                         .start_trb = xhci->event_ring->first_seg->trbs,
1623                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1624                         .input_dma = xhci->cmd_ring->first_seg->dma,
1625                         .result_seg = NULL,
1626                 },
1627                 /* Test feeding a valid start and end TRB from a different ring */
1628                 {       .input_seg = xhci->event_ring->first_seg,
1629                         .start_trb = xhci->cmd_ring->first_seg->trbs,
1630                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1631                         .input_dma = xhci->cmd_ring->first_seg->dma,
1632                         .result_seg = NULL,
1633                 },
1634                 /* TRB in this ring, but after this TD */
1635                 {       .input_seg = xhci->event_ring->first_seg,
1636                         .start_trb = &xhci->event_ring->first_seg->trbs[0],
1637                         .end_trb = &xhci->event_ring->first_seg->trbs[3],
1638                         .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1639                         .result_seg = NULL,
1640                 },
1641                 /* TRB in this ring, but before this TD */
1642                 {       .input_seg = xhci->event_ring->first_seg,
1643                         .start_trb = &xhci->event_ring->first_seg->trbs[3],
1644                         .end_trb = &xhci->event_ring->first_seg->trbs[6],
1645                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1646                         .result_seg = NULL,
1647                 },
1648                 /* TRB in this ring, but after this wrapped TD */
1649                 {       .input_seg = xhci->event_ring->first_seg,
1650                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1651                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1652                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1653                         .result_seg = NULL,
1654                 },
1655                 /* TRB in this ring, but before this wrapped TD */
1656                 {       .input_seg = xhci->event_ring->first_seg,
1657                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1658                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1659                         .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
1660                         .result_seg = NULL,
1661                 },
1662                 /* TRB not in this ring, and we have a wrapped TD */
1663                 {       .input_seg = xhci->event_ring->first_seg,
1664                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1665                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1666                         .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
1667                         .result_seg = NULL,
1668                 },
1669         };
1670
1671         unsigned int num_tests;
1672         int i, ret;
1673
1674         num_tests = ARRAY_SIZE(simple_test_vector);
1675         for (i = 0; i < num_tests; i++) {
1676                 ret = xhci_test_trb_in_td(xhci,
1677                                 xhci->event_ring->first_seg,
1678                                 xhci->event_ring->first_seg->trbs,
1679                                 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1680                                 simple_test_vector[i].input_dma,
1681                                 simple_test_vector[i].result_seg,
1682                                 "Simple", i);
1683                 if (ret < 0)
1684                         return ret;
1685         }
1686
1687         num_tests = ARRAY_SIZE(complex_test_vector);
1688         for (i = 0; i < num_tests; i++) {
1689                 ret = xhci_test_trb_in_td(xhci,
1690                                 complex_test_vector[i].input_seg,
1691                                 complex_test_vector[i].start_trb,
1692                                 complex_test_vector[i].end_trb,
1693                                 complex_test_vector[i].input_dma,
1694                                 complex_test_vector[i].result_seg,
1695                                 "Complex", i);
1696                 if (ret < 0)
1697                         return ret;
1698         }
1699         xhci_dbg(xhci, "TRB math tests passed.\n");
1700         return 0;
1701 }
1702
1703 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
1704 {
1705         u64 temp;
1706         dma_addr_t deq;
1707
1708         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
1709                         xhci->event_ring->dequeue);
1710         if (deq == 0 && !in_interrupt())
1711                 xhci_warn(xhci, "WARN something wrong with SW event ring "
1712                                 "dequeue ptr.\n");
1713         /* Update HC event ring dequeue pointer */
1714         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
1715         temp &= ERST_PTR_MASK;
1716         /* Don't clear the EHB bit (which is RW1C) because
1717          * there might be more events to service.
1718          */
1719         temp &= ~ERST_EHB;
1720         xhci_dbg(xhci, "// Write event ring dequeue pointer, "
1721                         "preserving EHB bit\n");
1722         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
1723                         &xhci->ir_set->erst_dequeue);
1724 }
1725
1726 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
1727                 __le32 __iomem *addr, u8 major_revision)
1728 {
1729         u32 temp, port_offset, port_count;
1730         int i;
1731
1732         if (major_revision > 0x03) {
1733                 xhci_warn(xhci, "Ignoring unknown port speed, "
1734                                 "Ext Cap %p, revision = 0x%x\n",
1735                                 addr, major_revision);
1736                 /* Ignoring port protocol we can't understand. FIXME */
1737                 return;
1738         }
1739
1740         /* Port offset and count in the third dword, see section 7.2 */
1741         temp = xhci_readl(xhci, addr + 2);
1742         port_offset = XHCI_EXT_PORT_OFF(temp);
1743         port_count = XHCI_EXT_PORT_COUNT(temp);
1744         xhci_dbg(xhci, "Ext Cap %p, port offset = %u, "
1745                         "count = %u, revision = 0x%x\n",
1746                         addr, port_offset, port_count, major_revision);
1747         /* Port count includes the current port offset */
1748         if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
1749                 /* WTF? "Valid values are ‘1’ to MaxPorts" */
1750                 return;
1751         port_offset--;
1752         for (i = port_offset; i < (port_offset + port_count); i++) {
1753                 /* Duplicate entry.  Ignore the port if the revisions differ. */
1754                 if (xhci->port_array[i] != 0) {
1755                         xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
1756                                         " port %u\n", addr, i);
1757                         xhci_warn(xhci, "Port was marked as USB %u, "
1758                                         "duplicated as USB %u\n",
1759                                         xhci->port_array[i], major_revision);
1760                         /* Only adjust the roothub port counts if we haven't
1761                          * found a similar duplicate.
1762                          */
1763                         if (xhci->port_array[i] != major_revision &&
1764                                 xhci->port_array[i] != DUPLICATE_ENTRY) {
1765                                 if (xhci->port_array[i] == 0x03)
1766                                         xhci->num_usb3_ports--;
1767                                 else
1768                                         xhci->num_usb2_ports--;
1769                                 xhci->port_array[i] = DUPLICATE_ENTRY;
1770                         }
1771                         /* FIXME: Should we disable the port? */
1772                         continue;
1773                 }
1774                 xhci->port_array[i] = major_revision;
1775                 if (major_revision == 0x03)
1776                         xhci->num_usb3_ports++;
1777                 else
1778                         xhci->num_usb2_ports++;
1779         }
1780         /* FIXME: Should we disable ports not in the Extended Capabilities? */
1781 }
1782
1783 /*
1784  * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
1785  * specify what speeds each port is supposed to be.  We can't count on the port
1786  * speed bits in the PORTSC register being correct until a device is connected,
1787  * but we need to set up the two fake roothubs with the correct number of USB
1788  * 3.0 and USB 2.0 ports at host controller initialization time.
1789  */
1790 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
1791 {
1792         __le32 __iomem *addr;
1793         u32 offset;
1794         unsigned int num_ports;
1795         int i, port_index;
1796
1797         addr = &xhci->cap_regs->hcc_params;
1798         offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr));
1799         if (offset == 0) {
1800                 xhci_err(xhci, "No Extended Capability registers, "
1801                                 "unable to set up roothub.\n");
1802                 return -ENODEV;
1803         }
1804
1805         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1806         xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
1807         if (!xhci->port_array)
1808                 return -ENOMEM;
1809
1810         /*
1811          * For whatever reason, the first capability offset is from the
1812          * capability register base, not from the HCCPARAMS register.
1813          * See section 5.3.6 for offset calculation.
1814          */
1815         addr = &xhci->cap_regs->hc_capbase + offset;
1816         while (1) {
1817                 u32 cap_id;
1818
1819                 cap_id = xhci_readl(xhci, addr);
1820                 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
1821                         xhci_add_in_port(xhci, num_ports, addr,
1822                                         (u8) XHCI_EXT_PORT_MAJOR(cap_id));
1823                 offset = XHCI_EXT_CAPS_NEXT(cap_id);
1824                 if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
1825                                 == num_ports)
1826                         break;
1827                 /*
1828                  * Once you're into the Extended Capabilities, the offset is
1829                  * always relative to the register holding the offset.
1830                  */
1831                 addr += offset;
1832         }
1833
1834         if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
1835                 xhci_warn(xhci, "No ports on the roothubs?\n");
1836                 return -ENODEV;
1837         }
1838         xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
1839                         xhci->num_usb2_ports, xhci->num_usb3_ports);
1840
1841         /* Place limits on the number of roothub ports so that the hub
1842          * descriptors aren't longer than the USB core will allocate.
1843          */
1844         if (xhci->num_usb3_ports > 15) {
1845                 xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
1846                 xhci->num_usb3_ports = 15;
1847         }
1848         if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
1849                 xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
1850                                 USB_MAXCHILDREN);
1851                 xhci->num_usb2_ports = USB_MAXCHILDREN;
1852         }
1853
1854         /*
1855          * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
1856          * Not sure how the USB core will handle a hub with no ports...
1857          */
1858         if (xhci->num_usb2_ports) {
1859                 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
1860                                 xhci->num_usb2_ports, flags);
1861                 if (!xhci->usb2_ports)
1862                         return -ENOMEM;
1863
1864                 port_index = 0;
1865                 for (i = 0; i < num_ports; i++) {
1866                         if (xhci->port_array[i] == 0x03 ||
1867                                         xhci->port_array[i] == 0 ||
1868                                         xhci->port_array[i] == DUPLICATE_ENTRY)
1869                                 continue;
1870
1871                         xhci->usb2_ports[port_index] =
1872                                 &xhci->op_regs->port_status_base +
1873                                 NUM_PORT_REGS*i;
1874                         xhci_dbg(xhci, "USB 2.0 port at index %u, "
1875                                         "addr = %p\n", i,
1876                                         xhci->usb2_ports[port_index]);
1877                         port_index++;
1878                         if (port_index == xhci->num_usb2_ports)
1879                                 break;
1880                 }
1881         }
1882         if (xhci->num_usb3_ports) {
1883                 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
1884                                 xhci->num_usb3_ports, flags);
1885                 if (!xhci->usb3_ports)
1886                         return -ENOMEM;
1887
1888                 port_index = 0;
1889                 for (i = 0; i < num_ports; i++)
1890                         if (xhci->port_array[i] == 0x03) {
1891                                 xhci->usb3_ports[port_index] =
1892                                         &xhci->op_regs->port_status_base +
1893                                         NUM_PORT_REGS*i;
1894                                 xhci_dbg(xhci, "USB 3.0 port at index %u, "
1895                                                 "addr = %p\n", i,
1896                                                 xhci->usb3_ports[port_index]);
1897                                 port_index++;
1898                                 if (port_index == xhci->num_usb3_ports)
1899                                         break;
1900                         }
1901         }
1902         return 0;
1903 }
1904
1905 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
1906 {
1907         dma_addr_t      dma;
1908         struct device   *dev = xhci_to_hcd(xhci)->self.controller;
1909         unsigned int    val, val2;
1910         u64             val_64;
1911         struct xhci_segment     *seg;
1912         u32 page_size;
1913         int i;
1914
1915         page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
1916         xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
1917         for (i = 0; i < 16; i++) {
1918                 if ((0x1 & page_size) != 0)
1919                         break;
1920                 page_size = page_size >> 1;
1921         }
1922         if (i < 16)
1923                 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
1924         else
1925                 xhci_warn(xhci, "WARN: no supported page size\n");
1926         /* Use 4K pages, since that's common and the minimum the HC supports */
1927         xhci->page_shift = 12;
1928         xhci->page_size = 1 << xhci->page_shift;
1929         xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
1930
1931         /*
1932          * Program the Number of Device Slots Enabled field in the CONFIG
1933          * register with the max value of slots the HC can handle.
1934          */
1935         val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
1936         xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
1937                         (unsigned int) val);
1938         val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
1939         val |= (val2 & ~HCS_SLOTS_MASK);
1940         xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
1941                         (unsigned int) val);
1942         xhci_writel(xhci, val, &xhci->op_regs->config_reg);
1943
1944         /*
1945          * Section 5.4.8 - doorbell array must be
1946          * "physically contiguous and 64-byte (cache line) aligned".
1947          */
1948         xhci->dcbaa = pci_alloc_consistent(to_pci_dev(dev),
1949                         sizeof(*xhci->dcbaa), &dma);
1950         if (!xhci->dcbaa)
1951                 goto fail;
1952         memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
1953         xhci->dcbaa->dma = dma;
1954         xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
1955                         (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
1956         xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
1957
1958         /*
1959          * Initialize the ring segment pool.  The ring must be a contiguous
1960          * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
1961          * however, the command ring segment needs 64-byte aligned segments,
1962          * so we pick the greater alignment need.
1963          */
1964         xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
1965                         SEGMENT_SIZE, 64, xhci->page_size);
1966
1967         /* See Table 46 and Note on Figure 55 */
1968         xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
1969                         2112, 64, xhci->page_size);
1970         if (!xhci->segment_pool || !xhci->device_pool)
1971                 goto fail;
1972
1973         /* Linear stream context arrays don't have any boundary restrictions,
1974          * and only need to be 16-byte aligned.
1975          */
1976         xhci->small_streams_pool =
1977                 dma_pool_create("xHCI 256 byte stream ctx arrays",
1978                         dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
1979         xhci->medium_streams_pool =
1980                 dma_pool_create("xHCI 1KB stream ctx arrays",
1981                         dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
1982         /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
1983          * will be allocated with pci_alloc_consistent()
1984          */
1985
1986         if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
1987                 goto fail;
1988
1989         /* Set up the command ring to have one segments for now. */
1990         xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, flags);
1991         if (!xhci->cmd_ring)
1992                 goto fail;
1993         xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
1994         xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
1995                         (unsigned long long)xhci->cmd_ring->first_seg->dma);
1996
1997         /* Set the address in the Command Ring Control register */
1998         val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1999         val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2000                 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2001                 xhci->cmd_ring->cycle_state;
2002         xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
2003         xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2004         xhci_dbg_cmd_ptrs(xhci);
2005
2006         val = xhci_readl(xhci, &xhci->cap_regs->db_off);
2007         val &= DBOFF_MASK;
2008         xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
2009                         " from cap regs base addr\n", val);
2010         xhci->dba = (void __iomem *) xhci->cap_regs + val;
2011         xhci_dbg_regs(xhci);
2012         xhci_print_run_regs(xhci);
2013         /* Set ir_set to interrupt register set 0 */
2014         xhci->ir_set = &xhci->run_regs->ir_set[0];
2015
2016         /*
2017          * Event ring setup: Allocate a normal ring, but also setup
2018          * the event ring segment table (ERST).  Section 4.9.3.
2019          */
2020         xhci_dbg(xhci, "// Allocating event ring\n");
2021         xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, flags);
2022         if (!xhci->event_ring)
2023                 goto fail;
2024         if (xhci_check_trb_in_td_math(xhci, flags) < 0)
2025                 goto fail;
2026
2027         xhci->erst.entries = pci_alloc_consistent(to_pci_dev(dev),
2028                         sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS, &dma);
2029         if (!xhci->erst.entries)
2030                 goto fail;
2031         xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
2032                         (unsigned long long)dma);
2033
2034         memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2035         xhci->erst.num_entries = ERST_NUM_SEGS;
2036         xhci->erst.erst_dma_addr = dma;
2037         xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2038                         xhci->erst.num_entries,
2039                         xhci->erst.entries,
2040                         (unsigned long long)xhci->erst.erst_dma_addr);
2041
2042         /* set ring base address and size for each segment table entry */
2043         for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2044                 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2045                 entry->seg_addr = cpu_to_le64(seg->dma);
2046                 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2047                 entry->rsvd = 0;
2048                 seg = seg->next;
2049         }
2050
2051         /* set ERST count with the number of entries in the segment table */
2052         val = xhci_readl(xhci, &xhci->ir_set->erst_size);
2053         val &= ERST_SIZE_MASK;
2054         val |= ERST_NUM_SEGS;
2055         xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2056                         val);
2057         xhci_writel(xhci, val, &xhci->ir_set->erst_size);
2058
2059         xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
2060         /* set the segment table base address */
2061         xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2062                         (unsigned long long)xhci->erst.erst_dma_addr);
2063         val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2064         val_64 &= ERST_PTR_MASK;
2065         val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2066         xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2067
2068         /* Set the event ring dequeue address */
2069         xhci_set_hc_event_deq(xhci);
2070         xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
2071         xhci_print_ir_set(xhci, 0);
2072
2073         /*
2074          * XXX: Might need to set the Interrupter Moderation Register to
2075          * something other than the default (~1ms minimum between interrupts).
2076          * See section 5.5.1.2.
2077          */
2078         init_completion(&xhci->addr_dev);
2079         for (i = 0; i < MAX_HC_SLOTS; ++i)
2080                 xhci->devs[i] = NULL;
2081         for (i = 0; i < USB_MAXCHILDREN; ++i) {
2082                 xhci->bus_state[0].resume_done[i] = 0;
2083                 xhci->bus_state[1].resume_done[i] = 0;
2084         }
2085
2086         if (scratchpad_alloc(xhci, flags))
2087                 goto fail;
2088         if (xhci_setup_port_arrays(xhci, flags))
2089                 goto fail;
2090
2091         return 0;
2092
2093 fail:
2094         xhci_warn(xhci, "Couldn't initialize memory\n");
2095         xhci_mem_cleanup(xhci);
2096         return -ENOMEM;
2097 }