drivers/usb/host/xhci-hub.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23
  24 #include <linux/slab.h>
  25 #include <linux/device.h>
  26 #include <asm/unaligned.h>
  27
  28 #include "xhci.h"
  29 #include "xhci-trace.h"
  30
  31 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  32 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  33                          PORT_RC | PORT_PLC | PORT_PE)
  34
  35 /* USB 3.0 BOS descriptor and a capability descriptor, combined */
  36 static u8 usb_bos_descriptor [] = {
  37         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  38         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  39         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  40         0x1,                            /*  __u8 bNumDeviceCaps */
  41         /* First device capability */
  42         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  43         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  44         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  45         0x00,                           /* bmAttributes, LTM off by default */
  46         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  47         0x03,                           /* bFunctionalitySupport,
  48                                            USB 3.0 speed only */
  49         0x00,                           /* bU1DevExitLat, set later. */
  50         0x00, 0x00                      /* __le16 bU2DevExitLat, set later. */
  51 };
  52
  53
  54 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
  55                 struct usb_hub_descriptor *desc, int ports)
  56 {
  57         u16 temp;
  58
  59         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
  60         desc->bHubContrCurrent = 0;
  61
  62         desc->bNbrPorts = ports;
  63         temp = 0;
  64         /* Bits 1:0 - support per-port power switching, or power always on */
  65         if (HCC_PPC(xhci->hcc_params))
  66                 temp |= HUB_CHAR_INDV_PORT_LPSM;
  67         else
  68                 temp |= HUB_CHAR_NO_LPSM;
  69         /* Bit  2 - root hubs are not part of a compound device */
  70         /* Bits 4:3 - individual port over current protection */
  71         temp |= HUB_CHAR_INDV_PORT_OCPM;
  72         /* Bits 6:5 - no TTs in root ports */
  73         /* Bit  7 - no port indicators */
  74         desc->wHubCharacteristics = cpu_to_le16(temp);
  75 }
  76
  77 /* Fill in the USB 2.0 roothub descriptor */
  78 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  79                 struct usb_hub_descriptor *desc)
  80 {
  81         int ports;
  82         u16 temp;
  83         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
  84         u32 portsc;
  85         unsigned int i;
  86
  87         ports = xhci->num_usb2_ports;
  88
  89         xhci_common_hub_descriptor(xhci, desc, ports);
  90         desc->bDescriptorType = USB_DT_HUB;
  91         temp = 1 + (ports / 8);
  92         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
  93
  94         /* The Device Removable bits are reported on a byte granularity.
  95          * If the port doesn't exist within that byte, the bit is set to 0.
  96          */
  97         memset(port_removable, 0, sizeof(port_removable));
  98         for (i = 0; i < ports; i++) {
  99                 portsc = readl(xhci->usb2_ports[i]);
 100                 /* If a device is removable, PORTSC reports a 0, same as in the
 101                  * hub descriptor DeviceRemovable bits.
 102                  */
 103                 if (portsc & PORT_DEV_REMOVE)
 104                         /* This math is hairy because bit 0 of DeviceRemovable
 105                          * is reserved, and bit 1 is for port 1, etc.
 106                          */
 107                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 108         }
 109
 110         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 111          * ports on it.  The USB 2.0 specification says that there are two
 112          * variable length fields at the end of the hub descriptor:
 113          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 114          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 115          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 116          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 117          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 118          * set of ports that actually exist.
 119          */
 120         memset(desc->u.hs.DeviceRemovable, 0xff,
 121                         sizeof(desc->u.hs.DeviceRemovable));
 122         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 123                         sizeof(desc->u.hs.PortPwrCtrlMask));
 124
 125         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 126                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 127                                 sizeof(__u8));
 128 }
 129
 130 /* Fill in the USB 3.0 roothub descriptor */
 131 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 132                 struct usb_hub_descriptor *desc)
 133 {
 134         int ports;
 135         u16 port_removable;
 136         u32 portsc;
 137         unsigned int i;
 138
 139         ports = xhci->num_usb3_ports;
 140         xhci_common_hub_descriptor(xhci, desc, ports);
 141         desc->bDescriptorType = USB_DT_SS_HUB;
 142         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 143
 144         /* header decode latency should be zero for roothubs,
 145          * see section 4.23.5.2.
 146          */
 147         desc->u.ss.bHubHdrDecLat = 0;
 148         desc->u.ss.wHubDelay = 0;
 149
 150         port_removable = 0;
 151         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 152         for (i = 0; i < ports; i++) {
 153                 portsc = readl(xhci->usb3_ports[i]);
 154                 if (portsc & PORT_DEV_REMOVE)
 155                         port_removable |= 1 << (i + 1);
 156         }
 157
 158         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 159 }
 160
 161 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 162                 struct usb_hub_descriptor *desc)
 163 {
 164
 165         if (hcd->speed == HCD_USB3)
 166                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 167         else
 168                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 169
 170 }
 171
 172 static unsigned int xhci_port_speed(unsigned int port_status)
 173 {
 174         if (DEV_LOWSPEED(port_status))
 175                 return USB_PORT_STAT_LOW_SPEED;
 176         if (DEV_HIGHSPEED(port_status))
 177                 return USB_PORT_STAT_HIGH_SPEED;
 178         /*
 179          * FIXME: Yes, we should check for full speed, but the core uses that as
 180          * a default in portspeed() in usb/core/hub.c (which is the only place
 181          * USB_PORT_STAT_*_SPEED is used).
 182          */
 183         return 0;
 184 }
 185
 186 /*
 187  * These bits are Read Only (RO) and should be saved and written to the
 188  * registers: 0, 3, 10:13, 30
 189  * connect status, over-current status, port speed, and device removable.
 190  * connect status and port speed are also sticky - meaning they're in
 191  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 192  */
 193 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 194 /*
 195  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 196  * bits 5:8, 9, 14:15, 25:27
 197  * link state, port power, port indicator state, "wake on" enable state
 198  */
 199 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 200 /*
 201  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 202  * bit 4 (port reset)
 203  */
 204 #define XHCI_PORT_RW1S  ((1<<4))
 205 /*
 206  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 207  * bits 1, 17, 18, 19, 20, 21, 22, 23
 208  * port enable/disable, and
 209  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 210  * over-current, reset, link state, and L1 change
 211  */
 212 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 213 /*
 214  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 215  * latched in
 216  */
 217 #define XHCI_PORT_RW    ((1<<16))
 218 /*
 219  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 220  * bits 2, 24, 28:31
 221  */
 222 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 223
 224 /*
 225  * Given a port state, this function returns a value that would result in the
 226  * port being in the same state, if the value was written to the port status
 227  * control register.
 228  * Save Read Only (RO) bits and save read/write bits where
 229  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 230  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 231  */
 232 u32 xhci_port_state_to_neutral(u32 state)
 233 {
 234         /* Save read-only status and port state */
 235         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 236 }
 237
 238 /*
 239  * find slot id based on port number.
 240  * @port: The one-based port number from one of the two split roothubs.
 241  */
 242 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 243                 u16 port)
 244 {
 245         int slot_id;
 246         int i;
 247         enum usb_device_speed speed;
 248
 249         slot_id = 0;
 250         for (i = 0; i < MAX_HC_SLOTS; i++) {
 251                 if (!xhci->devs[i])
 252                         continue;
 253                 speed = xhci->devs[i]->udev->speed;
 254                 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
 255                                 && xhci->devs[i]->fake_port == port) {
 256                         slot_id = i;
 257                         break;
 258                 }
 259         }
 260
 261         return slot_id;
 262 }
 263
 264 /*
 265  * Stop device
 266  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 267  * to complete.
 268  * suspend will set to 1, if suspend bit need to set in command.
 269  */
 270 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 271 {
 272         struct xhci_virt_device *virt_dev;
 273         struct xhci_command *cmd;
 274         unsigned long flags;
 275         int ret;
 276         int i;
 277
 278         ret = 0;
 279         virt_dev = xhci->devs[slot_id];
 280         cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 281         if (!cmd) {
 282                 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
 283                 return -ENOMEM;
 284         }
 285
 286         spin_lock_irqsave(&xhci->lock, flags);
 287         for (i = LAST_EP_INDEX; i > 0; i--) {
 288                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 289                         struct xhci_command *command;
 290                         command = xhci_alloc_command(xhci, false, false,
 291                                                      GFP_NOWAIT);
 292                         if (!command) {
 293                                 spin_unlock_irqrestore(&xhci->lock, flags);
 294                                 xhci_free_command(xhci, cmd);
 295                                 return -ENOMEM;
 296
 297                         }
 298                         xhci_queue_stop_endpoint(xhci, command, slot_id, i,
 299                                                  suspend);
 300                 }
 301         }
 302         xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 303         xhci_ring_cmd_db(xhci);
 304         spin_unlock_irqrestore(&xhci->lock, flags);
 305
 306         /* Wait for last stop endpoint command to finish */
 307         wait_for_completion(cmd->completion);
 308
 309         if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) {
 310                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 311                 ret = -ETIME;
 312         }
 313         xhci_free_command(xhci, cmd);
 314         return ret;
 315 }
 316
 317 /*
 318  * Ring device, it rings the all doorbells unconditionally.
 319  */
 320 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 321 {
 322         int i, s;
 323         struct xhci_virt_ep *ep;
 324
 325         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 326                 ep = &xhci->devs[slot_id]->eps[i];
 327
 328                 if (ep->ep_state & EP_HAS_STREAMS) {
 329                         for (s = 1; s < ep->stream_info->num_streams; s++)
 330                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 331                 } else if (ep->ring && ep->ring->dequeue) {
 332                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 333                 }
 334         }
 335
 336         return;
 337 }
 338
 339 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 340                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 341 {
 342         /* Don't allow the USB core to disable SuperSpeed ports. */
 343         if (hcd->speed == HCD_USB3) {
 344                 xhci_dbg(xhci, "Ignoring request to disable "
 345                                 "SuperSpeed port.\n");
 346                 return;
 347         }
 348
 349         /* Write 1 to disable the port */
 350         writel(port_status | PORT_PE, addr);
 351         port_status = readl(addr);
 352         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 353                         wIndex, port_status);
 354 }
 355
 356 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 357                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 358 {
 359         char *port_change_bit;
 360         u32 status;
 361
 362         switch (wValue) {
 363         case USB_PORT_FEAT_C_RESET:
 364                 status = PORT_RC;
 365                 port_change_bit = "reset";
 366                 break;
 367         case USB_PORT_FEAT_C_BH_PORT_RESET:
 368                 status = PORT_WRC;
 369                 port_change_bit = "warm(BH) reset";
 370                 break;
 371         case USB_PORT_FEAT_C_CONNECTION:
 372                 status = PORT_CSC;
 373                 port_change_bit = "connect";
 374                 break;
 375         case USB_PORT_FEAT_C_OVER_CURRENT:
 376                 status = PORT_OCC;
 377                 port_change_bit = "over-current";
 378                 break;
 379         case USB_PORT_FEAT_C_ENABLE:
 380                 status = PORT_PEC;
 381                 port_change_bit = "enable/disable";
 382                 break;
 383         case USB_PORT_FEAT_C_SUSPEND:
 384                 status = PORT_PLC;
 385                 port_change_bit = "suspend/resume";
 386                 break;
 387         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 388                 status = PORT_PLC;
 389                 port_change_bit = "link state";
 390                 break;
 391         default:
 392                 /* Should never happen */
 393                 return;
 394         }
 395         /* Change bits are all write 1 to clear */
 396         writel(port_status | status, addr);
 397         port_status = readl(addr);
 398         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 399                         port_change_bit, wIndex, port_status);
 400 }
 401
 402 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 403 {
 404         int max_ports;
 405         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 406
 407         if (hcd->speed == HCD_USB3) {
 408                 max_ports = xhci->num_usb3_ports;
 409                 *port_array = xhci->usb3_ports;
 410         } else {
 411                 max_ports = xhci->num_usb2_ports;
 412                 *port_array = xhci->usb2_ports;
 413         }
 414
 415         return max_ports;
 416 }
 417
 418 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 419                                 int port_id, u32 link_state)
 420 {
 421         u32 temp;
 422
 423         temp = readl(port_array[port_id]);
 424         temp = xhci_port_state_to_neutral(temp);
 425         temp &= ~PORT_PLS_MASK;
 426         temp |= PORT_LINK_STROBE | link_state;
 427         writel(temp, port_array[port_id]);
 428 }
 429
 430 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 431                 __le32 __iomem **port_array, int port_id, u16 wake_mask)
 432 {
 433         u32 temp;
 434
 435         temp = readl(port_array[port_id]);
 436         temp = xhci_port_state_to_neutral(temp);
 437
 438         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 439                 temp |= PORT_WKCONN_E;
 440         else
 441                 temp &= ~PORT_WKCONN_E;
 442
 443         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 444                 temp |= PORT_WKDISC_E;
 445         else
 446                 temp &= ~PORT_WKDISC_E;
 447
 448         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 449                 temp |= PORT_WKOC_E;
 450         else
 451                 temp &= ~PORT_WKOC_E;
 452
 453         writel(temp, port_array[port_id]);
 454 }
 455
 456 /* Test and clear port RWC bit */
 457 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 458                                 int port_id, u32 port_bit)
 459 {
 460         u32 temp;
 461
 462         temp = readl(port_array[port_id]);
 463         if (temp & port_bit) {
 464                 temp = xhci_port_state_to_neutral(temp);
 465                 temp |= port_bit;
 466                 writel(temp, port_array[port_id]);
 467         }
 468 }
 469
 470 /* Updates Link Status for USB 2.1 port */
 471 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 472 {
 473         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 474                 *status |= USB_PORT_STAT_L1;
 475 }
 476
 477 /* Updates Link Status for super Speed port */
 478 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 479                 u32 *status, u32 status_reg)
 480 {
 481         u32 pls = status_reg & PORT_PLS_MASK;
 482
 483         /* resume state is a xHCI internal state.
 484          * Do not report it to usb core.
 485          */
 486         if (pls == XDEV_RESUME)
 487                 return;
 488
 489         /* When the CAS bit is set then warm reset
 490          * should be performed on port
 491          */
 492         if (status_reg & PORT_CAS) {
 493                 /* The CAS bit can be set while the port is
 494                  * in any link state.
 495                  * Only roothubs have CAS bit, so we
 496                  * pretend to be in compliance mode
 497                  * unless we're already in compliance
 498                  * or the inactive state.
 499                  */
 500                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 501                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 502                         pls = USB_SS_PORT_LS_COMP_MOD;
 503                 }
 504                 /* Return also connection bit -
 505                  * hub state machine resets port
 506                  * when this bit is set.
 507                  */
 508                 pls |= USB_PORT_STAT_CONNECTION;
 509         } else {
 510                 /*
 511                  * If CAS bit isn't set but the Port is already at
 512                  * Compliance Mode, fake a connection so the USB core
 513                  * notices the Compliance state and resets the port.
 514                  * This resolves an issue generated by the SN65LVPE502CP
 515                  * in which sometimes the port enters compliance mode
 516                  * caused by a delay on the host-device negotiation.
 517                  */
 518                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 519                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 520                         pls |= USB_PORT_STAT_CONNECTION;
 521         }
 522
 523         /* update status field */
 524         *status |= pls;
 525 }
 526
 527 /*
 528  * Function for Compliance Mode Quirk.
 529  *
 530  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 531  * the compliance mode timer is deleted. A port won't enter
 532  * compliance mode if it has previously entered U0.
 533  */
 534 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 535                                     u16 wIndex)
 536 {
 537         u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
 538         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 539
 540         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 541                 return;
 542
 543         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 544                 xhci->port_status_u0 |= 1 << wIndex;
 545                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 546                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 547                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 548                                 "All USB3 ports have entered U0 already!");
 549                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 550                                 "Compliance Mode Recovery Timer Deleted.");
 551                 }
 552         }
 553 }
 554
 555 /*
 556  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 557  * 3.0 hubs use.
 558  *
 559  * Possible side effects:
 560  *  - Mark a port as being done with device resume,
 561  *    and ring the endpoint doorbells.
 562  *  - Stop the Synopsys redriver Compliance Mode polling.
 563  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
 564  */
 565 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 566                 struct xhci_bus_state *bus_state,
 567                 __le32 __iomem **port_array,
 568                 u16 wIndex, u32 raw_port_status,
 569                 unsigned long flags)
 570         __releases(&xhci->lock)
 571         __acquires(&xhci->lock)
 572 {
 573         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 574         u32 status = 0;
 575         int slot_id;
 576
 577         /* wPortChange bits */
 578         if (raw_port_status & PORT_CSC)
 579                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 580         if (raw_port_status & PORT_PEC)
 581                 status |= USB_PORT_STAT_C_ENABLE << 16;
 582         if ((raw_port_status & PORT_OCC))
 583                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 584         if ((raw_port_status & PORT_RC))
 585                 status |= USB_PORT_STAT_C_RESET << 16;
 586         /* USB3.0 only */
 587         if (hcd->speed == HCD_USB3) {
 588                 if ((raw_port_status & PORT_PLC))
 589                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 590                 if ((raw_port_status & PORT_WRC))
 591                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 592         }
 593
 594         if (hcd->speed != HCD_USB3) {
 595                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 596                                 && (raw_port_status & PORT_POWER))
 597                         status |= USB_PORT_STAT_SUSPEND;
 598         }
 599         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 600                         !DEV_SUPERSPEED(raw_port_status)) {
 601                 if ((raw_port_status & PORT_RESET) ||
 602                                 !(raw_port_status & PORT_PE))
 603                         return 0xffffffff;
 604                 if (time_after_eq(jiffies,
 605                                         bus_state->resume_done[wIndex])) {
 606                         int time_left;
 607
 608                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 609                                         wIndex + 1);
 610                         bus_state->resume_done[wIndex] = 0;
 611                         clear_bit(wIndex, &bus_state->resuming_ports);
 612
 613                         set_bit(wIndex, &bus_state->rexit_ports);
 614                         xhci_set_link_state(xhci, port_array, wIndex,
 615                                         XDEV_U0);
 616
 617                         spin_unlock_irqrestore(&xhci->lock, flags);
 618                         time_left = wait_for_completion_timeout(
 619                                         &bus_state->rexit_done[wIndex],
 620                                         msecs_to_jiffies(
 621                                                 XHCI_MAX_REXIT_TIMEOUT));
 622                         spin_lock_irqsave(&xhci->lock, flags);
 623
 624                         if (time_left) {
 625                                 slot_id = xhci_find_slot_id_by_port(hcd,
 626                                                 xhci, wIndex + 1);
 627                                 if (!slot_id) {
 628                                         xhci_dbg(xhci, "slot_id is zero\n");
 629                                         return 0xffffffff;
 630                                 }
 631                                 xhci_ring_device(xhci, slot_id);
 632                         } else {
 633                                 int port_status = readl(port_array[wIndex]);
 634                                 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
 635                                                 XHCI_MAX_REXIT_TIMEOUT,
 636                                                 port_status);
 637                                 status |= USB_PORT_STAT_SUSPEND;
 638                                 clear_bit(wIndex, &bus_state->rexit_ports);
 639                         }
 640
 641                         bus_state->port_c_suspend |= 1 << wIndex;
 642                         bus_state->suspended_ports &= ~(1 << wIndex);
 643                 } else {
 644                         /*
 645                          * The resume has been signaling for less than
 646                          * 20ms. Report the port status as SUSPEND,
 647                          * let the usbcore check port status again
 648                          * and clear resume signaling later.
 649                          */
 650                         status |= USB_PORT_STAT_SUSPEND;
 651                 }
 652         }
 653         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0
 654                         && (raw_port_status & PORT_POWER)
 655                         && (bus_state->suspended_ports & (1 << wIndex))) {
 656                 bus_state->suspended_ports &= ~(1 << wIndex);
 657                 if (hcd->speed != HCD_USB3)
 658                         bus_state->port_c_suspend |= 1 << wIndex;
 659         }
 660         if (raw_port_status & PORT_CONNECT) {
 661                 status |= USB_PORT_STAT_CONNECTION;
 662                 status |= xhci_port_speed(raw_port_status);
 663         }
 664         if (raw_port_status & PORT_PE)
 665                 status |= USB_PORT_STAT_ENABLE;
 666         if (raw_port_status & PORT_OC)
 667                 status |= USB_PORT_STAT_OVERCURRENT;
 668         if (raw_port_status & PORT_RESET)
 669                 status |= USB_PORT_STAT_RESET;
 670         if (raw_port_status & PORT_POWER) {
 671                 if (hcd->speed == HCD_USB3)
 672                         status |= USB_SS_PORT_STAT_POWER;
 673                 else
 674                         status |= USB_PORT_STAT_POWER;
 675         }
 676         /* Update Port Link State */
 677         if (hcd->speed == HCD_USB3) {
 678                 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
 679                 /*
 680                  * Verify if all USB3 Ports Have entered U0 already.
 681                  * Delete Compliance Mode Timer if so.
 682                  */
 683                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
 684         } else {
 685                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
 686         }
 687         if (bus_state->port_c_suspend & (1 << wIndex))
 688                 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
 689
 690         return status;
 691 }
 692
 693 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 694                 u16 wIndex, char *buf, u16 wLength)
 695 {
 696         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 697         int max_ports;
 698         unsigned long flags;
 699         u32 temp, status;
 700         int retval = 0;
 701         __le32 __iomem **port_array;
 702         int slot_id;
 703         struct xhci_bus_state *bus_state;
 704         u16 link_state = 0;
 705         u16 wake_mask = 0;
 706         u16 timeout = 0;
 707
 708         max_ports = xhci_get_ports(hcd, &port_array);
 709         bus_state = &xhci->bus_state[hcd_index(hcd)];
 710
 711         spin_lock_irqsave(&xhci->lock, flags);
 712         switch (typeReq) {
 713         case GetHubStatus:
 714                 /* No power source, over-current reported per port */
 715                 memset(buf, 0, 4);
 716                 break;
 717         case GetHubDescriptor:
 718                 /* Check to make sure userspace is asking for the USB 3.0 hub
 719                  * descriptor for the USB 3.0 roothub.  If not, we stall the
 720                  * endpoint, like external hubs do.
 721                  */
 722                 if (hcd->speed == HCD_USB3 &&
 723                                 (wLength < USB_DT_SS_HUB_SIZE ||
 724                                  wValue != (USB_DT_SS_HUB << 8))) {
 725                         xhci_dbg(xhci, "Wrong hub descriptor type for "
 726                                         "USB 3.0 roothub.\n");
 727                         goto error;
 728                 }
 729                 xhci_hub_descriptor(hcd, xhci,
 730                                 (struct usb_hub_descriptor *) buf);
 731                 break;
 732         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
 733                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
 734                         goto error;
 735
 736                 if (hcd->speed != HCD_USB3)
 737                         goto error;
 738
 739                 /* Set the U1 and U2 exit latencies. */
 740                 memcpy(buf, &usb_bos_descriptor,
 741                                 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
 742                 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 743                         temp = readl(&xhci->cap_regs->hcs_params3);
 744                         buf[12] = HCS_U1_LATENCY(temp);
 745                         put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 746                 }
 747
 748                 /* Indicate whether the host has LTM support. */
 749                 temp = readl(&xhci->cap_regs->hcc_params);
 750                 if (HCC_LTC(temp))
 751                         buf[8] |= USB_LTM_SUPPORT;
 752
 753                 spin_unlock_irqrestore(&xhci->lock, flags);
 754                 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 755         case GetPortStatus:
 756                 if (!wIndex || wIndex > max_ports)
 757                         goto error;
 758                 wIndex--;
 759                 temp = readl(port_array[wIndex]);
 760                 if (temp == 0xffffffff) {
 761                         retval = -ENODEV;
 762                         break;
 763                 }
 764                 status = xhci_get_port_status(hcd, bus_state, port_array,
 765                                 wIndex, temp, flags);
 766                 if (status == 0xffffffff)
 767                         goto error;
 768
 769                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
 770                                 wIndex, temp);
 771                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
 772
 773                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
 774                 break;
 775         case SetPortFeature:
 776                 if (wValue == USB_PORT_FEAT_LINK_STATE)
 777                         link_state = (wIndex & 0xff00) >> 3;
 778                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
 779                         wake_mask = wIndex & 0xff00;
 780                 /* The MSB of wIndex is the U1/U2 timeout */
 781                 timeout = (wIndex & 0xff00) >> 8;
 782                 wIndex &= 0xff;
 783                 if (!wIndex || wIndex > max_ports)
 784                         goto error;
 785                 wIndex--;
 786                 temp = readl(port_array[wIndex]);
 787                 if (temp == 0xffffffff) {
 788                         retval = -ENODEV;
 789                         break;
 790                 }
 791                 temp = xhci_port_state_to_neutral(temp);
 792                 /* FIXME: What new port features do we need to support? */
 793                 switch (wValue) {
 794                 case USB_PORT_FEAT_SUSPEND:
 795                         temp = readl(port_array[wIndex]);
 796                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
 797                                 /* Resume the port to U0 first */
 798                                 xhci_set_link_state(xhci, port_array, wIndex,
 799                                                         XDEV_U0);
 800                                 spin_unlock_irqrestore(&xhci->lock, flags);
 801                                 msleep(10);
 802                                 spin_lock_irqsave(&xhci->lock, flags);
 803                         }
 804                         /* In spec software should not attempt to suspend
 805                          * a port unless the port reports that it is in the
 806                          * enabled (PED = ‘1’,PLS < ‘3’) state.
 807                          */
 808                         temp = readl(port_array[wIndex]);
 809                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
 810                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
 811                                 xhci_warn(xhci, "USB core suspending device "
 812                                           "not in U0/U1/U2.\n");
 813                                 goto error;
 814                         }
 815
 816                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 817                                         wIndex + 1);
 818                         if (!slot_id) {
 819                                 xhci_warn(xhci, "slot_id is zero\n");
 820                                 goto error;
 821                         }
 822                         /* unlock to execute stop endpoint commands */
 823                         spin_unlock_irqrestore(&xhci->lock, flags);
 824                         xhci_stop_device(xhci, slot_id, 1);
 825                         spin_lock_irqsave(&xhci->lock, flags);
 826
 827                         xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
 828
 829                         spin_unlock_irqrestore(&xhci->lock, flags);
 830                         msleep(10); /* wait device to enter */
 831                         spin_lock_irqsave(&xhci->lock, flags);
 832
 833                         temp = readl(port_array[wIndex]);
 834                         bus_state->suspended_ports |= 1 << wIndex;
 835                         break;
 836                 case USB_PORT_FEAT_LINK_STATE:
 837                         temp = readl(port_array[wIndex]);
 838
 839                         /* Disable port */
 840                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
 841                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
 842                                 temp = xhci_port_state_to_neutral(temp);
 843                                 /*
 844                                  * Clear all change bits, so that we get a new
 845                                  * connection event.
 846                                  */
 847                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
 848                                         PORT_OCC | PORT_RC | PORT_PLC |
 849                                         PORT_CEC;
 850                                 writel(temp | PORT_PE, port_array[wIndex]);
 851                                 temp = readl(port_array[wIndex]);
 852                                 break;
 853                         }
 854
 855                         /* Put link in RxDetect (enable port) */
 856                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
 857                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
 858                                 xhci_set_link_state(xhci, port_array, wIndex,
 859                                                 link_state);
 860                                 temp = readl(port_array[wIndex]);
 861                                 break;
 862                         }
 863
 864                         /* Software should not attempt to set
 865                          * port link state above '3' (U3) and the port
 866                          * must be enabled.
 867                          */
 868                         if ((temp & PORT_PE) == 0 ||
 869                                 (link_state > USB_SS_PORT_LS_U3)) {
 870                                 xhci_warn(xhci, "Cannot set link state.\n");
 871                                 goto error;
 872                         }
 873
 874                         if (link_state == USB_SS_PORT_LS_U3) {
 875                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 876                                                 wIndex + 1);
 877                                 if (slot_id) {
 878                                         /* unlock to execute stop endpoint
 879                                          * commands */
 880                                         spin_unlock_irqrestore(&xhci->lock,
 881                                                                 flags);
 882                                         xhci_stop_device(xhci, slot_id, 1);
 883                                         spin_lock_irqsave(&xhci->lock, flags);
 884                                 }
 885                         }
 886
 887                         xhci_set_link_state(xhci, port_array, wIndex,
 888                                                 link_state);
 889
 890                         spin_unlock_irqrestore(&xhci->lock, flags);
 891                         msleep(20); /* wait device to enter */
 892                         spin_lock_irqsave(&xhci->lock, flags);
 893
 894                         temp = readl(port_array[wIndex]);
 895                         if (link_state == USB_SS_PORT_LS_U3)
 896                                 bus_state->suspended_ports |= 1 << wIndex;
 897                         break;
 898                 case USB_PORT_FEAT_POWER:
 899                         /*
 900                          * Turn on ports, even if there isn't per-port switching.
 901                          * HC will report connect events even before this is set.
 902                          * However, hub_wq will ignore the roothub events until
 903                          * the roothub is registered.
 904                          */
 905                         writel(temp | PORT_POWER, port_array[wIndex]);
 906
 907                         temp = readl(port_array[wIndex]);
 908                         xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n", wIndex, temp);
 909
 910                         spin_unlock_irqrestore(&xhci->lock, flags);
 911                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 912                                         wIndex);
 913                         if (temp)
 914                                 usb_acpi_set_power_state(hcd->self.root_hub,
 915                                                 wIndex, true);
 916                         spin_lock_irqsave(&xhci->lock, flags);
 917                         break;
 918                 case USB_PORT_FEAT_RESET:
 919                         temp = (temp | PORT_RESET);
 920                         writel(temp, port_array[wIndex]);
 921
 922                         temp = readl(port_array[wIndex]);
 923                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
 924                         break;
 925                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
 926                         xhci_set_remote_wake_mask(xhci, port_array,
 927                                         wIndex, wake_mask);
 928                         temp = readl(port_array[wIndex]);
 929                         xhci_dbg(xhci, "set port remote wake mask, "
 930                                         "actual port %d status  = 0x%x\n",
 931                                         wIndex, temp);
 932                         break;
 933                 case USB_PORT_FEAT_BH_PORT_RESET:
 934                         temp |= PORT_WR;
 935                         writel(temp, port_array[wIndex]);
 936
 937                         temp = readl(port_array[wIndex]);
 938                         break;
 939                 case USB_PORT_FEAT_U1_TIMEOUT:
 940                         if (hcd->speed != HCD_USB3)
 941                                 goto error;
 942                         temp = readl(port_array[wIndex] + PORTPMSC);
 943                         temp &= ~PORT_U1_TIMEOUT_MASK;
 944                         temp |= PORT_U1_TIMEOUT(timeout);
 945                         writel(temp, port_array[wIndex] + PORTPMSC);
 946                         break;
 947                 case USB_PORT_FEAT_U2_TIMEOUT:
 948                         if (hcd->speed != HCD_USB3)
 949                                 goto error;
 950                         temp = readl(port_array[wIndex] + PORTPMSC);
 951                         temp &= ~PORT_U2_TIMEOUT_MASK;
 952                         temp |= PORT_U2_TIMEOUT(timeout);
 953                         writel(temp, port_array[wIndex] + PORTPMSC);
 954                         break;
 955                 default:
 956                         goto error;
 957                 }
 958                 /* unblock any posted writes */
 959                 temp = readl(port_array[wIndex]);
 960                 break;
 961         case ClearPortFeature:
 962                 if (!wIndex || wIndex > max_ports)
 963                         goto error;
 964                 wIndex--;
 965                 temp = readl(port_array[wIndex]);
 966                 if (temp == 0xffffffff) {
 967                         retval = -ENODEV;
 968                         break;
 969                 }
 970                 /* FIXME: What new port features do we need to support? */
 971                 temp = xhci_port_state_to_neutral(temp);
 972                 switch (wValue) {
 973                 case USB_PORT_FEAT_SUSPEND:
 974                         temp = readl(port_array[wIndex]);
 975                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
 976                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
 977                         if (temp & PORT_RESET)
 978                                 goto error;
 979                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
 980                                 if ((temp & PORT_PE) == 0)
 981                                         goto error;
 982
 983                                 xhci_set_link_state(xhci, port_array, wIndex,
 984                                                         XDEV_RESUME);
 985                                 spin_unlock_irqrestore(&xhci->lock, flags);
 986                                 msleep(20);
 987                                 spin_lock_irqsave(&xhci->lock, flags);
 988                                 xhci_set_link_state(xhci, port_array, wIndex,
 989                                                         XDEV_U0);
 990                         }
 991                         bus_state->port_c_suspend |= 1 << wIndex;
 992
 993                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 994                                         wIndex + 1);
 995                         if (!slot_id) {
 996                                 xhci_dbg(xhci, "slot_id is zero\n");
 997                                 goto error;
 998                         }
 999                         xhci_ring_device(xhci, slot_id);
1000                         break;
1001                 case USB_PORT_FEAT_C_SUSPEND:
1002                         bus_state->port_c_suspend &= ~(1 << wIndex);
1003                 case USB_PORT_FEAT_C_RESET:
1004                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1005                 case USB_PORT_FEAT_C_CONNECTION:
1006                 case USB_PORT_FEAT_C_OVER_CURRENT:
1007                 case USB_PORT_FEAT_C_ENABLE:
1008                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1009                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1010                                         port_array[wIndex], temp);
1011                         break;
1012                 case USB_PORT_FEAT_ENABLE:
1013                         xhci_disable_port(hcd, xhci, wIndex,
1014                                         port_array[wIndex], temp);
1015                         break;
1016                 case USB_PORT_FEAT_POWER:
1017                         writel(temp & ~PORT_POWER, port_array[wIndex]);
1018
1019                         spin_unlock_irqrestore(&xhci->lock, flags);
1020                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
1021                                         wIndex);
1022                         if (temp)
1023                                 usb_acpi_set_power_state(hcd->self.root_hub,
1024                                                 wIndex, false);
1025                         spin_lock_irqsave(&xhci->lock, flags);
1026                         break;
1027                 default:
1028                         goto error;
1029                 }
1030                 break;
1031         default:
1032 error:
1033                 /* "stall" on error */
1034                 retval = -EPIPE;
1035         }
1036         spin_unlock_irqrestore(&xhci->lock, flags);
1037         return retval;
1038 }
1039
1040 /*
1041  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1042  * Ports are 0-indexed from the HCD point of view,
1043  * and 1-indexed from the USB core pointer of view.
1044  *
1045  * Note that the status change bits will be cleared as soon as a port status
1046  * change event is generated, so we use the saved status from that event.
1047  */
1048 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1049 {
1050         unsigned long flags;
1051         u32 temp, status;
1052         u32 mask;
1053         int i, retval;
1054         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1055         int max_ports;
1056         __le32 __iomem **port_array;
1057         struct xhci_bus_state *bus_state;
1058         bool reset_change = false;
1059
1060         max_ports = xhci_get_ports(hcd, &port_array);
1061         bus_state = &xhci->bus_state[hcd_index(hcd)];
1062
1063         /* Initial status is no changes */
1064         retval = (max_ports + 8) / 8;
1065         memset(buf, 0, retval);
1066
1067         /*
1068          * Inform the usbcore about resume-in-progress by returning
1069          * a non-zero value even if there are no status changes.
1070          */
1071         status = bus_state->resuming_ports;
1072
1073         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
1074
1075         spin_lock_irqsave(&xhci->lock, flags);
1076         /* For each port, did anything change?  If so, set that bit in buf. */
1077         for (i = 0; i < max_ports; i++) {
1078                 temp = readl(port_array[i]);
1079                 if (temp == 0xffffffff) {
1080                         retval = -ENODEV;
1081                         break;
1082                 }
1083                 if ((temp & mask) != 0 ||
1084                         (bus_state->port_c_suspend & 1 << i) ||
1085                         (bus_state->resume_done[i] && time_after_eq(
1086                             jiffies, bus_state->resume_done[i]))) {
1087                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1088                         status = 1;
1089                 }
1090                 if ((temp & PORT_RC))
1091                         reset_change = true;
1092         }
1093         if (!status && !reset_change) {
1094                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1095                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1096         }
1097         spin_unlock_irqrestore(&xhci->lock, flags);
1098         return status ? retval : 0;
1099 }
1100
1101 #ifdef CONFIG_PM
1102
1103 int xhci_bus_suspend(struct usb_hcd *hcd)
1104 {
1105         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1106         int max_ports, port_index;
1107         __le32 __iomem **port_array;
1108         struct xhci_bus_state *bus_state;
1109         unsigned long flags;
1110
1111         max_ports = xhci_get_ports(hcd, &port_array);
1112         bus_state = &xhci->bus_state[hcd_index(hcd)];
1113
1114         spin_lock_irqsave(&xhci->lock, flags);
1115
1116         if (hcd->self.root_hub->do_remote_wakeup) {
1117                 if (bus_state->resuming_ports) {
1118                         spin_unlock_irqrestore(&xhci->lock, flags);
1119                         xhci_dbg(xhci, "suspend failed because "
1120                                                 "a port is resuming\n");
1121                         return -EBUSY;
1122                 }
1123         }
1124
1125         port_index = max_ports;
1126         bus_state->bus_suspended = 0;
1127         while (port_index--) {
1128                 /* suspend the port if the port is not suspended */
1129                 u32 t1, t2;
1130                 int slot_id;
1131
1132                 t1 = readl(port_array[port_index]);
1133                 t2 = xhci_port_state_to_neutral(t1);
1134
1135                 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1136                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1137                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1138                                         port_index + 1);
1139                         if (slot_id) {
1140                                 spin_unlock_irqrestore(&xhci->lock, flags);
1141                                 xhci_stop_device(xhci, slot_id, 1);
1142                                 spin_lock_irqsave(&xhci->lock, flags);
1143                         }
1144                         t2 &= ~PORT_PLS_MASK;
1145                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1146                         set_bit(port_index, &bus_state->bus_suspended);
1147                 }
1148                 /* USB core sets remote wake mask for USB 3.0 hubs,
1149                  * including the USB 3.0 roothub, but only if CONFIG_PM
1150                  * is enabled, so also enable remote wake here.
1151                  */
1152                 if (hcd->self.root_hub->do_remote_wakeup
1153                                 && device_may_wakeup(hcd->self.controller)) {
1154
1155                         if (t1 & PORT_CONNECT) {
1156                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1157                                 t2 &= ~PORT_WKCONN_E;
1158                         } else {
1159                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1160                                 t2 &= ~PORT_WKDISC_E;
1161                         }
1162                 } else
1163                         t2 &= ~PORT_WAKE_BITS;
1164
1165                 t1 = xhci_port_state_to_neutral(t1);
1166                 if (t1 != t2)
1167                         writel(t2, port_array[port_index]);
1168         }
1169         hcd->state = HC_STATE_SUSPENDED;
1170         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1171         spin_unlock_irqrestore(&xhci->lock, flags);
1172         return 0;
1173 }
1174
1175 int xhci_bus_resume(struct usb_hcd *hcd)
1176 {
1177         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1178         int max_ports, port_index;
1179         __le32 __iomem **port_array;
1180         struct xhci_bus_state *bus_state;
1181         u32 temp;
1182         unsigned long flags;
1183
1184         max_ports = xhci_get_ports(hcd, &port_array);
1185         bus_state = &xhci->bus_state[hcd_index(hcd)];
1186
1187         if (time_before(jiffies, bus_state->next_statechange))
1188                 msleep(5);
1189
1190         spin_lock_irqsave(&xhci->lock, flags);
1191         if (!HCD_HW_ACCESSIBLE(hcd)) {
1192                 spin_unlock_irqrestore(&xhci->lock, flags);
1193                 return -ESHUTDOWN;
1194         }
1195
1196         /* delay the irqs */
1197         temp = readl(&xhci->op_regs->command);
1198         temp &= ~CMD_EIE;
1199         writel(temp, &xhci->op_regs->command);
1200
1201         port_index = max_ports;
1202         while (port_index--) {
1203                 /* Check whether need resume ports. If needed
1204                    resume port and disable remote wakeup */
1205                 u32 temp;
1206                 int slot_id;
1207
1208                 temp = readl(port_array[port_index]);
1209                 if (DEV_SUPERSPEED(temp))
1210                         temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1211                 else
1212                         temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1213                 if (test_bit(port_index, &bus_state->bus_suspended) &&
1214                     (temp & PORT_PLS_MASK)) {
1215                         if (DEV_SUPERSPEED(temp)) {
1216                                 xhci_set_link_state(xhci, port_array,
1217                                                         port_index, XDEV_U0);
1218                         } else {
1219                                 xhci_set_link_state(xhci, port_array,
1220                                                 port_index, XDEV_RESUME);
1221
1222                                 spin_unlock_irqrestore(&xhci->lock, flags);
1223                                 msleep(20);
1224                                 spin_lock_irqsave(&xhci->lock, flags);
1225
1226                                 xhci_set_link_state(xhci, port_array,
1227                                                         port_index, XDEV_U0);
1228                         }
1229                         /* wait for the port to enter U0 and report port link
1230                          * state change.
1231                          */
1232                         spin_unlock_irqrestore(&xhci->lock, flags);
1233                         msleep(20);
1234                         spin_lock_irqsave(&xhci->lock, flags);
1235
1236                         /* Clear PLC */
1237                         xhci_test_and_clear_bit(xhci, port_array, port_index,
1238                                                 PORT_PLC);
1239
1240                         slot_id = xhci_find_slot_id_by_port(hcd,
1241                                         xhci, port_index + 1);
1242                         if (slot_id)
1243                                 xhci_ring_device(xhci, slot_id);
1244                 } else
1245                         writel(temp, port_array[port_index]);
1246         }
1247
1248         (void) readl(&xhci->op_regs->command);
1249
1250         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1251         /* re-enable irqs */
1252         temp = readl(&xhci->op_regs->command);
1253         temp |= CMD_EIE;
1254         writel(temp, &xhci->op_regs->command);
1255         temp = readl(&xhci->op_regs->command);
1256
1257         spin_unlock_irqrestore(&xhci->lock, flags);
1258         return 0;
1259 }
1260
1261 #endif  /* CONFIG_PM */