drivers/usb/host/ohci-hcd.c

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * [ Initialisation is based on Linus'  ]
   8  * [ uhci code and gregs ohci fragments ]
   9  * [ (C) Copyright 1999 Linus Torvalds  ]
  10  * [ (C) Copyright 1999 Gregory P. Smith]
  11  *
  12  *
  13  * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
  14  * interfaces (though some non-x86 Intel chips use it).  It supports
  15  * smarter hardware than UHCI.  A download link for the spec available
  16  * through the http://www.usb.org website.
  17  *
  18  * This file is licenced under the GPL.
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/pci.h>
  24 #include <linux/kernel.h>
  25 #include <linux/delay.h>
  26 #include <linux/ioport.h>
  27 #include <linux/sched.h>
  28 #include <linux/slab.h>
  29 #include <linux/errno.h>
  30 #include <linux/init.h>
  31 #include <linux/timer.h>
  32 #include <linux/list.h>
  33 #include <linux/usb.h>
  34 #include <linux/usb/otg.h>
  35 #include <linux/usb/hcd.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/dmapool.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/debugfs.h>
  40
  41 #include <asm/io.h>
  42 #include <asm/irq.h>
  43 #include <asm/system.h>
  44 #include <asm/unaligned.h>
  45 #include <asm/byteorder.h>
  46
  47
  48 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
  49 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
  50
  51 /*-------------------------------------------------------------------------*/
  52
  53 #undef OHCI_VERBOSE_DEBUG       /* not always helpful */
  54
  55 /* For initializing controller (mask in an HCFS mode too) */
  56 #define OHCI_CONTROL_INIT       OHCI_CTRL_CBSR
  57 #define OHCI_INTR_INIT \
  58                 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
  59                 | OHCI_INTR_RD | OHCI_INTR_WDH)
  60
  61 #ifdef __hppa__
  62 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
  63 #define IR_DISABLE
  64 #endif
  65
  66 #ifdef CONFIG_ARCH_OMAP
  67 /* OMAP doesn't support IR (no SMM; not needed) */
  68 #define IR_DISABLE
  69 #endif
  70
  71 /*-------------------------------------------------------------------------*/
  72
  73 static const char       hcd_name [] = "ohci_hcd";
  74
  75 #define STATECHANGE_DELAY       msecs_to_jiffies(300)
  76
  77 #include "ohci.h"
  78
  79 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
  80 static int ohci_init (struct ohci_hcd *ohci);
  81 static void ohci_stop (struct usb_hcd *hcd);
  82
  83 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
  84 static int ohci_restart (struct ohci_hcd *ohci);
  85 #endif
  86
  87 #ifdef CONFIG_PCI
  88 static void quirk_amd_pll(int state);
  89 static void amd_iso_dev_put(void);
  90 static void sb800_prefetch(struct ohci_hcd *ohci, int on);
  91 #else
  92 static inline void quirk_amd_pll(int state)
  93 {
  94         return;
  95 }
  96 static inline void amd_iso_dev_put(void)
  97 {
  98         return;
  99 }
 100 static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
 101 {
 102         return;
 103 }
 104 #endif
 105
 106
 107 #include "ohci-hub.c"
 108 #include "ohci-dbg.c"
 109 #include "ohci-mem.c"
 110 #include "ohci-q.c"
 111
 112
 113 /*
 114  * On architectures with edge-triggered interrupts we must never return
 115  * IRQ_NONE.
 116  */
 117 #if defined(CONFIG_SA1111)  /* ... or other edge-triggered systems */
 118 #define IRQ_NOTMINE     IRQ_HANDLED
 119 #else
 120 #define IRQ_NOTMINE     IRQ_NONE
 121 #endif
 122
 123
 124 /* Some boards misreport power switching/overcurrent */
 125 static int distrust_firmware = 1;
 126 module_param (distrust_firmware, bool, 0);
 127 MODULE_PARM_DESC (distrust_firmware,
 128         "true to distrust firmware power/overcurrent setup");
 129
 130 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
 131 static int no_handshake = 0;
 132 module_param (no_handshake, bool, 0);
 133 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
 134
 135 /*-------------------------------------------------------------------------*/
 136
 137 /*
 138  * queue up an urb for anything except the root hub
 139  */
 140 static int ohci_urb_enqueue (
 141         struct usb_hcd  *hcd,
 142         struct urb      *urb,
 143         gfp_t           mem_flags
 144 ) {
 145         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
 146         struct ed       *ed;
 147         urb_priv_t      *urb_priv;
 148         unsigned int    pipe = urb->pipe;
 149         int             i, size = 0;
 150         unsigned long   flags;
 151         int             retval = 0;
 152
 153 #ifdef OHCI_VERBOSE_DEBUG
 154         urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS);
 155 #endif
 156
 157         /* every endpoint has a ed, locate and maybe (re)initialize it */
 158         if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
 159                 return -ENOMEM;
 160
 161         /* for the private part of the URB we need the number of TDs (size) */
 162         switch (ed->type) {
 163                 case PIPE_CONTROL:
 164                         /* td_submit_urb() doesn't yet handle these */
 165                         if (urb->transfer_buffer_length > 4096)
 166                                 return -EMSGSIZE;
 167
 168                         /* 1 TD for setup, 1 for ACK, plus ... */
 169                         size = 2;
 170                         /* FALLTHROUGH */
 171                 // case PIPE_INTERRUPT:
 172                 // case PIPE_BULK:
 173                 default:
 174                         /* one TD for every 4096 Bytes (can be upto 8K) */
 175                         size += urb->transfer_buffer_length / 4096;
 176                         /* ... and for any remaining bytes ... */
 177                         if ((urb->transfer_buffer_length % 4096) != 0)
 178                                 size++;
 179                         /* ... and maybe a zero length packet to wrap it up */
 180                         if (size == 0)
 181                                 size++;
 182                         else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
 183                                 && (urb->transfer_buffer_length
 184                                         % usb_maxpacket (urb->dev, pipe,
 185                                                 usb_pipeout (pipe))) == 0)
 186                                 size++;
 187                         break;
 188                 case PIPE_ISOCHRONOUS: /* number of packets from URB */
 189                         size = urb->number_of_packets;
 190                         break;
 191         }
 192
 193         /* allocate the private part of the URB */
 194         urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
 195                         mem_flags);
 196         if (!urb_priv)
 197                 return -ENOMEM;
 198         INIT_LIST_HEAD (&urb_priv->pending);
 199         urb_priv->length = size;
 200         urb_priv->ed = ed;
 201
 202         /* allocate the TDs (deferring hash chain updates) */
 203         for (i = 0; i < size; i++) {
 204                 urb_priv->td [i] = td_alloc (ohci, mem_flags);
 205                 if (!urb_priv->td [i]) {
 206                         urb_priv->length = i;
 207                         urb_free_priv (ohci, urb_priv);
 208                         return -ENOMEM;
 209                 }
 210         }
 211
 212         spin_lock_irqsave (&ohci->lock, flags);
 213
 214         /* don't submit to a dead HC */
 215         if (!HCD_HW_ACCESSIBLE(hcd)) {
 216                 retval = -ENODEV;
 217                 goto fail;
 218         }
 219         if (!HC_IS_RUNNING(hcd->state)) {
 220                 retval = -ENODEV;
 221                 goto fail;
 222         }
 223         retval = usb_hcd_link_urb_to_ep(hcd, urb);
 224         if (retval)
 225                 goto fail;
 226
 227         /* schedule the ed if needed */
 228         if (ed->state == ED_IDLE) {
 229                 retval = ed_schedule (ohci, ed);
 230                 if (retval < 0) {
 231                         usb_hcd_unlink_urb_from_ep(hcd, urb);
 232                         goto fail;
 233                 }
 234                 if (ed->type == PIPE_ISOCHRONOUS) {
 235                         u16     frame = ohci_frame_no(ohci);
 236
 237                         /* delay a few frames before the first TD */
 238                         frame += max_t (u16, 8, ed->interval);
 239                         frame &= ~(ed->interval - 1);
 240                         frame |= ed->branch;
 241                         urb->start_frame = frame;
 242
 243                         /* yes, only URB_ISO_ASAP is supported, and
 244                          * urb->start_frame is never used as input.
 245                          */
 246                 }
 247         } else if (ed->type == PIPE_ISOCHRONOUS)
 248                 urb->start_frame = ed->last_iso + ed->interval;
 249
 250         /* fill the TDs and link them to the ed; and
 251          * enable that part of the schedule, if needed
 252          * and update count of queued periodic urbs
 253          */
 254         urb->hcpriv = urb_priv;
 255         td_submit_urb (ohci, urb);
 256
 257 fail:
 258         if (retval)
 259                 urb_free_priv (ohci, urb_priv);
 260         spin_unlock_irqrestore (&ohci->lock, flags);
 261         return retval;
 262 }
 263
 264 /*
 265  * decouple the URB from the HC queues (TDs, urb_priv).
 266  * reporting is always done
 267  * asynchronously, and we might be dealing with an urb that's
 268  * partially transferred, or an ED with other urbs being unlinked.
 269  */
 270 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
 271 {
 272         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 273         unsigned long           flags;
 274         int                     rc;
 275
 276 #ifdef OHCI_VERBOSE_DEBUG
 277         urb_print(urb, "UNLINK", 1, status);
 278 #endif
 279
 280         spin_lock_irqsave (&ohci->lock, flags);
 281         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
 282         if (rc) {
 283                 ;       /* Do nothing */
 284         } else if (HC_IS_RUNNING(hcd->state)) {
 285                 urb_priv_t  *urb_priv;
 286
 287                 /* Unless an IRQ completed the unlink while it was being
 288                  * handed to us, flag it for unlink and giveback, and force
 289                  * some upcoming INTR_SF to call finish_unlinks()
 290                  */
 291                 urb_priv = urb->hcpriv;
 292                 if (urb_priv) {
 293                         if (urb_priv->ed->state == ED_OPER)
 294                                 start_ed_unlink (ohci, urb_priv->ed);
 295                 }
 296         } else {
 297                 /*
 298                  * with HC dead, we won't respect hc queue pointers
 299                  * any more ... just clean up every urb's memory.
 300                  */
 301                 if (urb->hcpriv)
 302                         finish_urb(ohci, urb, status);
 303         }
 304         spin_unlock_irqrestore (&ohci->lock, flags);
 305         return rc;
 306 }
 307
 308 /*-------------------------------------------------------------------------*/
 309
 310 /* frees config/altsetting state for endpoints,
 311  * including ED memory, dummy TD, and bulk/intr data toggle
 312  */
 313
 314 static void
 315 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
 316 {
 317         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 318         unsigned long           flags;
 319         struct ed               *ed = ep->hcpriv;
 320         unsigned                limit = 1000;
 321
 322         /* ASSERT:  any requests/urbs are being unlinked */
 323         /* ASSERT:  nobody can be submitting urbs for this any more */
 324
 325         if (!ed)
 326                 return;
 327
 328 rescan:
 329         spin_lock_irqsave (&ohci->lock, flags);
 330
 331         if (!HC_IS_RUNNING (hcd->state)) {
 332 sanitize:
 333                 ed->state = ED_IDLE;
 334                 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
 335                         ohci->eds_scheduled--;
 336                 finish_unlinks (ohci, 0);
 337         }
 338
 339         switch (ed->state) {
 340         case ED_UNLINK:         /* wait for hw to finish? */
 341                 /* major IRQ delivery trouble loses INTR_SF too... */
 342                 if (limit-- == 0) {
 343                         ohci_warn(ohci, "ED unlink timeout\n");
 344                         if (quirk_zfmicro(ohci)) {
 345                                 ohci_warn(ohci, "Attempting ZF TD recovery\n");
 346                                 ohci->ed_to_check = ed;
 347                                 ohci->zf_delay = 2;
 348                         }
 349                         goto sanitize;
 350                 }
 351                 spin_unlock_irqrestore (&ohci->lock, flags);
 352                 schedule_timeout_uninterruptible(1);
 353                 goto rescan;
 354         case ED_IDLE:           /* fully unlinked */
 355                 if (list_empty (&ed->td_list)) {
 356                         td_free (ohci, ed->dummy);
 357                         ed_free (ohci, ed);
 358                         break;
 359                 }
 360                 /* else FALL THROUGH */
 361         default:
 362                 /* caller was supposed to have unlinked any requests;
 363                  * that's not our job.  can't recover; must leak ed.
 364                  */
 365                 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
 366                         ed, ep->desc.bEndpointAddress, ed->state,
 367                         list_empty (&ed->td_list) ? "" : " (has tds)");
 368                 td_free (ohci, ed->dummy);
 369                 break;
 370         }
 371         ep->hcpriv = NULL;
 372         spin_unlock_irqrestore (&ohci->lock, flags);
 373         return;
 374 }
 375
 376 static int ohci_get_frame (struct usb_hcd *hcd)
 377 {
 378         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 379
 380         return ohci_frame_no(ohci);
 381 }
 382
 383 static void ohci_usb_reset (struct ohci_hcd *ohci)
 384 {
 385         ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
 386         ohci->hc_control &= OHCI_CTRL_RWC;
 387         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 388 }
 389
 390 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
 391  * other cases where the next software may expect clean state from the
 392  * "firmware".  this is bus-neutral, unlike shutdown() methods.
 393  */
 394 static void
 395 ohci_shutdown (struct usb_hcd *hcd)
 396 {
 397         struct ohci_hcd *ohci;
 398
 399         ohci = hcd_to_ohci (hcd);
 400         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 401         ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
 402
 403         /* If the SHUTDOWN quirk is set, don't put the controller in RESET */
 404         ohci->hc_control &= (ohci->flags & OHCI_QUIRK_SHUTDOWN ?
 405                         OHCI_CTRL_RWC | OHCI_CTRL_HCFS :
 406                         OHCI_CTRL_RWC);
 407         ohci_writel(ohci, ohci->hc_control, &ohci->regs->control);
 408
 409         /* flush the writes */
 410         (void) ohci_readl (ohci, &ohci->regs->control);
 411 }
 412
 413 static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
 414 {
 415         return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
 416                 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
 417                         == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
 418                 && !list_empty(&ed->td_list);
 419 }
 420
 421 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
 422  * an interrupt TD but neglects to add it to the donelist.  On systems with
 423  * this chipset, we need to periodically check the state of the queues to look
 424  * for such "lost" TDs.
 425  */
 426 static void unlink_watchdog_func(unsigned long _ohci)
 427 {
 428         unsigned long   flags;
 429         unsigned        max;
 430         unsigned        seen_count = 0;
 431         unsigned        i;
 432         struct ed       **seen = NULL;
 433         struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
 434
 435         spin_lock_irqsave(&ohci->lock, flags);
 436         max = ohci->eds_scheduled;
 437         if (!max)
 438                 goto done;
 439
 440         if (ohci->ed_to_check)
 441                 goto out;
 442
 443         seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
 444         if (!seen)
 445                 goto out;
 446
 447         for (i = 0; i < NUM_INTS; i++) {
 448                 struct ed       *ed = ohci->periodic[i];
 449
 450                 while (ed) {
 451                         unsigned        temp;
 452
 453                         /* scan this branch of the periodic schedule tree */
 454                         for (temp = 0; temp < seen_count; temp++) {
 455                                 if (seen[temp] == ed) {
 456                                         /* we've checked it and what's after */
 457                                         ed = NULL;
 458                                         break;
 459                                 }
 460                         }
 461                         if (!ed)
 462                                 break;
 463                         seen[seen_count++] = ed;
 464                         if (!check_ed(ohci, ed)) {
 465                                 ed = ed->ed_next;
 466                                 continue;
 467                         }
 468
 469                         /* HC's TD list is empty, but HCD sees at least one
 470                          * TD that's not been sent through the donelist.
 471                          */
 472                         ohci->ed_to_check = ed;
 473                         ohci->zf_delay = 2;
 474
 475                         /* The HC may wait until the next frame to report the
 476                          * TD as done through the donelist and INTR_WDH.  (We
 477                          * just *assume* it's not a multi-TD interrupt URB;
 478                          * those could defer the IRQ more than one frame, using
 479                          * DI...)  Check again after the next INTR_SF.
 480                          */
 481                         ohci_writel(ohci, OHCI_INTR_SF,
 482                                         &ohci->regs->intrstatus);
 483                         ohci_writel(ohci, OHCI_INTR_SF,
 484                                         &ohci->regs->intrenable);
 485
 486                         /* flush those writes */
 487                         (void) ohci_readl(ohci, &ohci->regs->control);
 488
 489                         goto out;
 490                 }
 491         }
 492 out:
 493         kfree(seen);
 494         if (ohci->eds_scheduled)
 495                 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
 496 done:
 497         spin_unlock_irqrestore(&ohci->lock, flags);
 498 }
 499
 500 /*-------------------------------------------------------------------------*
 501  * HC functions
 502  *-------------------------------------------------------------------------*/
 503
 504 /* init memory, and kick BIOS/SMM off */
 505
 506 static int ohci_init (struct ohci_hcd *ohci)
 507 {
 508         int ret;
 509         struct usb_hcd *hcd = ohci_to_hcd(ohci);
 510
 511         if (distrust_firmware)
 512                 ohci->flags |= OHCI_QUIRK_HUB_POWER;
 513
 514         disable (ohci);
 515         ohci->regs = hcd->regs;
 516
 517         /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
 518          * was never needed for most non-PCI systems ... remove the code?
 519          */
 520
 521 #ifndef IR_DISABLE
 522         /* SMM owns the HC?  not for long! */
 523         if (!no_handshake && ohci_readl (ohci,
 524                                         &ohci->regs->control) & OHCI_CTRL_IR) {
 525                 u32 temp;
 526
 527                 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
 528
 529                 /* this timeout is arbitrary.  we make it long, so systems
 530                  * depending on usb keyboards may be usable even if the
 531                  * BIOS/SMM code seems pretty broken.
 532                  */
 533                 temp = 500;     /* arbitrary: five seconds */
 534
 535                 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
 536                 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
 537                 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
 538                         msleep (10);
 539                         if (--temp == 0) {
 540                                 ohci_err (ohci, "USB HC takeover failed!"
 541                                         "  (BIOS/SMM bug)\n");
 542                                 return -EBUSY;
 543                         }
 544                 }
 545                 ohci_usb_reset (ohci);
 546         }
 547 #endif
 548
 549         /* Disable HC interrupts */
 550         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 551
 552         /* flush the writes, and save key bits like RWC */
 553         if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
 554                 ohci->hc_control |= OHCI_CTRL_RWC;
 555
 556         /* Read the number of ports unless overridden */
 557         if (ohci->num_ports == 0)
 558                 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
 559
 560         if (ohci->hcca)
 561                 return 0;
 562
 563         ohci->hcca = dma_alloc_coherent (hcd->self.controller,
 564                         sizeof *ohci->hcca, &ohci->hcca_dma, 0);
 565         if (!ohci->hcca)
 566                 return -ENOMEM;
 567
 568         if ((ret = ohci_mem_init (ohci)) < 0)
 569                 ohci_stop (hcd);
 570         else {
 571                 create_debug_files (ohci);
 572         }
 573
 574         return ret;
 575 }
 576
 577 /*-------------------------------------------------------------------------*/
 578
 579 /* Start an OHCI controller, set the BUS operational
 580  * resets USB and controller
 581  * enable interrupts
 582  */
 583 static int ohci_run (struct ohci_hcd *ohci)
 584 {
 585         u32                     mask, val;
 586         int                     first = ohci->fminterval == 0;
 587         struct usb_hcd          *hcd = ohci_to_hcd(ohci);
 588
 589         disable (ohci);
 590
 591         /* boot firmware should have set this up (5.1.1.3.1) */
 592         if (first) {
 593
 594                 val = ohci_readl (ohci, &ohci->regs->fminterval);
 595                 ohci->fminterval = val & 0x3fff;
 596                 if (ohci->fminterval != FI)
 597                         ohci_dbg (ohci, "fminterval delta %d\n",
 598                                 ohci->fminterval - FI);
 599                 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
 600                 /* also: power/overcurrent flags in roothub.a */
 601         }
 602
 603         /* Reset USB nearly "by the book".  RemoteWakeupConnected has
 604          * to be checked in case boot firmware (BIOS/SMM/...) has set up
 605          * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
 606          * If the bus glue detected wakeup capability then it should
 607          * already be enabled; if so we'll just enable it again.
 608          */
 609         if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
 610                 device_set_wakeup_capable(hcd->self.controller, 1);
 611
 612         switch (ohci->hc_control & OHCI_CTRL_HCFS) {
 613         case OHCI_USB_OPER:
 614                 val = 0;
 615                 break;
 616         case OHCI_USB_SUSPEND:
 617         case OHCI_USB_RESUME:
 618                 ohci->hc_control &= OHCI_CTRL_RWC;
 619                 ohci->hc_control |= OHCI_USB_RESUME;
 620                 val = 10 /* msec wait */;
 621                 break;
 622         // case OHCI_USB_RESET:
 623         default:
 624                 ohci->hc_control &= OHCI_CTRL_RWC;
 625                 ohci->hc_control |= OHCI_USB_RESET;
 626                 val = 50 /* msec wait */;
 627                 break;
 628         }
 629         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 630         // flush the writes
 631         (void) ohci_readl (ohci, &ohci->regs->control);
 632         msleep(val);
 633
 634         memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
 635
 636         /* 2msec timelimit here means no irqs/preempt */
 637         spin_lock_irq (&ohci->lock);
 638
 639 retry:
 640         /* HC Reset requires max 10 us delay */
 641         ohci_writel (ohci, OHCI_HCR,  &ohci->regs->cmdstatus);
 642         val = 30;       /* ... allow extra time */
 643         while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
 644                 if (--val == 0) {
 645                         spin_unlock_irq (&ohci->lock);
 646                         ohci_err (ohci, "USB HC reset timed out!\n");
 647                         return -1;
 648                 }
 649                 udelay (1);
 650         }
 651
 652         /* now we're in the SUSPEND state ... must go OPERATIONAL
 653          * within 2msec else HC enters RESUME
 654          *
 655          * ... but some hardware won't init fmInterval "by the book"
 656          * (SiS, OPTi ...), so reset again instead.  SiS doesn't need
 657          * this if we write fmInterval after we're OPERATIONAL.
 658          * Unclear about ALi, ServerWorks, and others ... this could
 659          * easily be a longstanding bug in chip init on Linux.
 660          */
 661         if (ohci->flags & OHCI_QUIRK_INITRESET) {
 662                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 663                 // flush those writes
 664                 (void) ohci_readl (ohci, &ohci->regs->control);
 665         }
 666
 667         /* Tell the controller where the control and bulk lists are
 668          * The lists are empty now. */
 669         ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
 670         ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
 671
 672         /* a reset clears this */
 673         ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
 674
 675         periodic_reinit (ohci);
 676
 677         /* some OHCI implementations are finicky about how they init.
 678          * bogus values here mean not even enumeration could work.
 679          */
 680         if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
 681                         || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
 682                 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
 683                         ohci->flags |= OHCI_QUIRK_INITRESET;
 684                         ohci_dbg (ohci, "enabling initreset quirk\n");
 685                         goto retry;
 686                 }
 687                 spin_unlock_irq (&ohci->lock);
 688                 ohci_err (ohci, "init err (%08x %04x)\n",
 689                         ohci_readl (ohci, &ohci->regs->fminterval),
 690                         ohci_readl (ohci, &ohci->regs->periodicstart));
 691                 return -EOVERFLOW;
 692         }
 693
 694         /* use rhsc irqs after khubd is fully initialized */
 695         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 696         hcd->uses_new_polling = 1;
 697
 698         /* start controller operations */
 699         ohci->hc_control &= OHCI_CTRL_RWC;
 700         ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
 701         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 702         hcd->state = HC_STATE_RUNNING;
 703
 704         /* wake on ConnectStatusChange, matching external hubs */
 705         ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
 706
 707         /* Choose the interrupts we care about now, others later on demand */
 708         mask = OHCI_INTR_INIT;
 709         ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
 710         ohci_writel (ohci, mask, &ohci->regs->intrenable);
 711
 712         /* handle root hub init quirks ... */
 713         val = roothub_a (ohci);
 714         val &= ~(RH_A_PSM | RH_A_OCPM);
 715         if (ohci->flags & OHCI_QUIRK_SUPERIO) {
 716                 /* NSC 87560 and maybe others */
 717                 val |= RH_A_NOCP;
 718                 val &= ~(RH_A_POTPGT | RH_A_NPS);
 719                 ohci_writel (ohci, val, &ohci->regs->roothub.a);
 720         } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
 721                         (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
 722                 /* hub power always on; required for AMD-756 and some
 723                  * Mac platforms.  ganged overcurrent reporting, if any.
 724                  */
 725                 val |= RH_A_NPS;
 726                 ohci_writel (ohci, val, &ohci->regs->roothub.a);
 727         }
 728         ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
 729         ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
 730                                                 &ohci->regs->roothub.b);
 731         // flush those writes
 732         (void) ohci_readl (ohci, &ohci->regs->control);
 733
 734         ohci->next_statechange = jiffies + STATECHANGE_DELAY;
 735         spin_unlock_irq (&ohci->lock);
 736
 737         // POTPGT delay is bits 24-31, in 2 ms units.
 738         mdelay ((val >> 23) & 0x1fe);
 739         hcd->state = HC_STATE_RUNNING;
 740
 741         if (quirk_zfmicro(ohci)) {
 742                 /* Create timer to watch for bad queue state on ZF Micro */
 743                 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
 744                                 (unsigned long) ohci);
 745
 746                 ohci->eds_scheduled = 0;
 747                 ohci->ed_to_check = NULL;
 748         }
 749
 750         ohci_dump (ohci, 1);
 751
 752         return 0;
 753 }
 754
 755 /*-------------------------------------------------------------------------*/
 756
 757 /* an interrupt happens */
 758
 759 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
 760 {
 761         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 762         struct ohci_regs __iomem *regs = ohci->regs;
 763         int                     ints;
 764
 765         /* Read interrupt status (and flush pending writes).  We ignore the
 766          * optimization of checking the LSB of hcca->done_head; it doesn't
 767          * work on all systems (edge triggering for OHCI can be a factor).
 768          */
 769         ints = ohci_readl(ohci, &regs->intrstatus);
 770
 771         /* Check for an all 1's result which is a typical consequence
 772          * of dead, unclocked, or unplugged (CardBus...) devices
 773          */
 774         if (ints == ~(u32)0) {
 775                 disable (ohci);
 776                 ohci_dbg (ohci, "device removed!\n");
 777                 return IRQ_HANDLED;
 778         }
 779
 780         /* We only care about interrupts that are enabled */
 781         ints &= ohci_readl(ohci, &regs->intrenable);
 782
 783         /* interrupt for some other device? */
 784         if (ints == 0)
 785                 return IRQ_NOTMINE;
 786
 787         if (ints & OHCI_INTR_UE) {
 788                 // e.g. due to PCI Master/Target Abort
 789                 if (quirk_nec(ohci)) {
 790                         /* Workaround for a silicon bug in some NEC chips used
 791                          * in Apple's PowerBooks. Adapted from Darwin code.
 792                          */
 793                         ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
 794
 795                         ohci_writel (ohci, OHCI_INTR_UE, &regs->intrdisable);
 796
 797                         schedule_work (&ohci->nec_work);
 798                 } else {
 799                         disable (ohci);
 800                         ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
 801                 }
 802
 803                 ohci_dump (ohci, 1);
 804                 ohci_usb_reset (ohci);
 805         }
 806
 807         if (ints & OHCI_INTR_RHSC) {
 808                 ohci_vdbg(ohci, "rhsc\n");
 809                 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
 810                 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
 811                                 &regs->intrstatus);
 812
 813                 /* NOTE: Vendors didn't always make the same implementation
 814                  * choices for RHSC.  Many followed the spec; RHSC triggers
 815                  * on an edge, like setting and maybe clearing a port status
 816                  * change bit.  With others it's level-triggered, active
 817                  * until khubd clears all the port status change bits.  We'll
 818                  * always disable it here and rely on polling until khubd
 819                  * re-enables it.
 820                  */
 821                 ohci_writel(ohci, OHCI_INTR_RHSC, &regs->intrdisable);
 822                 usb_hcd_poll_rh_status(hcd);
 823         }
 824
 825         /* For connect and disconnect events, we expect the controller
 826          * to turn on RHSC along with RD.  But for remote wakeup events
 827          * this might not happen.
 828          */
 829         else if (ints & OHCI_INTR_RD) {
 830                 ohci_vdbg(ohci, "resume detect\n");
 831                 ohci_writel(ohci, OHCI_INTR_RD, &regs->intrstatus);
 832                 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 833                 if (ohci->autostop) {
 834                         spin_lock (&ohci->lock);
 835                         ohci_rh_resume (ohci);
 836                         spin_unlock (&ohci->lock);
 837                 } else
 838                         usb_hcd_resume_root_hub(hcd);
 839         }
 840
 841         if (ints & OHCI_INTR_WDH) {
 842                 spin_lock (&ohci->lock);
 843                 dl_done_list (ohci);
 844                 spin_unlock (&ohci->lock);
 845         }
 846
 847         if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
 848                 spin_lock(&ohci->lock);
 849                 if (ohci->ed_to_check) {
 850                         struct ed *ed = ohci->ed_to_check;
 851
 852                         if (check_ed(ohci, ed)) {
 853                                 /* HC thinks the TD list is empty; HCD knows
 854                                  * at least one TD is outstanding
 855                                  */
 856                                 if (--ohci->zf_delay == 0) {
 857                                         struct td *td = list_entry(
 858                                                 ed->td_list.next,
 859                                                 struct td, td_list);
 860                                         ohci_warn(ohci,
 861                                                   "Reclaiming orphan TD %p\n",
 862                                                   td);
 863                                         takeback_td(ohci, td);
 864                                         ohci->ed_to_check = NULL;
 865                                 }
 866                         } else
 867                                 ohci->ed_to_check = NULL;
 868                 }
 869                 spin_unlock(&ohci->lock);
 870         }
 871
 872         /* could track INTR_SO to reduce available PCI/... bandwidth */
 873
 874         /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
 875          * when there's still unlinking to be done (next frame).
 876          */
 877         spin_lock (&ohci->lock);
 878         if (ohci->ed_rm_list)
 879                 finish_unlinks (ohci, ohci_frame_no(ohci));
 880         if ((ints & OHCI_INTR_SF) != 0
 881                         && !ohci->ed_rm_list
 882                         && !ohci->ed_to_check
 883                         && HC_IS_RUNNING(hcd->state))
 884                 ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
 885         spin_unlock (&ohci->lock);
 886
 887         if (HC_IS_RUNNING(hcd->state)) {
 888                 ohci_writel (ohci, ints, &regs->intrstatus);
 889                 ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
 890                 // flush those writes
 891                 (void) ohci_readl (ohci, &ohci->regs->control);
 892         }
 893
 894         return IRQ_HANDLED;
 895 }
 896
 897 /*-------------------------------------------------------------------------*/
 898
 899 static void ohci_stop (struct usb_hcd *hcd)
 900 {
 901         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 902
 903         ohci_dump (ohci, 1);
 904
 905         flush_scheduled_work();
 906
 907         ohci_usb_reset (ohci);
 908         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 909         free_irq(hcd->irq, hcd);
 910         hcd->irq = -1;
 911
 912         if (quirk_zfmicro(ohci))
 913                 del_timer(&ohci->unlink_watchdog);
 914         if (quirk_amdiso(ohci))
 915                 amd_iso_dev_put();
 916
 917         remove_debug_files (ohci);
 918         ohci_mem_cleanup (ohci);
 919         if (ohci->hcca) {
 920                 dma_free_coherent (hcd->self.controller,
 921                                 sizeof *ohci->hcca,
 922                                 ohci->hcca, ohci->hcca_dma);
 923                 ohci->hcca = NULL;
 924                 ohci->hcca_dma = 0;
 925         }
 926 }
 927
 928 /*-------------------------------------------------------------------------*/
 929
 930 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
 931
 932 /* must not be called from interrupt context */
 933 static int ohci_restart (struct ohci_hcd *ohci)
 934 {
 935         int temp;
 936         int i;
 937         struct urb_priv *priv;
 938
 939         spin_lock_irq(&ohci->lock);
 940         disable (ohci);
 941
 942         /* Recycle any "live" eds/tds (and urbs). */
 943         if (!list_empty (&ohci->pending))
 944                 ohci_dbg(ohci, "abort schedule...\n");
 945         list_for_each_entry (priv, &ohci->pending, pending) {
 946                 struct urb      *urb = priv->td[0]->urb;
 947                 struct ed       *ed = priv->ed;
 948
 949                 switch (ed->state) {
 950                 case ED_OPER:
 951                         ed->state = ED_UNLINK;
 952                         ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
 953                         ed_deschedule (ohci, ed);
 954
 955                         ed->ed_next = ohci->ed_rm_list;
 956                         ed->ed_prev = NULL;
 957                         ohci->ed_rm_list = ed;
 958                         /* FALLTHROUGH */
 959                 case ED_UNLINK:
 960                         break;
 961                 default:
 962                         ohci_dbg(ohci, "bogus ed %p state %d\n",
 963                                         ed, ed->state);
 964                 }
 965
 966                 if (!urb->unlinked)
 967                         urb->unlinked = -ESHUTDOWN;
 968         }
 969         finish_unlinks (ohci, 0);
 970         spin_unlock_irq(&ohci->lock);
 971
 972         /* paranoia, in case that didn't work: */
 973
 974         /* empty the interrupt branches */
 975         for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
 976         for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
 977
 978         /* no EDs to remove */
 979         ohci->ed_rm_list = NULL;
 980
 981         /* empty control and bulk lists */
 982         ohci->ed_controltail = NULL;
 983         ohci->ed_bulktail    = NULL;
 984
 985         if ((temp = ohci_run (ohci)) < 0) {
 986                 ohci_err (ohci, "can't restart, %d\n", temp);
 987                 return temp;
 988         }
 989         ohci_dbg(ohci, "restart complete\n");
 990         return 0;
 991 }
 992
 993 #endif
 994
 995 /*-------------------------------------------------------------------------*/
 996
 997 MODULE_AUTHOR (DRIVER_AUTHOR);
 998 MODULE_DESCRIPTION(DRIVER_DESC);
 999 MODULE_LICENSE ("GPL");
1000
1001 #ifdef CONFIG_PCI
1002 #include "ohci-pci.c"
1003 #define PCI_DRIVER              ohci_pci_driver
1004 #endif
1005
1006 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1007 #include "ohci-sa1111.c"
1008 #define SA1111_DRIVER           ohci_hcd_sa1111_driver
1009 #endif
1010
1011 #if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX)
1012 #include "ohci-s3c2410.c"
1013 #define PLATFORM_DRIVER         ohci_hcd_s3c2410_driver
1014 #endif
1015
1016 #ifdef CONFIG_USB_OHCI_HCD_OMAP1
1017 #include "ohci-omap.c"
1018 #define OMAP1_PLATFORM_DRIVER   ohci_hcd_omap_driver
1019 #endif
1020
1021 #ifdef CONFIG_USB_OHCI_HCD_OMAP3
1022 #include "ohci-omap3.c"
1023 #define OMAP3_PLATFORM_DRIVER   ohci_hcd_omap3_driver
1024 #endif
1025
1026 #ifdef CONFIG_ARCH_LH7A404
1027 #include "ohci-lh7a404.c"
1028 #define PLATFORM_DRIVER         ohci_hcd_lh7a404_driver
1029 #endif
1030
1031 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1032 #include "ohci-pxa27x.c"
1033 #define PLATFORM_DRIVER         ohci_hcd_pxa27x_driver
1034 #endif
1035
1036 #ifdef CONFIG_ARCH_EP93XX
1037 #include "ohci-ep93xx.c"
1038 #define PLATFORM_DRIVER         ohci_hcd_ep93xx_driver
1039 #endif
1040
1041 #ifdef CONFIG_MIPS_ALCHEMY
1042 #include "ohci-au1xxx.c"
1043 #define PLATFORM_DRIVER         ohci_hcd_au1xxx_driver
1044 #endif
1045
1046 #ifdef CONFIG_PNX8550
1047 #include "ohci-pnx8550.c"
1048 #define PLATFORM_DRIVER         ohci_hcd_pnx8550_driver
1049 #endif
1050
1051 #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
1052 #include "ohci-ppc-soc.c"
1053 #define PLATFORM_DRIVER         ohci_hcd_ppc_soc_driver
1054 #endif
1055
1056 #ifdef CONFIG_ARCH_AT91
1057 #include "ohci-at91.c"
1058 #define PLATFORM_DRIVER         ohci_hcd_at91_driver
1059 #endif
1060
1061 #ifdef CONFIG_ARCH_PNX4008
1062 #include "ohci-pnx4008.c"
1063 #define PLATFORM_DRIVER         usb_hcd_pnx4008_driver
1064 #endif
1065
1066 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
1067 #include "ohci-da8xx.c"
1068 #define PLATFORM_DRIVER         ohci_hcd_da8xx_driver
1069 #endif
1070
1071 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
1072     defined(CONFIG_CPU_SUBTYPE_SH7721) || \
1073     defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1074     defined(CONFIG_CPU_SUBTYPE_SH7786)
1075 #include "ohci-sh.c"
1076 #define PLATFORM_DRIVER         ohci_hcd_sh_driver
1077 #endif
1078
1079
1080 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1081 #include "ohci-ppc-of.c"
1082 #define OF_PLATFORM_DRIVER      ohci_hcd_ppc_of_driver
1083 #endif
1084
1085 #ifdef CONFIG_PPC_PS3
1086 #include "ohci-ps3.c"
1087 #define PS3_SYSTEM_BUS_DRIVER   ps3_ohci_driver
1088 #endif
1089
1090 #ifdef CONFIG_USB_OHCI_HCD_SSB
1091 #include "ohci-ssb.c"
1092 #define SSB_OHCI_DRIVER         ssb_ohci_driver
1093 #endif
1094
1095 #ifdef CONFIG_MFD_SM501
1096 #include "ohci-sm501.c"
1097 #define SM501_OHCI_DRIVER       ohci_hcd_sm501_driver
1098 #endif
1099
1100 #ifdef CONFIG_MFD_TC6393XB
1101 #include "ohci-tmio.c"
1102 #define TMIO_OHCI_DRIVER        ohci_hcd_tmio_driver
1103 #endif
1104
1105 #ifdef CONFIG_MACH_JZ4740
1106 #include "ohci-jz4740.c"
1107 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1108 #endif
1109
1110 #if     !defined(PCI_DRIVER) &&         \
1111         !defined(PLATFORM_DRIVER) &&    \
1112         !defined(OMAP1_PLATFORM_DRIVER) &&      \
1113         !defined(OMAP3_PLATFORM_DRIVER) &&      \
1114         !defined(OF_PLATFORM_DRIVER) && \
1115         !defined(SA1111_DRIVER) &&      \
1116         !defined(PS3_SYSTEM_BUS_DRIVER) && \
1117         !defined(SM501_OHCI_DRIVER) && \
1118         !defined(TMIO_OHCI_DRIVER) && \
1119         !defined(SSB_OHCI_DRIVER)
1120 #error "missing bus glue for ohci-hcd"
1121 #endif
1122
1123 static int __init ohci_hcd_mod_init(void)
1124 {
1125         int retval = 0;
1126
1127         if (usb_disabled())
1128                 return -ENODEV;
1129
1130         printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1131         pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1132                 sizeof (struct ed), sizeof (struct td));
1133         set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1134
1135 #ifdef DEBUG
1136         ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1137         if (!ohci_debug_root) {
1138                 retval = -ENOENT;
1139                 goto error_debug;
1140         }
1141 #endif
1142
1143 #ifdef PS3_SYSTEM_BUS_DRIVER
1144         retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1145         if (retval < 0)
1146                 goto error_ps3;
1147 #endif
1148
1149 #ifdef PLATFORM_DRIVER
1150         retval = platform_driver_register(&PLATFORM_DRIVER);
1151         if (retval < 0)
1152                 goto error_platform;
1153 #endif
1154
1155 #ifdef OMAP1_PLATFORM_DRIVER
1156         retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER);
1157         if (retval < 0)
1158                 goto error_omap1_platform;
1159 #endif
1160
1161 #ifdef OMAP3_PLATFORM_DRIVER
1162         retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER);
1163         if (retval < 0)
1164                 goto error_omap3_platform;
1165 #endif
1166
1167 #ifdef OF_PLATFORM_DRIVER
1168         retval = of_register_platform_driver(&OF_PLATFORM_DRIVER);
1169         if (retval < 0)
1170                 goto error_of_platform;
1171 #endif
1172
1173 #ifdef SA1111_DRIVER
1174         retval = sa1111_driver_register(&SA1111_DRIVER);
1175         if (retval < 0)
1176                 goto error_sa1111;
1177 #endif
1178
1179 #ifdef PCI_DRIVER
1180         retval = pci_register_driver(&PCI_DRIVER);
1181         if (retval < 0)
1182                 goto error_pci;
1183 #endif
1184
1185 #ifdef SSB_OHCI_DRIVER
1186         retval = ssb_driver_register(&SSB_OHCI_DRIVER);
1187         if (retval)
1188                 goto error_ssb;
1189 #endif
1190
1191 #ifdef SM501_OHCI_DRIVER
1192         retval = platform_driver_register(&SM501_OHCI_DRIVER);
1193         if (retval < 0)
1194                 goto error_sm501;
1195 #endif
1196
1197 #ifdef TMIO_OHCI_DRIVER
1198         retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1199         if (retval < 0)
1200                 goto error_tmio;
1201 #endif
1202
1203         return retval;
1204
1205         /* Error path */
1206 #ifdef TMIO_OHCI_DRIVER
1207         platform_driver_unregister(&TMIO_OHCI_DRIVER);
1208  error_tmio:
1209 #endif
1210 #ifdef SM501_OHCI_DRIVER
1211         platform_driver_unregister(&SM501_OHCI_DRIVER);
1212  error_sm501:
1213 #endif
1214 #ifdef SSB_OHCI_DRIVER
1215         ssb_driver_unregister(&SSB_OHCI_DRIVER);
1216  error_ssb:
1217 #endif
1218 #ifdef PCI_DRIVER
1219         pci_unregister_driver(&PCI_DRIVER);
1220  error_pci:
1221 #endif
1222 #ifdef SA1111_DRIVER
1223         sa1111_driver_unregister(&SA1111_DRIVER);
1224  error_sa1111:
1225 #endif
1226 #ifdef OF_PLATFORM_DRIVER
1227         of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1228  error_of_platform:
1229 #endif
1230 #ifdef PLATFORM_DRIVER
1231         platform_driver_unregister(&PLATFORM_DRIVER);
1232  error_platform:
1233 #endif
1234 #ifdef OMAP1_PLATFORM_DRIVER
1235         platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1236  error_omap1_platform:
1237 #endif
1238 #ifdef OMAP3_PLATFORM_DRIVER
1239         platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1240  error_omap3_platform:
1241 #endif
1242 #ifdef PS3_SYSTEM_BUS_DRIVER
1243         ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1244  error_ps3:
1245 #endif
1246 #ifdef DEBUG
1247         debugfs_remove(ohci_debug_root);
1248         ohci_debug_root = NULL;
1249  error_debug:
1250 #endif
1251
1252         clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1253         return retval;
1254 }
1255 module_init(ohci_hcd_mod_init);
1256
1257 static void __exit ohci_hcd_mod_exit(void)
1258 {
1259 #ifdef TMIO_OHCI_DRIVER
1260         platform_driver_unregister(&TMIO_OHCI_DRIVER);
1261 #endif
1262 #ifdef SM501_OHCI_DRIVER
1263         platform_driver_unregister(&SM501_OHCI_DRIVER);
1264 #endif
1265 #ifdef SSB_OHCI_DRIVER
1266         ssb_driver_unregister(&SSB_OHCI_DRIVER);
1267 #endif
1268 #ifdef PCI_DRIVER
1269         pci_unregister_driver(&PCI_DRIVER);
1270 #endif
1271 #ifdef SA1111_DRIVER
1272         sa1111_driver_unregister(&SA1111_DRIVER);
1273 #endif
1274 #ifdef OF_PLATFORM_DRIVER
1275         of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1276 #endif
1277 #ifdef PLATFORM_DRIVER
1278         platform_driver_unregister(&PLATFORM_DRIVER);
1279 #endif
1280 #ifdef OMAP3_PLATFORM_DRIVER
1281         platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1282 #endif
1283 #ifdef PS3_SYSTEM_BUS_DRIVER
1284         ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1285 #endif
1286 #ifdef DEBUG
1287         debugfs_remove(ohci_debug_root);
1288 #endif
1289         clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1290 }
1291 module_exit(ohci_hcd_mod_exit);
1292