2 * Copyright (c) 2001-2002 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #ifndef __LINUX_EHCI_HCD_H
20 #define __LINUX_EHCI_HCD_H
22 /* definitions used for the EHCI driver */
25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
27 * the host controller implementation.
29 * To facilitate the strongest possible byte-order checking from "sparse"
30 * and so on, we use __leXX unless that's not practical.
32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33 typedef __u32 __bitwise __hc32;
34 typedef __u16 __bitwise __hc16;
40 /* statistics can be kept for tuning/monitoring */
45 unsigned long reclaim;
46 unsigned long lost_iaa;
48 /* termination of urbs from core */
49 unsigned long complete;
53 /* ehci_hcd->lock guards shared data against other CPUs:
54 * ehci_hcd: async, reclaim, periodic (and shadow), ...
55 * usb_host_endpoint: hcpriv
56 * ehci_qh: qh_next, qtd_list
59 * Also, hold this lock when talking to HC registers or
60 * when updating hw_* fields in shared qh/qtd/... structures.
63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
71 struct ehci_hcd { /* one per controller */
72 /* glue to PCI and HCD framework */
73 struct ehci_caps __iomem *caps;
74 struct ehci_regs __iomem *regs;
75 struct ehci_dbg_port __iomem *debug;
77 __u32 hcs_params; /* cached register copy */
79 enum ehci_rh_state rh_state;
81 /* async schedule support */
82 struct ehci_qh *async;
83 struct ehci_qh *dummy; /* For AMD quirk use */
84 struct ehci_qh *reclaim;
85 struct ehci_qh *qh_scan_next;
86 unsigned scanning : 1;
88 /* periodic schedule support */
89 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
90 unsigned periodic_size;
91 __hc32 *periodic; /* hw periodic table */
92 dma_addr_t periodic_dma;
93 unsigned i_thresh; /* uframes HC might cache */
95 union ehci_shadow *pshadow; /* mirror hw periodic table */
96 int next_uframe; /* scan periodic, start here */
97 unsigned periodic_sched; /* periodic activity count */
98 unsigned uframe_periodic_max; /* max periodic time per uframe */
101 /* list of itds & sitds completed while clock_frame was still active */
102 struct list_head cached_itd_list;
103 struct list_head cached_sitd_list;
104 unsigned clock_frame;
106 /* per root hub port */
107 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
109 /* bit vectors (one bit per port) */
110 unsigned long bus_suspended; /* which ports were
111 already suspended at the start of a bus suspend */
112 unsigned long companion_ports; /* which ports are
113 dedicated to the companion controller */
114 unsigned long owned_ports; /* which ports are
115 owned by the companion during a bus suspend */
116 unsigned long port_c_suspend; /* which ports have
117 the change-suspend feature turned on */
118 unsigned long suspended_ports; /* which ports are
121 /* per-HC memory pools (could be per-bus, but ...) */
122 struct dma_pool *qh_pool; /* qh per active urb */
123 struct dma_pool *qtd_pool; /* one or more per qh */
124 struct dma_pool *itd_pool; /* itd per iso urb */
125 struct dma_pool *sitd_pool; /* sitd per split iso urb */
127 struct timer_list iaa_watchdog;
128 struct timer_list watchdog;
129 unsigned long actions;
130 unsigned periodic_stamp;
131 unsigned random_frame;
132 unsigned long next_statechange;
133 ktime_t last_periodic_enable;
137 unsigned no_selective_suspend:1;
138 unsigned has_fsl_port_bug:1; /* FreeScale */
139 unsigned big_endian_mmio:1;
140 unsigned big_endian_desc:1;
141 unsigned big_endian_capbase:1;
142 unsigned has_amcc_usb23:1;
143 unsigned need_io_watchdog:1;
144 unsigned broken_periodic:1;
145 unsigned amd_pll_fix:1;
146 unsigned fs_i_thresh:1; /* Intel iso scheduling */
147 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/
148 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */
149 unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */
150 unsigned imx28_write_fix:1; /* For Freescale i.MX28 */
152 /* required for usb32 quirk */
153 #define OHCI_CTRL_HCFS (3 << 6)
154 #define OHCI_USB_OPER (2 << 6)
155 #define OHCI_USB_SUSPEND (3 << 6)
157 #define OHCI_HCCTRL_OFFSET 0x4
158 #define OHCI_HCCTRL_LEN 0x4
159 __hc32 *ohci_hcctrl_reg;
160 unsigned has_hostpc:1;
161 unsigned has_lpm:1; /* support link power management */
162 unsigned has_ppcd:1; /* support per-port change bits */
163 u8 sbrn; /* packed release number */
167 struct ehci_stats stats;
168 # define COUNT(x) do { (x)++; } while (0)
170 # define COUNT(x) do {} while (0)
175 struct dentry *debug_dir;
178 * OTG controllers and transceivers need software interaction
180 struct otg_transceiver *transceiver;
183 /* convert between an HCD pointer and the corresponding EHCI_HCD */
184 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
186 return (struct ehci_hcd *) (hcd->hcd_priv);
188 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
190 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
195 iaa_watchdog_start(struct ehci_hcd *ehci)
197 WARN_ON(timer_pending(&ehci->iaa_watchdog));
198 mod_timer(&ehci->iaa_watchdog,
199 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
202 static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
204 del_timer(&ehci->iaa_watchdog);
207 enum ehci_timer_action {
214 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
216 clear_bit (action, &ehci->actions);
219 static void free_cached_lists(struct ehci_hcd *ehci);
221 /*-------------------------------------------------------------------------*/
223 #include <linux/usb/ehci_def.h>
225 /*-------------------------------------------------------------------------*/
227 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
230 * EHCI Specification 0.95 Section 3.5
231 * QTD: describe data transfer components (buffer, direction, ...)
232 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
234 * These are associated only with "QH" (Queue Head) structures,
235 * used with control, bulk, and interrupt transfers.
238 /* first part defined by EHCI spec */
239 __hc32 hw_next; /* see EHCI 3.5.1 */
240 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
241 __hc32 hw_token; /* see EHCI 3.5.3 */
242 #define QTD_TOGGLE (1 << 31) /* data toggle */
243 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
244 #define QTD_IOC (1 << 15) /* interrupt on complete */
245 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
246 #define QTD_PID(tok) (((tok)>>8) & 0x3)
247 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
248 #define QTD_STS_HALT (1 << 6) /* halted on error */
249 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
250 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
251 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
252 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
253 #define QTD_STS_STS (1 << 1) /* split transaction state */
254 #define QTD_STS_PING (1 << 0) /* issue PING? */
256 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
257 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
258 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
260 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */
261 __hc32 hw_buf_hi [5]; /* Appendix B */
263 /* the rest is HCD-private */
264 dma_addr_t qtd_dma; /* qtd address */
265 struct list_head qtd_list; /* sw qtd list */
266 struct urb *urb; /* qtd's urb */
267 size_t length; /* length of buffer */
268 } __attribute__ ((aligned (32)));
270 /* mask NakCnt+T in qh->hw_alt_next */
271 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
273 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
275 /*-------------------------------------------------------------------------*/
277 /* type tag from {qh,itd,sitd,fstn}->hw_next */
278 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
281 * Now the following defines are not converted using the
282 * cpu_to_le32() macro anymore, since we have to support
283 * "dynamic" switching between be and le support, so that the driver
284 * can be used on one system with SoC EHCI controller using big-endian
285 * descriptors as well as a normal little-endian PCI EHCI controller.
287 /* values for that type tag */
288 #define Q_TYPE_ITD (0 << 1)
289 #define Q_TYPE_QH (1 << 1)
290 #define Q_TYPE_SITD (2 << 1)
291 #define Q_TYPE_FSTN (3 << 1)
293 /* next async queue entry, or pointer to interrupt/periodic QH */
294 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
296 /* for periodic/async schedules and qtd lists, mark end of list */
297 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
300 * Entries in periodic shadow table are pointers to one of four kinds
301 * of data structure. That's dictated by the hardware; a type tag is
302 * encoded in the low bits of the hardware's periodic schedule. Use
303 * Q_NEXT_TYPE to get the tag.
305 * For entries in the async schedule, the type tag always says "qh".
308 struct ehci_qh *qh; /* Q_TYPE_QH */
309 struct ehci_itd *itd; /* Q_TYPE_ITD */
310 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
311 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
312 __hc32 *hw_next; /* (all types) */
316 /*-------------------------------------------------------------------------*/
319 * EHCI Specification 0.95 Section 3.6
320 * QH: describes control/bulk/interrupt endpoints
321 * See Fig 3-7 "Queue Head Structure Layout".
323 * These appear in both the async and (for interrupt) periodic schedules.
326 /* first part defined by EHCI spec */
328 __hc32 hw_next; /* see EHCI 3.6.1 */
329 __hc32 hw_info1; /* see EHCI 3.6.2 */
330 #define QH_HEAD 0x00008000
331 __hc32 hw_info2; /* see EHCI 3.6.2 */
332 #define QH_SMASK 0x000000ff
333 #define QH_CMASK 0x0000ff00
334 #define QH_HUBADDR 0x007f0000
335 #define QH_HUBPORT 0x3f800000
336 #define QH_MULT 0xc0000000
337 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
339 /* qtd overlay (hardware parts of a struct ehci_qtd) */
344 __hc32 hw_buf_hi [5];
345 } __attribute__ ((aligned(32)));
348 struct ehci_qh_hw *hw;
349 /* the rest is HCD-private */
350 dma_addr_t qh_dma; /* address of qh */
351 union ehci_shadow qh_next; /* ptr to qh; or periodic */
352 struct list_head qtd_list; /* sw qtd list */
353 struct ehci_qtd *dummy;
354 struct ehci_qh *reclaim; /* next to reclaim */
356 struct ehci_hcd *ehci;
357 unsigned long unlink_time;
360 * Do NOT use atomic operations for QH refcounting. On some CPUs
361 * (PPC7448 for example), atomic operations cannot be performed on
362 * memory that is cache-inhibited (i.e. being used for DMA).
363 * Spinlocks are used to protect all QH fields.
368 u8 needs_rescan; /* Dequeue during giveback */
370 #define QH_STATE_LINKED 1 /* HC sees this */
371 #define QH_STATE_UNLINK 2 /* HC may still see this */
372 #define QH_STATE_IDLE 3 /* HC doesn't see this */
373 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
374 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
376 u8 xacterrs; /* XactErr retry counter */
377 #define QH_XACTERR_MAX 32 /* XactErr retry limit */
379 /* periodic schedule info */
380 u8 usecs; /* intr bandwidth */
381 u8 gap_uf; /* uframes split/csplit gap */
382 u8 c_usecs; /* ... split completion bw */
383 u16 tt_usecs; /* tt downstream bandwidth */
384 unsigned short period; /* polling interval */
385 unsigned short start; /* where polling starts */
386 #define NO_FRAME ((unsigned short)~0) /* pick new start */
388 struct usb_device *dev; /* access to TT */
389 unsigned is_out:1; /* bulk or intr OUT */
390 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
393 /*-------------------------------------------------------------------------*/
395 /* description of one iso transaction (up to 3 KB data if highspeed) */
396 struct ehci_iso_packet {
397 /* These will be copied to iTD when scheduling */
398 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
399 __hc32 transaction; /* itd->hw_transaction[i] |= */
400 u8 cross; /* buf crosses pages */
401 /* for full speed OUT splits */
405 /* temporary schedule data for packets from iso urbs (both speeds)
406 * each packet is one logical usb transaction to the device (not TT),
407 * beginning at stream->next_uframe
409 struct ehci_iso_sched {
410 struct list_head td_list;
412 struct ehci_iso_packet packet [0];
416 * ehci_iso_stream - groups all (s)itds for this endpoint.
417 * acts like a qh would, if EHCI had them for ISO.
419 struct ehci_iso_stream {
420 /* first field matches ehci_hq, but is NULL */
421 struct ehci_qh_hw *hw;
426 struct list_head td_list; /* queued itds/sitds */
427 struct list_head free_list; /* list of unused itds/sitds */
428 struct usb_device *udev;
429 struct usb_host_endpoint *ep;
431 /* output of (re)scheduling */
435 /* the rest is derived from the endpoint descriptor,
436 * trusting urb->interval == f(epdesc->bInterval) and
437 * including the extra info for hw_bufp[0..2]
446 /* This is used to initialize iTD's hw_bufp fields */
451 /* this is used to initialize sITD's tt info */
455 /*-------------------------------------------------------------------------*/
458 * EHCI Specification 0.95 Section 3.3
459 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
461 * Schedule records for high speed iso xfers
464 /* first part defined by EHCI spec */
465 __hc32 hw_next; /* see EHCI 3.3.1 */
466 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */
467 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
468 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
469 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
470 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
471 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
472 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
474 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
476 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */
477 __hc32 hw_bufp_hi [7]; /* Appendix B */
479 /* the rest is HCD-private */
480 dma_addr_t itd_dma; /* for this itd */
481 union ehci_shadow itd_next; /* ptr to periodic q entry */
484 struct ehci_iso_stream *stream; /* endpoint's queue */
485 struct list_head itd_list; /* list of stream's itds */
487 /* any/all hw_transactions here may be used by that urb */
488 unsigned frame; /* where scheduled */
490 unsigned index[8]; /* in urb->iso_frame_desc */
491 } __attribute__ ((aligned (32)));
493 /*-------------------------------------------------------------------------*/
496 * EHCI Specification 0.95 Section 3.4
497 * siTD, aka split-transaction isochronous Transfer Descriptor
498 * ... describe full speed iso xfers through TT in hubs
499 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
502 /* first part defined by EHCI spec */
504 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
505 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
506 __hc32 hw_uframe; /* EHCI table 3-10 */
507 __hc32 hw_results; /* EHCI table 3-11 */
508 #define SITD_IOC (1 << 31) /* interrupt on completion */
509 #define SITD_PAGE (1 << 30) /* buffer 0/1 */
510 #define SITD_LENGTH(x) (0x3ff & ((x)>>16))
511 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
512 #define SITD_STS_ERR (1 << 6) /* error from TT */
513 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
514 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
515 #define SITD_STS_XACT (1 << 3) /* illegal IN response */
516 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
517 #define SITD_STS_STS (1 << 1) /* split transaction state */
519 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
521 __hc32 hw_buf [2]; /* EHCI table 3-12 */
522 __hc32 hw_backpointer; /* EHCI table 3-13 */
523 __hc32 hw_buf_hi [2]; /* Appendix B */
525 /* the rest is HCD-private */
527 union ehci_shadow sitd_next; /* ptr to periodic q entry */
530 struct ehci_iso_stream *stream; /* endpoint's queue */
531 struct list_head sitd_list; /* list of stream's sitds */
534 } __attribute__ ((aligned (32)));
536 /*-------------------------------------------------------------------------*/
539 * EHCI Specification 0.96 Section 3.7
540 * Periodic Frame Span Traversal Node (FSTN)
542 * Manages split interrupt transactions (using TT) that span frame boundaries
543 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
544 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
545 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
548 __hc32 hw_next; /* any periodic q entry */
549 __hc32 hw_prev; /* qh or EHCI_LIST_END */
551 /* the rest is HCD-private */
553 union ehci_shadow fstn_next; /* ptr to periodic q entry */
554 } __attribute__ ((aligned (32)));
556 /*-------------------------------------------------------------------------*/
558 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
560 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
561 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
563 #define ehci_prepare_ports_for_controller_resume(ehci) \
564 ehci_adjust_port_wakeup_flags(ehci, false, false);
566 /*-------------------------------------------------------------------------*/
568 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
571 * Some EHCI controllers have a Transaction Translator built into the
572 * root hub. This is a non-standard feature. Each controller will need
573 * to add code to the following inline functions, and call them as
574 * needed (mostly in root hub code).
577 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
579 /* Returns the speed of a device attached to a port on the root hub. */
580 static inline unsigned int
581 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
583 if (ehci_is_TDI(ehci)) {
584 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
588 return USB_PORT_STAT_LOW_SPEED;
591 return USB_PORT_STAT_HIGH_SPEED;
594 return USB_PORT_STAT_HIGH_SPEED;
599 #define ehci_is_TDI(e) (0)
601 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
604 /*-------------------------------------------------------------------------*/
606 #ifdef CONFIG_PPC_83xx
607 /* Some Freescale processors have an erratum in which the TT
608 * port number in the queue head was 0..N-1 instead of 1..N.
610 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
612 #define ehci_has_fsl_portno_bug(e) (0)
616 * While most USB host controllers implement their registers in
617 * little-endian format, a minority (celleb companion chip) implement
618 * them in big endian format.
620 * This attempts to support either format at compile time without a
621 * runtime penalty, or both formats with the additional overhead
622 * of checking a flag bit.
624 * ehci_big_endian_capbase is a special quirk for controllers that
625 * implement the HC capability registers as separate registers and not
626 * as fields of a 32-bit register.
629 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
630 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
631 #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
633 #define ehci_big_endian_mmio(e) 0
634 #define ehci_big_endian_capbase(e) 0
638 * Big-endian read/write functions are arch-specific.
639 * Other arches can be added if/when they're needed.
641 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
642 #define readl_be(addr) __raw_readl((__force unsigned *)addr)
643 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
646 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
647 __u32 __iomem * regs)
649 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
650 return ehci_big_endian_mmio(ehci) ?
658 #ifdef CONFIG_SOC_IMX28
659 static inline void imx28_ehci_writel(const unsigned int val,
660 volatile __u32 __iomem *addr)
662 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
665 static inline void imx28_ehci_writel(const unsigned int val,
666 volatile __u32 __iomem *addr)
670 static inline void ehci_writel(const struct ehci_hcd *ehci,
671 const unsigned int val, __u32 __iomem *regs)
673 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
674 ehci_big_endian_mmio(ehci) ?
675 writel_be(val, regs) :
678 if (ehci->imx28_write_fix)
679 imx28_ehci_writel(val, regs);
686 * On certain ppc-44x SoC there is a HW issue, that could only worked around with
687 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch.
688 * Other common bits are dependent on has_amcc_usb23 quirk flag.
691 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
695 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
697 hc_control |= OHCI_USB_OPER;
699 hc_control |= OHCI_USB_SUSPEND;
701 writel_be(hc_control, ehci->ohci_hcctrl_reg);
702 (void) readl_be(ehci->ohci_hcctrl_reg);
705 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
709 /*-------------------------------------------------------------------------*/
712 * The AMCC 440EPx not only implements its EHCI registers in big-endian
713 * format, but also its DMA data structures (descriptors).
715 * EHCI controllers accessed through PCI work normally (little-endian
716 * everywhere), so we won't bother supporting a BE-only mode for now.
718 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
719 #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
722 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
724 return ehci_big_endian_desc(ehci)
725 ? (__force __hc32)cpu_to_be32(x)
726 : (__force __hc32)cpu_to_le32(x);
730 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
732 return ehci_big_endian_desc(ehci)
733 ? be32_to_cpu((__force __be32)x)
734 : le32_to_cpu((__force __le32)x);
737 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
739 return ehci_big_endian_desc(ehci)
740 ? be32_to_cpup((__force __be32 *)x)
741 : le32_to_cpup((__force __le32 *)x);
747 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
749 return cpu_to_le32(x);
753 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
755 return le32_to_cpu(x);
758 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
760 return le32_to_cpup(x);
765 /*-------------------------------------------------------------------------*/
769 /* For working around the MosChip frame-index-register bug */
770 static unsigned ehci_read_frame_index(struct ehci_hcd *ehci);
774 static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci)
776 return ehci_readl(ehci, &ehci->regs->frame_index);
781 /*-------------------------------------------------------------------------*/
784 #define STUB_DEBUG_FILES
787 /*-------------------------------------------------------------------------*/
789 #endif /* __LINUX_EHCI_HCD_H */