drivers/usb/host/ehci-tegra.c

   1 /*
   2  * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Copyright (C) 2009 NVIDIA Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/platform_data/tegra_usb.h>
  22 #include <linux/irq.h>
  23 #include <linux/usb/otg.h>
  24 #include <mach/usb_phy.h>
  25
  26 #define TEGRA_USB_DMA_ALIGN 32
  27
  28 struct tegra_ehci_hcd {
  29         struct ehci_hcd *ehci;
  30         struct tegra_usb_phy *phy;
  31         struct clk *clk;
  32         struct clk *emc_clk;
  33         struct otg_transceiver *transceiver;
  34         int host_resumed;
  35         int bus_suspended;
  36         int port_resuming;
  37         int power_down_on_bus_suspend;
  38         enum tegra_usb_phy_port_speed port_speed;
  39 };
  40
  41 static void tegra_ehci_power_up(struct usb_hcd *hcd)
  42 {
  43         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
  44
  45         clk_enable(tegra->emc_clk);
  46         clk_enable(tegra->clk);
  47         tegra_usb_phy_power_on(tegra->phy);
  48         tegra->host_resumed = 1;
  49 }
  50
  51 static void tegra_ehci_power_down(struct usb_hcd *hcd)
  52 {
  53         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
  54
  55         tegra->host_resumed = 0;
  56         tegra_usb_phy_power_off(tegra->phy);
  57         clk_disable(tegra->clk);
  58         clk_disable(tegra->emc_clk);
  59 }
  60
  61 static int tegra_ehci_internal_port_reset(
  62         struct ehci_hcd *ehci,
  63         u32 __iomem     *portsc_reg
  64 )
  65 {
  66         u32             temp;
  67         unsigned long   flags;
  68         int             retval = 0;
  69         int             i, tries;
  70         u32             saved_usbintr;
  71
  72         spin_lock_irqsave(&ehci->lock, flags);
  73         saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
  74         /* disable USB interrupt */
  75         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
  76         spin_unlock_irqrestore(&ehci->lock, flags);
  77
  78         /*
  79          * Here we have to do Port Reset at most twice for
  80          * Port Enable bit to be set.
  81          */
  82         for (i = 0; i < 2; i++) {
  83                 temp = ehci_readl(ehci, portsc_reg);
  84                 temp |= PORT_RESET;
  85                 ehci_writel(ehci, temp, portsc_reg);
  86                 mdelay(10);
  87                 temp &= ~PORT_RESET;
  88                 ehci_writel(ehci, temp, portsc_reg);
  89                 mdelay(1);
  90                 tries = 100;
  91                 do {
  92                         mdelay(1);
  93                         /*
  94                          * Up to this point, Port Enable bit is
  95                          * expected to be set after 2 ms waiting.
  96                          * USB1 usually takes extra 45 ms, for safety,
  97                          * we take 100 ms as timeout.
  98                          */
  99                         temp = ehci_readl(ehci, portsc_reg);
 100                 } while (!(temp & PORT_PE) && tries--);
 101                 if (temp & PORT_PE)
 102                         break;
 103         }
 104         if (i == 2)
 105                 retval = -ETIMEDOUT;
 106
 107         /*
 108          * Clear Connect Status Change bit if it's set.
 109          * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
 110          */
 111         if (temp & PORT_CSC)
 112                 ehci_writel(ehci, PORT_CSC, portsc_reg);
 113
 114         /*
 115          * Write to clear any interrupt status bits that might be set
 116          * during port reset.
 117          */
 118         temp = ehci_readl(ehci, &ehci->regs->status);
 119         ehci_writel(ehci, temp, &ehci->regs->status);
 120
 121         /* restore original interrupt enable bits */
 122         ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
 123         return retval;
 124 }
 125
 126 static int tegra_ehci_hub_control(
 127         struct usb_hcd  *hcd,
 128         u16             typeReq,
 129         u16             wValue,
 130         u16             wIndex,
 131         char            *buf,
 132         u16             wLength
 133 )
 134 {
 135         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 136         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 137         u32 __iomem     *status_reg;
 138         u32             temp;
 139         unsigned long   flags;
 140         int             retval = 0;
 141
 142         status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
 143
 144         spin_lock_irqsave(&ehci->lock, flags);
 145
 146         /*
 147          * In ehci_hub_control() for USB_PORT_FEAT_ENABLE clears the other bits
 148          * that are write on clear, by writing back the register read value, so
 149          * USB_PORT_FEAT_ENABLE is handled by masking the set on clear bits
 150          */
 151         if (typeReq == ClearPortFeature && wValue == USB_PORT_FEAT_ENABLE) {
 152                 temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS;
 153                 ehci_writel(ehci, temp & ~PORT_PE, status_reg);
 154                 goto done;
 155         }
 156
 157         else if (typeReq == GetPortStatus) {
 158                 temp = ehci_readl(ehci, status_reg);
 159                 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
 160                         /* Resume completed, re-enable disconnect detection */
 161                         tegra->port_resuming = 0;
 162                         tegra_usb_phy_postresume(tegra->phy);
 163                 }
 164         }
 165
 166         else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
 167                 temp = ehci_readl(ehci, status_reg);
 168                 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
 169                         retval = -EPIPE;
 170                         goto done;
 171                 }
 172
 173                 temp &= ~PORT_WKCONN_E;
 174                 temp |= PORT_WKDISC_E | PORT_WKOC_E;
 175                 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
 176
 177                 /*
 178                  * If a transaction is in progress, there may be a delay in
 179                  * suspending the port. Poll until the port is suspended.
 180                  */
 181                 if (handshake(ehci, status_reg, PORT_SUSPEND,
 182                                                 PORT_SUSPEND, 5000))
 183                         pr_err("%s: timeout waiting for SUSPEND\n", __func__);
 184
 185                 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
 186                 goto done;
 187         }
 188
 189         /* For USB1 port we need to issue Port Reset twice internally */
 190         if (tegra->phy->instance == 0 &&
 191            (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
 192                 spin_unlock_irqrestore(&ehci->lock, flags);
 193                 return tegra_ehci_internal_port_reset(ehci, status_reg);
 194         }
 195
 196         /*
 197          * Tegra host controller will time the resume operation to clear the bit
 198          * when the port control state switches to HS or FS Idle. This behavior
 199          * is different from EHCI where the host controller driver is required
 200          * to set this bit to a zero after the resume duration is timed in the
 201          * driver.
 202          */
 203         else if (typeReq == ClearPortFeature &&
 204                                         wValue == USB_PORT_FEAT_SUSPEND) {
 205                 temp = ehci_readl(ehci, status_reg);
 206                 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
 207                         retval = -EPIPE;
 208                         goto done;
 209                 }
 210
 211                 if (!(temp & PORT_SUSPEND))
 212                         goto done;
 213
 214                 /* Disable disconnect detection during port resume */
 215                 tegra_usb_phy_preresume(tegra->phy);
 216
 217                 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
 218
 219                 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
 220                 /* start resume signalling */
 221                 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
 222
 223                 spin_unlock_irqrestore(&ehci->lock, flags);
 224                 msleep(20);
 225                 spin_lock_irqsave(&ehci->lock, flags);
 226
 227                 /* Poll until the controller clears RESUME and SUSPEND */
 228                 if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
 229                         pr_err("%s: timeout waiting for RESUME\n", __func__);
 230                 if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
 231                         pr_err("%s: timeout waiting for SUSPEND\n", __func__);
 232
 233                 ehci->reset_done[wIndex-1] = 0;
 234
 235                 tegra->port_resuming = 1;
 236                 goto done;
 237         }
 238
 239         spin_unlock_irqrestore(&ehci->lock, flags);
 240
 241         /* Handle the hub control events here */
 242         return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
 243 done:
 244         spin_unlock_irqrestore(&ehci->lock, flags);
 245         return retval;
 246 }
 247
 248 static void tegra_ehci_restart(struct usb_hcd *hcd)
 249 {
 250         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 251
 252         ehci_reset(ehci);
 253
 254         /* setup the frame list and Async q heads */
 255         ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
 256         ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
 257         /* setup the command register and set the controller in RUN mode */
 258         ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
 259         ehci->command |= CMD_RUN;
 260         ehci_writel(ehci, ehci->command, &ehci->regs->command);
 261
 262         down_write(&ehci_cf_port_reset_rwsem);
 263         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
 264         /* flush posted writes */
 265         ehci_readl(ehci, &ehci->regs->command);
 266         up_write(&ehci_cf_port_reset_rwsem);
 267 }
 268
 269 static int tegra_usb_suspend(struct usb_hcd *hcd)
 270 {
 271         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 272         struct ehci_regs __iomem *hw = tegra->ehci->regs;
 273         unsigned long flags;
 274
 275         spin_lock_irqsave(&tegra->ehci->lock, flags);
 276
 277         tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
 278         ehci_halt(tegra->ehci);
 279         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 280
 281         spin_unlock_irqrestore(&tegra->ehci->lock, flags);
 282
 283         tegra_ehci_power_down(hcd);
 284         return 0;
 285 }
 286
 287 static int tegra_usb_resume(struct usb_hcd *hcd)
 288 {
 289         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 290         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 291         struct ehci_regs __iomem *hw = ehci->regs;
 292         unsigned long val;
 293
 294         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 295         tegra_ehci_power_up(hcd);
 296
 297         if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) {
 298                 /* Wait for the phy to detect new devices
 299                  * before we restart the controller */
 300                 msleep(10);
 301                 goto restart;
 302         }
 303
 304         /* Force the phy to keep data lines in suspend state */
 305         tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
 306
 307         /* Enable host mode */
 308         tdi_reset(ehci);
 309
 310         /* Enable Port Power */
 311         val = readl(&hw->port_status[0]);
 312         val |= PORT_POWER;
 313         writel(val, &hw->port_status[0]);
 314         udelay(10);
 315
 316         /* Check if the phy resume from LP0. When the phy resume from LP0
 317          * USB register will be reset. */
 318         if (!readl(&hw->async_next)) {
 319                 /* Program the field PTC based on the saved speed mode */
 320                 val = readl(&hw->port_status[0]);
 321                 val &= ~PORT_TEST(~0);
 322                 if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
 323                         val |= PORT_TEST_FORCE;
 324                 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
 325                         val |= PORT_TEST(6);
 326                 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
 327                         val |= PORT_TEST(7);
 328                 writel(val, &hw->port_status[0]);
 329                 udelay(10);
 330
 331                 /* Disable test mode by setting PTC field to NORMAL_OP */
 332                 val = readl(&hw->port_status[0]);
 333                 val &= ~PORT_TEST(~0);
 334                 writel(val, &hw->port_status[0]);
 335                 udelay(10);
 336         }
 337
 338         /* Poll until CCS is enabled */
 339         if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
 340                                                  PORT_CONNECT, 2000)) {
 341                 pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
 342                 goto restart;
 343         }
 344
 345         /* Poll until PE is enabled */
 346         if (handshake(ehci, &hw->port_status[0], PORT_PE,
 347                                                  PORT_PE, 2000)) {
 348                 pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
 349                 goto restart;
 350         }
 351
 352         /* Clear the PCI status, to avoid an interrupt taken upon resume */
 353         val = readl(&hw->status);
 354         val |= STS_PCD;
 355         writel(val, &hw->status);
 356
 357         /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
 358         val = readl(&hw->port_status[0]);
 359         if ((val & PORT_POWER) && (val & PORT_PE)) {
 360                 val |= PORT_SUSPEND;
 361                 writel(val, &hw->port_status[0]);
 362
 363                 /* Wait until port suspend completes */
 364                 if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
 365                                                          PORT_SUSPEND, 1000)) {
 366                         pr_err("%s: timeout waiting for PORT_SUSPEND\n",
 367                                                                 __func__);
 368                         goto restart;
 369                 }
 370         }
 371
 372         tegra_ehci_phy_restore_end(tegra->phy);
 373         return 0;
 374
 375 restart:
 376         if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH)
 377                 tegra_ehci_phy_restore_end(tegra->phy);
 378
 379         tegra_ehci_restart(hcd);
 380         return 0;
 381 }
 382
 383 static void tegra_ehci_shutdown(struct usb_hcd *hcd)
 384 {
 385         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 386
 387         /* ehci_shutdown touches the USB controller registers, make sure
 388          * controller has clocks to it */
 389         if (!tegra->host_resumed)
 390                 tegra_ehci_power_up(hcd);
 391
 392         ehci_shutdown(hcd);
 393 }
 394
 395 static int tegra_ehci_setup(struct usb_hcd *hcd)
 396 {
 397         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 398         int retval;
 399
 400         /* EHCI registers start at offset 0x100 */
 401         ehci->caps = hcd->regs + 0x100;
 402         ehci->regs = hcd->regs + 0x100 +
 403                 HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
 404
 405         dbg_hcs_params(ehci, "reset");
 406         dbg_hcc_params(ehci, "reset");
 407
 408         /* cache this readonly data; minimize chip reads */
 409         ehci->hcs_params = readl(&ehci->caps->hcs_params);
 410
 411         /* switch to host mode */
 412         hcd->has_tt = 1;
 413         ehci_reset(ehci);
 414
 415         retval = ehci_halt(ehci);
 416         if (retval)
 417                 return retval;
 418
 419         /* data structure init */
 420         retval = ehci_init(hcd);
 421         if (retval)
 422                 return retval;
 423
 424         ehci->sbrn = 0x20;
 425
 426         ehci_port_power(ehci, 1);
 427         return retval;
 428 }
 429
 430 #ifdef CONFIG_PM
 431 static int tegra_ehci_bus_suspend(struct usb_hcd *hcd)
 432 {
 433         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 434         int error_status = 0;
 435
 436         error_status = ehci_bus_suspend(hcd);
 437         if (!error_status && tegra->power_down_on_bus_suspend) {
 438                 tegra_usb_suspend(hcd);
 439                 tegra->bus_suspended = 1;
 440         }
 441
 442         return error_status;
 443 }
 444
 445 static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
 446 {
 447         struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
 448
 449         if (tegra->bus_suspended && tegra->power_down_on_bus_suspend) {
 450                 tegra_usb_resume(hcd);
 451                 tegra->bus_suspended = 0;
 452         }
 453
 454         tegra_usb_phy_preresume(tegra->phy);
 455         tegra->port_resuming = 1;
 456         return ehci_bus_resume(hcd);
 457 }
 458 #endif
 459
 460 struct temp_buffer {
 461         void *kmalloc_ptr;
 462         void *old_xfer_buffer;
 463         u8 data[0];
 464 };
 465
 466 static void free_temp_buffer(struct urb *urb)
 467 {
 468         enum dma_data_direction dir;
 469         struct temp_buffer *temp;
 470
 471         if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
 472                 return;
 473
 474         dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 475
 476         temp = container_of(urb->transfer_buffer, struct temp_buffer,
 477                             data);
 478
 479         if (dir == DMA_FROM_DEVICE)
 480                 memcpy(temp->old_xfer_buffer, temp->data,
 481                        urb->transfer_buffer_length);
 482         urb->transfer_buffer = temp->old_xfer_buffer;
 483         kfree(temp->kmalloc_ptr);
 484
 485         urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
 486 }
 487
 488 static int alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
 489 {
 490         enum dma_data_direction dir;
 491         struct temp_buffer *temp, *kmalloc_ptr;
 492         size_t kmalloc_size;
 493
 494         if (urb->num_sgs || urb->sg ||
 495             urb->transfer_buffer_length == 0 ||
 496             !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
 497                 return 0;
 498
 499         dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 500
 501         /* Allocate a buffer with enough padding for alignment */
 502         kmalloc_size = urb->transfer_buffer_length +
 503                 sizeof(struct temp_buffer) + TEGRA_USB_DMA_ALIGN - 1;
 504
 505         kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
 506         if (!kmalloc_ptr)
 507                 return -ENOMEM;
 508
 509         /* Position our struct temp_buffer such that data is aligned */
 510         temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
 511
 512         temp->kmalloc_ptr = kmalloc_ptr;
 513         temp->old_xfer_buffer = urb->transfer_buffer;
 514         if (dir == DMA_TO_DEVICE)
 515                 memcpy(temp->data, urb->transfer_buffer,
 516                        urb->transfer_buffer_length);
 517         urb->transfer_buffer = temp->data;
 518
 519         urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
 520
 521         return 0;
 522 }
 523
 524 static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
 525                                       gfp_t mem_flags)
 526 {
 527         int ret;
 528
 529         ret = alloc_temp_buffer(urb, mem_flags);
 530         if (ret)
 531                 return ret;
 532
 533         ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
 534         if (ret)
 535                 free_temp_buffer(urb);
 536
 537         return ret;
 538 }
 539
 540 static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
 541 {
 542         usb_hcd_unmap_urb_for_dma(hcd, urb);
 543         free_temp_buffer(urb);
 544 }
 545
 546 static const struct hc_driver tegra_ehci_hc_driver = {
 547         .description            = hcd_name,
 548         .product_desc           = "Tegra EHCI Host Controller",
 549         .hcd_priv_size          = sizeof(struct ehci_hcd),
 550
 551         .flags                  = HCD_USB2 | HCD_MEMORY,
 552
 553         .reset                  = tegra_ehci_setup,
 554         .irq                    = ehci_irq,
 555
 556         .start                  = ehci_run,
 557         .stop                   = ehci_stop,
 558         .shutdown               = tegra_ehci_shutdown,
 559         .urb_enqueue            = ehci_urb_enqueue,
 560         .urb_dequeue            = ehci_urb_dequeue,
 561         .map_urb_for_dma        = tegra_ehci_map_urb_for_dma,
 562         .unmap_urb_for_dma      = tegra_ehci_unmap_urb_for_dma,
 563         .endpoint_disable       = ehci_endpoint_disable,
 564         .endpoint_reset         = ehci_endpoint_reset,
 565         .get_frame_number       = ehci_get_frame,
 566         .hub_status_data        = ehci_hub_status_data,
 567         .hub_control            = tegra_ehci_hub_control,
 568         .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
 569 #ifdef CONFIG_PM
 570         .bus_suspend            = tegra_ehci_bus_suspend,
 571         .bus_resume             = tegra_ehci_bus_resume,
 572 #endif
 573         .relinquish_port        = ehci_relinquish_port,
 574         .port_handed_over       = ehci_port_handed_over,
 575 };
 576
 577 static int tegra_ehci_probe(struct platform_device *pdev)
 578 {
 579         struct resource *res;
 580         struct usb_hcd *hcd;
 581         struct tegra_ehci_hcd *tegra;
 582         struct tegra_ehci_platform_data *pdata;
 583         int err = 0;
 584         int irq;
 585         int instance = pdev->id;
 586
 587         pdata = pdev->dev.platform_data;
 588         if (!pdata) {
 589                 dev_err(&pdev->dev, "Platform data missing\n");
 590                 return -EINVAL;
 591         }
 592
 593         tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL);
 594         if (!tegra)
 595                 return -ENOMEM;
 596
 597         hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
 598                                         dev_name(&pdev->dev));
 599         if (!hcd) {
 600                 dev_err(&pdev->dev, "Unable to create HCD\n");
 601                 err = -ENOMEM;
 602                 goto fail_hcd;
 603         }
 604
 605         platform_set_drvdata(pdev, tegra);
 606
 607         tegra->clk = clk_get(&pdev->dev, NULL);
 608         if (IS_ERR(tegra->clk)) {
 609                 dev_err(&pdev->dev, "Can't get ehci clock\n");
 610                 err = PTR_ERR(tegra->clk);
 611                 goto fail_clk;
 612         }
 613
 614         err = clk_enable(tegra->clk);
 615         if (err)
 616                 goto fail_clken;
 617
 618         tegra->emc_clk = clk_get(&pdev->dev, "emc");
 619         if (IS_ERR(tegra->emc_clk)) {
 620                 dev_err(&pdev->dev, "Can't get emc clock\n");
 621                 err = PTR_ERR(tegra->emc_clk);
 622                 goto fail_emc_clk;
 623         }
 624
 625         clk_enable(tegra->emc_clk);
 626         clk_set_rate(tegra->emc_clk, 400000000);
 627
 628         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 629         if (!res) {
 630                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
 631                 err = -ENXIO;
 632                 goto fail_io;
 633         }
 634         hcd->rsrc_start = res->start;
 635         hcd->rsrc_len = resource_size(res);
 636         hcd->regs = ioremap(res->start, resource_size(res));
 637         if (!hcd->regs) {
 638                 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
 639                 err = -ENOMEM;
 640                 goto fail_io;
 641         }
 642
 643         tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config,
 644                                                 TEGRA_USB_PHY_MODE_HOST);
 645         if (IS_ERR(tegra->phy)) {
 646                 dev_err(&pdev->dev, "Failed to open USB phy\n");
 647                 err = -ENXIO;
 648                 goto fail_phy;
 649         }
 650
 651         err = tegra_usb_phy_power_on(tegra->phy);
 652         if (err) {
 653                 dev_err(&pdev->dev, "Failed to power on the phy\n");
 654                 goto fail;
 655         }
 656
 657         tegra->host_resumed = 1;
 658         tegra->power_down_on_bus_suspend = pdata->power_down_on_bus_suspend;
 659         tegra->ehci = hcd_to_ehci(hcd);
 660
 661         irq = platform_get_irq(pdev, 0);
 662         if (!irq) {
 663                 dev_err(&pdev->dev, "Failed to get IRQ\n");
 664                 err = -ENODEV;
 665                 goto fail;
 666         }
 667         set_irq_flags(irq, IRQF_VALID);
 668
 669 #ifdef CONFIG_USB_OTG_UTILS
 670         if (pdata->operating_mode == TEGRA_USB_OTG) {
 671                 tegra->transceiver = otg_get_transceiver();
 672                 if (tegra->transceiver)
 673                         otg_set_host(tegra->transceiver, &hcd->self);
 674         }
 675 #endif
 676
 677         err = usb_add_hcd(hcd, irq, IRQF_SHARED);
 678         if (err) {
 679                 dev_err(&pdev->dev, "Failed to add USB HCD\n");
 680                 goto fail;
 681         }
 682
 683         return err;
 684
 685 fail:
 686 #ifdef CONFIG_USB_OTG_UTILS
 687         if (tegra->transceiver) {
 688                 otg_set_host(tegra->transceiver, NULL);
 689                 otg_put_transceiver(tegra->transceiver);
 690         }
 691 #endif
 692         tegra_usb_phy_close(tegra->phy);
 693 fail_phy:
 694         iounmap(hcd->regs);
 695 fail_io:
 696         clk_disable(tegra->emc_clk);
 697         clk_put(tegra->emc_clk);
 698 fail_emc_clk:
 699         clk_disable(tegra->clk);
 700 fail_clken:
 701         clk_put(tegra->clk);
 702 fail_clk:
 703         usb_put_hcd(hcd);
 704 fail_hcd:
 705         kfree(tegra);
 706         return err;
 707 }
 708
 709 #ifdef CONFIG_PM
 710 static int tegra_ehci_resume(struct platform_device *pdev)
 711 {
 712         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
 713         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
 714
 715         if (tegra->bus_suspended)
 716                 return 0;
 717
 718         return tegra_usb_resume(hcd);
 719 }
 720
 721 static int tegra_ehci_suspend(struct platform_device *pdev, pm_message_t state)
 722 {
 723         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
 724         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
 725
 726         if (tegra->bus_suspended)
 727                 return 0;
 728
 729         if (time_before(jiffies, tegra->ehci->next_statechange))
 730                 msleep(10);
 731
 732         return tegra_usb_suspend(hcd);
 733 }
 734 #endif
 735
 736 static int tegra_ehci_remove(struct platform_device *pdev)
 737 {
 738         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
 739         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
 740
 741         if (tegra == NULL || hcd == NULL)
 742                 return -EINVAL;
 743
 744 #ifdef CONFIG_USB_OTG_UTILS
 745         if (tegra->transceiver) {
 746                 otg_set_host(tegra->transceiver, NULL);
 747                 otg_put_transceiver(tegra->transceiver);
 748         }
 749 #endif
 750
 751         usb_remove_hcd(hcd);
 752         usb_put_hcd(hcd);
 753
 754         tegra_usb_phy_close(tegra->phy);
 755         iounmap(hcd->regs);
 756
 757         clk_disable(tegra->clk);
 758         clk_put(tegra->clk);
 759
 760         clk_disable(tegra->emc_clk);
 761         clk_put(tegra->emc_clk);
 762
 763         kfree(tegra);
 764         return 0;
 765 }
 766
 767 static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
 768 {
 769         struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
 770         struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
 771
 772         if (hcd->driver->shutdown)
 773                 hcd->driver->shutdown(hcd);
 774 }
 775
 776 static struct platform_driver tegra_ehci_driver = {
 777         .probe          = tegra_ehci_probe,
 778         .remove         = tegra_ehci_remove,
 779 #ifdef CONFIG_PM
 780         .suspend        = tegra_ehci_suspend,
 781         .resume         = tegra_ehci_resume,
 782 #endif
 783         .shutdown       = tegra_ehci_hcd_shutdown,
 784         .driver         = {
 785                 .name   = "tegra-ehci",
 786         }
 787 };