drivers/usb/host/ehci-omap.c

   1 /*
   2  * ehci-omap.c - driver for USBHOST on OMAP 34xx processor
   3  *
   4  * Bus Glue for OMAP34xx USBHOST 3 port EHCI controller
   5  * Tested on OMAP3430 ES2.0 SDP
   6  *
   7  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   8  *      Author: Vikram Pandita <vikram.pandita@ti.com>
   9  *
  10  * Copyright (C) 2009 Nokia Corporation
  11  *      Contact: Felipe Balbi <felipe.balbi@nokia.com>
  12  *
  13  * Based on "ehci-fsl.c" and "ehci-au1xxx.c" ehci glue layers
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  28  *
  29  * TODO (last updated Feb 12, 2010):
  30  *      - add kernel-doc
  31  *      - enable AUTOIDLE
  32  *      - add suspend/resume
  33  *      - move workarounds to board-files
  34  */
  35
  36 #include <linux/platform_device.h>
  37 #include <linux/clk.h>
  38 #include <linux/gpio.h>
  39 #include <linux/regulator/consumer.h>
  40 #include <plat/usb.h>
  41
  42 /*
  43  * OMAP USBHOST Register addresses: VIRTUAL ADDRESSES
  44  *      Use ehci_omap_readl()/ehci_omap_writel() functions
  45  */
  46
  47 /* TLL Register Set */
  48 #define OMAP_USBTLL_REVISION                            (0x00)
  49 #define OMAP_USBTLL_SYSCONFIG                           (0x10)
  50 #define OMAP_USBTLL_SYSCONFIG_CACTIVITY                 (1 << 8)
  51 #define OMAP_USBTLL_SYSCONFIG_SIDLEMODE                 (1 << 3)
  52 #define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP                 (1 << 2)
  53 #define OMAP_USBTLL_SYSCONFIG_SOFTRESET                 (1 << 1)
  54 #define OMAP_USBTLL_SYSCONFIG_AUTOIDLE                  (1 << 0)
  55
  56 #define OMAP_USBTLL_SYSSTATUS                           (0x14)
  57 #define OMAP_USBTLL_SYSSTATUS_RESETDONE                 (1 << 0)
  58
  59 #define OMAP_USBTLL_IRQSTATUS                           (0x18)
  60 #define OMAP_USBTLL_IRQENABLE                           (0x1C)
  61
  62 #define OMAP_TLL_SHARED_CONF                            (0x30)
  63 #define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN             (1 << 6)
  64 #define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN            (1 << 5)
  65 #define OMAP_TLL_SHARED_CONF_USB_DIVRATION              (1 << 2)
  66 #define OMAP_TLL_SHARED_CONF_FCLK_REQ                   (1 << 1)
  67 #define OMAP_TLL_SHARED_CONF_FCLK_IS_ON                 (1 << 0)
  68
  69 #define OMAP_TLL_CHANNEL_CONF(num)                      (0x040 + 0x004 * num)
  70 #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF            (1 << 11)
  71 #define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE         (1 << 10)
  72 #define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE              (1 << 9)
  73 #define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE               (1 << 8)
  74 #define OMAP_TLL_CHANNEL_CONF_CHANEN                    (1 << 0)
  75
  76 #define OMAP_TLL_ULPI_FUNCTION_CTRL(num)                (0x804 + 0x100 * num)
  77 #define OMAP_TLL_ULPI_INTERFACE_CTRL(num)               (0x807 + 0x100 * num)
  78 #define OMAP_TLL_ULPI_OTG_CTRL(num)                     (0x80A + 0x100 * num)
  79 #define OMAP_TLL_ULPI_INT_EN_RISE(num)                  (0x80D + 0x100 * num)
  80 #define OMAP_TLL_ULPI_INT_EN_FALL(num)                  (0x810 + 0x100 * num)
  81 #define OMAP_TLL_ULPI_INT_STATUS(num)                   (0x813 + 0x100 * num)
  82 #define OMAP_TLL_ULPI_INT_LATCH(num)                    (0x814 + 0x100 * num)
  83 #define OMAP_TLL_ULPI_DEBUG(num)                        (0x815 + 0x100 * num)
  84 #define OMAP_TLL_ULPI_SCRATCH_REGISTER(num)             (0x816 + 0x100 * num)
  85
  86 #define OMAP_TLL_CHANNEL_COUNT                          3
  87 #define OMAP_TLL_CHANNEL_1_EN_MASK                      (1 << 1)
  88 #define OMAP_TLL_CHANNEL_2_EN_MASK                      (1 << 2)
  89 #define OMAP_TLL_CHANNEL_3_EN_MASK                      (1 << 4)
  90
  91 /* UHH Register Set */
  92 #define OMAP_UHH_REVISION                               (0x00)
  93 #define OMAP_UHH_SYSCONFIG                              (0x10)
  94 #define OMAP_UHH_SYSCONFIG_MIDLEMODE                    (1 << 12)
  95 #define OMAP_UHH_SYSCONFIG_CACTIVITY                    (1 << 8)
  96 #define OMAP_UHH_SYSCONFIG_SIDLEMODE                    (1 << 3)
  97 #define OMAP_UHH_SYSCONFIG_ENAWAKEUP                    (1 << 2)
  98 #define OMAP_UHH_SYSCONFIG_SOFTRESET                    (1 << 1)
  99 #define OMAP_UHH_SYSCONFIG_AUTOIDLE                     (1 << 0)
 100
 101 #define OMAP_UHH_SYSSTATUS                              (0x14)
 102 #define OMAP_UHH_HOSTCONFIG                             (0x40)
 103 #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS                 (1 << 0)
 104 #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS              (1 << 0)
 105 #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS              (1 << 11)
 106 #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS              (1 << 12)
 107 #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN              (1 << 2)
 108 #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN              (1 << 3)
 109 #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN             (1 << 4)
 110 #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN              (1 << 5)
 111 #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS           (1 << 8)
 112 #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS           (1 << 9)
 113 #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS           (1 << 10)
 114
 115 #define OMAP_UHH_DEBUG_CSR                              (0x44)
 116
 117 /* EHCI Register Set */
 118 #define EHCI_INSNREG05_ULPI                             (0xA4)
 119 #define EHCI_INSNREG05_ULPI_CONTROL_SHIFT               31
 120 #define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT               24
 121 #define EHCI_INSNREG05_ULPI_OPSEL_SHIFT                 22
 122 #define EHCI_INSNREG05_ULPI_REGADD_SHIFT                16
 123 #define EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT             8
 124 #define EHCI_INSNREG05_ULPI_WRDATA_SHIFT                0
 125
 126 /*-------------------------------------------------------------------------*/
 127
 128 static inline void ehci_omap_writel(void __iomem *base, u32 reg, u32 val)
 129 {
 130         __raw_writel(val, base + reg);
 131 }
 132
 133 static inline u32 ehci_omap_readl(void __iomem *base, u32 reg)
 134 {
 135         return __raw_readl(base + reg);
 136 }
 137
 138 static inline void ehci_omap_writeb(void __iomem *base, u8 reg, u8 val)
 139 {
 140         __raw_writeb(val, base + reg);
 141 }
 142
 143 static inline u8 ehci_omap_readb(void __iomem *base, u8 reg)
 144 {
 145         return __raw_readb(base + reg);
 146 }
 147
 148 /*-------------------------------------------------------------------------*/
 149
 150 struct ehci_hcd_omap {
 151         struct ehci_hcd         *ehci;
 152         struct device           *dev;
 153
 154         struct clk              *usbhost_ick;
 155         struct clk              *usbhost2_120m_fck;
 156         struct clk              *usbhost1_48m_fck;
 157         struct clk              *usbtll_fck;
 158         struct clk              *usbtll_ick;
 159
 160         /* FIXME the following two workarounds are
 161          * board specific not silicon-specific so these
 162          * should be moved to board-file instead.
 163          *
 164          * Maybe someone from TI will know better which
 165          * board is affected and needs the workarounds
 166          * to be applied
 167          */
 168
 169         /* gpio for resetting phy */
 170         int                     reset_gpio_port[OMAP3_HS_USB_PORTS];
 171
 172         /* phy reset workaround */
 173         int                     phy_reset;
 174
 175         /* desired phy_mode: TLL, PHY */
 176         enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
 177
 178         void __iomem            *uhh_base;
 179         void __iomem            *tll_base;
 180         void __iomem            *ehci_base;
 181
 182         /* Regulators for USB PHYs.
 183          * Each PHY can have a seperate regulator.
 184          */
 185         struct regulator        *regulator[OMAP3_HS_USB_PORTS];
 186 };
 187
 188 /*-------------------------------------------------------------------------*/
 189
 190 static void omap_usb_utmi_init(struct ehci_hcd_omap *omap, u8 tll_channel_mask)
 191 {
 192         unsigned reg;
 193         int i;
 194
 195         /* Program the 3 TLL channels upfront */
 196         for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
 197                 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
 198
 199                 /* Disable AutoIdle, BitStuffing and use SDR Mode */
 200                 reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
 201                                 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
 202                                 | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
 203                 ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
 204         }
 205
 206         /* Program Common TLL register */
 207         reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF);
 208         reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
 209                         | OMAP_TLL_SHARED_CONF_USB_DIVRATION
 210                         | OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN);
 211         reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
 212
 213         ehci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
 214
 215         /* Enable channels now */
 216         for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
 217                 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
 218
 219                 /* Enable only the reg that is needed */
 220                 if (!(tll_channel_mask & 1<<i))
 221                         continue;
 222
 223                 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
 224                 ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
 225
 226                 ehci_omap_writeb(omap->tll_base,
 227                                 OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe);
 228                 dev_dbg(omap->dev, "ULPI_SCRATCH_REG[ch=%d]= 0x%02x\n",
 229                                 i+1, ehci_omap_readb(omap->tll_base,
 230                                 OMAP_TLL_ULPI_SCRATCH_REGISTER(i)));
 231         }
 232 }
 233
 234 /*-------------------------------------------------------------------------*/
 235
 236 /* omap_start_ehc
 237  *      - Start the TI USBHOST controller
 238  */
 239 static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
 240 {
 241         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 242         u8 tll_ch_mask = 0;
 243         unsigned reg = 0;
 244         int ret = 0;
 245
 246         dev_dbg(omap->dev, "starting TI EHCI USB Controller\n");
 247
 248         /* Enable Clocks for USBHOST */
 249         omap->usbhost_ick = clk_get(omap->dev, "usbhost_ick");
 250         if (IS_ERR(omap->usbhost_ick)) {
 251                 ret =  PTR_ERR(omap->usbhost_ick);
 252                 goto err_host_ick;
 253         }
 254         clk_enable(omap->usbhost_ick);
 255
 256         omap->usbhost2_120m_fck = clk_get(omap->dev, "usbhost_120m_fck");
 257         if (IS_ERR(omap->usbhost2_120m_fck)) {
 258                 ret = PTR_ERR(omap->usbhost2_120m_fck);
 259                 goto err_host_120m_fck;
 260         }
 261         clk_enable(omap->usbhost2_120m_fck);
 262
 263         omap->usbhost1_48m_fck = clk_get(omap->dev, "usbhost_48m_fck");
 264         if (IS_ERR(omap->usbhost1_48m_fck)) {
 265                 ret = PTR_ERR(omap->usbhost1_48m_fck);
 266                 goto err_host_48m_fck;
 267         }
 268         clk_enable(omap->usbhost1_48m_fck);
 269
 270         if (omap->phy_reset) {
 271                 /* Refer: ISSUE1 */
 272                 if (gpio_is_valid(omap->reset_gpio_port[0])) {
 273                         gpio_request(omap->reset_gpio_port[0],
 274                                                 "USB1 PHY reset");
 275                         gpio_direction_output(omap->reset_gpio_port[0], 0);
 276                 }
 277
 278                 if (gpio_is_valid(omap->reset_gpio_port[1])) {
 279                         gpio_request(omap->reset_gpio_port[1],
 280                                                 "USB2 PHY reset");
 281                         gpio_direction_output(omap->reset_gpio_port[1], 0);
 282                 }
 283
 284                 /* Hold the PHY in RESET for enough time till DIR is high */
 285                 udelay(10);
 286         }
 287
 288         /* Configure TLL for 60Mhz clk for ULPI */
 289         omap->usbtll_fck = clk_get(omap->dev, "usbtll_fck");
 290         if (IS_ERR(omap->usbtll_fck)) {
 291                 ret = PTR_ERR(omap->usbtll_fck);
 292                 goto err_tll_fck;
 293         }
 294         clk_enable(omap->usbtll_fck);
 295
 296         omap->usbtll_ick = clk_get(omap->dev, "usbtll_ick");
 297         if (IS_ERR(omap->usbtll_ick)) {
 298                 ret = PTR_ERR(omap->usbtll_ick);
 299                 goto err_tll_ick;
 300         }
 301         clk_enable(omap->usbtll_ick);
 302
 303         /* perform TLL soft reset, and wait until reset is complete */
 304         ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
 305                         OMAP_USBTLL_SYSCONFIG_SOFTRESET);
 306
 307         /* Wait for TLL reset to complete */
 308         while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
 309                         & OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
 310                 cpu_relax();
 311
 312                 if (time_after(jiffies, timeout)) {
 313                         dev_dbg(omap->dev, "operation timed out\n");
 314                         ret = -EINVAL;
 315                         goto err_sys_status;
 316                 }
 317         }
 318
 319         dev_dbg(omap->dev, "TLL RESET DONE\n");
 320
 321         /* (1<<3) = no idle mode only for initial debugging */
 322         ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
 323                         OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
 324                         OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
 325                         OMAP_USBTLL_SYSCONFIG_CACTIVITY);
 326
 327
 328         /* Put UHH in NoIdle/NoStandby mode */
 329         reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
 330         reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
 331                         | OMAP_UHH_SYSCONFIG_SIDLEMODE
 332                         | OMAP_UHH_SYSCONFIG_CACTIVITY
 333                         | OMAP_UHH_SYSCONFIG_MIDLEMODE);
 334         reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
 335
 336         ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
 337
 338         reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
 339
 340         /* setup ULPI bypass and burst configurations */
 341         reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
 342                         | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
 343                         | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
 344         reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
 345
 346         if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN)
 347                 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
 348         if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN)
 349                 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
 350         if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN)
 351                 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
 352
 353         /* Bypass the TLL module for PHY mode operation */
 354          if (omap_rev() <= OMAP3430_REV_ES2_1) {
 355                 dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1 \n");
 356                 if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) ||
 357                         (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) ||
 358                                 (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY))
 359                         reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
 360                 else
 361                         reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
 362         } else {
 363                 dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n");
 364                 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY)
 365                         reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
 366                 else if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
 367                         reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
 368
 369                 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY)
 370                         reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
 371                 else if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
 372                         reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
 373
 374                 if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY)
 375                         reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
 376                 else if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
 377                         reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
 378
 379         }
 380         ehci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
 381         dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
 382
 383
 384         if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) ||
 385                 (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) ||
 386                         (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)) {
 387
 388                 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
 389                         tll_ch_mask |= OMAP_TLL_CHANNEL_1_EN_MASK;
 390                 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
 391                         tll_ch_mask |= OMAP_TLL_CHANNEL_2_EN_MASK;
 392                 if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
 393                         tll_ch_mask |= OMAP_TLL_CHANNEL_3_EN_MASK;
 394
 395                 /* Enable UTMI mode for required TLL channels */
 396                 omap_usb_utmi_init(omap, tll_ch_mask);
 397         }
 398
 399         if (omap->phy_reset) {
 400                 /* Refer ISSUE1:
 401                  * Hold the PHY in RESET for enough time till
 402                  * PHY is settled and ready
 403                  */
 404                 udelay(10);
 405
 406                 if (gpio_is_valid(omap->reset_gpio_port[0]))
 407                         gpio_set_value(omap->reset_gpio_port[0], 1);
 408
 409                 if (gpio_is_valid(omap->reset_gpio_port[1]))
 410                         gpio_set_value(omap->reset_gpio_port[1], 1);
 411         }
 412
 413         return 0;
 414
 415 err_sys_status:
 416         clk_disable(omap->usbtll_ick);
 417         clk_put(omap->usbtll_ick);
 418
 419 err_tll_ick:
 420         clk_disable(omap->usbtll_fck);
 421         clk_put(omap->usbtll_fck);
 422
 423 err_tll_fck:
 424         clk_disable(omap->usbhost1_48m_fck);
 425         clk_put(omap->usbhost1_48m_fck);
 426
 427         if (omap->phy_reset) {
 428                 if (gpio_is_valid(omap->reset_gpio_port[0]))
 429                         gpio_free(omap->reset_gpio_port[0]);
 430
 431                 if (gpio_is_valid(omap->reset_gpio_port[1]))
 432                         gpio_free(omap->reset_gpio_port[1]);
 433         }
 434
 435 err_host_48m_fck:
 436         clk_disable(omap->usbhost2_120m_fck);
 437         clk_put(omap->usbhost2_120m_fck);
 438
 439 err_host_120m_fck:
 440         clk_disable(omap->usbhost_ick);
 441         clk_put(omap->usbhost_ick);
 442
 443 err_host_ick:
 444         return ret;
 445 }
 446
 447 static void omap_stop_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
 448 {
 449         unsigned long timeout = jiffies + msecs_to_jiffies(100);
 450
 451         dev_dbg(omap->dev, "stopping TI EHCI USB Controller\n");
 452
 453         /* Reset OMAP modules for insmod/rmmod to work */
 454         ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG,
 455                         OMAP_UHH_SYSCONFIG_SOFTRESET);
 456         while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
 457                                 & (1 << 0))) {
 458                 cpu_relax();
 459
 460                 if (time_after(jiffies, timeout))
 461                         dev_dbg(omap->dev, "operation timed out\n");
 462         }
 463
 464         while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
 465                                 & (1 << 1))) {
 466                 cpu_relax();
 467
 468                 if (time_after(jiffies, timeout))
 469                         dev_dbg(omap->dev, "operation timed out\n");
 470         }
 471
 472         while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
 473                                 & (1 << 2))) {
 474                 cpu_relax();
 475
 476                 if (time_after(jiffies, timeout))
 477                         dev_dbg(omap->dev, "operation timed out\n");
 478         }
 479
 480         ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1));
 481
 482         while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
 483                                 & (1 << 0))) {
 484                 cpu_relax();
 485
 486                 if (time_after(jiffies, timeout))
 487                         dev_dbg(omap->dev, "operation timed out\n");
 488         }
 489
 490         if (omap->usbtll_fck != NULL) {
 491                 clk_disable(omap->usbtll_fck);
 492                 clk_put(omap->usbtll_fck);
 493                 omap->usbtll_fck = NULL;
 494         }
 495
 496         if (omap->usbhost_ick != NULL) {
 497                 clk_disable(omap->usbhost_ick);
 498                 clk_put(omap->usbhost_ick);
 499                 omap->usbhost_ick = NULL;
 500         }
 501
 502         if (omap->usbhost1_48m_fck != NULL) {
 503                 clk_disable(omap->usbhost1_48m_fck);
 504                 clk_put(omap->usbhost1_48m_fck);
 505                 omap->usbhost1_48m_fck = NULL;
 506         }
 507
 508         if (omap->usbhost2_120m_fck != NULL) {
 509                 clk_disable(omap->usbhost2_120m_fck);
 510                 clk_put(omap->usbhost2_120m_fck);
 511                 omap->usbhost2_120m_fck = NULL;
 512         }
 513
 514         if (omap->usbtll_ick != NULL) {
 515                 clk_disable(omap->usbtll_ick);
 516                 clk_put(omap->usbtll_ick);
 517                 omap->usbtll_ick = NULL;
 518         }
 519
 520         if (omap->phy_reset) {
 521                 if (gpio_is_valid(omap->reset_gpio_port[0]))
 522                         gpio_free(omap->reset_gpio_port[0]);
 523
 524                 if (gpio_is_valid(omap->reset_gpio_port[1]))
 525                         gpio_free(omap->reset_gpio_port[1]);
 526         }
 527
 528         dev_dbg(omap->dev, "Clock to USB host has been disabled\n");
 529 }
 530
 531 /*-------------------------------------------------------------------------*/
 532
 533 static const struct hc_driver ehci_omap_hc_driver;
 534
 535 /* configure so an HC device and id are always provided */
 536 /* always called with process context; sleeping is OK */
 537
 538 /**
 539  * ehci_hcd_omap_probe - initialize TI-based HCDs
 540  *
 541  * Allocates basic resources for this USB host controller, and
 542  * then invokes the start() method for the HCD associated with it
 543  * through the hotplug entry's driver_data.
 544  */
 545 static int ehci_hcd_omap_probe(struct platform_device *pdev)
 546 {
 547         struct ehci_hcd_omap_platform_data *pdata = pdev->dev.platform_data;
 548         struct ehci_hcd_omap *omap;
 549         struct resource *res;
 550         struct usb_hcd *hcd;
 551
 552         int irq = platform_get_irq(pdev, 0);
 553         int ret = -ENODEV;
 554         int i;
 555         char supply[7];
 556
 557         if (!pdata) {
 558                 dev_dbg(&pdev->dev, "missing platform_data\n");
 559                 goto err_pdata;
 560         }
 561
 562         if (usb_disabled())
 563                 goto err_disabled;
 564
 565         omap = kzalloc(sizeof(*omap), GFP_KERNEL);
 566         if (!omap) {
 567                 ret = -ENOMEM;
 568                 goto err_disabled;
 569         }
 570
 571         hcd = usb_create_hcd(&ehci_omap_hc_driver, &pdev->dev,
 572                         dev_name(&pdev->dev));
 573         if (!hcd) {
 574                 dev_dbg(&pdev->dev, "failed to create hcd with err %d\n", ret);
 575                 ret = -ENOMEM;
 576                 goto err_create_hcd;
 577         }
 578
 579         platform_set_drvdata(pdev, omap);
 580         omap->dev               = &pdev->dev;
 581         omap->phy_reset         = pdata->phy_reset;
 582         omap->reset_gpio_port[0]        = pdata->reset_gpio_port[0];
 583         omap->reset_gpio_port[1]        = pdata->reset_gpio_port[1];
 584         omap->reset_gpio_port[2]        = pdata->reset_gpio_port[2];
 585         omap->port_mode[0]              = pdata->port_mode[0];
 586         omap->port_mode[1]              = pdata->port_mode[1];
 587         omap->port_mode[2]              = pdata->port_mode[2];
 588         omap->ehci              = hcd_to_ehci(hcd);
 589         omap->ehci->sbrn        = 0x20;
 590
 591         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 592
 593         hcd->rsrc_start = res->start;
 594         hcd->rsrc_len = resource_size(res);
 595
 596         hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
 597         if (!hcd->regs) {
 598                 dev_err(&pdev->dev, "EHCI ioremap failed\n");
 599                 ret = -ENOMEM;
 600                 goto err_ioremap;
 601         }
 602
 603         /* we know this is the memory we want, no need to ioremap again */
 604         omap->ehci->caps = hcd->regs;
 605         omap->ehci_base = hcd->regs;
 606
 607         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 608         omap->uhh_base = ioremap(res->start, resource_size(res));
 609         if (!omap->uhh_base) {
 610                 dev_err(&pdev->dev, "UHH ioremap failed\n");
 611                 ret = -ENOMEM;
 612                 goto err_uhh_ioremap;
 613         }
 614
 615         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
 616         omap->tll_base = ioremap(res->start, resource_size(res));
 617         if (!omap->tll_base) {
 618                 dev_err(&pdev->dev, "TLL ioremap failed\n");
 619                 ret = -ENOMEM;
 620                 goto err_tll_ioremap;
 621         }
 622
 623         /* get ehci regulator and enable */
 624         for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) {
 625                 if (omap->port_mode[i] != EHCI_HCD_OMAP_MODE_PHY) {
 626                         omap->regulator[i] = NULL;
 627                         continue;
 628                 }
 629                 snprintf(supply, sizeof(supply), "hsusb%d", i);
 630                 omap->regulator[i] = regulator_get(omap->dev, supply);
 631                 if (IS_ERR(omap->regulator[i]))
 632                         dev_dbg(&pdev->dev,
 633                         "failed to get ehci port%d regulator\n", i);
 634                 else
 635                         regulator_enable(omap->regulator[i]);
 636         }
 637
 638         ret = omap_start_ehc(omap, hcd);
 639         if (ret) {
 640                 dev_dbg(&pdev->dev, "failed to start ehci\n");
 641                 goto err_start;
 642         }
 643
 644         omap->ehci->regs = hcd->regs
 645                 + HC_LENGTH(readl(&omap->ehci->caps->hc_capbase));
 646
 647         dbg_hcs_params(omap->ehci, "reset");
 648         dbg_hcc_params(omap->ehci, "reset");
 649
 650         /* cache this readonly data; minimize chip reads */
 651         omap->ehci->hcs_params = readl(&omap->ehci->caps->hcs_params);
 652
 653         ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
 654         if (ret) {
 655                 dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret);
 656                 goto err_add_hcd;
 657         }
 658
 659         return 0;
 660
 661 err_add_hcd:
 662         omap_stop_ehc(omap, hcd);
 663
 664 err_start:
 665         for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) {
 666                 if (omap->regulator[i]) {
 667                         regulator_disable(omap->regulator[i]);
 668                         regulator_put(omap->regulator[i]);
 669                 }
 670         }
 671         iounmap(omap->tll_base);
 672
 673 err_tll_ioremap:
 674         iounmap(omap->uhh_base);
 675
 676 err_uhh_ioremap:
 677         iounmap(hcd->regs);
 678
 679 err_ioremap:
 680         usb_put_hcd(hcd);
 681
 682 err_create_hcd:
 683         kfree(omap);
 684 err_disabled:
 685 err_pdata:
 686         return ret;
 687 }
 688
 689 /* may be called without controller electrically present */
 690 /* may be called with controller, bus, and devices active */
 691
 692 /**
 693  * ehci_hcd_omap_remove - shutdown processing for EHCI HCDs
 694  * @pdev: USB Host Controller being removed
 695  *
 696  * Reverses the effect of usb_ehci_hcd_omap_probe(), first invoking
 697  * the HCD's stop() method.  It is always called from a thread
 698  * context, normally "rmmod", "apmd", or something similar.
 699  */
 700 static int ehci_hcd_omap_remove(struct platform_device *pdev)
 701 {
 702         struct ehci_hcd_omap *omap = platform_get_drvdata(pdev);
 703         struct usb_hcd *hcd = ehci_to_hcd(omap->ehci);
 704         int i;
 705
 706         usb_remove_hcd(hcd);
 707         omap_stop_ehc(omap, hcd);
 708         iounmap(hcd->regs);
 709         for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) {
 710                 if (omap->regulator[i]) {
 711                         regulator_disable(omap->regulator[i]);
 712                         regulator_put(omap->regulator[i]);
 713                 }
 714         }
 715         iounmap(omap->tll_base);
 716         iounmap(omap->uhh_base);
 717         usb_put_hcd(hcd);
 718         kfree(omap);
 719
 720         return 0;
 721 }
 722
 723 static void ehci_hcd_omap_shutdown(struct platform_device *pdev)
 724 {
 725         struct ehci_hcd_omap *omap = platform_get_drvdata(pdev);
 726         struct usb_hcd *hcd = ehci_to_hcd(omap->ehci);
 727
 728         if (hcd->driver->shutdown)
 729                 hcd->driver->shutdown(hcd);
 730 }
 731
 732 static struct platform_driver ehci_hcd_omap_driver = {
 733         .probe                  = ehci_hcd_omap_probe,
 734         .remove                 = ehci_hcd_omap_remove,
 735         .shutdown               = ehci_hcd_omap_shutdown,
 736         /*.suspend              = ehci_hcd_omap_suspend, */
 737         /*.resume               = ehci_hcd_omap_resume, */
 738         .driver = {
 739                 .name           = "ehci-omap",
 740         }
 741 };
 742
 743 /*-------------------------------------------------------------------------*/
 744
 745 static const struct hc_driver ehci_omap_hc_driver = {
 746         .description            = hcd_name,
 747         .product_desc           = "OMAP-EHCI Host Controller",
 748         .hcd_priv_size          = sizeof(struct ehci_hcd),
 749
 750         /*
 751          * generic hardware linkage
 752          */
 753         .irq                    = ehci_irq,
 754         .flags                  = HCD_MEMORY | HCD_USB2,
 755
 756         /*
 757          * basic lifecycle operations
 758          */
 759         .reset                  = ehci_init,
 760         .start                  = ehci_run,
 761         .stop                   = ehci_stop,
 762         .shutdown               = ehci_shutdown,
 763
 764         /*
 765          * managing i/o requests and associated device resources
 766          */
 767         .urb_enqueue            = ehci_urb_enqueue,
 768         .urb_dequeue            = ehci_urb_dequeue,
 769         .endpoint_disable       = ehci_endpoint_disable,
 770         .endpoint_reset         = ehci_endpoint_reset,
 771
 772         /*
 773          * scheduling support
 774          */
 775         .get_frame_number       = ehci_get_frame,
 776
 777         /*
 778          * root hub support
 779          */
 780         .hub_status_data        = ehci_hub_status_data,
 781         .hub_control            = ehci_hub_control,
 782         .bus_suspend            = ehci_bus_suspend,
 783         .bus_resume             = ehci_bus_resume,
 784
 785         .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
 786 };
 787
 788 MODULE_ALIAS("platform:omap-ehci");
 789 MODULE_AUTHOR("Texas Instruments, Inc.");
 790 MODULE_AUTHOR("Felipe Balbi <felipe.balbi@nokia.com>");
 791