drivers/usb/host/ehci-omap.c

   1 /*
   2  * ehci-omap.c - driver for USBHOST on OMAP3/4 processors
   3  *
   4  * Bus Glue for the EHCI controllers in OMAP3/4
   5  * Tested on several OMAP3 boards, and OMAP4 Pandaboard
   6  *
   7  * Copyright (C) 2007-2010 Texas Instruments, Inc.
   8  *      Author: Vikram Pandita <vikram.pandita@ti.com>
   9  *      Author: Anand Gadiyar <gadiyar@ti.com>
  10  *
  11  * Copyright (C) 2009 Nokia Corporation
  12  *      Contact: Felipe Balbi <felipe.balbi@nokia.com>
  13  *
  14  * Based on "ehci-fsl.c" and "ehci-au1xxx.c" ehci glue layers
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  29  *
  30  * TODO (last updated Nov 21, 2010):
  31  *      - add kernel-doc
  32  *      - enable AUTOIDLE
  33  *      - add suspend/resume
  34  *      - move workarounds to board-files
  35  *      - factor out code common to OHCI
  36  *      - add HSIC and TLL support
  37  *      - convert to use hwmod and runtime PM
  38  */
  39
  40 #include <linux/platform_device.h>
  41 #include <linux/clk.h>
  42 #include <linux/gpio.h>
  43 #include <linux/regulator/consumer.h>
  44 #include <linux/slab.h>
  45 #include <linux/usb/ulpi.h>
  46 #include <plat/usb.h>
  47
  48 /*
  49  * OMAP USBHOST Register addresses: VIRTUAL ADDRESSES
  50  *      Use ehci_omap_readl()/ehci_omap_writel() functions
  51  */
  52
  53 /* TLL Register Set */
  54 #define OMAP_USBTLL_REVISION                            (0x00)
  55 #define OMAP_USBTLL_SYSCONFIG                           (0x10)
  56 #define OMAP_USBTLL_SYSCONFIG_CACTIVITY                 (1 << 8)
  57 #define OMAP_USBTLL_SYSCONFIG_SIDLEMODE                 (1 << 3)
  58 #define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP                 (1 << 2)
  59 #define OMAP_USBTLL_SYSCONFIG_SOFTRESET                 (1 << 1)
  60 #define OMAP_USBTLL_SYSCONFIG_AUTOIDLE                  (1 << 0)
  61
  62 #define OMAP_USBTLL_SYSSTATUS                           (0x14)
  63 #define OMAP_USBTLL_SYSSTATUS_RESETDONE                 (1 << 0)
  64
  65 #define OMAP_USBTLL_IRQSTATUS                           (0x18)
  66 #define OMAP_USBTLL_IRQENABLE                           (0x1C)
  67
  68 #define OMAP_TLL_SHARED_CONF                            (0x30)
  69 #define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN             (1 << 6)
  70 #define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN            (1 << 5)
  71 #define OMAP_TLL_SHARED_CONF_USB_DIVRATION              (1 << 2)
  72 #define OMAP_TLL_SHARED_CONF_FCLK_REQ                   (1 << 1)
  73 #define OMAP_TLL_SHARED_CONF_FCLK_IS_ON                 (1 << 0)
  74
  75 #define OMAP_TLL_CHANNEL_CONF(num)                      (0x040 + 0x004 * num)
  76 #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF            (1 << 11)
  77 #define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE         (1 << 10)
  78 #define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE              (1 << 9)
  79 #define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE               (1 << 8)
  80 #define OMAP_TLL_CHANNEL_CONF_CHANEN                    (1 << 0)
  81
  82 #define OMAP_TLL_ULPI_FUNCTION_CTRL(num)                (0x804 + 0x100 * num)
  83 #define OMAP_TLL_ULPI_INTERFACE_CTRL(num)               (0x807 + 0x100 * num)
  84 #define OMAP_TLL_ULPI_OTG_CTRL(num)                     (0x80A + 0x100 * num)
  85 #define OMAP_TLL_ULPI_INT_EN_RISE(num)                  (0x80D + 0x100 * num)
  86 #define OMAP_TLL_ULPI_INT_EN_FALL(num)                  (0x810 + 0x100 * num)
  87 #define OMAP_TLL_ULPI_INT_STATUS(num)                   (0x813 + 0x100 * num)
  88 #define OMAP_TLL_ULPI_INT_LATCH(num)                    (0x814 + 0x100 * num)
  89 #define OMAP_TLL_ULPI_DEBUG(num)                        (0x815 + 0x100 * num)
  90 #define OMAP_TLL_ULPI_SCRATCH_REGISTER(num)             (0x816 + 0x100 * num)
  91
  92 #define OMAP_TLL_CHANNEL_COUNT                          3
  93 #define OMAP_TLL_CHANNEL_1_EN_MASK                      (1 << 0)
  94 #define OMAP_TLL_CHANNEL_2_EN_MASK                      (1 << 1)
  95 #define OMAP_TLL_CHANNEL_3_EN_MASK                      (1 << 2)
  96
  97 /* UHH Register Set */
  98 #define OMAP_UHH_REVISION                               (0x00)
  99 #define OMAP_UHH_SYSCONFIG                              (0x10)
 100 #define OMAP_UHH_SYSCONFIG_MIDLEMODE                    (1 << 12)
 101 #define OMAP_UHH_SYSCONFIG_CACTIVITY                    (1 << 8)
 102 #define OMAP_UHH_SYSCONFIG_SIDLEMODE                    (1 << 3)
 103 #define OMAP_UHH_SYSCONFIG_ENAWAKEUP                    (1 << 2)
 104 #define OMAP_UHH_SYSCONFIG_SOFTRESET                    (1 << 1)
 105 #define OMAP_UHH_SYSCONFIG_AUTOIDLE                     (1 << 0)
 106
 107 #define OMAP_UHH_SYSSTATUS                              (0x14)
 108 #define OMAP_UHH_HOSTCONFIG                             (0x40)
 109 #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS                 (1 << 0)
 110 #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS              (1 << 0)
 111 #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS              (1 << 11)
 112 #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS              (1 << 12)
 113 #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN              (1 << 2)
 114 #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN              (1 << 3)
 115 #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN             (1 << 4)
 116 #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN              (1 << 5)
 117 #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS           (1 << 8)
 118 #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS           (1 << 9)
 119 #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS           (1 << 10)
 120
 121 /* OMAP4-specific defines */
 122 #define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR              (3 << 2)
 123 #define OMAP4_UHH_SYSCONFIG_NOIDLE                      (1 << 2)
 124
 125 #define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR             (3 << 4)
 126 #define OMAP4_UHH_SYSCONFIG_NOSTDBY                     (1 << 4)
 127 #define OMAP4_UHH_SYSCONFIG_SOFTRESET                   (1 << 0)
 128
 129 #define OMAP4_P1_MODE_CLEAR                             (3 << 16)
 130 #define OMAP4_P1_MODE_TLL                               (1 << 16)
 131 #define OMAP4_P1_MODE_HSIC                              (3 << 16)
 132 #define OMAP4_P2_MODE_CLEAR                             (3 << 18)
 133 #define OMAP4_P2_MODE_TLL                               (1 << 18)
 134 #define OMAP4_P2_MODE_HSIC                              (3 << 18)
 135
 136 #define OMAP_REV2_TLL_CHANNEL_COUNT                     2
 137
 138 #define OMAP_UHH_DEBUG_CSR                              (0x44)
 139
 140 /* EHCI Register Set */
 141 #define EHCI_INSNREG04                                  (0xA0)
 142 #define EHCI_INSNREG04_DISABLE_UNSUSPEND                (1 << 5)
 143 #define EHCI_INSNREG05_ULPI                             (0xA4)
 144 #define EHCI_INSNREG05_ULPI_CONTROL_SHIFT               31
 145 #define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT               24
 146 #define EHCI_INSNREG05_ULPI_OPSEL_SHIFT                 22
 147 #define EHCI_INSNREG05_ULPI_REGADD_SHIFT                16
 148 #define EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT             8
 149 #define EHCI_INSNREG05_ULPI_WRDATA_SHIFT                0
 150
 151 /* Values of UHH_REVISION - Note: these are not given in the TRM */
 152 #define OMAP_EHCI_REV1  0x00000010      /* OMAP3 */
 153 #define OMAP_EHCI_REV2  0x50700100      /* OMAP4 */
 154
 155 #define is_omap_ehci_rev1(x)    (x->omap_ehci_rev == OMAP_EHCI_REV1)
 156 #define is_omap_ehci_rev2(x)    (x->omap_ehci_rev == OMAP_EHCI_REV2)
 157
 158 #define is_ehci_phy_mode(x)     (x == EHCI_HCD_OMAP_MODE_PHY)
 159 #define is_ehci_tll_mode(x)     (x == EHCI_HCD_OMAP_MODE_TLL)
 160 #define is_ehci_hsic_mode(x)    (x == EHCI_HCD_OMAP_MODE_HSIC)
 161
 162 /*-------------------------------------------------------------------------*/
 163
 164 static inline void ehci_omap_writel(void __iomem *base, u32 reg, u32 val)
 165 {
 166         __raw_writel(val, base + reg);
 167 }
 168
 169 static inline u32 ehci_omap_readl(void __iomem *base, u32 reg)
 170 {
 171         return __raw_readl(base + reg);
 172 }
 173
 174 static inline void ehci_omap_writeb(void __iomem *base, u8 reg, u8 val)
 175 {
 176         __raw_writeb(val, base + reg);
 177 }
 178
 179 static inline u8 ehci_omap_readb(void __iomem *base, u8 reg)
 180 {
 181         return __raw_readb(base + reg);
 182 }
 183
 184 /*-------------------------------------------------------------------------*/
 185
 186 struct ehci_hcd_omap {
 187         struct ehci_hcd         *ehci;
 188         struct device           *dev;
 189
 190         struct clk              *usbhost_ick;
 191         struct clk              *usbhost_hs_fck;
 192         struct clk              *usbhost_fs_fck;
 193         struct clk              *usbtll_fck;
 194         struct clk              *usbtll_ick;
 195         struct clk              *xclk60mhsp1_ck;
 196         struct clk              *xclk60mhsp2_ck;
 197         struct clk              *utmi_p1_fck;
 198         struct clk              *utmi_p2_fck;
 199
 200         /* FIXME the following two workarounds are
 201          * board specific not silicon-specific so these
 202          * should be moved to board-file instead.
 203          *
 204          * Maybe someone from TI will know better which
 205          * board is affected and needs the workarounds
 206          * to be applied
 207          */
 208
 209         /* gpio for resetting phy */
 210         int                     reset_gpio_port[OMAP3_HS_USB_PORTS];
 211
 212         /* phy reset workaround */
 213         int                     phy_reset;
 214
 215         /* IP revision */
 216         u32                     omap_ehci_rev;
 217
 218         /* desired phy_mode: TLL, PHY */
 219         enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
 220
 221         void __iomem            *uhh_base;
 222         void __iomem            *tll_base;
 223         void __iomem            *ehci_base;
 224
 225         /* Regulators for USB PHYs.
 226          * Each PHY can have a separate regulator.
 227          */
 228         struct regulator        *regulator[OMAP3_HS_USB_PORTS];
 229 };
 230
 231 /*-------------------------------------------------------------------------*/
 232
 233 static void omap_usb_utmi_init(struct ehci_hcd_omap *omap, u8 tll_channel_mask,
 234                                 u8 tll_channel_count)
 235 {
 236         unsigned reg;
 237         int i;
 238
 239         /* Program the 3 TLL channels upfront */
 240         for (i = 0; i < tll_channel_count; i++) {
 241                 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
 242
 243                 /* Disable AutoIdle, BitStuffing and use SDR Mode */
 244                 reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
 245                                 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
 246                                 | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
 247                 ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
 248         }
 249
 250         /* Program Common TLL register */
 251         reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF);
 252         reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
 253                         | OMAP_TLL_SHARED_CONF_USB_DIVRATION
 254                         | OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN);
 255         reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
 256
 257         ehci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
 258
 259         /* Enable channels now */
 260         for (i = 0; i < tll_channel_count; i++) {
 261                 reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
 262
 263                 /* Enable only the reg that is needed */
 264                 if (!(tll_channel_mask & 1<<i))
 265                         continue;
 266
 267                 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
 268                 ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
 269
 270                 ehci_omap_writeb(omap->tll_base,
 271                                 OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe);
 272                 dev_dbg(omap->dev, "ULPI_SCRATCH_REG[ch=%d]= 0x%02x\n",
 273                                 i+1, ehci_omap_readb(omap->tll_base,
 274                                 OMAP_TLL_ULPI_SCRATCH_REGISTER(i)));
 275         }
 276 }
 277
 278 /*-------------------------------------------------------------------------*/
 279
 280 static void omap_ehci_soft_phy_reset(struct ehci_hcd_omap *omap, u8 port)
 281 {
 282         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 283         unsigned reg = 0;
 284
 285         reg = ULPI_FUNC_CTRL_RESET
 286                 /* FUNCTION_CTRL_SET register */
 287                 | (ULPI_SET(ULPI_FUNC_CTRL) << EHCI_INSNREG05_ULPI_REGADD_SHIFT)
 288                 /* Write */
 289                 | (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT)
 290                 /* PORTn */
 291                 | ((port + 1) << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT)
 292                 /* start ULPI access*/
 293                 | (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT);
 294
 295         ehci_omap_writel(omap->ehci_base, EHCI_INSNREG05_ULPI, reg);
 296
 297         /* Wait for ULPI access completion */
 298         while ((ehci_omap_readl(omap->ehci_base, EHCI_INSNREG05_ULPI)
 299                         & (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT))) {
 300                 cpu_relax();
 301
 302                 if (time_after(jiffies, timeout)) {
 303                         dev_dbg(omap->dev, "phy reset operation timed out\n");
 304                         break;
 305                 }
 306         }
 307 }
 308
 309 /* omap_start_ehc
 310  *      - Start the TI USBHOST controller
 311  */
 312 static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
 313 {
 314         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 315         u8 tll_ch_mask = 0;
 316         unsigned reg = 0;
 317         int ret = 0;
 318
 319         dev_dbg(omap->dev, "starting TI EHCI USB Controller\n");
 320
 321         /* Enable Clocks for USBHOST */
 322         omap->usbhost_ick = clk_get(omap->dev, "usbhost_ick");
 323         if (IS_ERR(omap->usbhost_ick)) {
 324                 ret =  PTR_ERR(omap->usbhost_ick);
 325                 goto err_host_ick;
 326         }
 327         clk_enable(omap->usbhost_ick);
 328
 329         omap->usbhost_hs_fck = clk_get(omap->dev, "hs_fck");
 330         if (IS_ERR(omap->usbhost_hs_fck)) {
 331                 ret = PTR_ERR(omap->usbhost_hs_fck);
 332                 goto err_host_120m_fck;
 333         }
 334         clk_enable(omap->usbhost_hs_fck);
 335
 336         omap->usbhost_fs_fck = clk_get(omap->dev, "fs_fck");
 337         if (IS_ERR(omap->usbhost_fs_fck)) {
 338                 ret = PTR_ERR(omap->usbhost_fs_fck);
 339                 goto err_host_48m_fck;
 340         }
 341         clk_enable(omap->usbhost_fs_fck);
 342
 343         if (omap->phy_reset) {
 344                 /* Refer: ISSUE1 */
 345                 if (gpio_is_valid(omap->reset_gpio_port[0])) {
 346                         gpio_request(omap->reset_gpio_port[0],
 347                                                 "USB1 PHY reset");
 348                         gpio_direction_output(omap->reset_gpio_port[0], 0);
 349                 }
 350
 351                 if (gpio_is_valid(omap->reset_gpio_port[1])) {
 352                         gpio_request(omap->reset_gpio_port[1],
 353                                                 "USB2 PHY reset");
 354                         gpio_direction_output(omap->reset_gpio_port[1], 0);
 355                 }
 356
 357                 /* Hold the PHY in RESET for enough time till DIR is high */
 358                 udelay(10);
 359         }
 360
 361         /* Configure TLL for 60Mhz clk for ULPI */
 362         omap->usbtll_fck = clk_get(omap->dev, "usbtll_fck");
 363         if (IS_ERR(omap->usbtll_fck)) {
 364                 ret = PTR_ERR(omap->usbtll_fck);
 365                 goto err_tll_fck;
 366         }
 367         clk_enable(omap->usbtll_fck);
 368
 369         omap->usbtll_ick = clk_get(omap->dev, "usbtll_ick");
 370         if (IS_ERR(omap->usbtll_ick)) {
 371                 ret = PTR_ERR(omap->usbtll_ick);
 372                 goto err_tll_ick;
 373         }
 374         clk_enable(omap->usbtll_ick);
 375
 376         omap->omap_ehci_rev = ehci_omap_readl(omap->uhh_base,
 377                                                 OMAP_UHH_REVISION);
 378         dev_dbg(omap->dev, "OMAP UHH_REVISION 0x%x\n",
 379                                         omap->omap_ehci_rev);
 380
 381         /*
 382          * Enable per-port clocks as needed (newer controllers only).
 383          * - External ULPI clock for PHY mode
 384          * - Internal clocks for TLL and HSIC modes (TODO)
 385          */
 386         if (is_omap_ehci_rev2(omap)) {
 387                 switch (omap->port_mode[0]) {
 388                 case EHCI_HCD_OMAP_MODE_PHY:
 389                         omap->xclk60mhsp1_ck = clk_get(omap->dev,
 390                                                         "xclk60mhsp1_ck");
 391                         if (IS_ERR(omap->xclk60mhsp1_ck)) {
 392                                 ret = PTR_ERR(omap->xclk60mhsp1_ck);
 393                                 dev_err(omap->dev,
 394                                         "Unable to get Port1 ULPI clock\n");
 395                         }
 396
 397                         omap->utmi_p1_fck = clk_get(omap->dev,
 398                                                         "utmi_p1_gfclk");
 399                         if (IS_ERR(omap->utmi_p1_fck)) {
 400                                 ret = PTR_ERR(omap->utmi_p1_fck);
 401                                 dev_err(omap->dev,
 402                                         "Unable to get utmi_p1_fck\n");
 403                         }
 404
 405                         ret = clk_set_parent(omap->utmi_p1_fck,
 406                                                 omap->xclk60mhsp1_ck);
 407                         if (ret != 0) {
 408                                 dev_err(omap->dev,
 409                                         "Unable to set P1 f-clock\n");
 410                         }
 411                         break;
 412                 case EHCI_HCD_OMAP_MODE_TLL:
 413                         /* TODO */
 414                 default:
 415                         break;
 416                 }
 417                 switch (omap->port_mode[1]) {
 418                 case EHCI_HCD_OMAP_MODE_PHY:
 419                         omap->xclk60mhsp2_ck = clk_get(omap->dev,
 420                                                         "xclk60mhsp2_ck");
 421                         if (IS_ERR(omap->xclk60mhsp2_ck)) {
 422                                 ret = PTR_ERR(omap->xclk60mhsp2_ck);
 423                                 dev_err(omap->dev,
 424                                         "Unable to get Port2 ULPI clock\n");
 425                         }
 426
 427                         omap->utmi_p2_fck = clk_get(omap->dev,
 428                                                         "utmi_p2_gfclk");
 429                         if (IS_ERR(omap->utmi_p2_fck)) {
 430                                 ret = PTR_ERR(omap->utmi_p2_fck);
 431                                 dev_err(omap->dev,
 432                                         "Unable to get utmi_p2_fck\n");
 433                         }
 434
 435                         ret = clk_set_parent(omap->utmi_p2_fck,
 436                                                 omap->xclk60mhsp2_ck);
 437                         if (ret != 0) {
 438                                 dev_err(omap->dev,
 439                                         "Unable to set P2 f-clock\n");
 440                         }
 441                         break;
 442                 case EHCI_HCD_OMAP_MODE_TLL:
 443                         /* TODO */
 444                 default:
 445                         break;
 446                 }
 447         }
 448
 449
 450         /* perform TLL soft reset, and wait until reset is complete */
 451         ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
 452                         OMAP_USBTLL_SYSCONFIG_SOFTRESET);
 453
 454         /* Wait for TLL reset to complete */
 455         while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
 456                         & OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
 457                 cpu_relax();
 458
 459                 if (time_after(jiffies, timeout)) {
 460                         dev_dbg(omap->dev, "operation timed out\n");
 461                         ret = -EINVAL;
 462                         goto err_sys_status;
 463                 }
 464         }
 465
 466         dev_dbg(omap->dev, "TLL RESET DONE\n");
 467
 468         /* (1<<3) = no idle mode only for initial debugging */
 469         ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
 470                         OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
 471                         OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
 472                         OMAP_USBTLL_SYSCONFIG_CACTIVITY);
 473
 474
 475         /* Put UHH in NoIdle/NoStandby mode */
 476         reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
 477         if (is_omap_ehci_rev1(omap)) {
 478                 reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
 479                                 | OMAP_UHH_SYSCONFIG_SIDLEMODE
 480                                 | OMAP_UHH_SYSCONFIG_CACTIVITY
 481                                 | OMAP_UHH_SYSCONFIG_MIDLEMODE);
 482                 reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
 483
 484
 485         } else if (is_omap_ehci_rev2(omap)) {
 486                 reg &= ~OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR;
 487                 reg |= OMAP4_UHH_SYSCONFIG_NOIDLE;
 488                 reg &= ~OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR;
 489                 reg |= OMAP4_UHH_SYSCONFIG_NOSTDBY;
 490         }
 491         ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
 492
 493         reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
 494
 495         /* setup ULPI bypass and burst configurations */
 496         reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
 497                         | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
 498                         | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
 499         reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
 500
 501         if (is_omap_ehci_rev1(omap)) {
 502                 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN)
 503                         reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
 504                 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN)
 505                         reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
 506                 if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN)
 507                         reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
 508
 509                 /* Bypass the TLL module for PHY mode operation */
 510                 if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) {
 511                         dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1\n");
 512                         if (is_ehci_phy_mode(omap->port_mode[0]) ||
 513                                 is_ehci_phy_mode(omap->port_mode[1]) ||
 514                                         is_ehci_phy_mode(omap->port_mode[2]))
 515                                 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
 516                         else
 517                                 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
 518                 } else {
 519                         dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n");
 520                         if (is_ehci_phy_mode(omap->port_mode[0]))
 521                                 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
 522                         else if (is_ehci_tll_mode(omap->port_mode[0]))
 523                                 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
 524
 525                         if (is_ehci_phy_mode(omap->port_mode[1]))
 526                                 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
 527                         else if (is_ehci_tll_mode(omap->port_mode[1]))
 528                                 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
 529
 530                         if (is_ehci_phy_mode(omap->port_mode[2]))
 531                                 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
 532                         else if (is_ehci_tll_mode(omap->port_mode[2]))
 533                                 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
 534                 }
 535         } else if (is_omap_ehci_rev2(omap)) {
 536                 /* Clear port mode fields for PHY mode*/
 537                 reg &= ~OMAP4_P1_MODE_CLEAR;
 538                 reg &= ~OMAP4_P2_MODE_CLEAR;
 539
 540                 if (is_ehci_tll_mode(omap->port_mode[0]))
 541                         reg |= OMAP4_P1_MODE_TLL;
 542                 else if (is_ehci_hsic_mode(omap->port_mode[0]))
 543                         reg |= OMAP4_P1_MODE_HSIC;
 544
 545                 if (is_ehci_tll_mode(omap->port_mode[1]))
 546                         reg |= OMAP4_P2_MODE_TLL;
 547                 else if (is_ehci_hsic_mode(omap->port_mode[1]))
 548                         reg |= OMAP4_P2_MODE_HSIC;
 549         }
 550
 551         ehci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
 552         dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
 553
 554
 555         /*
 556          * An undocumented "feature" in the OMAP3 EHCI controller,
 557          * causes suspended ports to be taken out of suspend when
 558          * the USBCMD.Run/Stop bit is cleared (for example when
 559          * we do ehci_bus_suspend).
 560          * This breaks suspend-resume if the root-hub is allowed
 561          * to suspend. Writing 1 to this undocumented register bit
 562          * disables this feature and restores normal behavior.
 563          */
 564         ehci_omap_writel(omap->ehci_base, EHCI_INSNREG04,
 565                                 EHCI_INSNREG04_DISABLE_UNSUSPEND);
 566
 567         if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) ||
 568                 (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) ||
 569                         (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)) {
 570
 571                 if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
 572                         tll_ch_mask |= OMAP_TLL_CHANNEL_1_EN_MASK;
 573                 if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
 574                         tll_ch_mask |= OMAP_TLL_CHANNEL_2_EN_MASK;
 575                 if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
 576                         tll_ch_mask |= OMAP_TLL_CHANNEL_3_EN_MASK;
 577
 578                 /* Enable UTMI mode for required TLL channels */
 579                 omap_usb_utmi_init(omap, tll_ch_mask, OMAP_TLL_CHANNEL_COUNT);
 580         }
 581
 582         if (omap->phy_reset) {
 583                 /* Refer ISSUE1:
 584                  * Hold the PHY in RESET for enough time till
 585                  * PHY is settled and ready
 586                  */
 587                 udelay(10);
 588
 589                 if (gpio_is_valid(omap->reset_gpio_port[0]))
 590                         gpio_set_value(omap->reset_gpio_port[0], 1);
 591
 592                 if (gpio_is_valid(omap->reset_gpio_port[1]))
 593                         gpio_set_value(omap->reset_gpio_port[1], 1);
 594         }
 595
 596         /* Soft reset the PHY using PHY reset command over ULPI */
 597         if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY)
 598                 omap_ehci_soft_phy_reset(omap, 0);
 599         if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY)
 600                 omap_ehci_soft_phy_reset(omap, 1);
 601
 602         return 0;
 603
 604 err_sys_status:
 605         clk_disable(omap->utmi_p2_fck);
 606         clk_put(omap->utmi_p2_fck);
 607         clk_disable(omap->xclk60mhsp2_ck);
 608         clk_put(omap->xclk60mhsp2_ck);
 609         clk_disable(omap->utmi_p1_fck);
 610         clk_put(omap->utmi_p1_fck);
 611         clk_disable(omap->xclk60mhsp1_ck);
 612         clk_put(omap->xclk60mhsp1_ck);
 613         clk_disable(omap->usbtll_ick);
 614         clk_put(omap->usbtll_ick);
 615
 616 err_tll_ick:
 617         clk_disable(omap->usbtll_fck);
 618         clk_put(omap->usbtll_fck);
 619
 620 err_tll_fck:
 621         clk_disable(omap->usbhost_fs_fck);
 622         clk_put(omap->usbhost_fs_fck);
 623
 624         if (omap->phy_reset) {
 625                 if (gpio_is_valid(omap->reset_gpio_port[0]))
 626                         gpio_free(omap->reset_gpio_port[0]);
 627
 628                 if (gpio_is_valid(omap->reset_gpio_port[1]))
 629                         gpio_free(omap->reset_gpio_port[1]);
 630         }
 631
 632 err_host_48m_fck:
 633         clk_disable(omap->usbhost_hs_fck);
 634         clk_put(omap->usbhost_hs_fck);
 635
 636 err_host_120m_fck:
 637         clk_disable(omap->usbhost_ick);
 638         clk_put(omap->usbhost_ick);
 639
 640 err_host_ick:
 641         return ret;
 642 }
 643
 644 static void omap_stop_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
 645 {
 646         unsigned long timeout = jiffies + msecs_to_jiffies(100);
 647
 648         dev_dbg(omap->dev, "stopping TI EHCI USB Controller\n");
 649
 650         /* Reset OMAP modules for insmod/rmmod to work */
 651         ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG,
 652                         is_omap_ehci_rev2(omap) ?
 653                         OMAP4_UHH_SYSCONFIG_SOFTRESET :
 654                         OMAP_UHH_SYSCONFIG_SOFTRESET);
 655         while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
 656                                 & (1 << 0))) {
 657                 cpu_relax();
 658
 659                 if (time_after(jiffies, timeout))
 660                         dev_dbg(omap->dev, "operation timed out\n");
 661         }
 662
 663         while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
 664                                 & (1 << 1))) {
 665                 cpu_relax();
 666
 667                 if (time_after(jiffies, timeout))
 668                         dev_dbg(omap->dev, "operation timed out\n");
 669         }
 670
 671         while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
 672                                 & (1 << 2))) {
 673                 cpu_relax();
 674
 675                 if (time_after(jiffies, timeout))
 676                         dev_dbg(omap->dev, "operation timed out\n");
 677         }
 678
 679         ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1));
 680
 681         while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
 682                                 & (1 << 0))) {
 683                 cpu_relax();
 684
 685                 if (time_after(jiffies, timeout))
 686                         dev_dbg(omap->dev, "operation timed out\n");
 687         }
 688
 689         if (omap->usbtll_fck != NULL) {
 690                 clk_disable(omap->usbtll_fck);
 691                 clk_put(omap->usbtll_fck);
 692                 omap->usbtll_fck = NULL;
 693         }
 694
 695         if (omap->usbhost_ick != NULL) {
 696                 clk_disable(omap->usbhost_ick);
 697                 clk_put(omap->usbhost_ick);
 698                 omap->usbhost_ick = NULL;
 699         }
 700
 701         if (omap->usbhost_fs_fck != NULL) {
 702                 clk_disable(omap->usbhost_fs_fck);
 703                 clk_put(omap->usbhost_fs_fck);
 704                 omap->usbhost_fs_fck = NULL;
 705         }
 706
 707         if (omap->usbhost_hs_fck != NULL) {
 708                 clk_disable(omap->usbhost_hs_fck);
 709                 clk_put(omap->usbhost_hs_fck);
 710                 omap->usbhost_hs_fck = NULL;
 711         }
 712
 713         if (omap->usbtll_ick != NULL) {
 714                 clk_disable(omap->usbtll_ick);
 715                 clk_put(omap->usbtll_ick);
 716                 omap->usbtll_ick = NULL;
 717         }
 718
 719         if (is_omap_ehci_rev2(omap)) {
 720                 if (omap->xclk60mhsp1_ck != NULL) {
 721                         clk_disable(omap->xclk60mhsp1_ck);
 722                         clk_put(omap->xclk60mhsp1_ck);
 723                         omap->xclk60mhsp1_ck = NULL;
 724                 }
 725
 726                 if (omap->utmi_p1_fck != NULL) {
 727                         clk_disable(omap->utmi_p1_fck);
 728                         clk_put(omap->utmi_p1_fck);
 729                         omap->utmi_p1_fck = NULL;
 730                 }
 731
 732                 if (omap->xclk60mhsp2_ck != NULL) {
 733                         clk_disable(omap->xclk60mhsp2_ck);
 734                         clk_put(omap->xclk60mhsp2_ck);
 735                         omap->xclk60mhsp2_ck = NULL;
 736                 }
 737
 738                 if (omap->utmi_p2_fck != NULL) {
 739                         clk_disable(omap->utmi_p2_fck);
 740                         clk_put(omap->utmi_p2_fck);
 741                         omap->utmi_p2_fck = NULL;
 742                 }
 743         }
 744
 745         if (omap->phy_reset) {
 746                 if (gpio_is_valid(omap->reset_gpio_port[0]))
 747                         gpio_free(omap->reset_gpio_port[0]);
 748
 749                 if (gpio_is_valid(omap->reset_gpio_port[1]))
 750                         gpio_free(omap->reset_gpio_port[1]);
 751         }
 752
 753         dev_dbg(omap->dev, "Clock to USB host has been disabled\n");
 754 }
 755
 756 /*-------------------------------------------------------------------------*/
 757
 758 static const struct hc_driver ehci_omap_hc_driver;
 759
 760 /* configure so an HC device and id are always provided */
 761 /* always called with process context; sleeping is OK */
 762
 763 /**
 764  * ehci_hcd_omap_probe - initialize TI-based HCDs
 765  *
 766  * Allocates basic resources for this USB host controller, and
 767  * then invokes the start() method for the HCD associated with it
 768  * through the hotplug entry's driver_data.
 769  */
 770 static int ehci_hcd_omap_probe(struct platform_device *pdev)
 771 {
 772         struct ehci_hcd_omap_platform_data *pdata = pdev->dev.platform_data;
 773         struct ehci_hcd_omap *omap;
 774         struct resource *res;
 775         struct usb_hcd *hcd;
 776
 777         int irq = platform_get_irq(pdev, 0);
 778         int ret = -ENODEV;
 779         int i;
 780         char supply[7];
 781
 782         if (!pdata) {
 783                 dev_dbg(&pdev->dev, "missing platform_data\n");
 784                 goto err_pdata;
 785         }
 786
 787         if (usb_disabled())
 788                 goto err_disabled;
 789
 790         omap = kzalloc(sizeof(*omap), GFP_KERNEL);
 791         if (!omap) {
 792                 ret = -ENOMEM;
 793                 goto err_disabled;
 794         }
 795
 796         hcd = usb_create_hcd(&ehci_omap_hc_driver, &pdev->dev,
 797                         dev_name(&pdev->dev));
 798         if (!hcd) {
 799                 dev_err(&pdev->dev, "failed to create hcd with err %d\n", ret);
 800                 ret = -ENOMEM;
 801                 goto err_create_hcd;
 802         }
 803
 804         platform_set_drvdata(pdev, omap);
 805         omap->dev               = &pdev->dev;
 806         omap->phy_reset         = pdata->phy_reset;
 807         omap->reset_gpio_port[0]        = pdata->reset_gpio_port[0];
 808         omap->reset_gpio_port[1]        = pdata->reset_gpio_port[1];
 809         omap->reset_gpio_port[2]        = pdata->reset_gpio_port[2];
 810         omap->port_mode[0]              = pdata->port_mode[0];
 811         omap->port_mode[1]              = pdata->port_mode[1];
 812         omap->port_mode[2]              = pdata->port_mode[2];
 813         omap->ehci              = hcd_to_ehci(hcd);
 814         omap->ehci->sbrn        = 0x20;
 815
 816         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 817
 818         hcd->rsrc_start = res->start;
 819         hcd->rsrc_len = resource_size(res);
 820
 821         hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
 822         if (!hcd->regs) {
 823                 dev_err(&pdev->dev, "EHCI ioremap failed\n");
 824                 ret = -ENOMEM;
 825                 goto err_ioremap;
 826         }
 827
 828         /* we know this is the memory we want, no need to ioremap again */
 829         omap->ehci->caps = hcd->regs;
 830         omap->ehci_base = hcd->regs;
 831
 832         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 833         omap->uhh_base = ioremap(res->start, resource_size(res));
 834         if (!omap->uhh_base) {
 835                 dev_err(&pdev->dev, "UHH ioremap failed\n");
 836                 ret = -ENOMEM;
 837                 goto err_uhh_ioremap;
 838         }
 839
 840         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
 841         omap->tll_base = ioremap(res->start, resource_size(res));
 842         if (!omap->tll_base) {
 843                 dev_err(&pdev->dev, "TLL ioremap failed\n");
 844                 ret = -ENOMEM;
 845                 goto err_tll_ioremap;
 846         }
 847
 848         /* get ehci regulator and enable */
 849         for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) {
 850                 if (omap->port_mode[i] != EHCI_HCD_OMAP_MODE_PHY) {
 851                         omap->regulator[i] = NULL;
 852                         continue;
 853                 }
 854                 snprintf(supply, sizeof(supply), "hsusb%d", i);
 855                 omap->regulator[i] = regulator_get(omap->dev, supply);
 856                 if (IS_ERR(omap->regulator[i])) {
 857                         omap->regulator[i] = NULL;
 858                         dev_dbg(&pdev->dev,
 859                         "failed to get ehci port%d regulator\n", i);
 860                 } else {
 861                         regulator_enable(omap->regulator[i]);
 862                 }
 863         }
 864
 865         ret = omap_start_ehc(omap, hcd);
 866         if (ret) {
 867                 dev_err(&pdev->dev, "failed to start ehci with err %d\n", ret);
 868                 goto err_start;
 869         }
 870
 871         omap->ehci->regs = hcd->regs
 872                 + HC_LENGTH(readl(&omap->ehci->caps->hc_capbase));
 873
 874         dbg_hcs_params(omap->ehci, "reset");
 875         dbg_hcc_params(omap->ehci, "reset");
 876
 877         /* cache this readonly data; minimize chip reads */
 878         omap->ehci->hcs_params = readl(&omap->ehci->caps->hcs_params);
 879
 880         ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
 881         if (ret) {
 882                 dev_err(&pdev->dev, "failed to add hcd with err %d\n", ret);
 883                 goto err_add_hcd;
 884         }
 885
 886         /* root ports should always stay powered */
 887         ehci_port_power(omap->ehci, 1);
 888
 889         return 0;
 890
 891 err_add_hcd:
 892         omap_stop_ehc(omap, hcd);
 893
 894 err_start:
 895         for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) {
 896                 if (omap->regulator[i]) {
 897                         regulator_disable(omap->regulator[i]);
 898                         regulator_put(omap->regulator[i]);
 899                 }
 900         }
 901         iounmap(omap->tll_base);
 902
 903 err_tll_ioremap:
 904         iounmap(omap->uhh_base);
 905
 906 err_uhh_ioremap:
 907         iounmap(hcd->regs);
 908
 909 err_ioremap:
 910         usb_put_hcd(hcd);
 911
 912 err_create_hcd:
 913         kfree(omap);
 914 err_disabled:
 915 err_pdata:
 916         return ret;
 917 }
 918
 919 /* may be called without controller electrically present */
 920 /* may be called with controller, bus, and devices active */
 921
 922 /**
 923  * ehci_hcd_omap_remove - shutdown processing for EHCI HCDs
 924  * @pdev: USB Host Controller being removed
 925  *
 926  * Reverses the effect of usb_ehci_hcd_omap_probe(), first invoking
 927  * the HCD's stop() method.  It is always called from a thread
 928  * context, normally "rmmod", "apmd", or something similar.
 929  */
 930 static int ehci_hcd_omap_remove(struct platform_device *pdev)
 931 {
 932         struct ehci_hcd_omap *omap = platform_get_drvdata(pdev);
 933         struct usb_hcd *hcd = ehci_to_hcd(omap->ehci);
 934         int i;
 935
 936         usb_remove_hcd(hcd);
 937         omap_stop_ehc(omap, hcd);
 938         iounmap(hcd->regs);
 939         for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) {
 940                 if (omap->regulator[i]) {
 941                         regulator_disable(omap->regulator[i]);
 942                         regulator_put(omap->regulator[i]);
 943                 }
 944         }
 945         iounmap(omap->tll_base);
 946         iounmap(omap->uhh_base);
 947         usb_put_hcd(hcd);
 948         kfree(omap);
 949
 950         return 0;
 951 }
 952
 953 static void ehci_hcd_omap_shutdown(struct platform_device *pdev)
 954 {
 955         struct ehci_hcd_omap *omap = platform_get_drvdata(pdev);
 956         struct usb_hcd *hcd = ehci_to_hcd(omap->ehci);
 957
 958         if (hcd->driver->shutdown)
 959                 hcd->driver->shutdown(hcd);
 960 }
 961
 962 static struct platform_driver ehci_hcd_omap_driver = {
 963         .probe                  = ehci_hcd_omap_probe,
 964         .remove                 = ehci_hcd_omap_remove,
 965         .shutdown               = ehci_hcd_omap_shutdown,
 966         /*.suspend              = ehci_hcd_omap_suspend, */
 967         /*.resume               = ehci_hcd_omap_resume, */
 968         .driver = {
 969                 .name           = "ehci-omap",
 970         }
 971 };
 972
 973 /*-------------------------------------------------------------------------*/
 974
 975 static const struct hc_driver ehci_omap_hc_driver = {
 976         .description            = hcd_name,
 977         .product_desc           = "OMAP-EHCI Host Controller",
 978         .hcd_priv_size          = sizeof(struct ehci_hcd),
 979
 980         /*
 981          * generic hardware linkage
 982          */
 983         .irq                    = ehci_irq,
 984         .flags                  = HCD_MEMORY | HCD_USB2,
 985
 986         /*
 987          * basic lifecycle operations
 988          */
 989         .reset                  = ehci_init,
 990         .start                  = ehci_run,
 991         .stop                   = ehci_stop,
 992         .shutdown               = ehci_shutdown,
 993
 994         /*
 995          * managing i/o requests and associated device resources
 996          */
 997         .urb_enqueue            = ehci_urb_enqueue,
 998         .urb_dequeue            = ehci_urb_dequeue,
 999         .endpoint_disable       = ehci_endpoint_disable,
1000         .endpoint_reset         = ehci_endpoint_reset,
1001
1002         /*
1003          * scheduling support
1004          */
1005         .get_frame_number       = ehci_get_frame,
1006
1007         /*
1008          * root hub support
1009          */
1010         .hub_status_data        = ehci_hub_status_data,
1011         .hub_control            = ehci_hub_control,
1012         .bus_suspend            = ehci_bus_suspend,
1013         .bus_resume             = ehci_bus_resume,
1014
1015         .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
1016 };
1017
1018 MODULE_ALIAS("platform:omap-ehci");
1019 MODULE_AUTHOR("Texas Instruments, Inc.");
1020 MODULE_AUTHOR("Felipe Balbi <felipe.balbi@nokia.com>");
1021