2 * Copyright (c) 2000-2004 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/dmapool.h>
22 #include <linux/kernel.h>
23 #include <linux/delay.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/vmalloc.h>
27 #include <linux/errno.h>
28 #include <linux/init.h>
29 #include <linux/timer.h>
30 #include <linux/ktime.h>
31 #include <linux/list.h>
32 #include <linux/interrupt.h>
33 #include <linux/usb.h>
34 #include <linux/usb/hcd.h>
35 #include <linux/moduleparam.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/debugfs.h>
38 #include <linux/slab.h>
39 #include <linux/uaccess.h>
41 #include <asm/byteorder.h>
44 #include <asm/system.h>
45 #include <asm/unaligned.h>
47 /*-------------------------------------------------------------------------*/
50 * EHCI hc_driver implementation ... experimental, incomplete.
51 * Based on the final 1.0 register interface specification.
53 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
54 * First was PCMCIA, like ISA; then CardBus, which is PCI.
55 * Next comes "CardBay", using USB 2.0 signals.
57 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
58 * Special thanks to Intel and VIA for providing host controllers to
59 * test this driver on, and Cypress (including In-System Design) for
60 * providing early devices for those host controllers to talk to!
63 #define DRIVER_AUTHOR "David Brownell"
64 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
66 static const char hcd_name [] = "ehci_hcd";
76 /* magic numbers that can affect system performance */
77 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
78 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
79 #define EHCI_TUNE_RL_TT 0
80 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
81 #define EHCI_TUNE_MULT_TT 1
83 * Some drivers think it's safe to schedule isochronous transfers more than
84 * 256 ms into the future (partly as a result of an old bug in the scheduling
85 * code). In an attempt to avoid trouble, we will use a minimum scheduling
86 * length of 512 frames instead of 256.
88 #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
90 #define EHCI_IAA_MSECS 10 /* arbitrary */
91 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
92 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
93 #define EHCI_SHRINK_FRAMES 5 /* async qh unlink delay */
95 /* Initial IRQ latency: faster than hw default */
96 static int log2_irq_thresh = 0; // 0 to 6
97 module_param (log2_irq_thresh, int, S_IRUGO);
98 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
100 /* initial park setting: slower than hw default */
101 static unsigned park = 0;
102 module_param (park, uint, S_IRUGO);
103 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
105 /* for flakey hardware, ignore overcurrent indicators */
106 static int ignore_oc = 0;
107 module_param (ignore_oc, bool, S_IRUGO);
108 MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
110 /* for link power management(LPM) feature */
111 static unsigned int hird;
112 module_param(hird, int, S_IRUGO);
113 MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us\n");
115 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
117 /* for ASPM quirk of ISOC on AMD SB800 */
118 static struct pci_dev *amd_nb_dev;
120 /*-------------------------------------------------------------------------*/
123 #include "ehci-dbg.c"
125 /*-------------------------------------------------------------------------*/
128 timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action)
130 /* Don't override timeouts which shrink or (later) disable
131 * the async ring; just the I/O watchdog. Note that if a
132 * SHRINK were pending, OFF would never be requested.
134 if (timer_pending(&ehci->watchdog)
135 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF))
139 if (!test_and_set_bit(action, &ehci->actions)) {
143 case TIMER_IO_WATCHDOG:
144 if (!ehci->need_io_watchdog)
148 case TIMER_ASYNC_OFF:
149 t = EHCI_ASYNC_JIFFIES;
151 /* case TIMER_ASYNC_SHRINK: */
153 /* add a jiffie since we synch against the
154 * 8 KHz uframe counter.
156 t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1;
159 mod_timer(&ehci->watchdog, t + jiffies);
163 /*-------------------------------------------------------------------------*/
166 * handshake - spin reading hc until handshake completes or fails
167 * @ptr: address of hc register to be read
168 * @mask: bits to look at in result of read
169 * @done: value of those bits when handshake succeeds
170 * @usec: timeout in microseconds
172 * Returns negative errno, or zero on success
174 * Success happens when the "mask" bits have the specified value (hardware
175 * handshake done). There are two failure modes: "usec" have passed (major
176 * hardware flakeout), or the register reads as all-ones (hardware removed).
178 * That last failure should_only happen in cases like physical cardbus eject
179 * before driver shutdown. But it also seems to be caused by bugs in cardbus
180 * bridge shutdown: shutting down the bridge before the devices using it.
182 static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
183 u32 mask, u32 done, int usec)
188 result = ehci_readl(ehci, ptr);
189 if (result == ~(u32)0) /* card removed */
200 /* check TDI/ARC silicon is in host mode */
201 static int tdi_in_host_mode (struct ehci_hcd *ehci)
203 u32 __iomem *reg_ptr;
206 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
207 tmp = ehci_readl(ehci, reg_ptr);
208 return (tmp & 3) == USBMODE_CM_HC;
211 /* force HC to halt state from unknown (EHCI spec section 2.3) */
212 static int ehci_halt (struct ehci_hcd *ehci)
214 u32 temp = ehci_readl(ehci, &ehci->regs->status);
216 /* disable any irqs left enabled by previous code */
217 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
219 if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) {
223 if ((temp & STS_HALT) != 0)
226 temp = ehci_readl(ehci, &ehci->regs->command);
228 ehci_writel(ehci, temp, &ehci->regs->command);
229 return handshake (ehci, &ehci->regs->status,
230 STS_HALT, STS_HALT, 16 * 125);
233 static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
234 u32 mask, u32 done, int usec)
238 error = handshake(ehci, ptr, mask, done, usec);
241 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
242 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n",
243 ptr, mask, done, error);
249 /* put TDI/ARC silicon into EHCI mode */
250 static void tdi_reset (struct ehci_hcd *ehci)
252 u32 __iomem *reg_ptr;
255 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
256 tmp = ehci_readl(ehci, reg_ptr);
257 tmp |= USBMODE_CM_HC;
258 /* The default byte access to MMR space is LE after
259 * controller reset. Set the required endian mode
260 * for transfer buffers to match the host microprocessor
262 if (ehci_big_endian_mmio(ehci))
264 ehci_writel(ehci, tmp, reg_ptr);
267 /* reset a non-running (STS_HALT == 1) controller */
268 static int ehci_reset (struct ehci_hcd *ehci)
271 u32 command = ehci_readl(ehci, &ehci->regs->command);
273 /* If the EHCI debug controller is active, special care must be
274 * taken before and after a host controller reset */
275 if (ehci->debug && !dbgp_reset_prep())
278 command |= CMD_RESET;
279 dbg_cmd (ehci, "reset", command);
280 ehci_writel(ehci, command, &ehci->regs->command);
281 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
282 ehci->next_statechange = jiffies;
283 retval = handshake (ehci, &ehci->regs->command,
284 CMD_RESET, 0, 250 * 1000);
286 if (ehci->has_hostpc) {
287 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
288 (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX));
289 ehci_writel(ehci, TXFIFO_DEFAULT,
290 (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING));
295 if (ehci_is_TDI(ehci))
299 dbgp_external_startup();
304 /* idle the controller (from running) */
305 static void ehci_quiesce (struct ehci_hcd *ehci)
310 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
314 /* wait for any schedule enables/disables to take effect */
315 temp = ehci_readl(ehci, &ehci->regs->command) << 10;
316 temp &= STS_ASS | STS_PSS;
317 if (handshake_on_error_set_halt(ehci, &ehci->regs->status,
318 STS_ASS | STS_PSS, temp, 16 * 125))
321 /* then disable anything that's still active */
322 temp = ehci_readl(ehci, &ehci->regs->command);
323 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
324 ehci_writel(ehci, temp, &ehci->regs->command);
326 /* hardware can take 16 microframes to turn off ... */
327 handshake_on_error_set_halt(ehci, &ehci->regs->status,
328 STS_ASS | STS_PSS, 0, 16 * 125);
331 /*-------------------------------------------------------------------------*/
333 static void end_unlink_async(struct ehci_hcd *ehci);
334 static void ehci_work(struct ehci_hcd *ehci);
336 #include "ehci-hub.c"
337 #include "ehci-lpm.c"
338 #include "ehci-mem.c"
340 #include "ehci-sched.c"
342 /*-------------------------------------------------------------------------*/
344 static void ehci_iaa_watchdog(unsigned long param)
346 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
349 spin_lock_irqsave (&ehci->lock, flags);
351 /* Lost IAA irqs wedge things badly; seen first with a vt8235.
352 * So we need this watchdog, but must protect it against both
353 * (a) SMP races against real IAA firing and retriggering, and
354 * (b) clean HC shutdown, when IAA watchdog was pending.
357 && !timer_pending(&ehci->iaa_watchdog)
358 && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
361 /* If we get here, IAA is *REALLY* late. It's barely
362 * conceivable that the system is so busy that CMD_IAAD
363 * is still legitimately set, so let's be sure it's
364 * clear before we read STS_IAA. (The HC should clear
365 * CMD_IAAD when it sets STS_IAA.)
367 cmd = ehci_readl(ehci, &ehci->regs->command);
369 ehci_writel(ehci, cmd & ~CMD_IAAD,
370 &ehci->regs->command);
372 /* If IAA is set here it either legitimately triggered
373 * before we cleared IAAD above (but _way_ late, so we'll
374 * still count it as lost) ... or a silicon erratum:
375 * - VIA seems to set IAA without triggering the IRQ;
376 * - IAAD potentially cleared without setting IAA.
378 status = ehci_readl(ehci, &ehci->regs->status);
379 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
380 COUNT (ehci->stats.lost_iaa);
381 ehci_writel(ehci, STS_IAA, &ehci->regs->status);
384 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",
386 end_unlink_async(ehci);
389 spin_unlock_irqrestore(&ehci->lock, flags);
392 static void ehci_watchdog(unsigned long param)
394 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
397 spin_lock_irqsave(&ehci->lock, flags);
399 /* stop async processing after it's idled a bit */
400 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
401 start_unlink_async (ehci, ehci->async);
403 /* ehci could run by timer, without IRQs ... */
406 spin_unlock_irqrestore (&ehci->lock, flags);
409 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
410 * The firmware seems to think that powering off is a wakeup event!
411 * This routine turns off remote wakeup and everything else, on all ports.
413 static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
415 int port = HCS_N_PORTS(ehci->hcs_params);
418 ehci_writel(ehci, PORT_RWC_BITS,
419 &ehci->regs->port_status[port]);
423 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
424 * Should be called with ehci->lock held.
426 static void ehci_silence_controller(struct ehci_hcd *ehci)
429 ehci_turn_off_all_ports(ehci);
431 /* make BIOS/etc use companion controller during reboot */
432 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
434 /* unblock posted writes */
435 ehci_readl(ehci, &ehci->regs->configured_flag);
438 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
439 * This forcibly disables dma and IRQs, helping kexec and other cases
440 * where the next system software may expect clean state.
442 static void ehci_shutdown(struct usb_hcd *hcd)
444 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
446 del_timer_sync(&ehci->watchdog);
447 del_timer_sync(&ehci->iaa_watchdog);
449 spin_lock_irq(&ehci->lock);
450 ehci_silence_controller(ehci);
451 spin_unlock_irq(&ehci->lock);
454 static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
458 if (!HCS_PPC (ehci->hcs_params))
461 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
462 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
463 (void) ehci_hub_control(ehci_to_hcd(ehci),
464 is_on ? SetPortFeature : ClearPortFeature,
467 /* Flush those writes */
468 ehci_readl(ehci, &ehci->regs->command);
472 /*-------------------------------------------------------------------------*/
475 * ehci_work is called from some interrupts, timers, and so on.
476 * it calls driver completion functions, after dropping ehci->lock.
478 static void ehci_work (struct ehci_hcd *ehci)
480 timer_action_done (ehci, TIMER_IO_WATCHDOG);
482 /* another CPU may drop ehci->lock during a schedule scan while
483 * it reports urb completions. this flag guards against bogus
484 * attempts at re-entrant schedule scanning.
490 if (ehci->next_uframe != -1)
491 scan_periodic (ehci);
494 /* the IO watchdog guards against hardware or driver bugs that
495 * misplace IRQs, and should let us run completely without IRQs.
496 * such lossage has been observed on both VT6202 and VT8235.
498 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) &&
499 (ehci->async->qh_next.ptr != NULL ||
500 ehci->periodic_sched != 0))
501 timer_action (ehci, TIMER_IO_WATCHDOG);
505 * Called when the ehci_hcd module is removed.
507 static void ehci_stop (struct usb_hcd *hcd)
509 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
511 ehci_dbg (ehci, "stop\n");
513 /* no more interrupts ... */
514 del_timer_sync (&ehci->watchdog);
515 del_timer_sync(&ehci->iaa_watchdog);
517 spin_lock_irq(&ehci->lock);
518 if (HC_IS_RUNNING (hcd->state))
521 ehci_silence_controller(ehci);
523 spin_unlock_irq(&ehci->lock);
525 remove_companion_file(ehci);
526 remove_debug_files (ehci);
528 /* root hub is shut down separately (first, when possible) */
529 spin_lock_irq (&ehci->lock);
532 spin_unlock_irq (&ehci->lock);
533 ehci_mem_cleanup (ehci);
536 pci_dev_put(amd_nb_dev);
541 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
542 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
543 ehci->stats.lost_iaa);
544 ehci_dbg (ehci, "complete %ld unlink %ld\n",
545 ehci->stats.complete, ehci->stats.unlink);
548 dbg_status (ehci, "ehci_stop completed",
549 ehci_readl(ehci, &ehci->regs->status));
552 /* one-time init, only for memory state */
553 static int ehci_init(struct usb_hcd *hcd)
555 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
559 struct ehci_qh_hw *hw;
561 spin_lock_init(&ehci->lock);
564 * keep io watchdog by default, those good HCDs could turn off it later
566 ehci->need_io_watchdog = 1;
567 init_timer(&ehci->watchdog);
568 ehci->watchdog.function = ehci_watchdog;
569 ehci->watchdog.data = (unsigned long) ehci;
571 init_timer(&ehci->iaa_watchdog);
572 ehci->iaa_watchdog.function = ehci_iaa_watchdog;
573 ehci->iaa_watchdog.data = (unsigned long) ehci;
575 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
578 * hw default: 1K periodic list heads, one per frame.
579 * periodic_size can shrink by USBCMD update if hcc_params allows.
581 ehci->periodic_size = DEFAULT_I_TDPS;
582 INIT_LIST_HEAD(&ehci->cached_itd_list);
583 INIT_LIST_HEAD(&ehci->cached_sitd_list);
585 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
586 /* periodic schedule size can be smaller than default */
587 switch (EHCI_TUNE_FLS) {
588 case 0: ehci->periodic_size = 1024; break;
589 case 1: ehci->periodic_size = 512; break;
590 case 2: ehci->periodic_size = 256; break;
594 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
597 /* controllers may cache some of the periodic schedule ... */
598 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
599 ehci->i_thresh = 2 + 8;
600 else // N microframes cached
601 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
603 ehci->reclaim = NULL;
604 ehci->next_uframe = -1;
605 ehci->clock_frame = -1;
608 * dedicate a qh for the async ring head, since we couldn't unlink
609 * a 'real' qh without stopping the async schedule [4.8]. use it
610 * as the 'reclamation list head' too.
611 * its dummy is used in hw_alt_next of many tds, to prevent the qh
612 * from automatically advancing to the next td after short reads.
614 ehci->async->qh_next.qh = NULL;
615 hw = ehci->async->hw;
616 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
617 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
618 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
619 hw->hw_qtd_next = EHCI_LIST_END(ehci);
620 ehci->async->qh_state = QH_STATE_LINKED;
621 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
623 /* clear interrupt enables, set irq latency */
624 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
626 temp = 1 << (16 + log2_irq_thresh);
627 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
629 ehci_dbg(ehci, "enable per-port change event\n");
632 if (HCC_CANPARK(hcc_params)) {
633 /* HW default park == 3, on hardware that supports it (like
634 * NVidia and ALI silicon), maximizes throughput on the async
635 * schedule by avoiding QH fetches between transfers.
637 * With fast usb storage devices and NForce2, "park" seems to
638 * make problems: throughput reduction (!), data errors...
641 park = min(park, (unsigned) 3);
645 ehci_dbg(ehci, "park %d\n", park);
647 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
648 /* periodic schedule size can be smaller than default */
650 temp |= (EHCI_TUNE_FLS << 2);
652 if (HCC_LPM(hcc_params)) {
653 /* support link power management EHCI 1.1 addendum */
654 ehci_dbg(ehci, "support lpm\n");
657 ehci_dbg(ehci, "hird %d invalid, use default 0",
663 ehci->command = temp;
665 /* Accept arbitrarily long scatter-gather lists */
666 if (!(hcd->driver->flags & HCD_LOCAL_MEM))
667 hcd->self.sg_tablesize = ~0;
671 /* start HC running; it's halted, ehci_init() has been run (once) */
672 static int ehci_run (struct usb_hcd *hcd)
674 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
679 hcd->uses_new_polling = 1;
681 /* EHCI spec section 4.1 */
683 * TDI driver does the ehci_reset in their reset callback.
684 * Don't reset here, because configuration settings will
687 if (!ehci_is_TDI(ehci) && (retval = ehci_reset(ehci)) != 0) {
688 ehci_mem_cleanup(ehci);
691 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
692 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
695 * hcc_params controls whether ehci->regs->segment must (!!!)
696 * be used; it constrains QH/ITD/SITD and QTD locations.
697 * pci_pool consistent memory always uses segment zero.
698 * streaming mappings for I/O buffers, like pci_map_single(),
699 * can return segments above 4GB, if the device allows.
701 * NOTE: the dma mask is visible through dma_supported(), so
702 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
703 * Scsi_Host.highmem_io, and so forth. It's readonly to all
704 * host side drivers though.
706 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
707 if (HCC_64BIT_ADDR(hcc_params)) {
708 ehci_writel(ehci, 0, &ehci->regs->segment);
710 // this is deeply broken on almost all architectures
711 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
712 ehci_info(ehci, "enabled 64bit DMA\n");
717 // Philips, Intel, and maybe others need CMD_RUN before the
718 // root hub will detect new devices (why?); NEC doesn't
719 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
720 ehci->command |= CMD_RUN;
721 ehci_writel(ehci, ehci->command, &ehci->regs->command);
722 dbg_cmd (ehci, "init", ehci->command);
725 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
726 * are explicitly handed to companion controller(s), so no TT is
727 * involved with the root hub. (Except where one is integrated,
728 * and there's no companion controller unless maybe for USB OTG.)
730 * Turning on the CF flag will transfer ownership of all ports
731 * from the companions to the EHCI controller. If any of the
732 * companions are in the middle of a port reset at the time, it
733 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
734 * guarantees that no resets are in progress. After we set CF,
735 * a short delay lets the hardware catch up; new resets shouldn't
736 * be started before the port switching actions could complete.
738 down_write(&ehci_cf_port_reset_rwsem);
739 hcd->state = HC_STATE_RUNNING;
740 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
741 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
743 up_write(&ehci_cf_port_reset_rwsem);
744 ehci->last_periodic_enable = ktime_get_real();
746 temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
748 "USB %x.%x started, EHCI %x.%02x%s\n",
749 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
750 temp >> 8, temp & 0xff,
751 ignore_oc ? ", overcurrent ignored" : "");
753 ehci_writel(ehci, INTR_MASK,
754 &ehci->regs->intr_enable); /* Turn On Interrupts */
756 /* GRR this is run-once init(), being done every time the HC starts.
757 * So long as they're part of class devices, we can't do it init()
758 * since the class device isn't created that early.
760 create_debug_files(ehci);
761 create_companion_file(ehci);
766 /*-------------------------------------------------------------------------*/
768 static irqreturn_t ehci_irq (struct usb_hcd *hcd)
770 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
771 u32 status, masked_status, pcd_status = 0, cmd;
774 spin_lock (&ehci->lock);
776 status = ehci_readl(ehci, &ehci->regs->status);
778 /* e.g. cardbus physical eject */
779 if (status == ~(u32) 0) {
780 ehci_dbg (ehci, "device removed\n");
784 masked_status = status & INTR_MASK;
785 if (!masked_status) { /* irq sharing? */
786 spin_unlock(&ehci->lock);
790 /* clear (just) interrupts */
791 ehci_writel(ehci, masked_status, &ehci->regs->status);
792 cmd = ehci_readl(ehci, &ehci->regs->command);
796 /* unrequested/ignored: Frame List Rollover */
797 dbg_status (ehci, "irq", status);
800 /* INT, ERR, and IAA interrupt rates can be throttled */
802 /* normal [4.15.1.2] or error [4.15.1.1] completion */
803 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
804 if (likely ((status & STS_ERR) == 0))
805 COUNT (ehci->stats.normal);
807 COUNT (ehci->stats.error);
811 /* complete the unlinking of some qh [4.15.2.3] */
812 if (status & STS_IAA) {
813 /* guard against (alleged) silicon errata */
814 if (cmd & CMD_IAAD) {
815 ehci_writel(ehci, cmd & ~CMD_IAAD,
816 &ehci->regs->command);
817 ehci_dbg(ehci, "IAA with IAAD still set?\n");
820 COUNT(ehci->stats.reclaim);
821 end_unlink_async(ehci);
823 ehci_dbg(ehci, "IAA with nothing to reclaim?\n");
826 /* remote wakeup [4.3.1] */
827 if (status & STS_PCD) {
828 unsigned i = HCS_N_PORTS (ehci->hcs_params);
831 /* kick root hub later */
834 /* resume root hub? */
835 if (!(cmd & CMD_RUN))
836 usb_hcd_resume_root_hub(hcd);
838 /* get per-port change detect bits */
845 /* leverage per-port change bits feature */
846 if (ehci->has_ppcd && !(ppcd & (1 << i)))
848 pstatus = ehci_readl(ehci,
849 &ehci->regs->port_status[i]);
851 if (pstatus & PORT_OWNER)
853 if (!(test_bit(i, &ehci->suspended_ports) &&
854 ((pstatus & PORT_RESUME) ||
855 !(pstatus & PORT_SUSPEND)) &&
856 (pstatus & PORT_PE) &&
857 ehci->reset_done[i] == 0))
860 /* start 20 msec resume signaling from this port,
861 * and make khubd collect PORT_STAT_C_SUSPEND to
862 * stop that signaling. Use 5 ms extra for safety,
863 * like usb_port_resume() does.
865 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25);
866 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
867 mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
871 /* PCI errors [4.15.2.4] */
872 if (unlikely ((status & STS_FATAL) != 0)) {
873 ehci_err(ehci, "fatal error\n");
874 dbg_cmd(ehci, "fatal", cmd);
875 dbg_status(ehci, "fatal", status);
879 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
880 /* generic layer kills/unlinks all urbs, then
881 * uses ehci_stop to clean up the rest
888 spin_unlock (&ehci->lock);
890 usb_hcd_poll_rh_status(hcd);
894 /*-------------------------------------------------------------------------*/
897 * non-error returns are a promise to giveback() the urb later
898 * we drop ownership so next owner (or urb unlink) can get it
900 * urb + dev is in hcd.self.controller.urb_list
901 * we're queueing TDs onto software and hardware lists
903 * hcd-specific init for hcpriv hasn't been done yet
905 * NOTE: control, bulk, and interrupt share the same code to append TDs
906 * to a (possibly active) QH, and the same QH scanning code.
908 static int ehci_urb_enqueue (
913 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
914 struct list_head qtd_list;
916 INIT_LIST_HEAD (&qtd_list);
918 switch (usb_pipetype (urb->pipe)) {
920 /* qh_completions() code doesn't handle all the fault cases
921 * in multi-TD control transfers. Even 1KB is rare anyway.
923 if (urb->transfer_buffer_length > (16 * 1024))
926 /* case PIPE_BULK: */
928 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
930 return submit_async(ehci, urb, &qtd_list, mem_flags);
933 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
935 return intr_submit(ehci, urb, &qtd_list, mem_flags);
937 case PIPE_ISOCHRONOUS:
938 if (urb->dev->speed == USB_SPEED_HIGH)
939 return itd_submit (ehci, urb, mem_flags);
941 return sitd_submit (ehci, urb, mem_flags);
945 static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
948 if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim)
949 end_unlink_async(ehci);
951 /* If the QH isn't linked then there's nothing we can do
952 * unless we were called during a giveback, in which case
953 * qh_completions() has to deal with it.
955 if (qh->qh_state != QH_STATE_LINKED) {
956 if (qh->qh_state == QH_STATE_COMPLETING)
957 qh->needs_rescan = 1;
961 /* defer till later if busy */
963 struct ehci_qh *last;
965 for (last = ehci->reclaim;
967 last = last->reclaim)
969 qh->qh_state = QH_STATE_UNLINK_WAIT;
972 /* start IAA cycle */
974 start_unlink_async (ehci, qh);
977 /* remove from hardware lists
978 * completions normally happen asynchronously
981 static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
983 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
988 spin_lock_irqsave (&ehci->lock, flags);
989 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
993 switch (usb_pipetype (urb->pipe)) {
994 // case PIPE_CONTROL:
997 qh = (struct ehci_qh *) urb->hcpriv;
1000 switch (qh->qh_state) {
1001 case QH_STATE_LINKED:
1002 case QH_STATE_COMPLETING:
1003 unlink_async(ehci, qh);
1005 case QH_STATE_UNLINK:
1006 case QH_STATE_UNLINK_WAIT:
1007 /* already started */
1010 /* QH might be waiting for a Clear-TT-Buffer */
1011 qh_completions(ehci, qh);
1016 case PIPE_INTERRUPT:
1017 qh = (struct ehci_qh *) urb->hcpriv;
1020 switch (qh->qh_state) {
1021 case QH_STATE_LINKED:
1022 case QH_STATE_COMPLETING:
1023 intr_deschedule (ehci, qh);
1026 qh_completions (ehci, qh);
1029 ehci_dbg (ehci, "bogus qh %p state %d\n",
1035 case PIPE_ISOCHRONOUS:
1038 // wait till next completion, do it then.
1039 // completion irqs can wait up to 1024 msec,
1043 spin_unlock_irqrestore (&ehci->lock, flags);
1047 /*-------------------------------------------------------------------------*/
1049 // bulk qh holds the data toggle
1052 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1054 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1055 unsigned long flags;
1056 struct ehci_qh *qh, *tmp;
1058 /* ASSERT: any requests/urbs are being unlinked */
1059 /* ASSERT: nobody can be submitting urbs for this any more */
1062 spin_lock_irqsave (&ehci->lock, flags);
1067 /* endpoints can be iso streams. for now, we don't
1068 * accelerate iso completions ... so spin a while.
1070 if (qh->hw == NULL) {
1071 ehci_vdbg (ehci, "iso delay\n");
1075 if (!HC_IS_RUNNING (hcd->state))
1076 qh->qh_state = QH_STATE_IDLE;
1077 switch (qh->qh_state) {
1078 case QH_STATE_LINKED:
1079 case QH_STATE_COMPLETING:
1080 for (tmp = ehci->async->qh_next.qh;
1082 tmp = tmp->qh_next.qh)
1084 /* periodic qh self-unlinks on empty, and a COMPLETING qh
1085 * may already be unlinked.
1088 unlink_async(ehci, qh);
1090 case QH_STATE_UNLINK: /* wait for hw to finish? */
1091 case QH_STATE_UNLINK_WAIT:
1093 spin_unlock_irqrestore (&ehci->lock, flags);
1094 schedule_timeout_uninterruptible(1);
1096 case QH_STATE_IDLE: /* fully unlinked */
1097 if (qh->clearing_tt)
1099 if (list_empty (&qh->qtd_list)) {
1103 /* else FALL THROUGH */
1105 /* caller was supposed to have unlinked any requests;
1106 * that's not our job. just leak this memory.
1108 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1109 qh, ep->desc.bEndpointAddress, qh->qh_state,
1110 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1115 spin_unlock_irqrestore (&ehci->lock, flags);
1119 ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1121 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1123 int eptype = usb_endpoint_type(&ep->desc);
1124 int epnum = usb_endpoint_num(&ep->desc);
1125 int is_out = usb_endpoint_dir_out(&ep->desc);
1126 unsigned long flags;
1128 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1131 spin_lock_irqsave(&ehci->lock, flags);
1134 /* For Bulk and Interrupt endpoints we maintain the toggle state
1135 * in the hardware; the toggle bits in udev aren't used at all.
1136 * When an endpoint is reset by usb_clear_halt() we must reset
1137 * the toggle bit in the QH.
1140 usb_settoggle(qh->dev, epnum, is_out, 0);
1141 if (!list_empty(&qh->qtd_list)) {
1142 WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1143 } else if (qh->qh_state == QH_STATE_LINKED ||
1144 qh->qh_state == QH_STATE_COMPLETING) {
1146 /* The toggle value in the QH can't be updated
1147 * while the QH is active. Unlink it now;
1148 * re-linking will call qh_refresh().
1150 if (eptype == USB_ENDPOINT_XFER_BULK)
1151 unlink_async(ehci, qh);
1153 intr_deschedule(ehci, qh);
1156 spin_unlock_irqrestore(&ehci->lock, flags);
1159 static int ehci_get_frame (struct usb_hcd *hcd)
1161 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1162 return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) %
1163 ehci->periodic_size;
1166 /*-------------------------------------------------------------------------*/
1168 MODULE_DESCRIPTION(DRIVER_DESC);
1169 MODULE_AUTHOR (DRIVER_AUTHOR);
1170 MODULE_LICENSE ("GPL");
1173 #include "ehci-pci.c"
1174 #define PCI_DRIVER ehci_pci_driver
1177 #ifdef CONFIG_USB_EHCI_FSL
1178 #include "ehci-fsl.c"
1179 #define PLATFORM_DRIVER ehci_fsl_driver
1182 #ifdef CONFIG_USB_EHCI_MXC
1183 #include "ehci-mxc.c"
1184 #define PLATFORM_DRIVER ehci_mxc_driver
1187 #ifdef CONFIG_CPU_SUBTYPE_SH7786
1188 #include "ehci-sh.c"
1189 #define PLATFORM_DRIVER ehci_hcd_sh_driver
1192 #ifdef CONFIG_SOC_AU1200
1193 #include "ehci-au1xxx.c"
1194 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
1197 #ifdef CONFIG_USB_EHCI_HCD_OMAP
1198 #include "ehci-omap.c"
1199 #define PLATFORM_DRIVER ehci_hcd_omap_driver
1202 #ifdef CONFIG_PPC_PS3
1203 #include "ehci-ps3.c"
1204 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
1207 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1208 #include "ehci-ppc-of.c"
1209 #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
1212 #ifdef CONFIG_XPS_USB_HCD_XILINX
1213 #include "ehci-xilinx-of.c"
1214 #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
1217 #ifdef CONFIG_PLAT_ORION
1218 #include "ehci-orion.c"
1219 #define PLATFORM_DRIVER ehci_orion_driver
1222 #ifdef CONFIG_ARCH_IXP4XX
1223 #include "ehci-ixp4xx.c"
1224 #define PLATFORM_DRIVER ixp4xx_ehci_driver
1227 #ifdef CONFIG_USB_W90X900_EHCI
1228 #include "ehci-w90x900.c"
1229 #define PLATFORM_DRIVER ehci_hcd_w90x900_driver
1232 #ifdef CONFIG_ARCH_AT91
1233 #include "ehci-atmel.c"
1234 #define PLATFORM_DRIVER ehci_atmel_driver
1237 #ifdef CONFIG_USB_OCTEON_EHCI
1238 #include "ehci-octeon.c"
1239 #define PLATFORM_DRIVER ehci_octeon_driver
1242 #ifdef CONFIG_USB_CNS3XXX_EHCI
1243 #include "ehci-cns3xxx.c"
1244 #define PLATFORM_DRIVER cns3xxx_ehci_driver
1247 #ifdef CONFIG_ARCH_VT8500
1248 #include "ehci-vt8500.c"
1249 #define PLATFORM_DRIVER vt8500_ehci_driver
1252 #ifdef CONFIG_PLAT_SPEAR
1253 #include "ehci-spear.c"
1254 #define PLATFORM_DRIVER spear_ehci_hcd_driver
1257 #ifdef CONFIG_USB_EHCI_MSM
1258 #include "ehci-msm.c"
1259 #define PLATFORM_DRIVER ehci_msm_driver
1262 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1263 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
1264 !defined(XILINX_OF_PLATFORM_DRIVER)
1265 #error "missing bus glue for ehci-hcd"
1268 static int __init ehci_hcd_init(void)
1275 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1276 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1277 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1278 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1279 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1280 " before uhci_hcd and ohci_hcd, not after\n");
1282 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1284 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1285 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1288 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1289 if (!ehci_debug_root) {
1295 #ifdef PLATFORM_DRIVER
1296 retval = platform_driver_register(&PLATFORM_DRIVER);
1302 retval = pci_register_driver(&PCI_DRIVER);
1307 #ifdef PS3_SYSTEM_BUS_DRIVER
1308 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1313 #ifdef OF_PLATFORM_DRIVER
1314 retval = of_register_platform_driver(&OF_PLATFORM_DRIVER);
1319 #ifdef XILINX_OF_PLATFORM_DRIVER
1320 retval = of_register_platform_driver(&XILINX_OF_PLATFORM_DRIVER);
1326 #ifdef XILINX_OF_PLATFORM_DRIVER
1327 /* of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); */
1330 #ifdef OF_PLATFORM_DRIVER
1331 of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1334 #ifdef PS3_SYSTEM_BUS_DRIVER
1335 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1339 pci_unregister_driver(&PCI_DRIVER);
1342 #ifdef PLATFORM_DRIVER
1343 platform_driver_unregister(&PLATFORM_DRIVER);
1347 debugfs_remove(ehci_debug_root);
1348 ehci_debug_root = NULL;
1351 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1354 module_init(ehci_hcd_init);
1356 static void __exit ehci_hcd_cleanup(void)
1358 #ifdef XILINX_OF_PLATFORM_DRIVER
1359 of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER);
1361 #ifdef OF_PLATFORM_DRIVER
1362 of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1364 #ifdef PLATFORM_DRIVER
1365 platform_driver_unregister(&PLATFORM_DRIVER);
1368 pci_unregister_driver(&PCI_DRIVER);
1370 #ifdef PS3_SYSTEM_BUS_DRIVER
1371 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1374 debugfs_remove(ehci_debug_root);
1376 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1378 module_exit(ehci_hcd_cleanup);