1 /* linux/drivers/usb/gadget/s3c-hsotg.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C USB2.0 High-speed / OtG driver
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/debugfs.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
34 #include <plat/regs-usb-hsotg-phy.h>
35 #include <plat/regs-usb-hsotg.h>
36 #include <mach/regs-sys.h>
37 #include <plat/udc-hs.h>
39 #define DMA_ADDR_INVALID (~((dma_addr_t)0))
43 * Unfortunately there seems to be a limit of the amount of data that can
44 * be transfered by IN transactions on EP0. This is either 127 bytes or 3
45 * packets (which practially means 1 packet and 63 bytes of data) when the
48 * This means if we are wanting to move >127 bytes of data, we need to
49 * split the transactions up, but just doing one packet at a time does
50 * not work (this may be an implicit DATA0 PID on first packet of the
51 * transaction) and doing 2 packets is outside the controller's limits.
53 * If we try to lower the MPS size for EP0, then no transfers work properly
54 * for EP0, and the system will fail basic enumeration. As no cause for this
55 * has currently been found, we cannot support any large IN transfers for
58 #define EP0_MPS_LIMIT 64
64 * struct s3c_hsotg_ep - driver endpoint definition.
65 * @ep: The gadget layer representation of the endpoint.
66 * @name: The driver generated name for the endpoint.
67 * @queue: Queue of requests for this endpoint.
68 * @parent: Reference back to the parent device structure.
69 * @req: The current request that the endpoint is processing. This is
70 * used to indicate an request has been loaded onto the endpoint
71 * and has yet to be completed (maybe due to data move, or simply
72 * awaiting an ack from the core all the data has been completed).
73 * @debugfs: File entry for debugfs file for this endpoint.
74 * @lock: State lock to protect contents of endpoint.
75 * @dir_in: Set to true if this endpoint is of the IN direction, which
76 * means that it is sending data to the Host.
77 * @index: The index for the endpoint registers.
78 * @name: The name array passed to the USB core.
79 * @halted: Set if the endpoint has been halted.
80 * @periodic: Set if this is a periodic ep, such as Interrupt
81 * @sent_zlp: Set if we've sent a zero-length packet.
82 * @total_data: The total number of data bytes done.
83 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
84 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
85 * @last_load: The offset of data for the last start of request.
86 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
88 * This is the driver's state for each registered enpoint, allowing it
89 * to keep track of transactions that need doing. Each endpoint has a
90 * lock to protect the state, to try and avoid using an overall lock
91 * for the host controller as much as possible.
93 * For periodic IN endpoints, we have fifo_size and fifo_load to try
94 * and keep track of the amount of data in the periodic FIFO for each
95 * of these as we don't have a status register that tells us how much
96 * is in each of them. (note, this may actually be useless information
97 * as in shared-fifo mode periodic in acts like a single-frame packet
100 struct s3c_hsotg_ep {
102 struct list_head queue;
103 struct s3c_hsotg *parent;
104 struct s3c_hsotg_req *req;
105 struct dentry *debugfs;
109 unsigned long total_data;
110 unsigned int size_loaded;
111 unsigned int last_load;
112 unsigned int fifo_load;
113 unsigned short fifo_size;
115 unsigned char dir_in;
118 unsigned int halted:1;
119 unsigned int periodic:1;
120 unsigned int sent_zlp:1;
125 #define S3C_HSOTG_EPS (8+1) /* limit to 9 for the moment */
128 * struct s3c_hsotg - driver state.
129 * @dev: The parent device supplied to the probe function
130 * @driver: USB gadget driver
131 * @plat: The platform specific configuration data.
132 * @regs: The memory area mapped for accessing registers.
133 * @regs_res: The resource that was allocated when claiming register space.
134 * @irq: The IRQ number we are using
135 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
136 * @debug_root: root directrory for debugfs.
137 * @debug_file: main status file for debugfs.
138 * @debug_fifo: FIFO status file for debugfs.
139 * @ep0_reply: Request used for ep0 reply.
140 * @ep0_buff: Buffer for EP0 reply data, if needed.
141 * @ctrl_buff: Buffer for EP0 control requests.
142 * @ctrl_req: Request for EP0 control packets.
143 * @eps: The endpoints being supplied to the gadget framework
147 struct usb_gadget_driver *driver;
148 struct s3c_hsotg_plat *plat;
151 struct resource *regs_res;
154 unsigned int dedicated_fifos:1;
156 struct dentry *debug_root;
157 struct dentry *debug_file;
158 struct dentry *debug_fifo;
160 struct usb_request *ep0_reply;
161 struct usb_request *ctrl_req;
165 struct usb_gadget gadget;
166 struct s3c_hsotg_ep eps[];
170 * struct s3c_hsotg_req - data transfer request
171 * @req: The USB gadget request
172 * @queue: The list of requests for the endpoint this is queued for.
173 * @in_progress: Has already had size/packets written to core
174 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
176 struct s3c_hsotg_req {
177 struct usb_request req;
178 struct list_head queue;
179 unsigned char in_progress;
180 unsigned char mapped;
183 /* conversion functions */
184 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
186 return container_of(req, struct s3c_hsotg_req, req);
189 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
191 return container_of(ep, struct s3c_hsotg_ep, ep);
194 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
196 return container_of(gadget, struct s3c_hsotg, gadget);
199 static inline void __orr32(void __iomem *ptr, u32 val)
201 writel(readl(ptr) | val, ptr);
204 static inline void __bic32(void __iomem *ptr, u32 val)
206 writel(readl(ptr) & ~val, ptr);
209 /* forward decleration of functions */
210 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
213 * using_dma - return the DMA status of the driver.
214 * @hsotg: The driver state.
216 * Return true if we're using DMA.
218 * Currently, we have the DMA support code worked into everywhere
219 * that needs it, but the AMBA DMA implementation in the hardware can
220 * only DMA from 32bit aligned addresses. This means that gadgets such
221 * as the CDC Ethernet cannot work as they often pass packets which are
224 * Unfortunately the choice to use DMA or not is global to the controller
225 * and seems to be only settable when the controller is being put through
226 * a core reset. This means we either need to fix the gadgets to take
227 * account of DMA alignment, or add bounce buffers (yuerk).
229 * Until this issue is sorted out, we always return 'false'.
231 static inline bool using_dma(struct s3c_hsotg *hsotg)
233 return false; /* support is not complete */
237 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
238 * @hsotg: The device state
239 * @ints: A bitmask of the interrupts to enable
241 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
243 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
246 new_gsintmsk = gsintmsk | ints;
248 if (new_gsintmsk != gsintmsk) {
249 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
250 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
255 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
256 * @hsotg: The device state
257 * @ints: A bitmask of the interrupts to enable
259 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
261 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
264 new_gsintmsk = gsintmsk & ~ints;
266 if (new_gsintmsk != gsintmsk)
267 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
271 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
272 * @hsotg: The device state
273 * @ep: The endpoint index
274 * @dir_in: True if direction is in.
275 * @en: The enable value, true to enable
277 * Set or clear the mask for an individual endpoint's interrupt
280 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
281 unsigned int ep, unsigned int dir_in,
291 local_irq_save(flags);
292 daint = readl(hsotg->regs + S3C_DAINTMSK);
297 writel(daint, hsotg->regs + S3C_DAINTMSK);
298 local_irq_restore(flags);
302 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
303 * @hsotg: The device instance.
305 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
313 /* the ryu 2.6.24 release ahs
314 writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);
315 writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |
316 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
317 hsotg->regs + S3C_GNPTXFSIZ);
320 /* set FIFO sizes to 2048/1024 */
322 writel(2048, hsotg->regs + S3C_GRXFSIZ);
323 writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
324 S3C_GNPTXFSIZ_NPTxFDep(1024),
325 hsotg->regs + S3C_GNPTXFSIZ);
327 /* arange all the rest of the TX FIFOs, as some versions of this
328 * block have overlapping default addresses. This also ensures
329 * that if the settings have been changed, then they are set to
332 /* start at the end of the GNPTXFSIZ, rounded up */
336 /* currently we allocate TX FIFOs for all possible endpoints,
337 * and assume that they are all the same size. */
339 for (ep = 0; ep <= 15; ep++) {
341 val |= size << S3C_DPTXFSIZn_DPTxFSize_SHIFT;
344 writel(val, hsotg->regs + S3C_DPTXFSIZn(ep));
347 /* according to p428 of the design guide, we need to ensure that
348 * all fifos are flushed before continuing */
350 writel(S3C_GRSTCTL_TxFNum(0x10) | S3C_GRSTCTL_TxFFlsh |
351 S3C_GRSTCTL_RxFFlsh, hsotg->regs + S3C_GRSTCTL);
353 /* wait until the fifos are both flushed */
356 val = readl(hsotg->regs + S3C_GRSTCTL);
358 if ((val & (S3C_GRSTCTL_TxFFlsh | S3C_GRSTCTL_RxFFlsh)) == 0)
361 if (--timeout == 0) {
363 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
370 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
374 * @ep: USB endpoint to allocate request for.
375 * @flags: Allocation flags
377 * Allocate a new USB request structure appropriate for the specified endpoint
379 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
382 struct s3c_hsotg_req *req;
384 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
388 INIT_LIST_HEAD(&req->queue);
390 req->req.dma = DMA_ADDR_INVALID;
395 * is_ep_periodic - return true if the endpoint is in periodic mode.
396 * @hs_ep: The endpoint to query.
398 * Returns true if the endpoint is in periodic mode, meaning it is being
399 * used for an Interrupt or ISO transfer.
401 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
403 return hs_ep->periodic;
407 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
408 * @hsotg: The device state.
409 * @hs_ep: The endpoint for the request
410 * @hs_req: The request being processed.
412 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
413 * of a request to ensure the buffer is ready for access by the caller.
415 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
416 struct s3c_hsotg_ep *hs_ep,
417 struct s3c_hsotg_req *hs_req)
419 struct usb_request *req = &hs_req->req;
420 enum dma_data_direction dir;
422 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
424 /* ignore this if we're not moving any data */
425 if (hs_req->req.length == 0)
428 if (hs_req->mapped) {
429 /* we mapped this, so unmap and remove the dma */
431 dma_unmap_single(hsotg->dev, req->dma, req->length, dir);
433 req->dma = DMA_ADDR_INVALID;
436 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
441 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
442 * @hsotg: The controller state.
443 * @hs_ep: The endpoint we're going to write for.
444 * @hs_req: The request to write data for.
446 * This is called when the TxFIFO has some space in it to hold a new
447 * transmission and we have something to give it. The actual setup of
448 * the data size is done elsewhere, so all we have to do is to actually
451 * The return value is zero if there is more space (or nothing was done)
452 * otherwise -ENOSPC is returned if the FIFO space was used up.
454 * This routine is only needed for PIO
456 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
457 struct s3c_hsotg_ep *hs_ep,
458 struct s3c_hsotg_req *hs_req)
460 bool periodic = is_ep_periodic(hs_ep);
461 u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS);
462 int buf_pos = hs_req->req.actual;
463 int to_write = hs_ep->size_loaded;
468 to_write -= (buf_pos - hs_ep->last_load);
470 /* if there's nothing to write, get out early */
474 if (periodic && !hsotg->dedicated_fifos) {
475 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
479 /* work out how much data was loaded so we can calculate
480 * how much data is left in the fifo. */
482 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
484 /* if shared fifo, we cannot write anything until the
485 * previous data has been completely sent.
487 if (hs_ep->fifo_load != 0) {
488 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
492 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
494 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
496 /* how much of the data has moved */
497 size_done = hs_ep->size_loaded - size_left;
499 /* how much data is left in the fifo */
500 can_write = hs_ep->fifo_load - size_done;
501 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
502 __func__, can_write);
504 can_write = hs_ep->fifo_size - can_write;
505 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
506 __func__, can_write);
508 if (can_write <= 0) {
509 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
512 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
513 can_write = readl(hsotg->regs + S3C_DTXFSTS(hs_ep->index));
518 if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
520 "%s: no queue slots available (0x%08x)\n",
523 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
527 can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
528 can_write *= 4; /* fifo size is in 32bit quantities. */
531 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
532 __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);
534 /* limit to 512 bytes of data, it seems at least on the non-periodic
535 * FIFO, requests of >512 cause the endpoint to get stuck with a
536 * fragment of the end of the transfer in it.
541 /* limit the write to one max-packet size worth of data, but allow
542 * the transfer to return that it did not run out of fifo space
544 if (to_write > hs_ep->ep.maxpacket) {
545 to_write = hs_ep->ep.maxpacket;
547 s3c_hsotg_en_gsint(hsotg,
548 periodic ? S3C_GINTSTS_PTxFEmp :
549 S3C_GINTSTS_NPTxFEmp);
552 /* see if we can write data */
554 if (to_write > can_write) {
555 to_write = can_write;
556 pkt_round = to_write % hs_ep->ep.maxpacket;
558 /* Not sure, but we probably shouldn't be writing partial
559 * packets into the FIFO, so round the write down to an
560 * exact number of packets.
562 * Note, we do not currently check to see if we can ever
563 * write a full packet or not to the FIFO.
567 to_write -= pkt_round;
569 /* enable correct FIFO interrupt to alert us when there
570 * is more room left. */
572 s3c_hsotg_en_gsint(hsotg,
573 periodic ? S3C_GINTSTS_PTxFEmp :
574 S3C_GINTSTS_NPTxFEmp);
577 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
578 to_write, hs_req->req.length, can_write, buf_pos);
583 hs_req->req.actual = buf_pos + to_write;
584 hs_ep->total_data += to_write;
587 hs_ep->fifo_load += to_write;
589 to_write = DIV_ROUND_UP(to_write, 4);
590 data = hs_req->req.buf + buf_pos;
592 writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write);
594 return (to_write >= can_write) ? -ENOSPC : 0;
598 * get_ep_limit - get the maximum data legnth for this endpoint
599 * @hs_ep: The endpoint
601 * Return the maximum data that can be queued in one go on a given endpoint
602 * so that transfers that are too long can be split.
604 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
606 int index = hs_ep->index;
611 maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1;
612 maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
615 /* maxsize = S3C_DIEPTSIZ0_XferSize_LIMIT + 1; */
617 maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
624 /* we made the constant loading easier above by using +1 */
628 /* constrain by packet count if maxpkts*pktsize is greater
629 * than the length register size. */
631 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
632 maxsize = maxpkt * hs_ep->ep.maxpacket;
638 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
639 * @hsotg: The controller state.
640 * @hs_ep: The endpoint to process a request for
641 * @hs_req: The request to start.
642 * @continuing: True if we are doing more for the current request.
644 * Start the given request running by setting the endpoint registers
645 * appropriately, and writing any data to the FIFOs.
647 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
648 struct s3c_hsotg_ep *hs_ep,
649 struct s3c_hsotg_req *hs_req,
652 struct usb_request *ureq = &hs_req->req;
653 int index = hs_ep->index;
654 int dir_in = hs_ep->dir_in;
664 if (hs_ep->req && !continuing) {
665 dev_err(hsotg->dev, "%s: active request\n", __func__);
668 } else if (hs_ep->req != hs_req && continuing) {
670 "%s: continue different req\n", __func__);
676 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
677 epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index);
679 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
680 __func__, readl(hsotg->regs + epctrl_reg), index,
681 hs_ep->dir_in ? "in" : "out");
683 length = ureq->length - ureq->actual;
687 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
688 ureq->buf, length, ureq->dma,
689 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
691 maxreq = get_ep_limit(hs_ep);
692 if (length > maxreq) {
693 int round = maxreq % hs_ep->ep.maxpacket;
695 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
696 __func__, length, maxreq, round);
698 /* round down to multiple of packets */
706 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
708 packets = 1; /* send one packet if length is zero. */
710 if (dir_in && index != 0)
711 epsize = S3C_DxEPTSIZ_MC(1);
715 if (index != 0 && ureq->zero) {
716 /* test for the packets being exactly right for the
719 if (length == (packets * hs_ep->ep.maxpacket))
723 epsize |= S3C_DxEPTSIZ_PktCnt(packets);
724 epsize |= S3C_DxEPTSIZ_XferSize(length);
726 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
727 __func__, packets, length, ureq->length, epsize, epsize_reg);
729 /* store the request as the current one we're doing */
732 /* write size / packets */
733 writel(epsize, hsotg->regs + epsize_reg);
735 ctrl = readl(hsotg->regs + epctrl_reg);
737 if (ctrl & S3C_DxEPCTL_Stall) {
738 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
740 /* not sure what we can do here, if it is EP0 then we should
741 * get this cleared once the endpoint has transmitted the
742 * STALL packet, otherwise it needs to be cleared by the
747 if (using_dma(hsotg)) {
748 unsigned int dma_reg;
750 /* write DMA address to control register, buffer already
751 * synced by s3c_hsotg_ep_queue(). */
753 dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index);
754 writel(ureq->dma, hsotg->regs + dma_reg);
756 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
757 __func__, ureq->dma, dma_reg);
760 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
761 ctrl |= S3C_DxEPCTL_USBActEp;
762 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
764 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
765 writel(ctrl, hsotg->regs + epctrl_reg);
767 /* set these, it seems that DMA support increments past the end
768 * of the packet buffer so we need to calculate the length from
769 * this information. */
770 hs_ep->size_loaded = length;
771 hs_ep->last_load = ureq->actual;
773 if (dir_in && !using_dma(hsotg)) {
774 /* set these anyway, we may need them for non-periodic in */
775 hs_ep->fifo_load = 0;
777 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
780 /* clear the INTknTXFEmpMsk when we start request, more as a aide
781 * to debugging to see what is going on. */
783 writel(S3C_DIEPMSK_INTknTXFEmpMsk,
784 hsotg->regs + S3C_DIEPINT(index));
786 /* Note, trying to clear the NAK here causes problems with transmit
787 * on the S3C6400 ending up with the TXFIFO becomming full. */
789 /* check ep is enabled */
790 if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna))
792 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
793 index, readl(hsotg->regs + epctrl_reg));
795 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
796 __func__, readl(hsotg->regs + epctrl_reg));
800 * s3c_hsotg_map_dma - map the DMA memory being used for the request
801 * @hsotg: The device state.
802 * @hs_ep: The endpoint the request is on.
803 * @req: The request being processed.
805 * We've been asked to queue a request, so ensure that the memory buffer
806 * is correctly setup for DMA. If we've been passed an extant DMA address
807 * then ensure the buffer has been synced to memory. If our buffer has no
808 * DMA memory, then we map the memory and mark our request to allow us to
809 * cleanup on completion.
811 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
812 struct s3c_hsotg_ep *hs_ep,
813 struct usb_request *req)
815 enum dma_data_direction dir;
816 struct s3c_hsotg_req *hs_req = our_req(req);
818 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
820 /* if the length is zero, ignore the DMA data */
821 if (hs_req->req.length == 0)
824 if (req->dma == DMA_ADDR_INVALID) {
827 dma = dma_map_single(hsotg->dev, req->buf, req->length, dir);
829 if (unlikely(dma_mapping_error(hsotg->dev, dma)))
833 dev_err(hsotg->dev, "%s: unaligned dma buffer\n",
836 dma_unmap_single(hsotg->dev, dma, req->length, dir);
843 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
850 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
851 __func__, req->buf, req->length);
856 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
859 struct s3c_hsotg_req *hs_req = our_req(req);
860 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
861 struct s3c_hsotg *hs = hs_ep->parent;
862 unsigned long irqflags;
865 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
866 ep->name, req, req->length, req->buf, req->no_interrupt,
867 req->zero, req->short_not_ok);
869 /* initialise status of the request */
870 INIT_LIST_HEAD(&hs_req->queue);
872 req->status = -EINPROGRESS;
874 /* if we're using DMA, sync the buffers as necessary */
876 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
881 spin_lock_irqsave(&hs_ep->lock, irqflags);
883 first = list_empty(&hs_ep->queue);
884 list_add_tail(&hs_req->queue, &hs_ep->queue);
887 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
889 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
894 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
895 struct usb_request *req)
897 struct s3c_hsotg_req *hs_req = our_req(req);
903 * s3c_hsotg_complete_oursetup - setup completion callback
904 * @ep: The endpoint the request was on.
905 * @req: The request completed.
907 * Called on completion of any requests the driver itself
908 * submitted that need cleaning up.
910 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
911 struct usb_request *req)
913 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
914 struct s3c_hsotg *hsotg = hs_ep->parent;
916 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
918 s3c_hsotg_ep_free_request(ep, req);
922 * ep_from_windex - convert control wIndex value to endpoint
923 * @hsotg: The driver state.
924 * @windex: The control request wIndex field (in host order).
926 * Convert the given wIndex into a pointer to an driver endpoint
927 * structure, or return NULL if it is not a valid endpoint.
929 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
932 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
933 int dir = (windex & USB_DIR_IN) ? 1 : 0;
934 int idx = windex & 0x7F;
939 if (idx > S3C_HSOTG_EPS)
942 if (idx && ep->dir_in != dir)
949 * s3c_hsotg_send_reply - send reply to control request
950 * @hsotg: The device state
952 * @buff: Buffer for request
953 * @length: Length of reply.
955 * Create a request and queue it on the given endpoint. This is useful as
956 * an internal method of sending replies to certain control requests, etc.
958 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
959 struct s3c_hsotg_ep *ep,
963 struct usb_request *req;
966 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
968 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
969 hsotg->ep0_reply = req;
971 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
975 req->buf = hsotg->ep0_buff;
976 req->length = length;
977 req->zero = 1; /* always do zero-length final transfer */
978 req->complete = s3c_hsotg_complete_oursetup;
981 memcpy(req->buf, buff, length);
985 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
987 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
995 * s3c_hsotg_process_req_status - process request GET_STATUS
996 * @hsotg: The device state
997 * @ctrl: USB control request
999 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
1000 struct usb_ctrlrequest *ctrl)
1002 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1003 struct s3c_hsotg_ep *ep;
1007 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1010 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1014 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1015 case USB_RECIP_DEVICE:
1016 reply = cpu_to_le16(0); /* bit 0 => self powered,
1017 * bit 1 => remote wakeup */
1020 case USB_RECIP_INTERFACE:
1021 /* currently, the data result should be zero */
1022 reply = cpu_to_le16(0);
1025 case USB_RECIP_ENDPOINT:
1026 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1030 reply = cpu_to_le16(ep->halted ? 1 : 0);
1037 if (le16_to_cpu(ctrl->wLength) != 2)
1040 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
1042 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1049 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1052 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1053 * @hsotg: The device state
1054 * @ctrl: USB control request
1056 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
1057 struct usb_ctrlrequest *ctrl)
1059 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1060 struct s3c_hsotg_ep *ep;
1062 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1063 __func__, set ? "SET" : "CLEAR");
1065 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
1066 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1068 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1069 __func__, le16_to_cpu(ctrl->wIndex));
1073 switch (le16_to_cpu(ctrl->wValue)) {
1074 case USB_ENDPOINT_HALT:
1075 s3c_hsotg_ep_sethalt(&ep->ep, set);
1082 return -ENOENT; /* currently only deal with endpoint */
1088 * s3c_hsotg_process_control - process a control request
1089 * @hsotg: The device state
1090 * @ctrl: The control request received
1092 * The controller has received the SETUP phase of a control request, and
1093 * needs to work out what to do next (and whether to pass it on to the
1096 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1097 struct usb_ctrlrequest *ctrl)
1099 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1105 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1106 ctrl->bRequest, ctrl->bRequestType,
1107 ctrl->wValue, ctrl->wLength);
1109 /* record the direction of the request, for later use when enquing
1110 * packets onto EP0. */
1112 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1113 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1115 /* if we've no data with this request, then the last part of the
1116 * transaction is going to implicitly be IN. */
1117 if (ctrl->wLength == 0)
1120 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1121 switch (ctrl->bRequest) {
1122 case USB_REQ_SET_ADDRESS:
1123 dcfg = readl(hsotg->regs + S3C_DCFG);
1124 dcfg &= ~S3C_DCFG_DevAddr_MASK;
1125 dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT;
1126 writel(dcfg, hsotg->regs + S3C_DCFG);
1128 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1130 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1133 case USB_REQ_GET_STATUS:
1134 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1137 case USB_REQ_CLEAR_FEATURE:
1138 case USB_REQ_SET_FEATURE:
1139 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1144 /* as a fallback, try delivering it to the driver to deal with */
1146 if (ret == 0 && hsotg->driver) {
1147 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1149 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1154 /* need to generate zlp in reply or take data */
1155 /* todo - deal with any data we might be sent? */
1156 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1160 /* the request is either unhandlable, or is not formatted correctly
1161 * so respond with a STALL for the status stage to indicate failure.
1168 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1169 reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0;
1171 /* S3C_DxEPCTL_Stall will be cleared by EP once it has
1172 * taken effect, so no need to clear later. */
1174 ctrl = readl(hsotg->regs + reg);
1175 ctrl |= S3C_DxEPCTL_Stall;
1176 ctrl |= S3C_DxEPCTL_CNAK;
1177 writel(ctrl, hsotg->regs + reg);
1180 "writen DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1181 ctrl, reg, readl(hsotg->regs + reg));
1183 /* don't belive we need to anything more to get the EP
1184 * to reply with a STALL packet */
1188 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1191 * s3c_hsotg_complete_setup - completion of a setup transfer
1192 * @ep: The endpoint the request was on.
1193 * @req: The request completed.
1195 * Called on completion of any requests the driver itself submitted for
1198 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1199 struct usb_request *req)
1201 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1202 struct s3c_hsotg *hsotg = hs_ep->parent;
1204 if (req->status < 0) {
1205 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1209 if (req->actual == 0)
1210 s3c_hsotg_enqueue_setup(hsotg);
1212 s3c_hsotg_process_control(hsotg, req->buf);
1216 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1217 * @hsotg: The device state.
1219 * Enqueue a request on EP0 if necessary to received any SETUP packets
1220 * received from the host.
1222 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1224 struct usb_request *req = hsotg->ctrl_req;
1225 struct s3c_hsotg_req *hs_req = our_req(req);
1228 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1232 req->buf = hsotg->ctrl_buff;
1233 req->complete = s3c_hsotg_complete_setup;
1235 if (!list_empty(&hs_req->queue)) {
1236 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1240 hsotg->eps[0].dir_in = 0;
1242 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1244 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1245 /* Don't think there's much we can do other than watch the
1251 * get_ep_head - return the first request on the endpoint
1252 * @hs_ep: The controller endpoint to get
1254 * Get the first request on the endpoint.
1256 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
1258 if (list_empty(&hs_ep->queue))
1261 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
1265 * s3c_hsotg_complete_request - complete a request given to us
1266 * @hsotg: The device state.
1267 * @hs_ep: The endpoint the request was on.
1268 * @hs_req: The request to complete.
1269 * @result: The result code (0 => Ok, otherwise errno)
1271 * The given request has finished, so call the necessary completion
1272 * if it has one and then look to see if we can start a new request
1275 * Note, expects the ep to already be locked as appropriate.
1277 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1278 struct s3c_hsotg_ep *hs_ep,
1279 struct s3c_hsotg_req *hs_req,
1285 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1289 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1290 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1292 /* only replace the status if we've not already set an error
1293 * from a previous transaction */
1295 if (hs_req->req.status == -EINPROGRESS)
1296 hs_req->req.status = result;
1299 list_del_init(&hs_req->queue);
1301 if (using_dma(hsotg))
1302 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1304 /* call the complete request with the locks off, just in case the
1305 * request tries to queue more work for this endpoint. */
1307 if (hs_req->req.complete) {
1308 spin_unlock(&hs_ep->lock);
1309 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1310 spin_lock(&hs_ep->lock);
1313 /* Look to see if there is anything else to do. Note, the completion
1314 * of the previous request may have caused a new request to be started
1315 * so be careful when doing this. */
1317 if (!hs_ep->req && result >= 0) {
1318 restart = !list_empty(&hs_ep->queue);
1320 hs_req = get_ep_head(hs_ep);
1321 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1327 * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
1328 * @hsotg: The device state.
1329 * @hs_ep: The endpoint the request was on.
1330 * @hs_req: The request to complete.
1331 * @result: The result code (0 => Ok, otherwise errno)
1333 * See s3c_hsotg_complete_request(), but called with the endpoint's
1336 static void s3c_hsotg_complete_request_lock(struct s3c_hsotg *hsotg,
1337 struct s3c_hsotg_ep *hs_ep,
1338 struct s3c_hsotg_req *hs_req,
1341 unsigned long flags;
1343 spin_lock_irqsave(&hs_ep->lock, flags);
1344 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1345 spin_unlock_irqrestore(&hs_ep->lock, flags);
1349 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1350 * @hsotg: The device state.
1351 * @ep_idx: The endpoint index for the data
1352 * @size: The size of data in the fifo, in bytes
1354 * The FIFO status shows there is data to read from the FIFO for a given
1355 * endpoint, so sort out whether we need to read the data into a request
1356 * that has been made for that endpoint.
1358 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1360 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1361 struct s3c_hsotg_req *hs_req = hs_ep->req;
1362 void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx);
1368 u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx));
1371 dev_warn(hsotg->dev,
1372 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1373 __func__, size, ep_idx, epctl);
1375 /* dump the data from the FIFO, we've nothing we can do */
1376 for (ptr = 0; ptr < size; ptr += 4)
1382 spin_lock(&hs_ep->lock);
1385 read_ptr = hs_req->req.actual;
1386 max_req = hs_req->req.length - read_ptr;
1388 if (to_read > max_req) {
1389 /* more data appeared than we where willing
1390 * to deal with in this request.
1393 /* currently we don't deal this */
1397 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1398 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1400 hs_ep->total_data += to_read;
1401 hs_req->req.actual += to_read;
1402 to_read = DIV_ROUND_UP(to_read, 4);
1404 /* note, we might over-write the buffer end by 3 bytes depending on
1405 * alignment of the data. */
1406 readsl(fifo, hs_req->req.buf + read_ptr, to_read);
1408 spin_unlock(&hs_ep->lock);
1412 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1413 * @hsotg: The device instance
1414 * @req: The request currently on this endpoint
1416 * Generate a zero-length IN packet request for terminating a SETUP
1419 * Note, since we don't write any data to the TxFIFO, then it is
1420 * currently belived that we do not need to wait for any space in
1423 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1424 struct s3c_hsotg_req *req)
1429 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1433 if (req->req.length == 0) {
1434 hsotg->eps[0].sent_zlp = 1;
1435 s3c_hsotg_enqueue_setup(hsotg);
1439 hsotg->eps[0].dir_in = 1;
1440 hsotg->eps[0].sent_zlp = 1;
1442 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1444 /* issue a zero-sized packet to terminate this */
1445 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
1446 S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0));
1448 ctrl = readl(hsotg->regs + S3C_DIEPCTL0);
1449 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
1450 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
1451 ctrl |= S3C_DxEPCTL_USBActEp;
1452 writel(ctrl, hsotg->regs + S3C_DIEPCTL0);
1456 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1457 * @hsotg: The device instance
1458 * @epnum: The endpoint received from
1459 * @was_setup: Set if processing a SetupDone event.
1461 * The RXFIFO has delivered an OutDone event, which means that the data
1462 * transfer for an OUT endpoint has been completed, either by a short
1463 * packet or by the finish of a transfer.
1465 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1466 int epnum, bool was_setup)
1468 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1469 struct s3c_hsotg_req *hs_req = hs_ep->req;
1470 struct usb_request *req = &hs_req->req;
1474 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1478 if (using_dma(hsotg)) {
1479 u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum));
1483 /* Calculate the size of the transfer by checking how much
1484 * is left in the endpoint size register and then working it
1485 * out from the amount we loaded for the transfer.
1487 * We need to do this as DMA pointers are always 32bit aligned
1488 * so may overshoot/undershoot the transfer.
1491 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1493 size_done = hs_ep->size_loaded - size_left;
1494 size_done += hs_ep->last_load;
1496 req->actual = size_done;
1499 if (req->actual < req->length && req->short_not_ok) {
1500 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1501 __func__, req->actual, req->length);
1503 /* todo - what should we return here? there's no one else
1504 * even bothering to check the status. */
1508 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1509 s3c_hsotg_send_zlp(hsotg, hs_req);
1512 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, result);
1516 * s3c_hsotg_read_frameno - read current frame number
1517 * @hsotg: The device instance
1519 * Return the current frame number
1521 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1525 dsts = readl(hsotg->regs + S3C_DSTS);
1526 dsts &= S3C_DSTS_SOFFN_MASK;
1527 dsts >>= S3C_DSTS_SOFFN_SHIFT;
1533 * s3c_hsotg_handle_rx - RX FIFO has data
1534 * @hsotg: The device instance
1536 * The IRQ handler has detected that the RX FIFO has some data in it
1537 * that requires processing, so find out what is in there and do the
1540 * The RXFIFO is a true FIFO, the packets comming out are still in packet
1541 * chunks, so if you have x packets received on an endpoint you'll get x
1542 * FIFO events delivered, each with a packet's worth of data in it.
1544 * When using DMA, we should not be processing events from the RXFIFO
1545 * as the actual data should be sent to the memory directly and we turn
1546 * on the completion interrupts to get notifications of transfer completion.
1548 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1550 u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP);
1551 u32 epnum, status, size;
1553 WARN_ON(using_dma(hsotg));
1555 epnum = grxstsr & S3C_GRXSTS_EPNum_MASK;
1556 status = grxstsr & S3C_GRXSTS_PktSts_MASK;
1558 size = grxstsr & S3C_GRXSTS_ByteCnt_MASK;
1559 size >>= S3C_GRXSTS_ByteCnt_SHIFT;
1562 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1563 __func__, grxstsr, size, epnum);
1565 #define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT)
1567 switch (status >> S3C_GRXSTS_PktSts_SHIFT) {
1568 case __status(S3C_GRXSTS_PktSts_GlobalOutNAK):
1569 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1572 case __status(S3C_GRXSTS_PktSts_OutDone):
1573 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1574 s3c_hsotg_read_frameno(hsotg));
1576 if (!using_dma(hsotg))
1577 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1580 case __status(S3C_GRXSTS_PktSts_SetupDone):
1582 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1583 s3c_hsotg_read_frameno(hsotg),
1584 readl(hsotg->regs + S3C_DOEPCTL(0)));
1586 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1589 case __status(S3C_GRXSTS_PktSts_OutRX):
1590 s3c_hsotg_rx_data(hsotg, epnum, size);
1593 case __status(S3C_GRXSTS_PktSts_SetupRX):
1595 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1596 s3c_hsotg_read_frameno(hsotg),
1597 readl(hsotg->regs + S3C_DOEPCTL(0)));
1599 s3c_hsotg_rx_data(hsotg, epnum, size);
1603 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1606 s3c_hsotg_dump(hsotg);
1612 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1613 * @mps: The maximum packet size in bytes.
1615 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1619 return S3C_D0EPCTL_MPS_64;
1621 return S3C_D0EPCTL_MPS_32;
1623 return S3C_D0EPCTL_MPS_16;
1625 return S3C_D0EPCTL_MPS_8;
1628 /* bad max packet size, warn and return invalid result */
1634 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1635 * @hsotg: The driver state.
1636 * @ep: The index number of the endpoint
1637 * @mps: The maximum packet size in bytes
1639 * Configure the maximum packet size for the given endpoint, updating
1640 * the hardware control registers to reflect this.
1642 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1643 unsigned int ep, unsigned int mps)
1645 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1646 void __iomem *regs = hsotg->regs;
1651 /* EP0 is a special case */
1652 mpsval = s3c_hsotg_ep0_mps(mps);
1656 if (mps >= S3C_DxEPCTL_MPS_LIMIT+1)
1662 hs_ep->ep.maxpacket = mps;
1664 /* update both the in and out endpoint controldir_ registers, even
1665 * if one of the directions may not be in use. */
1667 reg = readl(regs + S3C_DIEPCTL(ep));
1668 reg &= ~S3C_DxEPCTL_MPS_MASK;
1670 writel(reg, regs + S3C_DIEPCTL(ep));
1672 reg = readl(regs + S3C_DOEPCTL(ep));
1673 reg &= ~S3C_DxEPCTL_MPS_MASK;
1675 writel(reg, regs + S3C_DOEPCTL(ep));
1680 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1685 * s3c_hsotg_trytx - check to see if anything needs transmitting
1686 * @hsotg: The driver state
1687 * @hs_ep: The driver endpoint to check.
1689 * Check to see if there is a request that has data to send, and if so
1690 * make an attempt to write data into the FIFO.
1692 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1693 struct s3c_hsotg_ep *hs_ep)
1695 struct s3c_hsotg_req *hs_req = hs_ep->req;
1697 if (!hs_ep->dir_in || !hs_req)
1700 if (hs_req->req.actual < hs_req->req.length) {
1701 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1703 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1710 * s3c_hsotg_complete_in - complete IN transfer
1711 * @hsotg: The device state.
1712 * @hs_ep: The endpoint that has just completed.
1714 * An IN transfer has been completed, update the transfer's state and then
1715 * call the relevant completion routines.
1717 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1718 struct s3c_hsotg_ep *hs_ep)
1720 struct s3c_hsotg_req *hs_req = hs_ep->req;
1721 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
1722 int size_left, size_done;
1725 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1729 /* Calculate the size of the transfer by checking how much is left
1730 * in the endpoint size register and then working it out from
1731 * the amount we loaded for the transfer.
1733 * We do this even for DMA, as the transfer may have incremented
1734 * past the end of the buffer (DMA transfers are always 32bit
1738 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1740 size_done = hs_ep->size_loaded - size_left;
1741 size_done += hs_ep->last_load;
1743 if (hs_req->req.actual != size_done)
1744 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1745 __func__, hs_req->req.actual, size_done);
1747 hs_req->req.actual = size_done;
1749 /* if we did all of the transfer, and there is more data left
1750 * around, then try restarting the rest of the request */
1752 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1753 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1754 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1756 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, 0);
1760 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1761 * @hsotg: The driver state
1762 * @idx: The index for the endpoint (0..15)
1763 * @dir_in: Set if this is an IN endpoint
1765 * Process and clear any interrupt pending for an individual endpoint
1767 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1770 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1771 u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx);
1772 u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx);
1773 u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx);
1777 ints = readl(hsotg->regs + epint_reg);
1779 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1780 __func__, idx, dir_in ? "in" : "out", ints);
1782 if (ints & S3C_DxEPINT_XferCompl) {
1784 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1785 __func__, readl(hsotg->regs + epctl_reg),
1786 readl(hsotg->regs + epsiz_reg));
1788 /* we get OutDone from the FIFO, so we only need to look
1789 * at completing IN requests here */
1791 s3c_hsotg_complete_in(hsotg, hs_ep);
1793 if (idx == 0 && !hs_ep->req)
1794 s3c_hsotg_enqueue_setup(hsotg);
1795 } else if (using_dma(hsotg)) {
1796 /* We're using DMA, we need to fire an OutDone here
1797 * as we ignore the RXFIFO. */
1799 s3c_hsotg_handle_outdone(hsotg, idx, false);
1802 clear |= S3C_DxEPINT_XferCompl;
1805 if (ints & S3C_DxEPINT_EPDisbld) {
1806 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1807 clear |= S3C_DxEPINT_EPDisbld;
1810 if (ints & S3C_DxEPINT_AHBErr) {
1811 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1812 clear |= S3C_DxEPINT_AHBErr;
1815 if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */
1816 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1818 if (using_dma(hsotg) && idx == 0) {
1819 /* this is the notification we've received a
1820 * setup packet. In non-DMA mode we'd get this
1821 * from the RXFIFO, instead we need to process
1822 * the setup here. */
1827 s3c_hsotg_handle_outdone(hsotg, 0, true);
1830 clear |= S3C_DxEPINT_Setup;
1833 if (ints & S3C_DxEPINT_Back2BackSetup) {
1834 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1835 clear |= S3C_DxEPINT_Back2BackSetup;
1839 /* not sure if this is important, but we'll clear it anyway
1841 if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
1842 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1844 clear |= S3C_DIEPMSK_INTknTXFEmpMsk;
1847 /* this probably means something bad is happening */
1848 if (ints & S3C_DIEPMSK_INTknEPMisMsk) {
1849 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1851 clear |= S3C_DIEPMSK_INTknEPMisMsk;
1854 /* FIFO has space or is empty (see GAHBCFG) */
1855 if (hsotg->dedicated_fifos &&
1856 ints & S3C_DIEPMSK_TxFIFOEmpty) {
1857 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
1859 s3c_hsotg_trytx(hsotg, hs_ep);
1860 clear |= S3C_DIEPMSK_TxFIFOEmpty;
1864 writel(clear, hsotg->regs + epint_reg);
1868 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1869 * @hsotg: The device state.
1871 * Handle updating the device settings after the enumeration phase has
1874 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1876 u32 dsts = readl(hsotg->regs + S3C_DSTS);
1877 int ep0_mps = 0, ep_mps;
1879 /* This should signal the finish of the enumeration phase
1880 * of the USB handshaking, so we should now know what rate
1881 * we connected at. */
1883 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1885 /* note, since we're limited by the size of transfer on EP0, and
1886 * it seems IN transfers must be a even number of packets we do
1887 * not advertise a 64byte MPS on EP0. */
1889 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1890 switch (dsts & S3C_DSTS_EnumSpd_MASK) {
1891 case S3C_DSTS_EnumSpd_FS:
1892 case S3C_DSTS_EnumSpd_FS48:
1893 hsotg->gadget.speed = USB_SPEED_FULL;
1894 dev_info(hsotg->dev, "new device is full-speed\n");
1896 ep0_mps = EP0_MPS_LIMIT;
1900 case S3C_DSTS_EnumSpd_HS:
1901 dev_info(hsotg->dev, "new device is high-speed\n");
1902 hsotg->gadget.speed = USB_SPEED_HIGH;
1904 ep0_mps = EP0_MPS_LIMIT;
1908 case S3C_DSTS_EnumSpd_LS:
1909 hsotg->gadget.speed = USB_SPEED_LOW;
1910 dev_info(hsotg->dev, "new device is low-speed\n");
1912 /* note, we don't actually support LS in this driver at the
1913 * moment, and the documentation seems to imply that it isn't
1914 * supported by the PHYs on some of the devices.
1919 /* we should now know the maximum packet size for an
1920 * endpoint, so set the endpoints to a default value. */
1924 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
1925 for (i = 1; i < S3C_HSOTG_EPS; i++)
1926 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1929 /* ensure after enumeration our EP0 is active */
1931 s3c_hsotg_enqueue_setup(hsotg);
1933 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1934 readl(hsotg->regs + S3C_DIEPCTL0),
1935 readl(hsotg->regs + S3C_DOEPCTL0));
1939 * kill_all_requests - remove all requests from the endpoint's queue
1940 * @hsotg: The device state.
1941 * @ep: The endpoint the requests may be on.
1942 * @result: The result code to use.
1943 * @force: Force removal of any current requests
1945 * Go through the requests on the given endpoint and mark them
1946 * completed with the given result code.
1948 static void kill_all_requests(struct s3c_hsotg *hsotg,
1949 struct s3c_hsotg_ep *ep,
1950 int result, bool force)
1952 struct s3c_hsotg_req *req, *treq;
1953 unsigned long flags;
1955 spin_lock_irqsave(&ep->lock, flags);
1957 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
1958 /* currently, we can't do much about an already
1959 * running request on an in endpoint */
1961 if (ep->req == req && ep->dir_in && !force)
1964 s3c_hsotg_complete_request(hsotg, ep, req,
1968 spin_unlock_irqrestore(&ep->lock, flags);
1971 #define call_gadget(_hs, _entry) \
1972 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
1973 (_hs)->driver && (_hs)->driver->_entry) \
1974 (_hs)->driver->_entry(&(_hs)->gadget);
1977 * s3c_hsotg_disconnect_irq - disconnect irq service
1978 * @hsotg: The device state.
1980 * A disconnect IRQ has been received, meaning that the host has
1981 * lost contact with the bus. Remove all current transactions
1982 * and signal the gadget driver that this has happened.
1984 static void s3c_hsotg_disconnect_irq(struct s3c_hsotg *hsotg)
1988 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
1989 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
1991 call_gadget(hsotg, disconnect);
1995 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
1996 * @hsotg: The device state:
1997 * @periodic: True if this is a periodic FIFO interrupt
1999 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
2001 struct s3c_hsotg_ep *ep;
2004 /* look through for any more data to transmit */
2006 for (epno = 0; epno < S3C_HSOTG_EPS; epno++) {
2007 ep = &hsotg->eps[epno];
2012 if ((periodic && !ep->periodic) ||
2013 (!periodic && ep->periodic))
2016 ret = s3c_hsotg_trytx(hsotg, ep);
2022 static struct s3c_hsotg *our_hsotg;
2024 /* IRQ flags which will trigger a retry around the IRQ loop */
2025 #define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \
2026 S3C_GINTSTS_PTxFEmp | \
2030 * s3c_hsotg_irq - handle device interrupt
2031 * @irq: The IRQ number triggered
2032 * @pw: The pw value when registered the handler.
2034 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2036 struct s3c_hsotg *hsotg = pw;
2037 int retry_count = 8;
2042 gintsts = readl(hsotg->regs + S3C_GINTSTS);
2043 gintmsk = readl(hsotg->regs + S3C_GINTMSK);
2045 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2046 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2050 if (gintsts & S3C_GINTSTS_OTGInt) {
2051 u32 otgint = readl(hsotg->regs + S3C_GOTGINT);
2053 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2055 writel(otgint, hsotg->regs + S3C_GOTGINT);
2056 writel(S3C_GINTSTS_OTGInt, hsotg->regs + S3C_GINTSTS);
2059 if (gintsts & S3C_GINTSTS_DisconnInt) {
2060 dev_dbg(hsotg->dev, "%s: DisconnInt\n", __func__);
2061 writel(S3C_GINTSTS_DisconnInt, hsotg->regs + S3C_GINTSTS);
2063 s3c_hsotg_disconnect_irq(hsotg);
2066 if (gintsts & S3C_GINTSTS_SessReqInt) {
2067 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2068 writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS);
2071 if (gintsts & S3C_GINTSTS_EnumDone) {
2072 s3c_hsotg_irq_enumdone(hsotg);
2073 writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS);
2076 if (gintsts & S3C_GINTSTS_ConIDStsChng) {
2077 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2078 readl(hsotg->regs + S3C_DSTS),
2079 readl(hsotg->regs + S3C_GOTGCTL));
2081 writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS);
2084 if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) {
2085 u32 daint = readl(hsotg->regs + S3C_DAINT);
2086 u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT;
2087 u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT);
2090 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2092 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2094 s3c_hsotg_epint(hsotg, ep, 0);
2097 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2099 s3c_hsotg_epint(hsotg, ep, 1);
2102 writel(daint, hsotg->regs + S3C_DAINT);
2103 writel(gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt),
2104 hsotg->regs + S3C_GINTSTS);
2107 if (gintsts & S3C_GINTSTS_USBRst) {
2108 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2109 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2110 readl(hsotg->regs + S3C_GNPTXSTS));
2112 kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true);
2114 /* it seems after a reset we can end up with a situation
2115 * where the TXFIFO still has data in it... the docs
2116 * suggest resetting all the fifos, so use the init_fifo
2117 * code to relayout and flush the fifos.
2120 s3c_hsotg_init_fifo(hsotg);
2122 s3c_hsotg_enqueue_setup(hsotg);
2124 writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
2127 /* check both FIFOs */
2129 if (gintsts & S3C_GINTSTS_NPTxFEmp) {
2130 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2132 /* Disable the interrupt to stop it happening again
2133 * unless one of these endpoint routines decides that
2134 * it needs re-enabling */
2136 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
2137 s3c_hsotg_irq_fifoempty(hsotg, false);
2139 writel(S3C_GINTSTS_NPTxFEmp, hsotg->regs + S3C_GINTSTS);
2142 if (gintsts & S3C_GINTSTS_PTxFEmp) {
2143 dev_dbg(hsotg->dev, "PTxFEmp\n");
2145 /* See note in S3C_GINTSTS_NPTxFEmp */
2147 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
2148 s3c_hsotg_irq_fifoempty(hsotg, true);
2150 writel(S3C_GINTSTS_PTxFEmp, hsotg->regs + S3C_GINTSTS);
2153 if (gintsts & S3C_GINTSTS_RxFLvl) {
2154 /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2155 * we need to retry s3c_hsotg_handle_rx if this is still
2158 s3c_hsotg_handle_rx(hsotg);
2159 writel(S3C_GINTSTS_RxFLvl, hsotg->regs + S3C_GINTSTS);
2162 if (gintsts & S3C_GINTSTS_ModeMis) {
2163 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2164 writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS);
2167 if (gintsts & S3C_GINTSTS_USBSusp) {
2168 dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n");
2169 writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS);
2171 call_gadget(hsotg, suspend);
2174 if (gintsts & S3C_GINTSTS_WkUpInt) {
2175 dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n");
2176 writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS);
2178 call_gadget(hsotg, resume);
2181 if (gintsts & S3C_GINTSTS_ErlySusp) {
2182 dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n");
2183 writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS);
2186 /* these next two seem to crop-up occasionally causing the core
2187 * to shutdown the USB transfer, so try clearing them and logging
2190 if (gintsts & S3C_GINTSTS_GOUTNakEff) {
2191 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2193 s3c_hsotg_dump(hsotg);
2195 writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL);
2196 writel(S3C_GINTSTS_GOUTNakEff, hsotg->regs + S3C_GINTSTS);
2199 if (gintsts & S3C_GINTSTS_GINNakEff) {
2200 dev_info(hsotg->dev, "GINNakEff triggered\n");
2202 s3c_hsotg_dump(hsotg);
2204 writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL);
2205 writel(S3C_GINTSTS_GINNakEff, hsotg->regs + S3C_GINTSTS);
2208 /* if we've had fifo events, we should try and go around the
2209 * loop again to see if there's any point in returning yet. */
2211 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2218 * s3c_hsotg_ep_enable - enable the given endpoint
2219 * @ep: The USB endpint to configure
2220 * @desc: The USB endpoint descriptor to configure with.
2222 * This is called from the USB gadget code's usb_ep_enable().
2224 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2225 const struct usb_endpoint_descriptor *desc)
2227 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2228 struct s3c_hsotg *hsotg = hs_ep->parent;
2229 unsigned long flags;
2230 int index = hs_ep->index;
2238 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2239 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2240 desc->wMaxPacketSize, desc->bInterval);
2242 /* not to be called for EP0 */
2243 WARN_ON(index == 0);
2245 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2246 if (dir_in != hs_ep->dir_in) {
2247 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2251 mps = le16_to_cpu(desc->wMaxPacketSize);
2253 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2255 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2256 epctrl = readl(hsotg->regs + epctrl_reg);
2258 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2259 __func__, epctrl, epctrl_reg);
2261 spin_lock_irqsave(&hs_ep->lock, flags);
2263 epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK);
2264 epctrl |= S3C_DxEPCTL_MPS(mps);
2266 /* mark the endpoint as active, otherwise the core may ignore
2267 * transactions entirely for this endpoint */
2268 epctrl |= S3C_DxEPCTL_USBActEp;
2270 /* set the NAK status on the endpoint, otherwise we might try and
2271 * do something with data that we've yet got a request to process
2272 * since the RXFIFO will take data for an endpoint even if the
2273 * size register hasn't been set.
2276 epctrl |= S3C_DxEPCTL_SNAK;
2278 /* update the endpoint state */
2279 hs_ep->ep.maxpacket = mps;
2281 /* default, set to non-periodic */
2282 hs_ep->periodic = 0;
2284 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2285 case USB_ENDPOINT_XFER_ISOC:
2286 dev_err(hsotg->dev, "no current ISOC support\n");
2290 case USB_ENDPOINT_XFER_BULK:
2291 epctrl |= S3C_DxEPCTL_EPType_Bulk;
2294 case USB_ENDPOINT_XFER_INT:
2296 /* Allocate our TxFNum by simply using the index
2297 * of the endpoint for the moment. We could do
2298 * something better if the host indicates how
2299 * many FIFOs we are expecting to use. */
2301 hs_ep->periodic = 1;
2302 epctrl |= S3C_DxEPCTL_TxFNum(index);
2305 epctrl |= S3C_DxEPCTL_EPType_Intterupt;
2308 case USB_ENDPOINT_XFER_CONTROL:
2309 epctrl |= S3C_DxEPCTL_EPType_Control;
2313 /* if the hardware has dedicated fifos, we must give each IN EP
2314 * a unique tx-fifo even if it is non-periodic.
2316 if (dir_in && hsotg->dedicated_fifos)
2317 epctrl |= S3C_DxEPCTL_TxFNum(index);
2319 /* for non control endpoints, set PID to D0 */
2321 epctrl |= S3C_DxEPCTL_SetD0PID;
2323 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2326 writel(epctrl, hsotg->regs + epctrl_reg);
2327 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2328 __func__, readl(hsotg->regs + epctrl_reg));
2330 /* enable the endpoint interrupt */
2331 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2334 spin_unlock_irqrestore(&hs_ep->lock, flags);
2338 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2340 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2341 struct s3c_hsotg *hsotg = hs_ep->parent;
2342 int dir_in = hs_ep->dir_in;
2343 int index = hs_ep->index;
2344 unsigned long flags;
2348 dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2350 if (ep == &hsotg->eps[0].ep) {
2351 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2355 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2357 /* terminate all requests with shutdown */
2358 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2360 spin_lock_irqsave(&hs_ep->lock, flags);
2362 ctrl = readl(hsotg->regs + epctrl_reg);
2363 ctrl &= ~S3C_DxEPCTL_EPEna;
2364 ctrl &= ~S3C_DxEPCTL_USBActEp;
2365 ctrl |= S3C_DxEPCTL_SNAK;
2367 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2368 writel(ctrl, hsotg->regs + epctrl_reg);
2370 /* disable endpoint interrupts */
2371 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2373 spin_unlock_irqrestore(&hs_ep->lock, flags);
2378 * on_list - check request is on the given endpoint
2379 * @ep: The endpoint to check.
2380 * @test: The request to test if it is on the endpoint.
2382 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2384 struct s3c_hsotg_req *req, *treq;
2386 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2394 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2396 struct s3c_hsotg_req *hs_req = our_req(req);
2397 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2398 struct s3c_hsotg *hs = hs_ep->parent;
2399 unsigned long flags;
2401 dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2403 if (hs_req == hs_ep->req) {
2404 dev_dbg(hs->dev, "%s: already in progress\n", __func__);
2405 return -EINPROGRESS;
2408 spin_lock_irqsave(&hs_ep->lock, flags);
2410 if (!on_list(hs_ep, hs_req)) {
2411 spin_unlock_irqrestore(&hs_ep->lock, flags);
2415 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2416 spin_unlock_irqrestore(&hs_ep->lock, flags);
2421 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2423 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2424 struct s3c_hsotg *hs = hs_ep->parent;
2425 int index = hs_ep->index;
2426 unsigned long irqflags;
2430 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2432 spin_lock_irqsave(&hs_ep->lock, irqflags);
2434 /* write both IN and OUT control registers */
2436 epreg = S3C_DIEPCTL(index);
2437 epctl = readl(hs->regs + epreg);
2440 epctl |= S3C_DxEPCTL_Stall;
2442 epctl &= ~S3C_DxEPCTL_Stall;
2444 writel(epctl, hs->regs + epreg);
2446 epreg = S3C_DOEPCTL(index);
2447 epctl = readl(hs->regs + epreg);
2450 epctl |= S3C_DxEPCTL_Stall;
2452 epctl &= ~S3C_DxEPCTL_Stall;
2454 writel(epctl, hs->regs + epreg);
2456 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
2461 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2462 .enable = s3c_hsotg_ep_enable,
2463 .disable = s3c_hsotg_ep_disable,
2464 .alloc_request = s3c_hsotg_ep_alloc_request,
2465 .free_request = s3c_hsotg_ep_free_request,
2466 .queue = s3c_hsotg_ep_queue,
2467 .dequeue = s3c_hsotg_ep_dequeue,
2468 .set_halt = s3c_hsotg_ep_sethalt,
2469 /* note, don't belive we have any call for the fifo routines */
2473 * s3c_hsotg_corereset - issue softreset to the core
2474 * @hsotg: The device state
2476 * Issue a soft reset to the core, and await the core finishing it.
2478 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2483 dev_dbg(hsotg->dev, "resetting core\n");
2485 /* issue soft reset */
2486 writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL);
2490 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2491 } while (!(grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
2493 if (!(grstctl & S3C_GRSTCTL_CSftRst)) {
2494 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2501 u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2503 if (timeout-- < 0) {
2504 dev_info(hsotg->dev,
2505 "%s: reset failed, GRSTCTL=%08x\n",
2510 if (grstctl & S3C_GRSTCTL_CSftRst)
2513 if (!(grstctl & S3C_GRSTCTL_AHBIdle))
2516 break; /* reset done */
2519 dev_dbg(hsotg->dev, "reset successful\n");
2523 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
2525 struct s3c_hsotg *hsotg = our_hsotg;
2529 printk(KERN_ERR "%s: called with no device\n", __func__);
2534 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2538 if (driver->speed != USB_SPEED_HIGH &&
2539 driver->speed != USB_SPEED_FULL) {
2540 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2543 if (!driver->bind || !driver->setup) {
2544 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2548 WARN_ON(hsotg->driver);
2550 driver->driver.bus = NULL;
2551 hsotg->driver = driver;
2552 hsotg->gadget.dev.driver = &driver->driver;
2553 hsotg->gadget.dev.dma_mask = hsotg->dev->dma_mask;
2554 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2556 ret = device_add(&hsotg->gadget.dev);
2558 dev_err(hsotg->dev, "failed to register gadget device\n");
2562 ret = driver->bind(&hsotg->gadget);
2564 dev_err(hsotg->dev, "failed bind %s\n", driver->driver.name);
2566 hsotg->gadget.dev.driver = NULL;
2567 hsotg->driver = NULL;
2571 /* we must now enable ep0 ready for host detection and then
2572 * set configuration. */
2574 s3c_hsotg_corereset(hsotg);
2576 /* set the PLL on, remove the HNP/SRP and set the PHY */
2577 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
2578 (0x5 << 10), hsotg->regs + S3C_GUSBCFG);
2580 /* looks like soft-reset changes state of FIFOs */
2581 s3c_hsotg_init_fifo(hsotg);
2583 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2585 writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
2587 writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
2588 S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
2589 S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
2590 S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt |
2591 S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
2592 S3C_GINTSTS_ErlySusp,
2593 hsotg->regs + S3C_GINTMSK);
2595 if (using_dma(hsotg))
2596 writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
2597 S3C_GAHBCFG_HBstLen_Incr4,
2598 hsotg->regs + S3C_GAHBCFG);
2600 writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
2602 /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2603 * up being flooded with interrupts if the host is polling the
2604 * endpoint to try and read data. */
2606 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2607 S3C_DIEPMSK_INTknEPMisMsk |
2608 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk |
2609 ((hsotg->dedicated_fifos) ? S3C_DIEPMSK_TxFIFOEmpty : 0),
2610 hsotg->regs + S3C_DIEPMSK);
2612 /* don't need XferCompl, we get that from RXFIFO in slave mode. In
2613 * DMA mode we may need this. */
2614 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2615 S3C_DOEPMSK_EPDisbldMsk |
2616 (using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
2617 S3C_DIEPMSK_TimeOUTMsk) : 0),
2618 hsotg->regs + S3C_DOEPMSK);
2620 writel(0, hsotg->regs + S3C_DAINTMSK);
2622 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2623 readl(hsotg->regs + S3C_DIEPCTL0),
2624 readl(hsotg->regs + S3C_DOEPCTL0));
2626 /* enable in and out endpoint interrupts */
2627 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
2629 /* Enable the RXFIFO when in slave mode, as this is how we collect
2630 * the data. In DMA mode, we get events from the FIFO but also
2631 * things we cannot process, so do not use it. */
2632 if (!using_dma(hsotg))
2633 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
2635 /* Enable interrupts for EP0 in and out */
2636 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2637 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2639 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2640 udelay(10); /* see openiboot */
2641 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2643 dev_info(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
2645 /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
2646 writing to the EPCTL register.. */
2648 /* set to read 1 8byte packet */
2649 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
2650 S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2652 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2653 S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
2654 S3C_DxEPCTL_USBActEp,
2655 hsotg->regs + S3C_DOEPCTL0);
2657 /* enable, but don't activate EP0in */
2658 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2659 S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
2661 s3c_hsotg_enqueue_setup(hsotg);
2663 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2664 readl(hsotg->regs + S3C_DIEPCTL0),
2665 readl(hsotg->regs + S3C_DOEPCTL0));
2667 /* clear global NAKs */
2668 writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
2669 hsotg->regs + S3C_DCTL);
2671 /* must be at-least 3ms to allow bus to see disconnect */
2674 /* remove the soft-disconnect and let's go */
2675 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2677 /* report to the user, and return */
2679 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2683 hsotg->driver = NULL;
2684 hsotg->gadget.dev.driver = NULL;
2687 EXPORT_SYMBOL(usb_gadget_register_driver);
2689 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2691 struct s3c_hsotg *hsotg = our_hsotg;
2697 if (!driver || driver != hsotg->driver || !driver->unbind)
2700 /* all endpoints should be shutdown */
2701 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
2702 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2704 call_gadget(hsotg, disconnect);
2706 driver->unbind(&hsotg->gadget);
2707 hsotg->driver = NULL;
2708 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2710 device_del(&hsotg->gadget.dev);
2712 dev_info(hsotg->dev, "unregistered gadget driver '%s'\n",
2713 driver->driver.name);
2717 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2719 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2721 return s3c_hsotg_read_frameno(to_hsotg(gadget));
2724 static struct usb_gadget_ops s3c_hsotg_gadget_ops = {
2725 .get_frame = s3c_hsotg_gadget_getframe,
2729 * s3c_hsotg_initep - initialise a single endpoint
2730 * @hsotg: The device state.
2731 * @hs_ep: The endpoint to be initialised.
2732 * @epnum: The endpoint number
2734 * Initialise the given endpoint (as part of the probe and device state
2735 * creation) to give to the gadget driver. Setup the endpoint name, any
2736 * direction information and other state that may be required.
2738 static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
2739 struct s3c_hsotg_ep *hs_ep,
2747 else if ((epnum % 2) == 0) {
2754 hs_ep->index = epnum;
2756 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
2758 INIT_LIST_HEAD(&hs_ep->queue);
2759 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
2761 spin_lock_init(&hs_ep->lock);
2763 /* add to the list of endpoints known by the gadget driver */
2765 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
2767 hs_ep->parent = hsotg;
2768 hs_ep->ep.name = hs_ep->name;
2769 hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;
2770 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
2772 /* Read the FIFO size for the Periodic TX FIFO, even if we're
2773 * an OUT endpoint, we may as well do this if in future the
2774 * code is changed to make each endpoint's direction changeable.
2777 ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum));
2778 hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;
2780 /* if we're using dma, we need to set the next-endpoint pointer
2781 * to be something valid.
2784 if (using_dma(hsotg)) {
2785 u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15);
2786 writel(next, hsotg->regs + S3C_DIEPCTL(epnum));
2787 writel(next, hsotg->regs + S3C_DOEPCTL(epnum));
2792 * s3c_hsotg_otgreset - reset the OtG phy block
2793 * @hsotg: The host state.
2795 * Power up the phy, set the basic configuration and start the PHY.
2797 static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
2801 writel(0, S3C_PHYPWR);
2804 osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
2806 writel(osc | 0x10, S3C_PHYCLK);
2808 /* issue a full set of resets to the otg and core */
2810 writel(S3C_RSTCON_PHY, S3C_RSTCON);
2811 udelay(20); /* at-least 10uS */
2812 writel(0, S3C_RSTCON);
2816 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2820 /* unmask subset of endpoint interrupts */
2822 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2823 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2824 hsotg->regs + S3C_DIEPMSK);
2826 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2827 S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk,
2828 hsotg->regs + S3C_DOEPMSK);
2830 writel(0, hsotg->regs + S3C_DAINTMSK);
2832 /* Be in disconnected state until gadget is registered */
2833 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2836 /* post global nak until we're ready */
2837 writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak,
2838 hsotg->regs + S3C_DCTL);
2843 dev_info(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2844 readl(hsotg->regs + S3C_GRXFSIZ),
2845 readl(hsotg->regs + S3C_GNPTXFSIZ));
2847 s3c_hsotg_init_fifo(hsotg);
2849 /* set the PLL on, remove the HNP/SRP and set the PHY */
2850 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
2851 hsotg->regs + S3C_GUSBCFG);
2853 writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0,
2854 hsotg->regs + S3C_GAHBCFG);
2856 /* check hardware configuration */
2858 cfg4 = readl(hsotg->regs + 0x50);
2859 hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
2861 dev_info(hsotg->dev, "%s fifos\n",
2862 hsotg->dedicated_fifos ? "dedicated" : "shared");
2865 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
2867 struct device *dev = hsotg->dev;
2868 void __iomem *regs = hsotg->regs;
2872 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
2873 readl(regs + S3C_DCFG), readl(regs + S3C_DCTL),
2874 readl(regs + S3C_DIEPMSK));
2876 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
2877 readl(regs + S3C_GAHBCFG), readl(regs + 0x44));
2879 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2880 readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ));
2882 /* show periodic fifo settings */
2884 for (idx = 1; idx <= 15; idx++) {
2885 val = readl(regs + S3C_DPTXFSIZn(idx));
2886 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
2887 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2888 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2891 for (idx = 0; idx < 15; idx++) {
2893 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
2894 readl(regs + S3C_DIEPCTL(idx)),
2895 readl(regs + S3C_DIEPTSIZ(idx)),
2896 readl(regs + S3C_DIEPDMA(idx)));
2898 val = readl(regs + S3C_DOEPCTL(idx));
2900 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
2901 idx, readl(regs + S3C_DOEPCTL(idx)),
2902 readl(regs + S3C_DOEPTSIZ(idx)),
2903 readl(regs + S3C_DOEPDMA(idx)));
2907 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
2908 readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE));
2913 * state_show - debugfs: show overall driver and device state.
2914 * @seq: The seq file to write to.
2915 * @v: Unused parameter.
2917 * This debugfs entry shows the overall state of the hardware and
2918 * some general information about each of the endpoints available
2921 static int state_show(struct seq_file *seq, void *v)
2923 struct s3c_hsotg *hsotg = seq->private;
2924 void __iomem *regs = hsotg->regs;
2927 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
2928 readl(regs + S3C_DCFG),
2929 readl(regs + S3C_DCTL),
2930 readl(regs + S3C_DSTS));
2932 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
2933 readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK));
2935 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
2936 readl(regs + S3C_GINTMSK),
2937 readl(regs + S3C_GINTSTS));
2939 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
2940 readl(regs + S3C_DAINTMSK),
2941 readl(regs + S3C_DAINT));
2943 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
2944 readl(regs + S3C_GNPTXSTS),
2945 readl(regs + S3C_GRXSTSR));
2947 seq_printf(seq, "\nEndpoint status:\n");
2949 for (idx = 0; idx < 15; idx++) {
2952 in = readl(regs + S3C_DIEPCTL(idx));
2953 out = readl(regs + S3C_DOEPCTL(idx));
2955 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
2958 in = readl(regs + S3C_DIEPTSIZ(idx));
2959 out = readl(regs + S3C_DOEPTSIZ(idx));
2961 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
2964 seq_printf(seq, "\n");
2970 static int state_open(struct inode *inode, struct file *file)
2972 return single_open(file, state_show, inode->i_private);
2975 static const struct file_operations state_fops = {
2976 .owner = THIS_MODULE,
2979 .llseek = seq_lseek,
2980 .release = single_release,
2984 * fifo_show - debugfs: show the fifo information
2985 * @seq: The seq_file to write data to.
2986 * @v: Unused parameter.
2988 * Show the FIFO information for the overall fifo and all the
2989 * periodic transmission FIFOs.
2991 static int fifo_show(struct seq_file *seq, void *v)
2993 struct s3c_hsotg *hsotg = seq->private;
2994 void __iomem *regs = hsotg->regs;
2998 seq_printf(seq, "Non-periodic FIFOs:\n");
2999 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ));
3001 val = readl(regs + S3C_GNPTXFSIZ);
3002 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3003 val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT,
3004 val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK);
3006 seq_printf(seq, "\nPeriodic TXFIFOs:\n");
3008 for (idx = 1; idx <= 15; idx++) {
3009 val = readl(regs + S3C_DPTXFSIZn(idx));
3011 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3012 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
3013 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
3019 static int fifo_open(struct inode *inode, struct file *file)
3021 return single_open(file, fifo_show, inode->i_private);
3024 static const struct file_operations fifo_fops = {
3025 .owner = THIS_MODULE,
3028 .llseek = seq_lseek,
3029 .release = single_release,
3033 static const char *decode_direction(int is_in)
3035 return is_in ? "in" : "out";
3039 * ep_show - debugfs: show the state of an endpoint.
3040 * @seq: The seq_file to write data to.
3041 * @v: Unused parameter.
3043 * This debugfs entry shows the state of the given endpoint (one is
3044 * registered for each available).
3046 static int ep_show(struct seq_file *seq, void *v)
3048 struct s3c_hsotg_ep *ep = seq->private;
3049 struct s3c_hsotg *hsotg = ep->parent;
3050 struct s3c_hsotg_req *req;
3051 void __iomem *regs = hsotg->regs;
3052 int index = ep->index;
3053 int show_limit = 15;
3054 unsigned long flags;
3056 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
3057 ep->index, ep->ep.name, decode_direction(ep->dir_in));
3059 /* first show the register state */
3061 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3062 readl(regs + S3C_DIEPCTL(index)),
3063 readl(regs + S3C_DOEPCTL(index)));
3065 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3066 readl(regs + S3C_DIEPDMA(index)),
3067 readl(regs + S3C_DOEPDMA(index)));
3069 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3070 readl(regs + S3C_DIEPINT(index)),
3071 readl(regs + S3C_DOEPINT(index)));
3073 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3074 readl(regs + S3C_DIEPTSIZ(index)),
3075 readl(regs + S3C_DOEPTSIZ(index)));
3077 seq_printf(seq, "\n");
3078 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3079 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3081 seq_printf(seq, "request list (%p,%p):\n",
3082 ep->queue.next, ep->queue.prev);
3084 spin_lock_irqsave(&ep->lock, flags);
3086 list_for_each_entry(req, &ep->queue, queue) {
3087 if (--show_limit < 0) {
3088 seq_printf(seq, "not showing more requests...\n");
3092 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3093 req == ep->req ? '*' : ' ',
3094 req, req->req.length, req->req.buf);
3095 seq_printf(seq, "%d done, res %d\n",
3096 req->req.actual, req->req.status);
3099 spin_unlock_irqrestore(&ep->lock, flags);
3104 static int ep_open(struct inode *inode, struct file *file)
3106 return single_open(file, ep_show, inode->i_private);
3109 static const struct file_operations ep_fops = {
3110 .owner = THIS_MODULE,
3113 .llseek = seq_lseek,
3114 .release = single_release,
3118 * s3c_hsotg_create_debug - create debugfs directory and files
3119 * @hsotg: The driver state
3121 * Create the debugfs files to allow the user to get information
3122 * about the state of the system. The directory name is created
3123 * with the same name as the device itself, in case we end up
3124 * with multiple blocks in future systems.
3126 static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3128 struct dentry *root;
3131 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3132 hsotg->debug_root = root;
3134 dev_err(hsotg->dev, "cannot create debug root\n");
3138 /* create general state file */
3140 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3141 hsotg, &state_fops);
3143 if (IS_ERR(hsotg->debug_file))
3144 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3146 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3149 if (IS_ERR(hsotg->debug_fifo))
3150 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3152 /* create one file for each endpoint */
3154 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3155 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3157 ep->debugfs = debugfs_create_file(ep->name, 0444,
3158 root, ep, &ep_fops);
3160 if (IS_ERR(ep->debugfs))
3161 dev_err(hsotg->dev, "failed to create %s debug file\n",
3167 * s3c_hsotg_delete_debug - cleanup debugfs entries
3168 * @hsotg: The driver state
3170 * Cleanup (remove) the debugfs files for use on module exit.
3172 static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3176 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3177 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3178 debugfs_remove(ep->debugfs);
3181 debugfs_remove(hsotg->debug_file);
3182 debugfs_remove(hsotg->debug_fifo);
3183 debugfs_remove(hsotg->debug_root);
3187 * s3c_hsotg_gate - set the hardware gate for the block
3188 * @pdev: The device we bound to
3191 * Set the hardware gate setting into the block. If we end up on
3192 * something other than an S3C64XX, then we might need to change this
3193 * to using a platform data callback, or some other mechanism.
3195 static void s3c_hsotg_gate(struct platform_device *pdev, bool on)
3197 unsigned long flags;
3200 local_irq_save(flags);
3202 others = __raw_readl(S3C64XX_OTHERS);
3204 others |= S3C64XX_OTHERS_USBMASK;
3206 others &= ~S3C64XX_OTHERS_USBMASK;
3207 __raw_writel(others, S3C64XX_OTHERS);
3209 local_irq_restore(flags);
3212 static struct s3c_hsotg_plat s3c_hsotg_default_pdata;
3214 static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
3216 struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
3217 struct device *dev = &pdev->dev;
3218 struct s3c_hsotg *hsotg;
3219 struct resource *res;
3224 plat = &s3c_hsotg_default_pdata;
3226 hsotg = kzalloc(sizeof(struct s3c_hsotg) +
3227 sizeof(struct s3c_hsotg_ep) * S3C_HSOTG_EPS,
3230 dev_err(dev, "cannot get memory\n");
3237 platform_set_drvdata(pdev, hsotg);
3239 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3241 dev_err(dev, "cannot find register resource 0\n");
3246 hsotg->regs_res = request_mem_region(res->start, resource_size(res),
3248 if (!hsotg->regs_res) {
3249 dev_err(dev, "cannot reserve registers\n");
3254 hsotg->regs = ioremap(res->start, resource_size(res));
3256 dev_err(dev, "cannot map registers\n");
3261 ret = platform_get_irq(pdev, 0);
3263 dev_err(dev, "cannot find IRQ\n");
3269 ret = request_irq(ret, s3c_hsotg_irq, 0, dev_name(dev), hsotg);
3271 dev_err(dev, "cannot claim IRQ\n");
3275 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3277 device_initialize(&hsotg->gadget.dev);
3279 dev_set_name(&hsotg->gadget.dev, "gadget");
3281 hsotg->gadget.is_dualspeed = 1;
3282 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3283 hsotg->gadget.name = dev_name(dev);
3285 hsotg->gadget.dev.parent = dev;
3286 hsotg->gadget.dev.dma_mask = dev->dma_mask;
3288 /* setup endpoint information */
3290 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3291 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3293 /* allocate EP0 request */
3295 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3297 if (!hsotg->ctrl_req) {
3298 dev_err(dev, "failed to allocate ctrl req\n");
3302 /* reset the system */
3304 s3c_hsotg_gate(pdev, true);
3306 s3c_hsotg_otgreset(hsotg);
3307 s3c_hsotg_corereset(hsotg);
3308 s3c_hsotg_init(hsotg);
3310 /* initialise the endpoints now the core has been initialised */
3311 for (epnum = 0; epnum < S3C_HSOTG_EPS; epnum++)
3312 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3314 s3c_hsotg_create_debug(hsotg);
3316 s3c_hsotg_dump(hsotg);
3322 iounmap(hsotg->regs);
3325 release_resource(hsotg->regs_res);
3326 kfree(hsotg->regs_res);
3333 static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
3335 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3337 s3c_hsotg_delete_debug(hsotg);
3339 usb_gadget_unregister_driver(hsotg->driver);
3341 free_irq(hsotg->irq, hsotg);
3342 iounmap(hsotg->regs);
3344 release_resource(hsotg->regs_res);
3345 kfree(hsotg->regs_res);
3347 s3c_hsotg_gate(pdev, false);
3354 #define s3c_hsotg_suspend NULL
3355 #define s3c_hsotg_resume NULL
3358 static struct platform_driver s3c_hsotg_driver = {
3360 .name = "s3c-hsotg",
3361 .owner = THIS_MODULE,
3363 .probe = s3c_hsotg_probe,
3364 .remove = __devexit_p(s3c_hsotg_remove),
3365 .suspend = s3c_hsotg_suspend,
3366 .resume = s3c_hsotg_resume,
3369 static int __init s3c_hsotg_modinit(void)
3371 return platform_driver_register(&s3c_hsotg_driver);
3374 static void __exit s3c_hsotg_modexit(void)
3376 platform_driver_unregister(&s3c_hsotg_driver);
3379 module_init(s3c_hsotg_modinit);
3380 module_exit(s3c_hsotg_modexit);
3382 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3383 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3384 MODULE_LICENSE("GPL");
3385 MODULE_ALIAS("platform:s3c-hsotg");