drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/delay.h>
  41 #include <linux/slab.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/io.h>
  47 #include <linux/list.h>
  48 #include <linux/dma-mapping.h>
  49
  50 #include <linux/usb/ch9.h>
  51 #include <linux/usb/gadget.h>
  52
  53 #include "core.h"
  54 #include "gadget.h"
  55 #include "io.h"
  56
  57 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  58
  59 void dwc3_map_buffer_to_dma(struct dwc3_request *req)
  60 {
  61         struct dwc3                     *dwc = req->dep->dwc;
  62
  63         if (req->request.length == 0) {
  64                 /* req->request.dma = dwc->setup_buf_addr; */
  65                 return;
  66         }
  67
  68         if (req->request.dma == DMA_ADDR_INVALID) {
  69                 req->request.dma = dma_map_single(dwc->dev, req->request.buf,
  70                                 req->request.length, req->direction
  71                                 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  72                 req->mapped = true;
  73         }
  74 }
  75
  76 void dwc3_unmap_buffer_from_dma(struct dwc3_request *req)
  77 {
  78         struct dwc3                     *dwc = req->dep->dwc;
  79
  80         if (req->request.length == 0) {
  81                 req->request.dma = DMA_ADDR_INVALID;
  82                 return;
  83         }
  84
  85         if (req->mapped) {
  86                 dma_unmap_single(dwc->dev, req->request.dma,
  87                                 req->request.length, req->direction
  88                                 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  89                 req->mapped = 0;
  90                 req->request.dma = DMA_ADDR_INVALID;
  91         }
  92 }
  93
  94 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
  95                 int status)
  96 {
  97         struct dwc3                     *dwc = dep->dwc;
  98
  99         if (req->queued) {
 100                 dep->busy_slot++;
 101                 /*
 102                  * Skip LINK TRB. We can't use req->trb and check for
 103                  * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
 104                  * completed (not the LINK TRB).
 105                  */
 106                 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 107                                 usb_endpoint_xfer_isoc(dep->desc))
 108                         dep->busy_slot++;
 109         }
 110         list_del(&req->list);
 111
 112         if (req->request.status == -EINPROGRESS)
 113                 req->request.status = status;
 114
 115         dwc3_unmap_buffer_from_dma(req);
 116
 117         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 118                         req, dep->name, req->request.actual,
 119                         req->request.length, status);
 120
 121         spin_unlock(&dwc->lock);
 122         req->request.complete(&req->dep->endpoint, &req->request);
 123         spin_lock(&dwc->lock);
 124 }
 125
 126 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
 127 {
 128         switch (cmd) {
 129         case DWC3_DEPCMD_DEPSTARTCFG:
 130                 return "Start New Configuration";
 131         case DWC3_DEPCMD_ENDTRANSFER:
 132                 return "End Transfer";
 133         case DWC3_DEPCMD_UPDATETRANSFER:
 134                 return "Update Transfer";
 135         case DWC3_DEPCMD_STARTTRANSFER:
 136                 return "Start Transfer";
 137         case DWC3_DEPCMD_CLEARSTALL:
 138                 return "Clear Stall";
 139         case DWC3_DEPCMD_SETSTALL:
 140                 return "Set Stall";
 141         case DWC3_DEPCMD_GETSEQNUMBER:
 142                 return "Get Data Sequence Number";
 143         case DWC3_DEPCMD_SETTRANSFRESOURCE:
 144                 return "Set Endpoint Transfer Resource";
 145         case DWC3_DEPCMD_SETEPCONFIG:
 146                 return "Set Endpoint Configuration";
 147         default:
 148                 return "UNKNOWN command";
 149         }
 150 }
 151
 152 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 153                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 154 {
 155         struct dwc3_ep          *dep = dwc->eps[ep];
 156         u32                     timeout = 500;
 157         u32                     reg;
 158
 159         dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
 160                         dep->name,
 161                         dwc3_gadget_ep_cmd_string(cmd), params->param0.raw,
 162                         params->param1.raw, params->param2.raw);
 163
 164         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0.raw);
 165         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1.raw);
 166         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2.raw);
 167
 168         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 169         do {
 170                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 171                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 172                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 173                                         DWC3_DEPCMD_STATUS(reg));
 174                         return 0;
 175                 }
 176
 177                 /*
 178                  * We can't sleep here, because it is also called from
 179                  * interrupt context.
 180                  */
 181                 timeout--;
 182                 if (!timeout)
 183                         return -ETIMEDOUT;
 184
 185                 udelay(1);
 186         } while (1);
 187 }
 188
 189 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 190                 struct dwc3_trb_hw *trb)
 191 {
 192         u32             offset = trb - dep->trb_pool;
 193
 194         return dep->trb_pool_dma + offset;
 195 }
 196
 197 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 198 {
 199         struct dwc3             *dwc = dep->dwc;
 200
 201         if (dep->trb_pool)
 202                 return 0;
 203
 204         if (dep->number == 0 || dep->number == 1)
 205                 return 0;
 206
 207         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 208                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 209                         &dep->trb_pool_dma, GFP_KERNEL);
 210         if (!dep->trb_pool) {
 211                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 212                                 dep->name);
 213                 return -ENOMEM;
 214         }
 215
 216         return 0;
 217 }
 218
 219 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 220 {
 221         struct dwc3             *dwc = dep->dwc;
 222
 223         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 224                         dep->trb_pool, dep->trb_pool_dma);
 225
 226         dep->trb_pool = NULL;
 227         dep->trb_pool_dma = 0;
 228 }
 229
 230 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 231 {
 232         struct dwc3_gadget_ep_cmd_params params;
 233         u32                     cmd;
 234
 235         memset(&params, 0x00, sizeof(params));
 236
 237         if (dep->number != 1) {
 238                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 239                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 240                 if (dep->number > 1)
 241                         cmd |= DWC3_DEPCMD_PARAM(2);
 242
 243                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 244         }
 245
 246         return 0;
 247 }
 248
 249 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 250                 const struct usb_endpoint_descriptor *desc)
 251 {
 252         struct dwc3_gadget_ep_cmd_params params;
 253
 254         memset(&params, 0x00, sizeof(params));
 255
 256         params.param0.depcfg.ep_type = usb_endpoint_type(desc);
 257         params.param0.depcfg.max_packet_size = usb_endpoint_maxp(desc);
 258
 259         params.param1.depcfg.xfer_complete_enable = true;
 260         params.param1.depcfg.xfer_not_ready_enable = true;
 261
 262         if (usb_endpoint_xfer_isoc(desc))
 263                 params.param1.depcfg.xfer_in_progress_enable = true;
 264
 265         /*
 266          * We are doing 1:1 mapping for endpoints, meaning
 267          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 268          * so on. We consider the direction bit as part of the physical
 269          * endpoint number. So USB endpoint 0x81 is 0x03.
 270          */
 271         params.param1.depcfg.ep_number = dep->number;
 272
 273         /*
 274          * We must use the lower 16 TX FIFOs even though
 275          * HW might have more
 276          */
 277         if (dep->direction)
 278                 params.param0.depcfg.fifo_number = dep->number >> 1;
 279
 280         if (desc->bInterval) {
 281                 params.param1.depcfg.binterval_m1 = desc->bInterval - 1;
 282                 dep->interval = 1 << (desc->bInterval - 1);
 283         }
 284
 285         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 286                         DWC3_DEPCMD_SETEPCONFIG, &params);
 287 }
 288
 289 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 290 {
 291         struct dwc3_gadget_ep_cmd_params params;
 292
 293         memset(&params, 0x00, sizeof(params));
 294
 295         params.param0.depxfercfg.number_xfer_resources = 1;
 296
 297         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 298                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 299 }
 300
 301 /**
 302  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 303  * @dep: endpoint to be initialized
 304  * @desc: USB Endpoint Descriptor
 305  *
 306  * Caller should take care of locking
 307  */
 308 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 309                 const struct usb_endpoint_descriptor *desc)
 310 {
 311         struct dwc3             *dwc = dep->dwc;
 312         u32                     reg;
 313         int                     ret = -ENOMEM;
 314
 315         if (!(dep->flags & DWC3_EP_ENABLED)) {
 316                 ret = dwc3_gadget_start_config(dwc, dep);
 317                 if (ret)
 318                         return ret;
 319         }
 320
 321         ret = dwc3_gadget_set_ep_config(dwc, dep, desc);
 322         if (ret)
 323                 return ret;
 324
 325         if (!(dep->flags & DWC3_EP_ENABLED)) {
 326                 struct dwc3_trb_hw      *trb_st_hw;
 327                 struct dwc3_trb_hw      *trb_link_hw;
 328                 struct dwc3_trb         trb_link;
 329
 330                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 331                 if (ret)
 332                         return ret;
 333
 334                 dep->desc = desc;
 335                 dep->type = usb_endpoint_type(desc);
 336                 dep->flags |= DWC3_EP_ENABLED;
 337
 338                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 339                 reg |= DWC3_DALEPENA_EP(dep->number);
 340                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 341
 342                 if (!usb_endpoint_xfer_isoc(desc))
 343                         return 0;
 344
 345                 memset(&trb_link, 0, sizeof(trb_link));
 346
 347                 /* Link TRB for ISOC. The HWO but is never reset */
 348                 trb_st_hw = &dep->trb_pool[0];
 349
 350                 trb_link.bplh = dwc3_trb_dma_offset(dep, trb_st_hw);
 351                 trb_link.trbctl = DWC3_TRBCTL_LINK_TRB;
 352                 trb_link.hwo = true;
 353
 354                 trb_link_hw = &dep->trb_pool[DWC3_TRB_NUM - 1];
 355                 dwc3_trb_to_hw(&trb_link, trb_link_hw);
 356         }
 357
 358         return 0;
 359 }
 360
 361 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
 362 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 363 {
 364         struct dwc3_request             *req;
 365
 366         if (!list_empty(&dep->req_queued))
 367                 dwc3_stop_active_transfer(dwc, dep->number);
 368
 369         while (!list_empty(&dep->request_list)) {
 370                 req = next_request(&dep->request_list);
 371
 372                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 373         }
 374 }
 375
 376 /**
 377  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 378  * @dep: the endpoint to disable
 379  *
 380  * This function also removes requests which are currently processed ny the
 381  * hardware and those which are not yet scheduled.
 382  * Caller should take care of locking.
 383  */
 384 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 385 {
 386         struct dwc3             *dwc = dep->dwc;
 387         u32                     reg;
 388
 389         dep->flags &= ~DWC3_EP_ENABLED;
 390         dwc3_remove_requests(dwc, dep);
 391
 392         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 393         reg &= ~DWC3_DALEPENA_EP(dep->number);
 394         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 395
 396         dep->desc = NULL;
 397         dep->type = 0;
 398
 399         return 0;
 400 }
 401
 402 /* -------------------------------------------------------------------------- */
 403
 404 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 405                 const struct usb_endpoint_descriptor *desc)
 406 {
 407         return -EINVAL;
 408 }
 409
 410 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 411 {
 412         return -EINVAL;
 413 }
 414
 415 /* -------------------------------------------------------------------------- */
 416
 417 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 418                 const struct usb_endpoint_descriptor *desc)
 419 {
 420         struct dwc3_ep                  *dep;
 421         struct dwc3                     *dwc;
 422         unsigned long                   flags;
 423         int                             ret;
 424
 425         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 426                 pr_debug("dwc3: invalid parameters\n");
 427                 return -EINVAL;
 428         }
 429
 430         if (!desc->wMaxPacketSize) {
 431                 pr_debug("dwc3: missing wMaxPacketSize\n");
 432                 return -EINVAL;
 433         }
 434
 435         dep = to_dwc3_ep(ep);
 436         dwc = dep->dwc;
 437
 438         switch (usb_endpoint_type(desc)) {
 439         case USB_ENDPOINT_XFER_CONTROL:
 440                 strncat(dep->name, "-control", sizeof(dep->name));
 441                 break;
 442         case USB_ENDPOINT_XFER_ISOC:
 443                 strncat(dep->name, "-isoc", sizeof(dep->name));
 444                 break;
 445         case USB_ENDPOINT_XFER_BULK:
 446                 strncat(dep->name, "-bulk", sizeof(dep->name));
 447                 break;
 448         case USB_ENDPOINT_XFER_INT:
 449                 strncat(dep->name, "-int", sizeof(dep->name));
 450                 break;
 451         default:
 452                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 453         }
 454
 455         if (dep->flags & DWC3_EP_ENABLED) {
 456                 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
 457                                 dep->name);
 458                 return 0;
 459         }
 460
 461         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 462
 463         spin_lock_irqsave(&dwc->lock, flags);
 464         ret = __dwc3_gadget_ep_enable(dep, desc);
 465         spin_unlock_irqrestore(&dwc->lock, flags);
 466
 467         return ret;
 468 }
 469
 470 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 471 {
 472         struct dwc3_ep                  *dep;
 473         struct dwc3                     *dwc;
 474         unsigned long                   flags;
 475         int                             ret;
 476
 477         if (!ep) {
 478                 pr_debug("dwc3: invalid parameters\n");
 479                 return -EINVAL;
 480         }
 481
 482         dep = to_dwc3_ep(ep);
 483         dwc = dep->dwc;
 484
 485         if (!(dep->flags & DWC3_EP_ENABLED)) {
 486                 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
 487                                 dep->name);
 488                 return 0;
 489         }
 490
 491         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 492                         dep->number >> 1,
 493                         (dep->number & 1) ? "in" : "out");
 494
 495         spin_lock_irqsave(&dwc->lock, flags);
 496         ret = __dwc3_gadget_ep_disable(dep);
 497         spin_unlock_irqrestore(&dwc->lock, flags);
 498
 499         return ret;
 500 }
 501
 502 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 503         gfp_t gfp_flags)
 504 {
 505         struct dwc3_request             *req;
 506         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 507         struct dwc3                     *dwc = dep->dwc;
 508
 509         req = kzalloc(sizeof(*req), gfp_flags);
 510         if (!req) {
 511                 dev_err(dwc->dev, "not enough memory\n");
 512                 return NULL;
 513         }
 514
 515         req->epnum      = dep->number;
 516         req->dep        = dep;
 517         req->request.dma = DMA_ADDR_INVALID;
 518
 519         return &req->request;
 520 }
 521
 522 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 523                 struct usb_request *request)
 524 {
 525         struct dwc3_request             *req = to_dwc3_request(request);
 526
 527         kfree(req);
 528 }
 529
 530 /*
 531  * dwc3_prepare_trbs - setup TRBs from requests
 532  * @dep: endpoint for which requests are being prepared
 533  * @starting: true if the endpoint is idle and no requests are queued.
 534  *
 535  * The functions goes through the requests list and setups TRBs for the
 536  * transfers. The functions returns once there are not more TRBs available or
 537  * it run out of requests.
 538  */
 539 static struct dwc3_request *dwc3_prepare_trbs(struct dwc3_ep *dep,
 540                 bool starting)
 541 {
 542         struct dwc3_request     *req, *n, *ret = NULL;
 543         struct dwc3_trb_hw      *trb_hw;
 544         struct dwc3_trb         trb;
 545         u32                     trbs_left;
 546
 547         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 548
 549         /* the first request must not be queued */
 550         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 551         /*
 552          * if busy & slot are equal than it is either full or empty. If we are
 553          * starting to proceed requests then we are empty. Otherwise we ar
 554          * full and don't do anything
 555          */
 556         if (!trbs_left) {
 557                 if (!starting)
 558                         return NULL;
 559                 trbs_left = DWC3_TRB_NUM;
 560                 /*
 561                  * In case we start from scratch, we queue the ISOC requests
 562                  * starting from slot 1. This is done because we use ring
 563                  * buffer and have no LST bit to stop us. Instead, we place
 564                  * IOC bit TRB_NUM/4. We try to avoid to having an interrupt
 565                  * after the first request so we start at slot 1 and have
 566                  * 7 requests proceed before we hit the first IOC.
 567                  * Other transfer types don't use the ring buffer and are
 568                  * processed from the first TRB until the last one. Since we
 569                  * don't wrap around we have to start at the beginning.
 570                  */
 571                 if (usb_endpoint_xfer_isoc(dep->desc)) {
 572                         dep->busy_slot = 1;
 573                         dep->free_slot = 1;
 574                 } else {
 575                         dep->busy_slot = 0;
 576                         dep->free_slot = 0;
 577                 }
 578         }
 579
 580         /* The last TRB is a link TRB, not used for xfer */
 581         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc))
 582                 return NULL;
 583
 584         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 585                 unsigned int last_one = 0;
 586                 unsigned int cur_slot;
 587
 588                 trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 589                 cur_slot = dep->free_slot;
 590                 dep->free_slot++;
 591
 592                 /* Skip the LINK-TRB on ISOC */
 593                 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 594                                 usb_endpoint_xfer_isoc(dep->desc))
 595                         continue;
 596
 597                 dwc3_gadget_move_request_queued(req);
 598                 memset(&trb, 0, sizeof(trb));
 599                 trbs_left--;
 600
 601                 /* Is our TRB pool empty? */
 602                 if (!trbs_left)
 603                         last_one = 1;
 604                 /* Is this the last request? */
 605                 if (list_empty(&dep->request_list))
 606                         last_one = 1;
 607
 608                 /*
 609                  * FIXME we shouldn't need to set LST bit always but we are
 610                  * facing some weird problem with the Hardware where it doesn't
 611                  * complete even though it has been previously started.
 612                  *
 613                  * While we're debugging the problem, as a workaround to
 614                  * multiple TRBs handling, use only one TRB at a time.
 615                  */
 616                 last_one = 1;
 617
 618                 req->trb = trb_hw;
 619                 if (!ret)
 620                         ret = req;
 621
 622                 trb.bplh = req->request.dma;
 623
 624                 if (usb_endpoint_xfer_isoc(dep->desc)) {
 625                         trb.isp_imi = true;
 626                         trb.csp = true;
 627                 } else {
 628                         trb.lst = last_one;
 629                 }
 630
 631                 switch (usb_endpoint_type(dep->desc)) {
 632                 case USB_ENDPOINT_XFER_CONTROL:
 633                         trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP;
 634                         break;
 635
 636                 case USB_ENDPOINT_XFER_ISOC:
 637                         trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 638
 639                         /* IOC every DWC3_TRB_NUM / 4 so we can refill */
 640                         if (!(cur_slot % (DWC3_TRB_NUM / 4)))
 641                                 trb.ioc = last_one;
 642                         break;
 643
 644                 case USB_ENDPOINT_XFER_BULK:
 645                 case USB_ENDPOINT_XFER_INT:
 646                         trb.trbctl = DWC3_TRBCTL_NORMAL;
 647                         break;
 648                 default:
 649                         /*
 650                          * This is only possible with faulty memory because we
 651                          * checked it already :)
 652                          */
 653                         BUG();
 654                 }
 655
 656                 trb.length      = req->request.length;
 657                 trb.hwo = true;
 658
 659                 dwc3_trb_to_hw(&trb, trb_hw);
 660                 req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw);
 661
 662                 if (last_one)
 663                         break;
 664         }
 665
 666         return ret;
 667 }
 668
 669 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 670                 int start_new)
 671 {
 672         struct dwc3_gadget_ep_cmd_params params;
 673         struct dwc3_request             *req;
 674         struct dwc3                     *dwc = dep->dwc;
 675         int                             ret;
 676         u32                             cmd;
 677
 678         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 679                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
 680                 return -EBUSY;
 681         }
 682         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
 683
 684         /*
 685          * If we are getting here after a short-out-packet we don't enqueue any
 686          * new requests as we try to set the IOC bit only on the last request.
 687          */
 688         if (start_new) {
 689                 if (list_empty(&dep->req_queued))
 690                         dwc3_prepare_trbs(dep, start_new);
 691
 692                 /* req points to the first request which will be sent */
 693                 req = next_request(&dep->req_queued);
 694         } else {
 695                 /*
 696                  * req points to the first request where HWO changed
 697                  * from 0 to 1
 698                  */
 699                 req = dwc3_prepare_trbs(dep, start_new);
 700         }
 701         if (!req) {
 702                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 703                 return 0;
 704         }
 705
 706         memset(&params, 0, sizeof(params));
 707         params.param0.depstrtxfer.transfer_desc_addr_high =
 708                 upper_32_bits(req->trb_dma);
 709         params.param1.depstrtxfer.transfer_desc_addr_low =
 710                 lower_32_bits(req->trb_dma);
 711
 712         if (start_new)
 713                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 714         else
 715                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 716
 717         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 718         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 719         if (ret < 0) {
 720                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 721
 722                 /*
 723                  * FIXME we need to iterate over the list of requests
 724                  * here and stop, unmap, free and del each of the linked
 725                  * requests instead of we do now.
 726                  */
 727                 dwc3_unmap_buffer_from_dma(req);
 728                 list_del(&req->list);
 729                 return ret;
 730         }
 731
 732         dep->flags |= DWC3_EP_BUSY;
 733         dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
 734                         dep->number);
 735         if (!dep->res_trans_idx)
 736                 printk_once(KERN_ERR "%s() res_trans_idx is invalid\n", __func__);
 737         return 0;
 738 }
 739
 740 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
 741 {
 742         req->request.actual     = 0;
 743         req->request.status     = -EINPROGRESS;
 744         req->direction          = dep->direction;
 745         req->epnum              = dep->number;
 746
 747         /*
 748          * We only add to our list of requests now and
 749          * start consuming the list once we get XferNotReady
 750          * IRQ.
 751          *
 752          * That way, we avoid doing anything that we don't need
 753          * to do now and defer it until the point we receive a
 754          * particular token from the Host side.
 755          *
 756          * This will also avoid Host cancelling URBs due to too
 757          * many NACKs.
 758          */
 759         dwc3_map_buffer_to_dma(req);
 760         list_add_tail(&req->list, &dep->request_list);
 761
 762         /*
 763          * There is one special case: XferNotReady with
 764          * empty list of requests. We need to kick the
 765          * transfer here in that situation, otherwise
 766          * we will be NAKing forever.
 767          *
 768          * If we get XferNotReady before gadget driver
 769          * has a chance to queue a request, we will ACK
 770          * the IRQ but won't be able to receive the data
 771          * until the next request is queued. The following
 772          * code is handling exactly that.
 773          */
 774         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 775                 int ret;
 776                 int start_trans;
 777
 778                 start_trans = 1;
 779                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
 780                                 dep->flags & DWC3_EP_BUSY)
 781                         start_trans = 0;
 782
 783                 ret =  __dwc3_gadget_kick_transfer(dep, 0, start_trans);
 784                 if (ret && ret != -EBUSY) {
 785                         struct dwc3     *dwc = dep->dwc;
 786
 787                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
 788                                         dep->name);
 789                 }
 790         };
 791
 792         return 0;
 793 }
 794
 795 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
 796         gfp_t gfp_flags)
 797 {
 798         struct dwc3_request             *req = to_dwc3_request(request);
 799         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 800         struct dwc3                     *dwc = dep->dwc;
 801
 802         unsigned long                   flags;
 803
 804         int                             ret;
 805
 806         if (!dep->desc) {
 807                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
 808                                 request, ep->name);
 809                 return -ESHUTDOWN;
 810         }
 811
 812         dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
 813                         request, ep->name, request->length);
 814
 815         spin_lock_irqsave(&dwc->lock, flags);
 816         ret = __dwc3_gadget_ep_queue(dep, req);
 817         spin_unlock_irqrestore(&dwc->lock, flags);
 818
 819         return ret;
 820 }
 821
 822 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
 823                 struct usb_request *request)
 824 {
 825         struct dwc3_request             *req = to_dwc3_request(request);
 826         struct dwc3_request             *r = NULL;
 827
 828         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 829         struct dwc3                     *dwc = dep->dwc;
 830
 831         unsigned long                   flags;
 832         int                             ret = 0;
 833
 834         spin_lock_irqsave(&dwc->lock, flags);
 835
 836         list_for_each_entry(r, &dep->request_list, list) {
 837                 if (r == req)
 838                         break;
 839         }
 840
 841         if (r != req) {
 842                 list_for_each_entry(r, &dep->req_queued, list) {
 843                         if (r == req)
 844                                 break;
 845                 }
 846                 if (r == req) {
 847                         /* wait until it is processed */
 848                         dwc3_stop_active_transfer(dwc, dep->number);
 849                         goto out0;
 850                 }
 851                 dev_err(dwc->dev, "request %p was not queued to %s\n",
 852                                 request, ep->name);
 853                 ret = -EINVAL;
 854                 goto out0;
 855         }
 856
 857         /* giveback the request */
 858         dwc3_gadget_giveback(dep, req, -ECONNRESET);
 859
 860 out0:
 861         spin_unlock_irqrestore(&dwc->lock, flags);
 862
 863         return ret;
 864 }
 865
 866 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
 867 {
 868         struct dwc3_gadget_ep_cmd_params        params;
 869         struct dwc3                             *dwc = dep->dwc;
 870         int                                     ret;
 871
 872         memset(&params, 0x00, sizeof(params));
 873
 874         if (value) {
 875                 if (dep->number == 0 || dep->number == 1) {
 876                         /*
 877                          * Whenever EP0 is stalled, we will restart
 878                          * the state machine, thus moving back to
 879                          * Setup Phase
 880                          */
 881                         dwc->ep0state = EP0_SETUP_PHASE;
 882                 }
 883
 884                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 885                         DWC3_DEPCMD_SETSTALL, &params);
 886                 if (ret)
 887                         dev_err(dwc->dev, "failed to %s STALL on %s\n",
 888                                         value ? "set" : "clear",
 889                                         dep->name);
 890                 else
 891                         dep->flags |= DWC3_EP_STALL;
 892         } else {
 893                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 894                         DWC3_DEPCMD_CLEARSTALL, &params);
 895                 if (ret)
 896                         dev_err(dwc->dev, "failed to %s STALL on %s\n",
 897                                         value ? "set" : "clear",
 898                                         dep->name);
 899                 else
 900                         dep->flags &= ~DWC3_EP_STALL;
 901         }
 902         return ret;
 903 }
 904
 905 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
 906 {
 907         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 908         struct dwc3                     *dwc = dep->dwc;
 909
 910         unsigned long                   flags;
 911
 912         int                             ret;
 913
 914         spin_lock_irqsave(&dwc->lock, flags);
 915
 916         if (usb_endpoint_xfer_isoc(dep->desc)) {
 917                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
 918                 ret = -EINVAL;
 919                 goto out;
 920         }
 921
 922         ret = __dwc3_gadget_ep_set_halt(dep, value);
 923 out:
 924         spin_unlock_irqrestore(&dwc->lock, flags);
 925
 926         return ret;
 927 }
 928
 929 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
 930 {
 931         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 932
 933         dep->flags |= DWC3_EP_WEDGE;
 934
 935         return usb_ep_set_halt(ep);
 936 }
 937
 938 /* -------------------------------------------------------------------------- */
 939
 940 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
 941         .bLength        = USB_DT_ENDPOINT_SIZE,
 942         .bDescriptorType = USB_DT_ENDPOINT,
 943         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
 944 };
 945
 946 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
 947         .enable         = dwc3_gadget_ep0_enable,
 948         .disable        = dwc3_gadget_ep0_disable,
 949         .alloc_request  = dwc3_gadget_ep_alloc_request,
 950         .free_request   = dwc3_gadget_ep_free_request,
 951         .queue          = dwc3_gadget_ep0_queue,
 952         .dequeue        = dwc3_gadget_ep_dequeue,
 953         .set_halt       = dwc3_gadget_ep_set_halt,
 954         .set_wedge      = dwc3_gadget_ep_set_wedge,
 955 };
 956
 957 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
 958         .enable         = dwc3_gadget_ep_enable,
 959         .disable        = dwc3_gadget_ep_disable,
 960         .alloc_request  = dwc3_gadget_ep_alloc_request,
 961         .free_request   = dwc3_gadget_ep_free_request,
 962         .queue          = dwc3_gadget_ep_queue,
 963         .dequeue        = dwc3_gadget_ep_dequeue,
 964         .set_halt       = dwc3_gadget_ep_set_halt,
 965         .set_wedge      = dwc3_gadget_ep_set_wedge,
 966 };
 967
 968 /* -------------------------------------------------------------------------- */
 969
 970 static int dwc3_gadget_get_frame(struct usb_gadget *g)
 971 {
 972         struct dwc3             *dwc = gadget_to_dwc(g);
 973         u32                     reg;
 974
 975         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 976         return DWC3_DSTS_SOFFN(reg);
 977 }
 978
 979 static int dwc3_gadget_wakeup(struct usb_gadget *g)
 980 {
 981         struct dwc3             *dwc = gadget_to_dwc(g);
 982
 983         unsigned long           timeout;
 984         unsigned long           flags;
 985
 986         u32                     reg;
 987
 988         int                     ret = 0;
 989
 990         u8                      link_state;
 991         u8                      speed;
 992
 993         spin_lock_irqsave(&dwc->lock, flags);
 994
 995         /*
 996          * According to the Databook Remote wakeup request should
 997          * be issued only when the device is in early suspend state.
 998          *
 999          * We can check that via USB Link State bits in DSTS register.
1000          */
1001         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1002
1003         speed = reg & DWC3_DSTS_CONNECTSPD;
1004         if (speed == DWC3_DSTS_SUPERSPEED) {
1005                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1006                 ret = -EINVAL;
1007                 goto out;
1008         }
1009
1010         link_state = DWC3_DSTS_USBLNKST(reg);
1011
1012         switch (link_state) {
1013         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1014         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1015                 break;
1016         default:
1017                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1018                                 link_state);
1019                 ret = -EINVAL;
1020                 goto out;
1021         }
1022
1023         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1024
1025         /*
1026          * Switch link state to Recovery. In HS/FS/LS this means
1027          * RemoteWakeup Request
1028          */
1029         reg |= DWC3_DCTL_ULSTCHNG_RECOVERY;
1030         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1031
1032         /* wait for at least 2000us */
1033         usleep_range(2000, 2500);
1034
1035         /* write zeroes to Link Change Request */
1036         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1037         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1038
1039         /* pool until Link State change to ON */
1040         timeout = jiffies + msecs_to_jiffies(100);
1041
1042         while (!(time_after(jiffies, timeout))) {
1043                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1044
1045                 /* in HS, means ON */
1046                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1047                         break;
1048         }
1049
1050         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1051                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1052                 ret = -EINVAL;
1053         }
1054
1055 out:
1056         spin_unlock_irqrestore(&dwc->lock, flags);
1057
1058         return ret;
1059 }
1060
1061 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1062                 int is_selfpowered)
1063 {
1064         struct dwc3             *dwc = gadget_to_dwc(g);
1065
1066         dwc->is_selfpowered = !!is_selfpowered;
1067
1068         return 0;
1069 }
1070
1071 static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1072 {
1073         u32                     reg;
1074         u32                     timeout = 500;
1075
1076         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1077         if (is_on)
1078                 reg |= DWC3_DCTL_RUN_STOP;
1079         else
1080                 reg &= ~DWC3_DCTL_RUN_STOP;
1081
1082         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1083
1084         do {
1085                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1086                 if (is_on) {
1087                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1088                                 break;
1089                 } else {
1090                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1091                                 break;
1092                 }
1093                 timeout--;
1094                 if (!timeout)
1095                         break;
1096                 udelay(1);
1097         } while (1);
1098
1099         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1100                         dwc->gadget_driver
1101                         ? dwc->gadget_driver->function : "no-function",
1102                         is_on ? "connect" : "disconnect");
1103 }
1104
1105 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1106 {
1107         struct dwc3             *dwc = gadget_to_dwc(g);
1108         unsigned long           flags;
1109
1110         is_on = !!is_on;
1111
1112         spin_lock_irqsave(&dwc->lock, flags);
1113         dwc3_gadget_run_stop(dwc, is_on);
1114         spin_unlock_irqrestore(&dwc->lock, flags);
1115
1116         return 0;
1117 }
1118
1119 static int dwc3_gadget_start(struct usb_gadget *g,
1120                 struct usb_gadget_driver *driver)
1121 {
1122         struct dwc3             *dwc = gadget_to_dwc(g);
1123         struct dwc3_ep          *dep;
1124         unsigned long           flags;
1125         int                     ret = 0;
1126         u32                     reg;
1127
1128         spin_lock_irqsave(&dwc->lock, flags);
1129
1130         if (dwc->gadget_driver) {
1131                 dev_err(dwc->dev, "%s is already bound to %s\n",
1132                                 dwc->gadget.name,
1133                                 dwc->gadget_driver->driver.name);
1134                 ret = -EBUSY;
1135                 goto err0;
1136         }
1137
1138         dwc->gadget_driver      = driver;
1139         dwc->gadget.dev.driver  = &driver->driver;
1140
1141         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1142
1143         reg &= ~DWC3_GCTL_SCALEDOWN(3);
1144         reg &= ~DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG);
1145         reg &= ~DWC3_GCTL_DISSCRAMBLE;
1146         reg |= DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_DEVICE);
1147
1148         /*
1149          * WORKAROUND: DWC3 revisions <1.90a have a bug
1150          * when The device fails to connect at SuperSpeed
1151          * and falls back to high-speed mode which causes
1152          * the device to enter in a Connect/Disconnect loop
1153          */
1154         if (dwc->revision < DWC3_REVISION_190A)
1155                 reg |= DWC3_GCTL_U2RSTECN;
1156
1157         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1158
1159         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1160         reg &= ~(DWC3_DCFG_SPEED_MASK);
1161         reg |= DWC3_DCFG_SUPERSPEED;
1162         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1163
1164         /* Start with SuperSpeed Default */
1165         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1166
1167         dep = dwc->eps[0];
1168         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1169         if (ret) {
1170                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1171                 goto err0;
1172         }
1173
1174         dep = dwc->eps[1];
1175         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1176         if (ret) {
1177                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1178                 goto err1;
1179         }
1180
1181         /* begin to receive SETUP packets */
1182         dwc->ep0state = EP0_SETUP_PHASE;
1183         dwc3_ep0_out_start(dwc);
1184
1185         spin_unlock_irqrestore(&dwc->lock, flags);
1186
1187         return 0;
1188
1189 err1:
1190         __dwc3_gadget_ep_disable(dwc->eps[0]);
1191
1192 err0:
1193         spin_unlock_irqrestore(&dwc->lock, flags);
1194
1195         return ret;
1196 }
1197
1198 static int dwc3_gadget_stop(struct usb_gadget *g,
1199                 struct usb_gadget_driver *driver)
1200 {
1201         struct dwc3             *dwc = gadget_to_dwc(g);
1202         unsigned long           flags;
1203
1204         spin_lock_irqsave(&dwc->lock, flags);
1205
1206         __dwc3_gadget_ep_disable(dwc->eps[0]);
1207         __dwc3_gadget_ep_disable(dwc->eps[1]);
1208
1209         dwc->gadget_driver      = NULL;
1210         dwc->gadget.dev.driver  = NULL;
1211
1212         spin_unlock_irqrestore(&dwc->lock, flags);
1213
1214         return 0;
1215 }
1216 static const struct usb_gadget_ops dwc3_gadget_ops = {
1217         .get_frame              = dwc3_gadget_get_frame,
1218         .wakeup                 = dwc3_gadget_wakeup,
1219         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1220         .pullup                 = dwc3_gadget_pullup,
1221         .udc_start              = dwc3_gadget_start,
1222         .udc_stop               = dwc3_gadget_stop,
1223 };
1224
1225 /* -------------------------------------------------------------------------- */
1226
1227 static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1228 {
1229         struct dwc3_ep                  *dep;
1230         u8                              epnum;
1231
1232         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1233
1234         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1235                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1236                 if (!dep) {
1237                         dev_err(dwc->dev, "can't allocate endpoint %d\n",
1238                                         epnum);
1239                         return -ENOMEM;
1240                 }
1241
1242                 dep->dwc = dwc;
1243                 dep->number = epnum;
1244                 dwc->eps[epnum] = dep;
1245
1246                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1247                                 (epnum & 1) ? "in" : "out");
1248                 dep->endpoint.name = dep->name;
1249                 dep->direction = (epnum & 1);
1250
1251                 if (epnum == 0 || epnum == 1) {
1252                         dep->endpoint.maxpacket = 512;
1253                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1254                         if (!epnum)
1255                                 dwc->gadget.ep0 = &dep->endpoint;
1256                 } else {
1257                         int             ret;
1258
1259                         dep->endpoint.maxpacket = 1024;
1260                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1261                         list_add_tail(&dep->endpoint.ep_list,
1262                                         &dwc->gadget.ep_list);
1263
1264                         ret = dwc3_alloc_trb_pool(dep);
1265                         if (ret) {
1266                                 dev_err(dwc->dev, "%s: failed to allocate TRB pool\n", dep->name);
1267                                 return ret;
1268                         }
1269                 }
1270                 INIT_LIST_HEAD(&dep->request_list);
1271                 INIT_LIST_HEAD(&dep->req_queued);
1272         }
1273
1274         return 0;
1275 }
1276
1277 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1278 {
1279         struct dwc3_ep                  *dep;
1280         u8                              epnum;
1281
1282         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1283                 dep = dwc->eps[epnum];
1284                 dwc3_free_trb_pool(dep);
1285
1286                 if (epnum != 0 && epnum != 1)
1287                         list_del(&dep->endpoint.ep_list);
1288
1289                 kfree(dep);
1290         }
1291 }
1292
1293 static void dwc3_gadget_release(struct device *dev)
1294 {
1295         dev_dbg(dev, "%s\n", __func__);
1296 }
1297
1298 /* -------------------------------------------------------------------------- */
1299 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1300                 const struct dwc3_event_depevt *event, int status)
1301 {
1302         struct dwc3_request     *req;
1303         struct dwc3_trb         trb;
1304         unsigned int            count;
1305         unsigned int            s_pkt = 0;
1306
1307         do {
1308                 req = next_request(&dep->req_queued);
1309                 if (!req)
1310                         break;
1311
1312                 dwc3_trb_to_nat(req->trb, &trb);
1313
1314                 if (trb.hwo && status != -ESHUTDOWN)
1315                         /*
1316                          * We continue despite the error. There is not much we
1317                          * can do. If we don't clean in up we loop for ever. If
1318                          * we skip the TRB than it gets overwritten reused after
1319                          * a while since we use them in a ring buffer. a BUG()
1320                          * would help. Lets hope that if this occures, someone
1321                          * fixes the root cause instead of looking away :)
1322                          */
1323                         dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1324                                         dep->name, req->trb);
1325                 count = trb.length;
1326
1327                 if (dep->direction) {
1328                         if (count) {
1329                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1330                                                 dep->name);
1331                                 status = -ECONNRESET;
1332                         }
1333                 } else {
1334                         if (count && (event->status & DEPEVT_STATUS_SHORT))
1335                                 s_pkt = 1;
1336                 }
1337
1338                 /*
1339                  * We assume here we will always receive the entire data block
1340                  * which we should receive. Meaning, if we program RX to
1341                  * receive 4K but we receive only 2K, we assume that's all we
1342                  * should receive and we simply bounce the request back to the
1343                  * gadget driver for further processing.
1344                  */
1345                 req->request.actual += req->request.length - count;
1346                 dwc3_gadget_giveback(dep, req, status);
1347                 if (s_pkt)
1348                         break;
1349                 if ((event->status & DEPEVT_STATUS_LST) && trb.lst)
1350                         break;
1351                 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1352                         break;
1353         } while (1);
1354
1355         if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1356                 return 0;
1357         return 1;
1358 }
1359
1360 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1361                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1362                 int start_new)
1363 {
1364         unsigned                status = 0;
1365         int                     clean_busy;
1366
1367         if (event->status & DEPEVT_STATUS_BUSERR)
1368                 status = -ECONNRESET;
1369
1370         clean_busy =  dwc3_cleanup_done_reqs(dwc, dep, event, status);
1371         if (clean_busy) {
1372                 dep->flags &= ~DWC3_EP_BUSY;
1373                 dep->res_trans_idx = 0;
1374         }
1375 }
1376
1377 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1378                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1379 {
1380         u32 uf;
1381
1382         if (list_empty(&dep->request_list)) {
1383                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1384                         dep->name);
1385                 return;
1386         }
1387
1388         if (event->parameters) {
1389                 u32 mask;
1390
1391                 mask = ~(dep->interval - 1);
1392                 uf = event->parameters & mask;
1393                 /* 4 micro frames in the future */
1394                 uf += dep->interval * 4;
1395         } else {
1396                 uf = 0;
1397         }
1398
1399         __dwc3_gadget_kick_transfer(dep, uf, 1);
1400 }
1401
1402 static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1403                 const struct dwc3_event_depevt *event)
1404 {
1405         struct dwc3 *dwc = dep->dwc;
1406         struct dwc3_event_depevt mod_ev = *event;
1407
1408         /*
1409          * We were asked to remove one requests. It is possible that this
1410          * request and a few other were started together and have the same
1411          * transfer index. Since we stopped the complete endpoint we don't
1412          * know how many requests were already completed (and not yet)
1413          * reported and how could be done (later). We purge them all until
1414          * the end of the list.
1415          */
1416         mod_ev.status = DEPEVT_STATUS_LST;
1417         dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1418         dep->flags &= ~DWC3_EP_BUSY;
1419         /* pending requets are ignored and are queued on XferNotReady */
1420 }
1421
1422 static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1423                 const struct dwc3_event_depevt *event)
1424 {
1425         u32 param = event->parameters;
1426         u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1427
1428         switch (cmd_type) {
1429         case DWC3_DEPCMD_ENDTRANSFER:
1430                 dwc3_process_ep_cmd_complete(dep, event);
1431                 break;
1432         case DWC3_DEPCMD_STARTTRANSFER:
1433                 dep->res_trans_idx = param & 0x7f;
1434                 break;
1435         default:
1436                 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1437                                 __func__, cmd_type);
1438                 break;
1439         };
1440 }
1441
1442 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1443                 const struct dwc3_event_depevt *event)
1444 {
1445         struct dwc3_ep          *dep;
1446         u8                      epnum = event->endpoint_number;
1447
1448         dep = dwc->eps[epnum];
1449
1450         dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1451                         dwc3_ep_event_string(event->endpoint_event));
1452
1453         if (epnum == 0 || epnum == 1) {
1454                 dwc3_ep0_interrupt(dwc, event);
1455                 return;
1456         }
1457
1458         switch (event->endpoint_event) {
1459         case DWC3_DEPEVT_XFERCOMPLETE:
1460                 if (usb_endpoint_xfer_isoc(dep->desc)) {
1461                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1462                                         dep->name);
1463                         return;
1464                 }
1465
1466                 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1467                 break;
1468         case DWC3_DEPEVT_XFERINPROGRESS:
1469                 if (!usb_endpoint_xfer_isoc(dep->desc)) {
1470                         dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1471                                         dep->name);
1472                         return;
1473                 }
1474
1475                 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1476                 break;
1477         case DWC3_DEPEVT_XFERNOTREADY:
1478                 if (usb_endpoint_xfer_isoc(dep->desc)) {
1479                         dwc3_gadget_start_isoc(dwc, dep, event);
1480                 } else {
1481                         int ret;
1482
1483                         dev_vdbg(dwc->dev, "%s: reason %s\n",
1484                                         dep->name, event->status
1485                                         ? "Transfer Active"
1486                                         : "Transfer Not Active");
1487
1488                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1489                         if (!ret || ret == -EBUSY)
1490                                 return;
1491
1492                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1493                                         dep->name);
1494                 }
1495
1496                 break;
1497         case DWC3_DEPEVT_RXTXFIFOEVT:
1498                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1499                 break;
1500         case DWC3_DEPEVT_STREAMEVT:
1501                 dev_dbg(dwc->dev, "%s Stream Event\n", dep->name);
1502                 break;
1503         case DWC3_DEPEVT_EPCMDCMPLT:
1504                 dwc3_ep_cmd_compl(dep, event);
1505                 break;
1506         }
1507 }
1508
1509 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1510 {
1511         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1512                 spin_unlock(&dwc->lock);
1513                 dwc->gadget_driver->disconnect(&dwc->gadget);
1514                 spin_lock(&dwc->lock);
1515         }
1516 }
1517
1518 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1519 {
1520         struct dwc3_ep *dep;
1521         struct dwc3_gadget_ep_cmd_params params;
1522         u32 cmd;
1523         int ret;
1524
1525         dep = dwc->eps[epnum];
1526
1527         WARN_ON(!dep->res_trans_idx);
1528         if (dep->res_trans_idx) {
1529                 cmd = DWC3_DEPCMD_ENDTRANSFER;
1530                 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1531                 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1532                 memset(&params, 0, sizeof(params));
1533                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1534                 WARN_ON_ONCE(ret);
1535                 dep->res_trans_idx = 0;
1536         }
1537 }
1538
1539 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1540 {
1541         u32 epnum;
1542
1543         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1544                 struct dwc3_ep *dep;
1545
1546                 dep = dwc->eps[epnum];
1547                 if (!(dep->flags & DWC3_EP_ENABLED))
1548                         continue;
1549
1550                 dwc3_remove_requests(dwc, dep);
1551         }
1552 }
1553
1554 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1555 {
1556         u32 epnum;
1557
1558         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1559                 struct dwc3_ep *dep;
1560                 struct dwc3_gadget_ep_cmd_params params;
1561                 int ret;
1562
1563                 dep = dwc->eps[epnum];
1564
1565                 if (!(dep->flags & DWC3_EP_STALL))
1566                         continue;
1567
1568                 dep->flags &= ~DWC3_EP_STALL;
1569
1570                 memset(&params, 0, sizeof(params));
1571                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1572                                 DWC3_DEPCMD_CLEARSTALL, &params);
1573                 WARN_ON_ONCE(ret);
1574         }
1575 }
1576
1577 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1578 {
1579         dev_vdbg(dwc->dev, "%s\n", __func__);
1580 #if 0
1581         XXX
1582         U1/U2 is powersave optimization. Skip it for now. Anyway we need to
1583         enable it before we can disable it.
1584
1585         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1586         reg &= ~DWC3_DCTL_INITU1ENA;
1587         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1588
1589         reg &= ~DWC3_DCTL_INITU2ENA;
1590         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1591 #endif
1592
1593         dwc3_stop_active_transfers(dwc);
1594         dwc3_disconnect_gadget(dwc);
1595
1596         dwc->gadget.speed = USB_SPEED_UNKNOWN;
1597 }
1598
1599 static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
1600 {
1601         u32                     reg;
1602
1603         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1604
1605         if (on)
1606                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1607         else
1608                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1609
1610         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1611 }
1612
1613 static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
1614 {
1615         u32                     reg;
1616
1617         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1618
1619         if (on)
1620                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1621         else
1622                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1623
1624         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1625 }
1626
1627 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1628 {
1629         u32                     reg;
1630
1631         dev_vdbg(dwc->dev, "%s\n", __func__);
1632
1633         /* Enable PHYs */
1634         dwc3_gadget_usb2_phy_power(dwc, true);
1635         dwc3_gadget_usb3_phy_power(dwc, true);
1636
1637         if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
1638                 dwc3_disconnect_gadget(dwc);
1639
1640         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1641         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
1642         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1643
1644         dwc3_stop_active_transfers(dwc);
1645         dwc3_clear_stall_all_ep(dwc);
1646
1647         /* Reset device address to zero */
1648         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1649         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
1650         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1651
1652         /*
1653          * Wait for RxFifo to drain
1654          *
1655          * REVISIT probably shouldn't wait forever.
1656          * In case Hardware ends up in a screwed up
1657          * case, we error out, notify the user and,
1658          * maybe, WARN() or BUG() but leave the rest
1659          * of the kernel working fine.
1660          *
1661          * REVISIT the below is rather CPU intensive,
1662          * maybe we should read and if it doesn't work
1663          * sleep (not busy wait) for a few useconds.
1664          *
1665          * REVISIT why wait until the RXFIFO is empty anyway?
1666          */
1667         while (!(dwc3_readl(dwc->regs, DWC3_DSTS)
1668                                 & DWC3_DSTS_RXFIFOEMPTY))
1669                 cpu_relax();
1670 }
1671
1672 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
1673 {
1674         u32 reg;
1675         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
1676
1677         /*
1678          * We change the clock only at SS but I dunno why I would want to do
1679          * this. Maybe it becomes part of the power saving plan.
1680          */
1681
1682         if (speed != DWC3_DSTS_SUPERSPEED)
1683                 return;
1684
1685         /*
1686          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
1687          * each time on Connect Done.
1688          */
1689         if (!usb30_clock)
1690                 return;
1691
1692         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1693         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
1694         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1695 }
1696
1697 static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
1698 {
1699         switch (speed) {
1700         case USB_SPEED_SUPER:
1701                 dwc3_gadget_usb2_phy_power(dwc, false);
1702                 break;
1703         case USB_SPEED_HIGH:
1704         case USB_SPEED_FULL:
1705         case USB_SPEED_LOW:
1706                 dwc3_gadget_usb3_phy_power(dwc, false);
1707                 break;
1708         }
1709 }
1710
1711 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
1712 {
1713         struct dwc3_gadget_ep_cmd_params params;
1714         struct dwc3_ep          *dep;
1715         int                     ret;
1716         u32                     reg;
1717         u8                      speed;
1718
1719         dev_vdbg(dwc->dev, "%s\n", __func__);
1720
1721         memset(&params, 0x00, sizeof(params));
1722
1723         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1724         speed = reg & DWC3_DSTS_CONNECTSPD;
1725         dwc->speed = speed;
1726
1727         dwc3_update_ram_clk_sel(dwc, speed);
1728
1729         switch (speed) {
1730         case DWC3_DCFG_SUPERSPEED:
1731                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1732                 dwc->gadget.ep0->maxpacket = 512;
1733                 dwc->gadget.speed = USB_SPEED_SUPER;
1734                 break;
1735         case DWC3_DCFG_HIGHSPEED:
1736                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1737                 dwc->gadget.ep0->maxpacket = 64;
1738                 dwc->gadget.speed = USB_SPEED_HIGH;
1739                 break;
1740         case DWC3_DCFG_FULLSPEED2:
1741         case DWC3_DCFG_FULLSPEED1:
1742                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1743                 dwc->gadget.ep0->maxpacket = 64;
1744                 dwc->gadget.speed = USB_SPEED_FULL;
1745                 break;
1746         case DWC3_DCFG_LOWSPEED:
1747                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
1748                 dwc->gadget.ep0->maxpacket = 8;
1749                 dwc->gadget.speed = USB_SPEED_LOW;
1750                 break;
1751         }
1752
1753         /* Disable unneded PHY */
1754         dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
1755
1756         dep = dwc->eps[0];
1757         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1758         if (ret) {
1759                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1760                 return;
1761         }
1762
1763         dep = dwc->eps[1];
1764         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1765         if (ret) {
1766                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1767                 return;
1768         }
1769
1770         /*
1771          * Configure PHY via GUSB3PIPECTLn if required.
1772          *
1773          * Update GTXFIFOSIZn
1774          *
1775          * In both cases reset values should be sufficient.
1776          */
1777 }
1778
1779 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
1780 {
1781         dev_vdbg(dwc->dev, "%s\n", __func__);
1782
1783         /*
1784          * TODO take core out of low power mode when that's
1785          * implemented.
1786          */
1787
1788         dwc->gadget_driver->resume(&dwc->gadget);
1789 }
1790
1791 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
1792                 unsigned int evtinfo)
1793 {
1794         /*  The fith bit says SuperSpeed yes or no. */
1795         dwc->link_state = evtinfo & DWC3_LINK_STATE_MASK;
1796
1797         dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
1798 }
1799
1800 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
1801                 const struct dwc3_event_devt *event)
1802 {
1803         switch (event->type) {
1804         case DWC3_DEVICE_EVENT_DISCONNECT:
1805                 dwc3_gadget_disconnect_interrupt(dwc);
1806                 break;
1807         case DWC3_DEVICE_EVENT_RESET:
1808                 dwc3_gadget_reset_interrupt(dwc);
1809                 break;
1810         case DWC3_DEVICE_EVENT_CONNECT_DONE:
1811                 dwc3_gadget_conndone_interrupt(dwc);
1812                 break;
1813         case DWC3_DEVICE_EVENT_WAKEUP:
1814                 dwc3_gadget_wakeup_interrupt(dwc);
1815                 break;
1816         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
1817                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
1818                 break;
1819         case DWC3_DEVICE_EVENT_EOPF:
1820                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
1821                 break;
1822         case DWC3_DEVICE_EVENT_SOF:
1823                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
1824                 break;
1825         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
1826                 dev_vdbg(dwc->dev, "Erratic Error\n");
1827                 break;
1828         case DWC3_DEVICE_EVENT_CMD_CMPL:
1829                 dev_vdbg(dwc->dev, "Command Complete\n");
1830                 break;
1831         case DWC3_DEVICE_EVENT_OVERFLOW:
1832                 dev_vdbg(dwc->dev, "Overflow\n");
1833                 break;
1834         default:
1835                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
1836         }
1837 }
1838
1839 static void dwc3_process_event_entry(struct dwc3 *dwc,
1840                 const union dwc3_event *event)
1841 {
1842         /* Endpoint IRQ, handle it and return early */
1843         if (event->type.is_devspec == 0) {
1844                 /* depevt */
1845                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
1846         }
1847
1848         switch (event->type.type) {
1849         case DWC3_EVENT_TYPE_DEV:
1850                 dwc3_gadget_interrupt(dwc, &event->devt);
1851                 break;
1852         /* REVISIT what to do with Carkit and I2C events ? */
1853         default:
1854                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
1855         }
1856 }
1857
1858 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
1859 {
1860         struct dwc3_event_buffer *evt;
1861         int left;
1862         u32 count;
1863
1864         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
1865         count &= DWC3_GEVNTCOUNT_MASK;
1866         if (!count)
1867                 return IRQ_NONE;
1868
1869         evt = dwc->ev_buffs[buf];
1870         left = count;
1871
1872         while (left > 0) {
1873                 union dwc3_event event;
1874
1875                 memcpy(&event.raw, (evt->buf + evt->lpos), sizeof(event.raw));
1876                 dwc3_process_event_entry(dwc, &event);
1877                 /*
1878                  * XXX we wrap around correctly to the next entry as almost all
1879                  * entries are 4 bytes in size. There is one entry which has 12
1880                  * bytes which is a regular entry followed by 8 bytes data. ATM
1881                  * I don't know how things are organized if were get next to the
1882                  * a boundary so I worry about that once we try to handle that.
1883                  */
1884                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
1885                 left -= 4;
1886
1887                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
1888         }
1889
1890         return IRQ_HANDLED;
1891 }
1892
1893 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
1894 {
1895         struct dwc3                     *dwc = _dwc;
1896         int                             i;
1897         irqreturn_t                     ret = IRQ_NONE;
1898
1899         spin_lock(&dwc->lock);
1900
1901         for (i = 0; i < DWC3_EVENT_BUFFERS_NUM; i++) {
1902                 irqreturn_t status;
1903
1904                 status = dwc3_process_event_buf(dwc, i);
1905                 if (status == IRQ_HANDLED)
1906                         ret = status;
1907         }
1908
1909         spin_unlock(&dwc->lock);
1910
1911         return ret;
1912 }
1913
1914 /**
1915  * dwc3_gadget_init - Initializes gadget related registers
1916  * @dwc: Pointer to out controller context structure
1917  *
1918  * Returns 0 on success otherwise negative errno.
1919  */
1920 int __devinit dwc3_gadget_init(struct dwc3 *dwc)
1921 {
1922         u32                                     reg;
1923         int                                     ret;
1924         int                                     irq;
1925
1926         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
1927                         &dwc->ctrl_req_addr, GFP_KERNEL);
1928         if (!dwc->ctrl_req) {
1929                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
1930                 ret = -ENOMEM;
1931                 goto err0;
1932         }
1933
1934         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
1935                         &dwc->ep0_trb_addr, GFP_KERNEL);
1936         if (!dwc->ep0_trb) {
1937                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
1938                 ret = -ENOMEM;
1939                 goto err1;
1940         }
1941
1942         dwc->setup_buf = dma_alloc_coherent(dwc->dev,
1943                         sizeof(*dwc->setup_buf) * 2,
1944                         &dwc->setup_buf_addr, GFP_KERNEL);
1945         if (!dwc->setup_buf) {
1946                 dev_err(dwc->dev, "failed to allocate setup buffer\n");
1947                 ret = -ENOMEM;
1948                 goto err2;
1949         }
1950
1951         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
1952                         512, &dwc->ep0_bounce_addr, GFP_KERNEL);
1953         if (!dwc->ep0_bounce) {
1954                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
1955                 ret = -ENOMEM;
1956                 goto err3;
1957         }
1958
1959         dev_set_name(&dwc->gadget.dev, "gadget");
1960
1961         dwc->gadget.ops                 = &dwc3_gadget_ops;
1962         dwc->gadget.is_dualspeed        = true;
1963         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
1964         dwc->gadget.dev.parent          = dwc->dev;
1965
1966         dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
1967
1968         dwc->gadget.dev.dma_parms       = dwc->dev->dma_parms;
1969         dwc->gadget.dev.dma_mask        = dwc->dev->dma_mask;
1970         dwc->gadget.dev.release         = dwc3_gadget_release;
1971         dwc->gadget.name                = "dwc3-gadget";
1972
1973         /*
1974          * REVISIT: Here we should clear all pending IRQs to be
1975          * sure we're starting from a well known location.
1976          */
1977
1978         ret = dwc3_gadget_init_endpoints(dwc);
1979         if (ret)
1980                 goto err4;
1981
1982         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1983
1984         ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
1985                         "dwc3", dwc);
1986         if (ret) {
1987                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1988                                 irq, ret);
1989                 goto err5;
1990         }
1991
1992         /* Enable all but Start and End of Frame IRQs */
1993         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1994                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1995                         DWC3_DEVTEN_CMDCMPLTEN |
1996                         DWC3_DEVTEN_ERRTICERREN |
1997                         DWC3_DEVTEN_WKUPEVTEN |
1998                         DWC3_DEVTEN_ULSTCNGEN |
1999                         DWC3_DEVTEN_CONNECTDONEEN |
2000                         DWC3_DEVTEN_USBRSTEN |
2001                         DWC3_DEVTEN_DISCONNEVTEN);
2002         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2003
2004         ret = device_register(&dwc->gadget.dev);
2005         if (ret) {
2006                 dev_err(dwc->dev, "failed to register gadget device\n");
2007                 put_device(&dwc->gadget.dev);
2008                 goto err6;
2009         }
2010
2011         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2012         if (ret) {
2013                 dev_err(dwc->dev, "failed to register udc\n");
2014                 goto err7;
2015         }
2016
2017         return 0;
2018
2019 err7:
2020         device_unregister(&dwc->gadget.dev);
2021
2022 err6:
2023         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2024         free_irq(irq, dwc);
2025
2026 err5:
2027         dwc3_gadget_free_endpoints(dwc);
2028
2029 err4:
2030         dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2031                         dwc->ep0_bounce_addr);
2032
2033 err3:
2034         dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2035                         dwc->setup_buf, dwc->setup_buf_addr);
2036
2037 err2:
2038         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2039                         dwc->ep0_trb, dwc->ep0_trb_addr);
2040
2041 err1:
2042         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2043                         dwc->ctrl_req, dwc->ctrl_req_addr);
2044
2045 err0:
2046         return ret;
2047 }
2048
2049 void dwc3_gadget_exit(struct dwc3 *dwc)
2050 {
2051         int                     irq;
2052         int                     i;
2053
2054         usb_del_gadget_udc(&dwc->gadget);
2055         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2056
2057         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2058         free_irq(irq, dwc);
2059
2060         for (i = 0; i < ARRAY_SIZE(dwc->eps); i++)
2061                 __dwc3_gadget_ep_disable(dwc->eps[i]);
2062
2063         dwc3_gadget_free_endpoints(dwc);
2064
2065         dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2066                         dwc->ep0_bounce_addr);
2067
2068         dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2069                         dwc->setup_buf, dwc->setup_buf_addr);
2070
2071         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2072                         dwc->ep0_trb, dwc->ep0_trb_addr);
2073
2074         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2075                         dwc->ctrl_req, dwc->ctrl_req_addr);
2076
2077         device_unregister(&dwc->gadget.dev);
2078 }