2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
41 #include <linux/notifier.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/scatterlist.h>
45 #include <linux/serial.h>
46 #include <linux/serial_sci.h>
47 #include <linux/sh_dma.h>
48 #include <linux/slab.h>
49 #include <linux/string.h>
50 #include <linux/sysrq.h>
51 #include <linux/timer.h>
52 #include <linux/tty.h>
53 #include <linux/tty_flip.h>
56 #include <asm/sh_bios.h>
62 struct uart_port port;
64 /* Platform configuration */
65 struct plat_sci_port *cfg;
67 unsigned int error_mask;
71 struct timer_list break_timer;
79 int irqs[SCIx_NR_IRQS];
80 char *irqstr[SCIx_NR_IRQS];
82 struct dma_chan *chan_tx;
83 struct dma_chan *chan_rx;
85 #ifdef CONFIG_SERIAL_SH_SCI_DMA
86 struct dma_async_tx_descriptor *desc_tx;
87 struct dma_async_tx_descriptor *desc_rx[2];
88 dma_cookie_t cookie_tx;
89 dma_cookie_t cookie_rx[2];
90 dma_cookie_t active_rx;
91 struct scatterlist sg_tx;
92 unsigned int sg_len_tx;
93 struct scatterlist sg_rx[2];
95 struct sh_dmae_slave param_tx;
96 struct sh_dmae_slave param_rx;
97 struct work_struct work_tx;
98 struct work_struct work_rx;
99 struct timer_list rx_timer;
100 unsigned int rx_timeout;
103 struct notifier_block freq_transition;
106 /* Function prototypes */
107 static void sci_start_tx(struct uart_port *port);
108 static void sci_stop_tx(struct uart_port *port);
109 static void sci_start_rx(struct uart_port *port);
111 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
113 static struct sci_port sci_ports[SCI_NPORTS];
114 static struct uart_driver sci_uart_driver;
116 static inline struct sci_port *
117 to_sci_port(struct uart_port *uart)
119 return container_of(uart, struct sci_port, port);
122 struct plat_sci_reg {
126 /* Helper for invalidating specific entries of an inherited map. */
127 #define sci_reg_invalid { .offset = 0, .size = 0 }
129 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
130 [SCIx_PROBE_REGTYPE] = {
131 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
135 * Common SCI definitions, dependent on the port's regshift
138 [SCIx_SCI_REGTYPE] = {
139 [SCSMR] = { 0x00, 8 },
140 [SCBRR] = { 0x01, 8 },
141 [SCSCR] = { 0x02, 8 },
142 [SCxTDR] = { 0x03, 8 },
143 [SCxSR] = { 0x04, 8 },
144 [SCxRDR] = { 0x05, 8 },
145 [SCFCR] = sci_reg_invalid,
146 [SCFDR] = sci_reg_invalid,
147 [SCTFDR] = sci_reg_invalid,
148 [SCRFDR] = sci_reg_invalid,
149 [SCSPTR] = sci_reg_invalid,
150 [SCLSR] = sci_reg_invalid,
151 [HSSRR] = sci_reg_invalid,
155 * Common definitions for legacy IrDA ports, dependent on
158 [SCIx_IRDA_REGTYPE] = {
159 [SCSMR] = { 0x00, 8 },
160 [SCBRR] = { 0x01, 8 },
161 [SCSCR] = { 0x02, 8 },
162 [SCxTDR] = { 0x03, 8 },
163 [SCxSR] = { 0x04, 8 },
164 [SCxRDR] = { 0x05, 8 },
165 [SCFCR] = { 0x06, 8 },
166 [SCFDR] = { 0x07, 16 },
167 [SCTFDR] = sci_reg_invalid,
168 [SCRFDR] = sci_reg_invalid,
169 [SCSPTR] = sci_reg_invalid,
170 [SCLSR] = sci_reg_invalid,
171 [HSSRR] = sci_reg_invalid,
175 * Common SCIFA definitions.
177 [SCIx_SCIFA_REGTYPE] = {
178 [SCSMR] = { 0x00, 16 },
179 [SCBRR] = { 0x04, 8 },
180 [SCSCR] = { 0x08, 16 },
181 [SCxTDR] = { 0x20, 8 },
182 [SCxSR] = { 0x14, 16 },
183 [SCxRDR] = { 0x24, 8 },
184 [SCFCR] = { 0x18, 16 },
185 [SCFDR] = { 0x1c, 16 },
186 [SCTFDR] = sci_reg_invalid,
187 [SCRFDR] = sci_reg_invalid,
188 [SCSPTR] = sci_reg_invalid,
189 [SCLSR] = sci_reg_invalid,
190 [HSSRR] = sci_reg_invalid,
194 * Common SCIFB definitions.
196 [SCIx_SCIFB_REGTYPE] = {
197 [SCSMR] = { 0x00, 16 },
198 [SCBRR] = { 0x04, 8 },
199 [SCSCR] = { 0x08, 16 },
200 [SCxTDR] = { 0x40, 8 },
201 [SCxSR] = { 0x14, 16 },
202 [SCxRDR] = { 0x60, 8 },
203 [SCFCR] = { 0x18, 16 },
204 [SCFDR] = sci_reg_invalid,
205 [SCTFDR] = { 0x38, 16 },
206 [SCRFDR] = { 0x3c, 16 },
207 [SCSPTR] = sci_reg_invalid,
208 [SCLSR] = sci_reg_invalid,
209 [HSSRR] = sci_reg_invalid,
213 * Common SH-2(A) SCIF definitions for ports with FIFO data
216 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
217 [SCSMR] = { 0x00, 16 },
218 [SCBRR] = { 0x04, 8 },
219 [SCSCR] = { 0x08, 16 },
220 [SCxTDR] = { 0x0c, 8 },
221 [SCxSR] = { 0x10, 16 },
222 [SCxRDR] = { 0x14, 8 },
223 [SCFCR] = { 0x18, 16 },
224 [SCFDR] = { 0x1c, 16 },
225 [SCTFDR] = sci_reg_invalid,
226 [SCRFDR] = sci_reg_invalid,
227 [SCSPTR] = { 0x20, 16 },
228 [SCLSR] = { 0x24, 16 },
229 [HSSRR] = sci_reg_invalid,
233 * Common SH-3 SCIF definitions.
235 [SCIx_SH3_SCIF_REGTYPE] = {
236 [SCSMR] = { 0x00, 8 },
237 [SCBRR] = { 0x02, 8 },
238 [SCSCR] = { 0x04, 8 },
239 [SCxTDR] = { 0x06, 8 },
240 [SCxSR] = { 0x08, 16 },
241 [SCxRDR] = { 0x0a, 8 },
242 [SCFCR] = { 0x0c, 8 },
243 [SCFDR] = { 0x0e, 16 },
244 [SCTFDR] = sci_reg_invalid,
245 [SCRFDR] = sci_reg_invalid,
246 [SCSPTR] = sci_reg_invalid,
247 [SCLSR] = sci_reg_invalid,
248 [HSSRR] = sci_reg_invalid,
252 * Common SH-4(A) SCIF(B) definitions.
254 [SCIx_SH4_SCIF_REGTYPE] = {
255 [SCSMR] = { 0x00, 16 },
256 [SCBRR] = { 0x04, 8 },
257 [SCSCR] = { 0x08, 16 },
258 [SCxTDR] = { 0x0c, 8 },
259 [SCxSR] = { 0x10, 16 },
260 [SCxRDR] = { 0x14, 8 },
261 [SCFCR] = { 0x18, 16 },
262 [SCFDR] = { 0x1c, 16 },
263 [SCTFDR] = sci_reg_invalid,
264 [SCRFDR] = sci_reg_invalid,
265 [SCSPTR] = { 0x20, 16 },
266 [SCLSR] = { 0x24, 16 },
267 [HSSRR] = sci_reg_invalid,
271 * Common HSCIF definitions.
273 [SCIx_HSCIF_REGTYPE] = {
274 [SCSMR] = { 0x00, 16 },
275 [SCBRR] = { 0x04, 8 },
276 [SCSCR] = { 0x08, 16 },
277 [SCxTDR] = { 0x0c, 8 },
278 [SCxSR] = { 0x10, 16 },
279 [SCxRDR] = { 0x14, 8 },
280 [SCFCR] = { 0x18, 16 },
281 [SCFDR] = { 0x1c, 16 },
282 [SCTFDR] = sci_reg_invalid,
283 [SCRFDR] = sci_reg_invalid,
284 [SCSPTR] = { 0x20, 16 },
285 [SCLSR] = { 0x24, 16 },
286 [HSSRR] = { 0x40, 16 },
290 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
293 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
294 [SCSMR] = { 0x00, 16 },
295 [SCBRR] = { 0x04, 8 },
296 [SCSCR] = { 0x08, 16 },
297 [SCxTDR] = { 0x0c, 8 },
298 [SCxSR] = { 0x10, 16 },
299 [SCxRDR] = { 0x14, 8 },
300 [SCFCR] = { 0x18, 16 },
301 [SCFDR] = { 0x1c, 16 },
302 [SCTFDR] = sci_reg_invalid,
303 [SCRFDR] = sci_reg_invalid,
304 [SCSPTR] = sci_reg_invalid,
305 [SCLSR] = { 0x24, 16 },
306 [HSSRR] = sci_reg_invalid,
310 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
313 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
314 [SCSMR] = { 0x00, 16 },
315 [SCBRR] = { 0x04, 8 },
316 [SCSCR] = { 0x08, 16 },
317 [SCxTDR] = { 0x0c, 8 },
318 [SCxSR] = { 0x10, 16 },
319 [SCxRDR] = { 0x14, 8 },
320 [SCFCR] = { 0x18, 16 },
321 [SCFDR] = { 0x1c, 16 },
322 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
323 [SCRFDR] = { 0x20, 16 },
324 [SCSPTR] = { 0x24, 16 },
325 [SCLSR] = { 0x28, 16 },
326 [HSSRR] = sci_reg_invalid,
330 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
333 [SCIx_SH7705_SCIF_REGTYPE] = {
334 [SCSMR] = { 0x00, 16 },
335 [SCBRR] = { 0x04, 8 },
336 [SCSCR] = { 0x08, 16 },
337 [SCxTDR] = { 0x20, 8 },
338 [SCxSR] = { 0x14, 16 },
339 [SCxRDR] = { 0x24, 8 },
340 [SCFCR] = { 0x18, 16 },
341 [SCFDR] = { 0x1c, 16 },
342 [SCTFDR] = sci_reg_invalid,
343 [SCRFDR] = sci_reg_invalid,
344 [SCSPTR] = sci_reg_invalid,
345 [SCLSR] = sci_reg_invalid,
346 [HSSRR] = sci_reg_invalid,
350 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
353 * The "offset" here is rather misleading, in that it refers to an enum
354 * value relative to the port mapping rather than the fixed offset
355 * itself, which needs to be manually retrieved from the platform's
356 * register map for the given port.
358 static unsigned int sci_serial_in(struct uart_port *p, int offset)
360 struct plat_sci_reg *reg = sci_getreg(p, offset);
363 return ioread8(p->membase + (reg->offset << p->regshift));
364 else if (reg->size == 16)
365 return ioread16(p->membase + (reg->offset << p->regshift));
367 WARN(1, "Invalid register access\n");
372 static void sci_serial_out(struct uart_port *p, int offset, int value)
374 struct plat_sci_reg *reg = sci_getreg(p, offset);
377 iowrite8(value, p->membase + (reg->offset << p->regshift));
378 else if (reg->size == 16)
379 iowrite16(value, p->membase + (reg->offset << p->regshift));
381 WARN(1, "Invalid register access\n");
384 static int sci_probe_regmap(struct plat_sci_port *cfg)
388 cfg->regtype = SCIx_SCI_REGTYPE;
391 cfg->regtype = SCIx_IRDA_REGTYPE;
394 cfg->regtype = SCIx_SCIFA_REGTYPE;
397 cfg->regtype = SCIx_SCIFB_REGTYPE;
401 * The SH-4 is a bit of a misnomer here, although that's
402 * where this particular port layout originated. This
403 * configuration (or some slight variation thereof)
404 * remains the dominant model for all SCIFs.
406 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
409 cfg->regtype = SCIx_HSCIF_REGTYPE;
412 printk(KERN_ERR "Can't probe register map for given port\n");
419 static void sci_port_enable(struct sci_port *sci_port)
421 if (!sci_port->port.dev)
424 pm_runtime_get_sync(sci_port->port.dev);
426 clk_prepare_enable(sci_port->iclk);
427 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
428 clk_prepare_enable(sci_port->fclk);
431 static void sci_port_disable(struct sci_port *sci_port)
433 if (!sci_port->port.dev)
436 /* Cancel the break timer to ensure that the timer handler will not try
437 * to access the hardware with clocks and power disabled. Reset the
438 * break flag to make the break debouncing state machine ready for the
441 del_timer_sync(&sci_port->break_timer);
442 sci_port->break_flag = 0;
444 clk_disable_unprepare(sci_port->fclk);
445 clk_disable_unprepare(sci_port->iclk);
447 pm_runtime_put_sync(sci_port->port.dev);
450 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
452 #ifdef CONFIG_CONSOLE_POLL
453 static int sci_poll_get_char(struct uart_port *port)
455 unsigned short status;
459 status = serial_port_in(port, SCxSR);
460 if (status & SCxSR_ERRORS(port)) {
461 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
467 if (!(status & SCxSR_RDxF(port)))
470 c = serial_port_in(port, SCxRDR);
473 serial_port_in(port, SCxSR);
474 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
480 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
482 unsigned short status;
485 status = serial_port_in(port, SCxSR);
486 } while (!(status & SCxSR_TDxE(port)));
488 serial_port_out(port, SCxTDR, c);
489 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
491 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
493 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
495 struct sci_port *s = to_sci_port(port);
496 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
499 * Use port-specific handler if provided.
501 if (s->cfg->ops && s->cfg->ops->init_pins) {
502 s->cfg->ops->init_pins(port, cflag);
507 * For the generic path SCSPTR is necessary. Bail out if that's
513 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
514 ((!(cflag & CRTSCTS)))) {
515 unsigned short status;
517 status = serial_port_in(port, SCSPTR);
518 status &= ~SCSPTR_CTSIO;
519 status |= SCSPTR_RTSIO;
520 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
524 static int sci_txfill(struct uart_port *port)
526 struct plat_sci_reg *reg;
528 reg = sci_getreg(port, SCTFDR);
530 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
532 reg = sci_getreg(port, SCFDR);
534 return serial_port_in(port, SCFDR) >> 8;
536 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
539 static int sci_txroom(struct uart_port *port)
541 return port->fifosize - sci_txfill(port);
544 static int sci_rxfill(struct uart_port *port)
546 struct plat_sci_reg *reg;
548 reg = sci_getreg(port, SCRFDR);
550 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
552 reg = sci_getreg(port, SCFDR);
554 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
556 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
560 * SCI helper for checking the state of the muxed port/RXD pins.
562 static inline int sci_rxd_in(struct uart_port *port)
564 struct sci_port *s = to_sci_port(port);
566 if (s->cfg->port_reg <= 0)
569 /* Cast for ARM damage */
570 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
573 /* ********************************************************************** *
574 * the interrupt related routines *
575 * ********************************************************************** */
577 static void sci_transmit_chars(struct uart_port *port)
579 struct circ_buf *xmit = &port->state->xmit;
580 unsigned int stopped = uart_tx_stopped(port);
581 unsigned short status;
585 status = serial_port_in(port, SCxSR);
586 if (!(status & SCxSR_TDxE(port))) {
587 ctrl = serial_port_in(port, SCSCR);
588 if (uart_circ_empty(xmit))
592 serial_port_out(port, SCSCR, ctrl);
596 count = sci_txroom(port);
604 } else if (!uart_circ_empty(xmit) && !stopped) {
605 c = xmit->buf[xmit->tail];
606 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
611 serial_port_out(port, SCxTDR, c);
614 } while (--count > 0);
616 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
618 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
619 uart_write_wakeup(port);
620 if (uart_circ_empty(xmit)) {
623 ctrl = serial_port_in(port, SCSCR);
625 if (port->type != PORT_SCI) {
626 serial_port_in(port, SCxSR); /* Dummy read */
627 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
631 serial_port_out(port, SCSCR, ctrl);
635 /* On SH3, SCIF may read end-of-break as a space->mark char */
636 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
638 static void sci_receive_chars(struct uart_port *port)
640 struct sci_port *sci_port = to_sci_port(port);
641 struct tty_port *tport = &port->state->port;
642 int i, count, copied = 0;
643 unsigned short status;
646 status = serial_port_in(port, SCxSR);
647 if (!(status & SCxSR_RDxF(port)))
651 /* Don't copy more bytes than there is room for in the buffer */
652 count = tty_buffer_request_room(tport, sci_rxfill(port));
654 /* If for any reason we can't copy more data, we're done! */
658 if (port->type == PORT_SCI) {
659 char c = serial_port_in(port, SCxRDR);
660 if (uart_handle_sysrq_char(port, c) ||
661 sci_port->break_flag)
664 tty_insert_flip_char(tport, c, TTY_NORMAL);
666 for (i = 0; i < count; i++) {
667 char c = serial_port_in(port, SCxRDR);
669 status = serial_port_in(port, SCxSR);
670 #if defined(CONFIG_CPU_SH3)
671 /* Skip "chars" during break */
672 if (sci_port->break_flag) {
674 (status & SCxSR_FER(port))) {
679 /* Nonzero => end-of-break */
680 dev_dbg(port->dev, "debounce<%02x>\n", c);
681 sci_port->break_flag = 0;
688 #endif /* CONFIG_CPU_SH3 */
689 if (uart_handle_sysrq_char(port, c)) {
694 /* Store data and status */
695 if (status & SCxSR_FER(port)) {
697 port->icount.frame++;
698 dev_notice(port->dev, "frame error\n");
699 } else if (status & SCxSR_PER(port)) {
701 port->icount.parity++;
702 dev_notice(port->dev, "parity error\n");
706 tty_insert_flip_char(tport, c, flag);
710 serial_port_in(port, SCxSR); /* dummy read */
711 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
714 port->icount.rx += count;
718 /* Tell the rest of the system the news. New characters! */
719 tty_flip_buffer_push(tport);
721 serial_port_in(port, SCxSR); /* dummy read */
722 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
726 #define SCI_BREAK_JIFFIES (HZ/20)
729 * The sci generates interrupts during the break,
730 * 1 per millisecond or so during the break period, for 9600 baud.
731 * So dont bother disabling interrupts.
732 * But dont want more than 1 break event.
733 * Use a kernel timer to periodically poll the rx line until
734 * the break is finished.
736 static inline void sci_schedule_break_timer(struct sci_port *port)
738 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
741 /* Ensure that two consecutive samples find the break over. */
742 static void sci_break_timer(unsigned long data)
744 struct sci_port *port = (struct sci_port *)data;
746 if (sci_rxd_in(&port->port) == 0) {
747 port->break_flag = 1;
748 sci_schedule_break_timer(port);
749 } else if (port->break_flag == 1) {
751 port->break_flag = 2;
752 sci_schedule_break_timer(port);
754 port->break_flag = 0;
757 static int sci_handle_errors(struct uart_port *port)
760 unsigned short status = serial_port_in(port, SCxSR);
761 struct tty_port *tport = &port->state->port;
762 struct sci_port *s = to_sci_port(port);
764 /* Handle overruns */
765 if (status & (1 << s->overrun_bit)) {
766 port->icount.overrun++;
769 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
772 dev_notice(port->dev, "overrun error");
775 if (status & SCxSR_FER(port)) {
776 if (sci_rxd_in(port) == 0) {
777 /* Notify of BREAK */
778 struct sci_port *sci_port = to_sci_port(port);
780 if (!sci_port->break_flag) {
783 sci_port->break_flag = 1;
784 sci_schedule_break_timer(sci_port);
786 /* Do sysrq handling. */
787 if (uart_handle_break(port))
790 dev_dbg(port->dev, "BREAK detected\n");
792 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
798 port->icount.frame++;
800 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
803 dev_notice(port->dev, "frame error\n");
807 if (status & SCxSR_PER(port)) {
809 port->icount.parity++;
811 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
814 dev_notice(port->dev, "parity error");
818 tty_flip_buffer_push(tport);
823 static int sci_handle_fifo_overrun(struct uart_port *port)
825 struct tty_port *tport = &port->state->port;
826 struct sci_port *s = to_sci_port(port);
827 struct plat_sci_reg *reg;
830 reg = sci_getreg(port, SCLSR);
834 if ((serial_port_in(port, SCLSR) & (1 << s->overrun_bit))) {
835 serial_port_out(port, SCLSR, 0);
837 port->icount.overrun++;
839 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
840 tty_flip_buffer_push(tport);
842 dev_notice(port->dev, "overrun error\n");
849 static int sci_handle_breaks(struct uart_port *port)
852 unsigned short status = serial_port_in(port, SCxSR);
853 struct tty_port *tport = &port->state->port;
854 struct sci_port *s = to_sci_port(port);
856 if (uart_handle_break(port))
859 if (!s->break_flag && status & SCxSR_BRK(port)) {
860 #if defined(CONFIG_CPU_SH3)
867 /* Notify of BREAK */
868 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
871 dev_dbg(port->dev, "BREAK detected\n");
875 tty_flip_buffer_push(tport);
877 copied += sci_handle_fifo_overrun(port);
882 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
884 #ifdef CONFIG_SERIAL_SH_SCI_DMA
885 struct uart_port *port = ptr;
886 struct sci_port *s = to_sci_port(port);
889 u16 scr = serial_port_in(port, SCSCR);
890 u16 ssr = serial_port_in(port, SCxSR);
892 /* Disable future Rx interrupts */
893 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
894 disable_irq_nosync(irq);
899 serial_port_out(port, SCSCR, scr);
900 /* Clear current interrupt */
901 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
902 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
903 jiffies, s->rx_timeout);
904 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
910 /* I think sci_receive_chars has to be called irrespective
911 * of whether the I_IXOFF is set, otherwise, how is the interrupt
914 sci_receive_chars(ptr);
919 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
921 struct uart_port *port = ptr;
924 spin_lock_irqsave(&port->lock, flags);
925 sci_transmit_chars(port);
926 spin_unlock_irqrestore(&port->lock, flags);
931 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
933 struct uart_port *port = ptr;
936 if (port->type == PORT_SCI) {
937 if (sci_handle_errors(port)) {
938 /* discard character in rx buffer */
939 serial_port_in(port, SCxSR);
940 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
943 sci_handle_fifo_overrun(port);
944 sci_rx_interrupt(irq, ptr);
947 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
949 /* Kick the transmission */
950 sci_tx_interrupt(irq, ptr);
955 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
957 struct uart_port *port = ptr;
960 sci_handle_breaks(port);
961 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
966 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
969 * Not all ports (such as SCIFA) will support REIE. Rather than
970 * special-casing the port type, we check the port initialization
971 * IRQ enable mask to see whether the IRQ is desired at all. If
972 * it's unset, it's logically inferred that there's no point in
975 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
978 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
980 unsigned short ssr_status, scr_status, err_enabled;
981 struct uart_port *port = ptr;
982 struct sci_port *s = to_sci_port(port);
983 irqreturn_t ret = IRQ_NONE;
985 ssr_status = serial_port_in(port, SCxSR);
986 scr_status = serial_port_in(port, SCSCR);
987 err_enabled = scr_status & port_rx_irq_mask(port);
990 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
992 ret = sci_tx_interrupt(irq, ptr);
995 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
998 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
999 (scr_status & SCSCR_RIE))
1000 ret = sci_rx_interrupt(irq, ptr);
1002 /* Error Interrupt */
1003 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1004 ret = sci_er_interrupt(irq, ptr);
1006 /* Break Interrupt */
1007 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1008 ret = sci_br_interrupt(irq, ptr);
1014 * Here we define a transition notifier so that we can update all of our
1015 * ports' baud rate when the peripheral clock changes.
1017 static int sci_notifier(struct notifier_block *self,
1018 unsigned long phase, void *p)
1020 struct sci_port *sci_port;
1021 unsigned long flags;
1023 sci_port = container_of(self, struct sci_port, freq_transition);
1025 if ((phase == CPUFREQ_POSTCHANGE) ||
1026 (phase == CPUFREQ_RESUMECHANGE)) {
1027 struct uart_port *port = &sci_port->port;
1029 spin_lock_irqsave(&port->lock, flags);
1030 port->uartclk = clk_get_rate(sci_port->iclk);
1031 spin_unlock_irqrestore(&port->lock, flags);
1037 static struct sci_irq_desc {
1039 irq_handler_t handler;
1040 } sci_irq_desc[] = {
1042 * Split out handlers, the default case.
1046 .handler = sci_er_interrupt,
1051 .handler = sci_rx_interrupt,
1056 .handler = sci_tx_interrupt,
1061 .handler = sci_br_interrupt,
1065 * Special muxed handler.
1069 .handler = sci_mpxed_interrupt,
1073 static int sci_request_irq(struct sci_port *port)
1075 struct uart_port *up = &port->port;
1078 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1079 struct sci_irq_desc *desc;
1082 if (SCIx_IRQ_IS_MUXED(port)) {
1086 irq = port->irqs[i];
1089 * Certain port types won't support all of the
1090 * available interrupt sources.
1092 if (unlikely(irq < 0))
1096 desc = sci_irq_desc + i;
1097 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1098 dev_name(up->dev), desc->desc);
1099 if (!port->irqstr[j]) {
1100 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1105 ret = request_irq(irq, desc->handler, up->irqflags,
1106 port->irqstr[j], port);
1107 if (unlikely(ret)) {
1108 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1117 free_irq(port->irqs[i], port);
1121 kfree(port->irqstr[j]);
1126 static void sci_free_irq(struct sci_port *port)
1131 * Intentionally in reverse order so we iterate over the muxed
1134 for (i = 0; i < SCIx_NR_IRQS; i++) {
1135 int irq = port->irqs[i];
1138 * Certain port types won't support all of the available
1139 * interrupt sources.
1141 if (unlikely(irq < 0))
1144 free_irq(port->irqs[i], port);
1145 kfree(port->irqstr[i]);
1147 if (SCIx_IRQ_IS_MUXED(port)) {
1148 /* If there's only one IRQ, we're done. */
1154 static unsigned int sci_tx_empty(struct uart_port *port)
1156 unsigned short status = serial_port_in(port, SCxSR);
1157 unsigned short in_tx_fifo = sci_txfill(port);
1159 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1163 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1164 * CTS/RTS is supported in hardware by at least one port and controlled
1165 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1166 * handled via the ->init_pins() op, which is a bit of a one-way street,
1167 * lacking any ability to defer pin control -- this will later be
1168 * converted over to the GPIO framework).
1170 * Other modes (such as loopback) are supported generically on certain
1171 * port types, but not others. For these it's sufficient to test for the
1172 * existence of the support register and simply ignore the port type.
1174 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1176 if (mctrl & TIOCM_LOOP) {
1177 struct plat_sci_reg *reg;
1180 * Standard loopback mode for SCFCR ports.
1182 reg = sci_getreg(port, SCFCR);
1184 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
1188 static unsigned int sci_get_mctrl(struct uart_port *port)
1191 * CTS/RTS is handled in hardware when supported, while nothing
1192 * else is wired up. Keep it simple and simply assert DSR/CAR.
1194 return TIOCM_DSR | TIOCM_CAR;
1197 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1198 static void sci_dma_tx_complete(void *arg)
1200 struct sci_port *s = arg;
1201 struct uart_port *port = &s->port;
1202 struct circ_buf *xmit = &port->state->xmit;
1203 unsigned long flags;
1205 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1207 spin_lock_irqsave(&port->lock, flags);
1209 xmit->tail += sg_dma_len(&s->sg_tx);
1210 xmit->tail &= UART_XMIT_SIZE - 1;
1212 port->icount.tx += sg_dma_len(&s->sg_tx);
1214 async_tx_ack(s->desc_tx);
1217 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1218 uart_write_wakeup(port);
1220 if (!uart_circ_empty(xmit)) {
1222 schedule_work(&s->work_tx);
1224 s->cookie_tx = -EINVAL;
1225 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1226 u16 ctrl = serial_port_in(port, SCSCR);
1227 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1231 spin_unlock_irqrestore(&port->lock, flags);
1234 /* Locking: called with port lock held */
1235 static int sci_dma_rx_push(struct sci_port *s, size_t count)
1237 struct uart_port *port = &s->port;
1238 struct tty_port *tport = &port->state->port;
1239 int i, active, room;
1241 room = tty_buffer_request_room(tport, count);
1243 if (s->active_rx == s->cookie_rx[0]) {
1245 } else if (s->active_rx == s->cookie_rx[1]) {
1248 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1253 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1258 for (i = 0; i < room; i++)
1259 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1262 port->icount.rx += room;
1267 static void sci_dma_rx_complete(void *arg)
1269 struct sci_port *s = arg;
1270 struct uart_port *port = &s->port;
1271 unsigned long flags;
1274 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
1276 spin_lock_irqsave(&port->lock, flags);
1278 count = sci_dma_rx_push(s, s->buf_len_rx);
1280 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1282 spin_unlock_irqrestore(&port->lock, flags);
1285 tty_flip_buffer_push(&port->state->port);
1287 schedule_work(&s->work_rx);
1290 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1292 struct dma_chan *chan = s->chan_rx;
1293 struct uart_port *port = &s->port;
1296 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1297 dma_release_channel(chan);
1298 if (sg_dma_address(&s->sg_rx[0]))
1299 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1300 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1305 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1307 struct dma_chan *chan = s->chan_tx;
1308 struct uart_port *port = &s->port;
1311 s->cookie_tx = -EINVAL;
1312 dma_release_channel(chan);
1317 static void sci_submit_rx(struct sci_port *s)
1319 struct dma_chan *chan = s->chan_rx;
1322 for (i = 0; i < 2; i++) {
1323 struct scatterlist *sg = &s->sg_rx[i];
1324 struct dma_async_tx_descriptor *desc;
1326 desc = dmaengine_prep_slave_sg(chan,
1327 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1330 s->desc_rx[i] = desc;
1331 desc->callback = sci_dma_rx_complete;
1332 desc->callback_param = s;
1333 s->cookie_rx[i] = desc->tx_submit(desc);
1336 if (!desc || s->cookie_rx[i] < 0) {
1338 async_tx_ack(s->desc_rx[0]);
1339 s->cookie_rx[0] = -EINVAL;
1343 s->cookie_rx[i] = -EINVAL;
1345 dev_warn(s->port.dev,
1346 "failed to re-start DMA, using PIO\n");
1347 sci_rx_dma_release(s, true);
1350 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1351 s->cookie_rx[i], i);
1354 s->active_rx = s->cookie_rx[0];
1356 dma_async_issue_pending(chan);
1359 static void work_fn_rx(struct work_struct *work)
1361 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1362 struct uart_port *port = &s->port;
1363 struct dma_async_tx_descriptor *desc;
1366 if (s->active_rx == s->cookie_rx[0]) {
1368 } else if (s->active_rx == s->cookie_rx[1]) {
1371 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1374 desc = s->desc_rx[new];
1376 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1378 /* Handle incomplete DMA receive */
1379 struct dma_chan *chan = s->chan_rx;
1380 struct shdma_desc *sh_desc = container_of(desc,
1381 struct shdma_desc, async_tx);
1382 unsigned long flags;
1385 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
1386 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
1387 sh_desc->partial, sh_desc->cookie);
1389 spin_lock_irqsave(&port->lock, flags);
1390 count = sci_dma_rx_push(s, sh_desc->partial);
1391 spin_unlock_irqrestore(&port->lock, flags);
1394 tty_flip_buffer_push(&port->state->port);
1401 s->cookie_rx[new] = desc->tx_submit(desc);
1402 if (s->cookie_rx[new] < 0) {
1403 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1404 sci_rx_dma_release(s, true);
1408 s->active_rx = s->cookie_rx[!new];
1410 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1411 s->cookie_rx[new], new, s->active_rx);
1414 static void work_fn_tx(struct work_struct *work)
1416 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1417 struct dma_async_tx_descriptor *desc;
1418 struct dma_chan *chan = s->chan_tx;
1419 struct uart_port *port = &s->port;
1420 struct circ_buf *xmit = &port->state->xmit;
1421 struct scatterlist *sg = &s->sg_tx;
1425 * Port xmit buffer is already mapped, and it is one page... Just adjust
1426 * offsets and lengths. Since it is a circular buffer, we have to
1427 * transmit till the end, and then the rest. Take the port lock to get a
1428 * consistent xmit buffer state.
1430 spin_lock_irq(&port->lock);
1431 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1432 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1434 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1435 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1436 spin_unlock_irq(&port->lock);
1438 BUG_ON(!sg_dma_len(sg));
1440 desc = dmaengine_prep_slave_sg(chan,
1441 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
1442 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1445 sci_tx_dma_release(s, true);
1449 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1451 spin_lock_irq(&port->lock);
1453 desc->callback = sci_dma_tx_complete;
1454 desc->callback_param = s;
1455 spin_unlock_irq(&port->lock);
1456 s->cookie_tx = desc->tx_submit(desc);
1457 if (s->cookie_tx < 0) {
1458 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1460 sci_tx_dma_release(s, true);
1464 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1465 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1467 dma_async_issue_pending(chan);
1471 static void sci_start_tx(struct uart_port *port)
1473 struct sci_port *s = to_sci_port(port);
1474 unsigned short ctrl;
1476 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1477 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1478 u16 new, scr = serial_port_in(port, SCSCR);
1482 new = scr & ~0x8000;
1484 serial_port_out(port, SCSCR, new);
1487 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1490 schedule_work(&s->work_tx);
1494 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1495 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1496 ctrl = serial_port_in(port, SCSCR);
1497 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1501 static void sci_stop_tx(struct uart_port *port)
1503 unsigned short ctrl;
1505 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1506 ctrl = serial_port_in(port, SCSCR);
1508 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1513 serial_port_out(port, SCSCR, ctrl);
1516 static void sci_start_rx(struct uart_port *port)
1518 unsigned short ctrl;
1520 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1522 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1525 serial_port_out(port, SCSCR, ctrl);
1528 static void sci_stop_rx(struct uart_port *port)
1530 unsigned short ctrl;
1532 ctrl = serial_port_in(port, SCSCR);
1534 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1537 ctrl &= ~port_rx_irq_mask(port);
1539 serial_port_out(port, SCSCR, ctrl);
1542 static void sci_enable_ms(struct uart_port *port)
1545 * Not supported by hardware, always a nop.
1549 static void sci_break_ctl(struct uart_port *port, int break_state)
1551 struct sci_port *s = to_sci_port(port);
1552 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1553 unsigned short scscr, scsptr;
1555 /* check wheter the port has SCSPTR */
1558 * Not supported by hardware. Most parts couple break and rx
1559 * interrupts together, with break detection always enabled.
1564 scsptr = serial_port_in(port, SCSPTR);
1565 scscr = serial_port_in(port, SCSCR);
1567 if (break_state == -1) {
1568 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1571 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1575 serial_port_out(port, SCSPTR, scsptr);
1576 serial_port_out(port, SCSCR, scscr);
1579 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1580 static bool filter(struct dma_chan *chan, void *slave)
1582 struct sh_dmae_slave *param = slave;
1584 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1585 param->shdma_slave.slave_id);
1587 chan->private = ¶m->shdma_slave;
1591 static void rx_timer_fn(unsigned long arg)
1593 struct sci_port *s = (struct sci_port *)arg;
1594 struct uart_port *port = &s->port;
1595 u16 scr = serial_port_in(port, SCSCR);
1597 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1599 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1601 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1602 dev_dbg(port->dev, "DMA Rx timed out\n");
1603 schedule_work(&s->work_rx);
1606 static void sci_request_dma(struct uart_port *port)
1608 struct sci_port *s = to_sci_port(port);
1609 struct sh_dmae_slave *param;
1610 struct dma_chan *chan;
1611 dma_cap_mask_t mask;
1614 dev_dbg(port->dev, "%s: port %d\n", __func__,
1617 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1621 dma_cap_set(DMA_SLAVE, mask);
1623 param = &s->param_tx;
1625 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1626 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1628 s->cookie_tx = -EINVAL;
1629 chan = dma_request_channel(mask, filter, param);
1630 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1633 sg_init_table(&s->sg_tx, 1);
1634 /* UART circular tx buffer is an aligned page. */
1635 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1636 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1638 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1639 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1641 sci_tx_dma_release(s, false);
1643 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1644 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1645 &sg_dma_address(&s->sg_tx));
1647 s->sg_len_tx = nent;
1649 INIT_WORK(&s->work_tx, work_fn_tx);
1652 param = &s->param_rx;
1654 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1655 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1657 chan = dma_request_channel(mask, filter, param);
1658 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1666 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1667 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1668 &dma[0], GFP_KERNEL);
1672 "failed to allocate dma buffer, using PIO\n");
1673 sci_rx_dma_release(s, true);
1677 buf[1] = buf[0] + s->buf_len_rx;
1678 dma[1] = dma[0] + s->buf_len_rx;
1680 for (i = 0; i < 2; i++) {
1681 struct scatterlist *sg = &s->sg_rx[i];
1683 sg_init_table(sg, 1);
1684 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1685 (uintptr_t)buf[i] & ~PAGE_MASK);
1686 sg_dma_address(sg) = dma[i];
1689 INIT_WORK(&s->work_rx, work_fn_rx);
1690 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1696 static void sci_free_dma(struct uart_port *port)
1698 struct sci_port *s = to_sci_port(port);
1701 sci_tx_dma_release(s, false);
1703 sci_rx_dma_release(s, false);
1706 static inline void sci_request_dma(struct uart_port *port)
1710 static inline void sci_free_dma(struct uart_port *port)
1715 static int sci_startup(struct uart_port *port)
1717 struct sci_port *s = to_sci_port(port);
1718 unsigned long flags;
1721 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1723 ret = sci_request_irq(s);
1724 if (unlikely(ret < 0))
1727 sci_request_dma(port);
1729 spin_lock_irqsave(&port->lock, flags);
1732 spin_unlock_irqrestore(&port->lock, flags);
1737 static void sci_shutdown(struct uart_port *port)
1739 struct sci_port *s = to_sci_port(port);
1740 unsigned long flags;
1742 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1744 spin_lock_irqsave(&port->lock, flags);
1747 spin_unlock_irqrestore(&port->lock, flags);
1753 static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1758 return freq / (16 * bps);
1760 return DIV_ROUND_CLOSEST(freq, 32 * bps) - 1;
1762 return freq / (8 * bps);
1764 return DIV_ROUND_CLOSEST(freq, 16 * bps) - 1;
1767 /* Warn, but use a safe default */
1770 return ((freq + 16 * bps) / (32 * bps) - 1);
1773 /* calculate sample rate, BRR, and clock select for HSCIF */
1774 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1775 int *brr, unsigned int *srr,
1779 int min_err = 1000; /* 100% */
1781 /* Find the combination of sample rate and clock select with the
1782 smallest deviation from the desired baud rate. */
1783 for (sr = 8; sr <= 32; sr++) {
1784 for (c = 0; c <= 3; c++) {
1785 /* integerized formulas from HSCIF documentation */
1786 br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1;
1787 if (br < 0 || br > 255)
1789 err = freq / ((br + 1) * bps * sr *
1790 (1 << (2 * c + 1)) / 1000) - 1000;
1791 if (min_err > err) {
1800 if (min_err == 1000) {
1809 static void sci_reset(struct uart_port *port)
1811 struct plat_sci_reg *reg;
1812 unsigned int status;
1815 status = serial_port_in(port, SCxSR);
1816 } while (!(status & SCxSR_TEND(port)));
1818 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1820 reg = sci_getreg(port, SCFCR);
1822 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1825 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1826 struct ktermios *old)
1828 struct sci_port *s = to_sci_port(port);
1829 struct plat_sci_reg *reg;
1830 unsigned int baud, smr_val, max_baud, cks = 0;
1832 unsigned int srr = 15;
1835 * earlyprintk comes here early on with port->uartclk set to zero.
1836 * the clock framework is not up and running at this point so here
1837 * we assume that 115200 is the maximum baud rate. please note that
1838 * the baud rate is not programmed during earlyprintk - it is assumed
1839 * that the previous boot loader has enabled required clocks and
1840 * setup the baud rate generator hardware for us already.
1842 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1844 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1845 if (likely(baud && port->uartclk)) {
1846 if (s->cfg->scbrr_algo_id == SCBRR_ALGO_6) {
1847 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1850 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud,
1852 for (cks = 0; t >= 256 && cks <= 3; cks++)
1861 smr_val = serial_port_in(port, SCSMR) & 3;
1863 if ((termios->c_cflag & CSIZE) == CS7)
1865 if (termios->c_cflag & PARENB)
1867 if (termios->c_cflag & PARODD)
1869 if (termios->c_cflag & CSTOPB)
1872 uart_update_timeout(port, termios->c_cflag, baud);
1874 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1875 __func__, smr_val, cks, t, s->cfg->scscr);
1878 serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
1879 serial_port_out(port, SCBRR, t);
1880 reg = sci_getreg(port, HSSRR);
1882 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1883 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1885 serial_port_out(port, SCSMR, smr_val);
1887 sci_init_pins(port, termios->c_cflag);
1889 reg = sci_getreg(port, SCFCR);
1891 unsigned short ctrl = serial_port_in(port, SCFCR);
1893 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1894 if (termios->c_cflag & CRTSCTS)
1901 * As we've done a sci_reset() above, ensure we don't
1902 * interfere with the FIFOs while toggling MCE. As the
1903 * reset values could still be set, simply mask them out.
1905 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1907 serial_port_out(port, SCFCR, ctrl);
1910 serial_port_out(port, SCSCR, s->cfg->scscr);
1912 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1914 * Calculate delay for 1.5 DMA buffers: see
1915 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1916 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1917 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1918 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1919 * sizes), but it has been found out experimentally, that this is not
1920 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1921 * as a minimum seem to work perfectly.
1924 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1927 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1928 s->rx_timeout * 1000 / HZ, port->timeout);
1929 if (s->rx_timeout < msecs_to_jiffies(20))
1930 s->rx_timeout = msecs_to_jiffies(20);
1934 if ((termios->c_cflag & CREAD) != 0)
1937 sci_port_disable(s);
1940 static void sci_pm(struct uart_port *port, unsigned int state,
1941 unsigned int oldstate)
1943 struct sci_port *sci_port = to_sci_port(port);
1947 sci_port_disable(sci_port);
1950 sci_port_enable(sci_port);
1955 static const char *sci_type(struct uart_port *port)
1957 switch (port->type) {
1975 static inline unsigned long sci_port_size(struct uart_port *port)
1978 * Pick an arbitrary size that encapsulates all of the base
1979 * registers by default. This can be optimized later, or derived
1980 * from platform resource data at such a time that ports begin to
1981 * behave more erratically.
1983 if (port->type == PORT_HSCIF)
1989 static int sci_remap_port(struct uart_port *port)
1991 unsigned long size = sci_port_size(port);
1994 * Nothing to do if there's already an established membase.
1999 if (port->flags & UPF_IOREMAP) {
2000 port->membase = ioremap_nocache(port->mapbase, size);
2001 if (unlikely(!port->membase)) {
2002 dev_err(port->dev, "can't remap port#%d\n", port->line);
2007 * For the simple (and majority of) cases where we don't
2008 * need to do any remapping, just cast the cookie
2011 port->membase = (void __iomem *)port->mapbase;
2017 static void sci_release_port(struct uart_port *port)
2019 if (port->flags & UPF_IOREMAP) {
2020 iounmap(port->membase);
2021 port->membase = NULL;
2024 release_mem_region(port->mapbase, sci_port_size(port));
2027 static int sci_request_port(struct uart_port *port)
2029 unsigned long size = sci_port_size(port);
2030 struct resource *res;
2033 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
2034 if (unlikely(res == NULL))
2037 ret = sci_remap_port(port);
2038 if (unlikely(ret != 0)) {
2039 release_resource(res);
2046 static void sci_config_port(struct uart_port *port, int flags)
2048 if (flags & UART_CONFIG_TYPE) {
2049 struct sci_port *sport = to_sci_port(port);
2051 port->type = sport->cfg->type;
2052 sci_request_port(port);
2056 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2058 if (ser->baud_base < 2400)
2059 /* No paper tape reader for Mitch.. */
2065 static struct uart_ops sci_uart_ops = {
2066 .tx_empty = sci_tx_empty,
2067 .set_mctrl = sci_set_mctrl,
2068 .get_mctrl = sci_get_mctrl,
2069 .start_tx = sci_start_tx,
2070 .stop_tx = sci_stop_tx,
2071 .stop_rx = sci_stop_rx,
2072 .enable_ms = sci_enable_ms,
2073 .break_ctl = sci_break_ctl,
2074 .startup = sci_startup,
2075 .shutdown = sci_shutdown,
2076 .set_termios = sci_set_termios,
2079 .release_port = sci_release_port,
2080 .request_port = sci_request_port,
2081 .config_port = sci_config_port,
2082 .verify_port = sci_verify_port,
2083 #ifdef CONFIG_CONSOLE_POLL
2084 .poll_get_char = sci_poll_get_char,
2085 .poll_put_char = sci_poll_put_char,
2089 static int sci_init_single(struct platform_device *dev,
2090 struct sci_port *sci_port, unsigned int index,
2091 struct plat_sci_port *p, bool early)
2093 struct uart_port *port = &sci_port->port;
2094 const struct resource *res;
2100 port->ops = &sci_uart_ops;
2101 port->iotype = UPIO_MEM;
2104 if (dev->num_resources) {
2105 /* Device has resources, use them. */
2106 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2110 port->mapbase = res->start;
2112 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2113 sci_port->irqs[i] = platform_get_irq(dev, i);
2115 /* The SCI generates several interrupts. They can be muxed
2116 * together or connected to different interrupt lines. In the
2117 * muxed case only one interrupt resource is specified. In the
2118 * non-muxed case three or four interrupt resources are
2119 * specified, as the BRI interrupt is optional.
2121 if (sci_port->irqs[0] < 0)
2124 if (sci_port->irqs[1] < 0) {
2125 sci_port->irqs[1] = sci_port->irqs[0];
2126 sci_port->irqs[2] = sci_port->irqs[0];
2127 sci_port->irqs[3] = sci_port->irqs[0];
2130 /* No resources, use old-style platform data. */
2131 port->mapbase = p->mapbase;
2132 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2133 sci_port->irqs[i] = p->irqs[i] ? p->irqs[i] : -ENXIO;
2138 port->fifosize = 256;
2141 port->fifosize = 128;
2144 port->fifosize = 64;
2147 port->fifosize = 16;
2154 if (p->regtype == SCIx_PROBE_REGTYPE) {
2155 ret = sci_probe_regmap(p);
2161 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2162 if (IS_ERR(sci_port->iclk)) {
2163 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2164 if (IS_ERR(sci_port->iclk)) {
2165 dev_err(&dev->dev, "can't get iclk\n");
2166 return PTR_ERR(sci_port->iclk);
2171 * The function clock is optional, ignore it if we can't
2174 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2175 if (IS_ERR(sci_port->fclk))
2176 sci_port->fclk = NULL;
2178 port->dev = &dev->dev;
2180 pm_runtime_enable(&dev->dev);
2183 sci_port->break_timer.data = (unsigned long)sci_port;
2184 sci_port->break_timer.function = sci_break_timer;
2185 init_timer(&sci_port->break_timer);
2188 * Establish some sensible defaults for the error detection.
2190 sci_port->error_mask = (p->type == PORT_SCI) ?
2191 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2194 * Establish sensible defaults for the overrun detection, unless
2195 * the part has explicitly disabled support for it.
2197 if (p->type == PORT_SCI)
2198 sci_port->overrun_bit = 5;
2199 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2200 sci_port->overrun_bit = 9;
2202 sci_port->overrun_bit = 0;
2205 * Make the error mask inclusive of overrun detection, if
2208 sci_port->error_mask |= 1 << sci_port->overrun_bit;
2210 port->type = p->type;
2211 port->flags = UPF_FIXED_PORT | p->flags;
2212 port->regshift = p->regshift;
2215 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2216 * for the multi-IRQ ports, which is where we are primarily
2217 * concerned with the shutdown path synchronization.
2219 * For the muxed case there's nothing more to do.
2221 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2224 port->serial_in = sci_serial_in;
2225 port->serial_out = sci_serial_out;
2227 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2228 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2229 p->dma_slave_tx, p->dma_slave_rx);
2234 static void sci_cleanup_single(struct sci_port *port)
2236 clk_put(port->iclk);
2237 clk_put(port->fclk);
2239 pm_runtime_disable(port->port.dev);
2242 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2243 static void serial_console_putchar(struct uart_port *port, int ch)
2245 sci_poll_put_char(port, ch);
2249 * Print a string to the serial port trying not to disturb
2250 * any possible real use of the port...
2252 static void serial_console_write(struct console *co, const char *s,
2255 struct sci_port *sci_port = &sci_ports[co->index];
2256 struct uart_port *port = &sci_port->port;
2257 unsigned short bits, ctrl;
2258 unsigned long flags;
2261 local_irq_save(flags);
2264 else if (oops_in_progress)
2265 locked = spin_trylock(&port->lock);
2267 spin_lock(&port->lock);
2269 /* first save the SCSCR then disable the interrupts */
2270 ctrl = serial_port_in(port, SCSCR);
2271 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2273 uart_console_write(port, s, count, serial_console_putchar);
2275 /* wait until fifo is empty and last bit has been transmitted */
2276 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2277 while ((serial_port_in(port, SCxSR) & bits) != bits)
2280 /* restore the SCSCR */
2281 serial_port_out(port, SCSCR, ctrl);
2284 spin_unlock(&port->lock);
2285 local_irq_restore(flags);
2288 static int serial_console_setup(struct console *co, char *options)
2290 struct sci_port *sci_port;
2291 struct uart_port *port;
2299 * Refuse to handle any bogus ports.
2301 if (co->index < 0 || co->index >= SCI_NPORTS)
2304 sci_port = &sci_ports[co->index];
2305 port = &sci_port->port;
2308 * Refuse to handle uninitialized ports.
2313 ret = sci_remap_port(port);
2314 if (unlikely(ret != 0))
2318 uart_parse_options(options, &baud, &parity, &bits, &flow);
2320 return uart_set_options(port, co, baud, parity, bits, flow);
2323 static struct console serial_console = {
2325 .device = uart_console_device,
2326 .write = serial_console_write,
2327 .setup = serial_console_setup,
2328 .flags = CON_PRINTBUFFER,
2330 .data = &sci_uart_driver,
2333 static struct console early_serial_console = {
2334 .name = "early_ttySC",
2335 .write = serial_console_write,
2336 .flags = CON_PRINTBUFFER,
2340 static char early_serial_buf[32];
2342 static int sci_probe_earlyprintk(struct platform_device *pdev)
2344 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2346 if (early_serial_console.data)
2349 early_serial_console.index = pdev->id;
2351 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2353 serial_console_setup(&early_serial_console, early_serial_buf);
2355 if (!strstr(early_serial_buf, "keep"))
2356 early_serial_console.flags |= CON_BOOT;
2358 register_console(&early_serial_console);
2362 #define SCI_CONSOLE (&serial_console)
2365 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2370 #define SCI_CONSOLE NULL
2372 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2374 static char banner[] __initdata =
2375 KERN_INFO "SuperH (H)SCI(F) driver initialized\n";
2377 static struct uart_driver sci_uart_driver = {
2378 .owner = THIS_MODULE,
2379 .driver_name = "sci",
2380 .dev_name = "ttySC",
2382 .minor = SCI_MINOR_START,
2384 .cons = SCI_CONSOLE,
2387 static int sci_remove(struct platform_device *dev)
2389 struct sci_port *port = platform_get_drvdata(dev);
2391 cpufreq_unregister_notifier(&port->freq_transition,
2392 CPUFREQ_TRANSITION_NOTIFIER);
2394 uart_remove_one_port(&sci_uart_driver, &port->port);
2396 sci_cleanup_single(port);
2401 static int sci_probe_single(struct platform_device *dev,
2403 struct plat_sci_port *p,
2404 struct sci_port *sciport)
2409 if (unlikely(index >= SCI_NPORTS)) {
2410 dev_notice(&dev->dev, "Attempting to register port "
2411 "%d when only %d are available.\n",
2412 index+1, SCI_NPORTS);
2413 dev_notice(&dev->dev, "Consider bumping "
2414 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2418 ret = sci_init_single(dev, sciport, index, p, false);
2422 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2424 sci_cleanup_single(sciport);
2431 static int sci_probe(struct platform_device *dev)
2433 struct plat_sci_port *p = dev_get_platdata(&dev->dev);
2434 struct sci_port *sp = &sci_ports[dev->id];
2438 * If we've come here via earlyprintk initialization, head off to
2439 * the special early probe. We don't have sufficient device state
2440 * to make it beyond this yet.
2442 if (is_early_platform_device(dev))
2443 return sci_probe_earlyprintk(dev);
2445 platform_set_drvdata(dev, sp);
2447 ret = sci_probe_single(dev, dev->id, p, sp);
2451 sp->freq_transition.notifier_call = sci_notifier;
2453 ret = cpufreq_register_notifier(&sp->freq_transition,
2454 CPUFREQ_TRANSITION_NOTIFIER);
2455 if (unlikely(ret < 0)) {
2456 sci_cleanup_single(sp);
2460 #ifdef CONFIG_SH_STANDARD_BIOS
2461 sh_bios_gdb_detach();
2467 static int sci_suspend(struct device *dev)
2469 struct sci_port *sport = dev_get_drvdata(dev);
2472 uart_suspend_port(&sci_uart_driver, &sport->port);
2477 static int sci_resume(struct device *dev)
2479 struct sci_port *sport = dev_get_drvdata(dev);
2482 uart_resume_port(&sci_uart_driver, &sport->port);
2487 static const struct dev_pm_ops sci_dev_pm_ops = {
2488 .suspend = sci_suspend,
2489 .resume = sci_resume,
2492 static struct platform_driver sci_driver = {
2494 .remove = sci_remove,
2497 .owner = THIS_MODULE,
2498 .pm = &sci_dev_pm_ops,
2502 static int __init sci_init(void)
2508 ret = uart_register_driver(&sci_uart_driver);
2509 if (likely(ret == 0)) {
2510 ret = platform_driver_register(&sci_driver);
2512 uart_unregister_driver(&sci_uart_driver);
2518 static void __exit sci_exit(void)
2520 platform_driver_unregister(&sci_driver);
2521 uart_unregister_driver(&sci_uart_driver);
2524 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2525 early_platform_init_buffer("earlyprintk", &sci_driver,
2526 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2528 module_init(sci_init);
2529 module_exit(sci_exit);
2531 MODULE_LICENSE("GPL");
2532 MODULE_ALIAS("platform:sh-sci");
2533 MODULE_AUTHOR("Paul Mundt");
2534 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");