drivers/tty/serial/pch_uart.c

   1 /*
   2  *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
   3  *
   4  *This program is free software; you can redistribute it and/or modify
   5  *it under the terms of the GNU General Public License as published by
   6  *the Free Software Foundation; version 2 of the License.
   7  *
   8  *This program is distributed in the hope that it will be useful,
   9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *GNU General Public License for more details.
  12  *
  13  *You should have received a copy of the GNU General Public License
  14  *along with this program; if not, write to the Free Software
  15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #include <linux/serial_reg.h>
  18 #include <linux/module.h>
  19 #include <linux/pci.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/dmi.h>
  24
  25 #include <linux/dmaengine.h>
  26 #include <linux/pch_dma.h>
  27
  28 enum {
  29         PCH_UART_HANDLED_RX_INT_SHIFT,
  30         PCH_UART_HANDLED_TX_INT_SHIFT,
  31         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  32         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  33         PCH_UART_HANDLED_MS_INT_SHIFT,
  34 };
  35
  36 enum {
  37         PCH_UART_8LINE,
  38         PCH_UART_2LINE,
  39 };
  40
  41 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  42
  43 /* Set the max number of UART port
  44  * Intel EG20T PCH: 4 port
  45  * OKI SEMICONDUCTOR ML7213 IOH: 3 port
  46 */
  47 #define PCH_UART_NR     4
  48
  49 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  50 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  51 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  52                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  53 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  54                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  55 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  56
  57 #define PCH_UART_RBR            0x00
  58 #define PCH_UART_THR            0x00
  59
  60 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  61                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  62 #define PCH_UART_IER_ERBFI      0x00000001
  63 #define PCH_UART_IER_ETBEI      0x00000002
  64 #define PCH_UART_IER_ELSI       0x00000004
  65 #define PCH_UART_IER_EDSSI      0x00000008
  66
  67 #define PCH_UART_IIR_IP                 0x00000001
  68 #define PCH_UART_IIR_IID                0x00000006
  69 #define PCH_UART_IIR_MSI                0x00000000
  70 #define PCH_UART_IIR_TRI                0x00000002
  71 #define PCH_UART_IIR_RRI                0x00000004
  72 #define PCH_UART_IIR_REI                0x00000006
  73 #define PCH_UART_IIR_TOI                0x00000008
  74 #define PCH_UART_IIR_FIFO256            0x00000020
  75 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  76 #define PCH_UART_IIR_FE                 0x000000C0
  77
  78 #define PCH_UART_FCR_FIFOE              0x00000001
  79 #define PCH_UART_FCR_RFR                0x00000002
  80 #define PCH_UART_FCR_TFR                0x00000004
  81 #define PCH_UART_FCR_DMS                0x00000008
  82 #define PCH_UART_FCR_FIFO256            0x00000020
  83 #define PCH_UART_FCR_RFTL               0x000000C0
  84
  85 #define PCH_UART_FCR_RFTL1              0x00000000
  86 #define PCH_UART_FCR_RFTL64             0x00000040
  87 #define PCH_UART_FCR_RFTL128            0x00000080
  88 #define PCH_UART_FCR_RFTL224            0x000000C0
  89 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
  90 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
  91 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
  92 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
  93 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
  94 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
  95 #define PCH_UART_FCR_RFTL_SHIFT         6
  96
  97 #define PCH_UART_LCR_WLS        0x00000003
  98 #define PCH_UART_LCR_STB        0x00000004
  99 #define PCH_UART_LCR_PEN        0x00000008
 100 #define PCH_UART_LCR_EPS        0x00000010
 101 #define PCH_UART_LCR_SP         0x00000020
 102 #define PCH_UART_LCR_SB         0x00000040
 103 #define PCH_UART_LCR_DLAB       0x00000080
 104 #define PCH_UART_LCR_NP         0x00000000
 105 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 106 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 107 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 108 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 109                                 PCH_UART_LCR_SP)
 110
 111 #define PCH_UART_LCR_5BIT       0x00000000
 112 #define PCH_UART_LCR_6BIT       0x00000001
 113 #define PCH_UART_LCR_7BIT       0x00000002
 114 #define PCH_UART_LCR_8BIT       0x00000003
 115
 116 #define PCH_UART_MCR_DTR        0x00000001
 117 #define PCH_UART_MCR_RTS        0x00000002
 118 #define PCH_UART_MCR_OUT        0x0000000C
 119 #define PCH_UART_MCR_LOOP       0x00000010
 120 #define PCH_UART_MCR_AFE        0x00000020
 121
 122 #define PCH_UART_LSR_DR         0x00000001
 123 #define PCH_UART_LSR_ERR        (1<<7)
 124
 125 #define PCH_UART_MSR_DCTS       0x00000001
 126 #define PCH_UART_MSR_DDSR       0x00000002
 127 #define PCH_UART_MSR_TERI       0x00000004
 128 #define PCH_UART_MSR_DDCD       0x00000008
 129 #define PCH_UART_MSR_CTS        0x00000010
 130 #define PCH_UART_MSR_DSR        0x00000020
 131 #define PCH_UART_MSR_RI         0x00000040
 132 #define PCH_UART_MSR_DCD        0x00000080
 133 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 134                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 135
 136 #define PCH_UART_DLL            0x00
 137 #define PCH_UART_DLM            0x01
 138
 139 #define DIV_ROUND(a, b) (((a) + ((b)/2)) / (b))
 140
 141 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 142 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 143 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 144 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 145 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 146
 147 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 148 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 149 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 150 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 151 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 152 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 153 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 154 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 155 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 156 #define PCH_UART_HAL_STB1               0
 157 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 158
 159 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 160 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 161 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 162                                         PCH_UART_HAL_CLR_RX_FIFO)
 163
 164 #define PCH_UART_HAL_DMA_MODE0          0
 165 #define PCH_UART_HAL_FIFO_DIS           0
 166 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 167 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 168                                         PCH_UART_FCR_FIFO256)
 169 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 170 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 171 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 172 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 173 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 174 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 175 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 176 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 177 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 178 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 179 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 180 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 181 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 182 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 183
 184 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 185 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 186 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 187 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 188 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 189
 190 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 191 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 192 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 193 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 194 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 195
 196 #define PCI_VENDOR_ID_ROHM              0x10DB
 197
 198 struct pch_uart_buffer {
 199         unsigned char *buf;
 200         int size;
 201 };
 202
 203 struct eg20t_port {
 204         struct uart_port port;
 205         int port_type;
 206         void __iomem *membase;
 207         resource_size_t mapbase;
 208         unsigned int iobase;
 209         struct pci_dev *pdev;
 210         int fifo_size;
 211         int base_baud;
 212         int start_tx;
 213         int start_rx;
 214         int tx_empty;
 215         int int_dis_flag;
 216         int trigger;
 217         int trigger_level;
 218         struct pch_uart_buffer rxbuf;
 219         unsigned int dmsr;
 220         unsigned int fcr;
 221         unsigned int mcr;
 222         unsigned int use_dma;
 223         unsigned int use_dma_flag;
 224         struct dma_async_tx_descriptor  *desc_tx;
 225         struct dma_async_tx_descriptor  *desc_rx;
 226         struct pch_dma_slave            param_tx;
 227         struct pch_dma_slave            param_rx;
 228         struct dma_chan                 *chan_tx;
 229         struct dma_chan                 *chan_rx;
 230         struct scatterlist              *sg_tx_p;
 231         int                             nent;
 232         struct scatterlist              sg_rx;
 233         int                             tx_dma_use;
 234         void                            *rx_buf_virt;
 235         dma_addr_t                      rx_buf_dma;
 236 };
 237
 238 /**
 239  * struct pch_uart_driver_data - private data structure for UART-DMA
 240  * @port_type:                  The number of DMA channel
 241  * @line_no:                    UART port line number (0, 1, 2...)
 242  */
 243 struct pch_uart_driver_data {
 244         int port_type;
 245         int line_no;
 246 };
 247
 248 enum pch_uart_num_t {
 249         pch_et20t_uart0 = 0,
 250         pch_et20t_uart1,
 251         pch_et20t_uart2,
 252         pch_et20t_uart3,
 253         pch_ml7213_uart0,
 254         pch_ml7213_uart1,
 255         pch_ml7213_uart2,
 256 };
 257
 258 static struct pch_uart_driver_data drv_dat[] = {
 259         [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
 260         [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
 261         [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
 262         [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
 263         [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
 264         [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
 265         [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
 266 };
 267
 268 static unsigned int default_baud = 9600;
 269 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 270 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 271 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 272 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 273
 274 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
 275                                  int base_baud)
 276 {
 277         struct eg20t_port *priv = pci_get_drvdata(pdev);
 278
 279         priv->trigger_level = 1;
 280         priv->fcr = 0;
 281 }
 282
 283 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
 284 {
 285         unsigned int msr = ioread8(base + UART_MSR);
 286         priv->dmsr |= msr & PCH_UART_MSR_DELTA;
 287
 288         return msr;
 289 }
 290
 291 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 292                                           unsigned int flag)
 293 {
 294         u8 ier = ioread8(priv->membase + UART_IER);
 295         ier |= flag & PCH_UART_IER_MASK;
 296         iowrite8(ier, priv->membase + UART_IER);
 297 }
 298
 299 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 300                                            unsigned int flag)
 301 {
 302         u8 ier = ioread8(priv->membase + UART_IER);
 303         ier &= ~(flag & PCH_UART_IER_MASK);
 304         iowrite8(ier, priv->membase + UART_IER);
 305 }
 306
 307 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
 308                                  unsigned int parity, unsigned int bits,
 309                                  unsigned int stb)
 310 {
 311         unsigned int dll, dlm, lcr;
 312         int div;
 313
 314         div = DIV_ROUND(priv->base_baud / 16, baud);
 315         if (div < 0 || USHRT_MAX <= div) {
 316                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 317                 return -EINVAL;
 318         }
 319
 320         dll = (unsigned int)div & 0x00FFU;
 321         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 322
 323         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 324                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 325                 return -EINVAL;
 326         }
 327
 328         if (bits & ~PCH_UART_LCR_WLS) {
 329                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 330                 return -EINVAL;
 331         }
 332
 333         if (stb & ~PCH_UART_LCR_STB) {
 334                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 335                 return -EINVAL;
 336         }
 337
 338         lcr = parity;
 339         lcr |= bits;
 340         lcr |= stb;
 341
 342         dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
 343                  __func__, baud, div, lcr, jiffies);
 344         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 345         iowrite8(dll, priv->membase + PCH_UART_DLL);
 346         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 347         iowrite8(lcr, priv->membase + UART_LCR);
 348
 349         return 0;
 350 }
 351
 352 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 353                                     unsigned int flag)
 354 {
 355         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 356                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 357                         __func__, flag);
 358                 return -EINVAL;
 359         }
 360
 361         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 362         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 363                  priv->membase + UART_FCR);
 364         iowrite8(priv->fcr, priv->membase + UART_FCR);
 365
 366         return 0;
 367 }
 368
 369 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 370                                  unsigned int dmamode,
 371                                  unsigned int fifo_size, unsigned int trigger)
 372 {
 373         u8 fcr;
 374
 375         if (dmamode & ~PCH_UART_FCR_DMS) {
 376                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 377                         __func__, dmamode);
 378                 return -EINVAL;
 379         }
 380
 381         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 382                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 383                         __func__, fifo_size);
 384                 return -EINVAL;
 385         }
 386
 387         if (trigger & ~PCH_UART_FCR_RFTL) {
 388                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 389                         __func__, trigger);
 390                 return -EINVAL;
 391         }
 392
 393         switch (priv->fifo_size) {
 394         case 256:
 395                 priv->trigger_level =
 396                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 397                 break;
 398         case 64:
 399                 priv->trigger_level =
 400                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 401                 break;
 402         case 16:
 403                 priv->trigger_level =
 404                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 405                 break;
 406         default:
 407                 priv->trigger_level =
 408                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 409                 break;
 410         }
 411         fcr =
 412             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 413         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 414         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 415                  priv->membase + UART_FCR);
 416         iowrite8(fcr, priv->membase + UART_FCR);
 417         priv->fcr = fcr;
 418
 419         return 0;
 420 }
 421
 422 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 423 {
 424         priv->dmsr = 0;
 425         return get_msr(priv, priv->membase);
 426 }
 427
 428 static void pch_uart_hal_write(struct eg20t_port *priv,
 429                               const unsigned char *buf, int tx_size)
 430 {
 431         int i;
 432         unsigned int thr;
 433
 434         for (i = 0; i < tx_size;) {
 435                 thr = buf[i++];
 436                 iowrite8(thr, priv->membase + PCH_UART_THR);
 437         }
 438 }
 439
 440 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 441                              int rx_size)
 442 {
 443         int i;
 444         u8 rbr, lsr;
 445
 446         lsr = ioread8(priv->membase + UART_LSR);
 447         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 448              i < rx_size && lsr & UART_LSR_DR;
 449              lsr = ioread8(priv->membase + UART_LSR)) {
 450                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 451                 buf[i++] = rbr;
 452         }
 453         return i;
 454 }
 455
 456 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
 457 {
 458         unsigned int iir;
 459         int ret;
 460
 461         iir = ioread8(priv->membase + UART_IIR);
 462         ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
 463         return ret;
 464 }
 465
 466 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 467 {
 468         return ioread8(priv->membase + UART_LSR);
 469 }
 470
 471 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 472 {
 473         unsigned int lcr;
 474
 475         lcr = ioread8(priv->membase + UART_LCR);
 476         if (on)
 477                 lcr |= PCH_UART_LCR_SB;
 478         else
 479                 lcr &= ~PCH_UART_LCR_SB;
 480
 481         iowrite8(lcr, priv->membase + UART_LCR);
 482 }
 483
 484 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 485                    int size)
 486 {
 487         struct uart_port *port;
 488         struct tty_struct *tty;
 489
 490         port = &priv->port;
 491         tty = tty_port_tty_get(&port->state->port);
 492         if (!tty) {
 493                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 494                 return -EBUSY;
 495         }
 496
 497         tty_insert_flip_string(tty, buf, size);
 498         tty_flip_buffer_push(tty);
 499         tty_kref_put(tty);
 500
 501         return 0;
 502 }
 503
 504 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 505 {
 506         int ret;
 507         struct uart_port *port = &priv->port;
 508
 509         if (port->x_char) {
 510                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 511                         __func__, port->x_char, jiffies);
 512                 buf[0] = port->x_char;
 513                 port->x_char = 0;
 514                 ret = 1;
 515         } else {
 516                 ret = 0;
 517         }
 518
 519         return ret;
 520 }
 521
 522 static int dma_push_rx(struct eg20t_port *priv, int size)
 523 {
 524         struct tty_struct *tty;
 525         int room;
 526         struct uart_port *port = &priv->port;
 527
 528         port = &priv->port;
 529         tty = tty_port_tty_get(&port->state->port);
 530         if (!tty) {
 531                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 532                 return 0;
 533         }
 534
 535         room = tty_buffer_request_room(tty, size);
 536
 537         if (room < size)
 538                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 539                          size - room);
 540         if (!room)
 541                 return room;
 542
 543         tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
 544
 545         port->icount.rx += room;
 546         tty_kref_put(tty);
 547
 548         return room;
 549 }
 550
 551 static void pch_free_dma(struct uart_port *port)
 552 {
 553         struct eg20t_port *priv;
 554         priv = container_of(port, struct eg20t_port, port);
 555
 556         if (priv->chan_tx) {
 557                 dma_release_channel(priv->chan_tx);
 558                 priv->chan_tx = NULL;
 559         }
 560         if (priv->chan_rx) {
 561                 dma_release_channel(priv->chan_rx);
 562                 priv->chan_rx = NULL;
 563         }
 564         if (sg_dma_address(&priv->sg_rx))
 565                 dma_free_coherent(port->dev, port->fifosize,
 566                                   sg_virt(&priv->sg_rx),
 567                                   sg_dma_address(&priv->sg_rx));
 568
 569         return;
 570 }
 571
 572 static bool filter(struct dma_chan *chan, void *slave)
 573 {
 574         struct pch_dma_slave *param = slave;
 575
 576         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 577                                                   chan->device->dev)) {
 578                 chan->private = param;
 579                 return true;
 580         } else {
 581                 return false;
 582         }
 583 }
 584
 585 static void pch_request_dma(struct uart_port *port)
 586 {
 587         dma_cap_mask_t mask;
 588         struct dma_chan *chan;
 589         struct pci_dev *dma_dev;
 590         struct pch_dma_slave *param;
 591         struct eg20t_port *priv =
 592                                 container_of(port, struct eg20t_port, port);
 593         dma_cap_zero(mask);
 594         dma_cap_set(DMA_SLAVE, mask);
 595
 596         dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(0xa, 0)); /* Get DMA's dev
 597                                                                 information */
 598         /* Set Tx DMA */
 599         param = &priv->param_tx;
 600         param->dma_dev = &dma_dev->dev;
 601         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 602
 603         param->tx_reg = port->mapbase + UART_TX;
 604         chan = dma_request_channel(mask, filter, param);
 605         if (!chan) {
 606                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 607                         __func__);
 608                 return;
 609         }
 610         priv->chan_tx = chan;
 611
 612         /* Set Rx DMA */
 613         param = &priv->param_rx;
 614         param->dma_dev = &dma_dev->dev;
 615         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 616
 617         param->rx_reg = port->mapbase + UART_RX;
 618         chan = dma_request_channel(mask, filter, param);
 619         if (!chan) {
 620                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 621                         __func__);
 622                 dma_release_channel(priv->chan_tx);
 623                 return;
 624         }
 625
 626         /* Get Consistent memory for DMA */
 627         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 628                                     &priv->rx_buf_dma, GFP_KERNEL);
 629         priv->chan_rx = chan;
 630 }
 631
 632 static void pch_dma_rx_complete(void *arg)
 633 {
 634         struct eg20t_port *priv = arg;
 635         struct uart_port *port = &priv->port;
 636         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
 637         int count;
 638
 639         if (!tty) {
 640                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 641                 return;
 642         }
 643
 644         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 645         count = dma_push_rx(priv, priv->trigger_level);
 646         if (count)
 647                 tty_flip_buffer_push(tty);
 648         tty_kref_put(tty);
 649         async_tx_ack(priv->desc_rx);
 650         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
 651 }
 652
 653 static void pch_dma_tx_complete(void *arg)
 654 {
 655         struct eg20t_port *priv = arg;
 656         struct uart_port *port = &priv->port;
 657         struct circ_buf *xmit = &port->state->xmit;
 658         struct scatterlist *sg = priv->sg_tx_p;
 659         int i;
 660
 661         for (i = 0; i < priv->nent; i++, sg++) {
 662                 xmit->tail += sg_dma_len(sg);
 663                 port->icount.tx += sg_dma_len(sg);
 664         }
 665         xmit->tail &= UART_XMIT_SIZE - 1;
 666         async_tx_ack(priv->desc_tx);
 667         dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
 668         priv->tx_dma_use = 0;
 669         priv->nent = 0;
 670         kfree(priv->sg_tx_p);
 671         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 672 }
 673
 674 static int pop_tx(struct eg20t_port *priv, int size)
 675 {
 676         int count = 0;
 677         struct uart_port *port = &priv->port;
 678         struct circ_buf *xmit = &port->state->xmit;
 679
 680         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 681                 goto pop_tx_end;
 682
 683         do {
 684                 int cnt_to_end =
 685                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 686                 int sz = min(size - count, cnt_to_end);
 687                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 688                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 689                 count += sz;
 690         } while (!uart_circ_empty(xmit) && count < size);
 691
 692 pop_tx_end:
 693         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 694                  count, size - count, jiffies);
 695
 696         return count;
 697 }
 698
 699 static int handle_rx_to(struct eg20t_port *priv)
 700 {
 701         struct pch_uart_buffer *buf;
 702         int rx_size;
 703         int ret;
 704         if (!priv->start_rx) {
 705                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
 706                 return 0;
 707         }
 708         buf = &priv->rxbuf;
 709         do {
 710                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 711                 ret = push_rx(priv, buf->buf, rx_size);
 712                 if (ret)
 713                         return 0;
 714         } while (rx_size == buf->size);
 715
 716         return PCH_UART_HANDLED_RX_INT;
 717 }
 718
 719 static int handle_rx(struct eg20t_port *priv)
 720 {
 721         return handle_rx_to(priv);
 722 }
 723
 724 static int dma_handle_rx(struct eg20t_port *priv)
 725 {
 726         struct uart_port *port = &priv->port;
 727         struct dma_async_tx_descriptor *desc;
 728         struct scatterlist *sg;
 729
 730         priv = container_of(port, struct eg20t_port, port);
 731         sg = &priv->sg_rx;
 732
 733         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 734
 735         sg_dma_len(sg) = priv->trigger_level;
 736
 737         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 738                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
 739                      ~PAGE_MASK);
 740
 741         sg_dma_address(sg) = priv->rx_buf_dma;
 742
 743         desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
 744                         sg, 1, DMA_FROM_DEVICE,
 745                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 746
 747         if (!desc)
 748                 return 0;
 749
 750         priv->desc_rx = desc;
 751         desc->callback = pch_dma_rx_complete;
 752         desc->callback_param = priv;
 753         desc->tx_submit(desc);
 754         dma_async_issue_pending(priv->chan_rx);
 755
 756         return PCH_UART_HANDLED_RX_INT;
 757 }
 758
 759 static unsigned int handle_tx(struct eg20t_port *priv)
 760 {
 761         struct uart_port *port = &priv->port;
 762         struct circ_buf *xmit = &port->state->xmit;
 763         int fifo_size;
 764         int tx_size;
 765         int size;
 766         int tx_empty;
 767
 768         if (!priv->start_tx) {
 769                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 770                         __func__, jiffies);
 771                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 772                 priv->tx_empty = 1;
 773                 return 0;
 774         }
 775
 776         fifo_size = max(priv->fifo_size, 1);
 777         tx_empty = 1;
 778         if (pop_tx_x(priv, xmit->buf)) {
 779                 pch_uart_hal_write(priv, xmit->buf, 1);
 780                 port->icount.tx++;
 781                 tx_empty = 0;
 782                 fifo_size--;
 783         }
 784         size = min(xmit->head - xmit->tail, fifo_size);
 785         if (size < 0)
 786                 size = fifo_size;
 787
 788         tx_size = pop_tx(priv, size);
 789         if (tx_size > 0) {
 790                 port->icount.tx += tx_size;
 791                 tx_empty = 0;
 792         }
 793
 794         priv->tx_empty = tx_empty;
 795
 796         if (tx_empty) {
 797                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 798                 uart_write_wakeup(port);
 799         }
 800
 801         return PCH_UART_HANDLED_TX_INT;
 802 }
 803
 804 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 805 {
 806         struct uart_port *port = &priv->port;
 807         struct circ_buf *xmit = &port->state->xmit;
 808         struct scatterlist *sg;
 809         int nent;
 810         int fifo_size;
 811         int tx_empty;
 812         struct dma_async_tx_descriptor *desc;
 813         int num;
 814         int i;
 815         int bytes;
 816         int size;
 817         int rem;
 818
 819         if (!priv->start_tx) {
 820                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 821                         __func__, jiffies);
 822                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 823                 priv->tx_empty = 1;
 824                 return 0;
 825         }
 826
 827         if (priv->tx_dma_use) {
 828                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 829                         __func__, jiffies);
 830                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 831                 priv->tx_empty = 1;
 832                 return 0;
 833         }
 834
 835         fifo_size = max(priv->fifo_size, 1);
 836         tx_empty = 1;
 837         if (pop_tx_x(priv, xmit->buf)) {
 838                 pch_uart_hal_write(priv, xmit->buf, 1);
 839                 port->icount.tx++;
 840                 tx_empty = 0;
 841                 fifo_size--;
 842         }
 843
 844         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 845                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 846                              xmit->tail, UART_XMIT_SIZE));
 847         if (!bytes) {
 848                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 849                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 850                 uart_write_wakeup(port);
 851                 return 0;
 852         }
 853
 854         if (bytes > fifo_size) {
 855                 num = bytes / fifo_size + 1;
 856                 size = fifo_size;
 857                 rem = bytes % fifo_size;
 858         } else {
 859                 num = 1;
 860                 size = bytes;
 861                 rem = bytes;
 862         }
 863
 864         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
 865                 __func__, num, size, rem);
 866
 867         priv->tx_dma_use = 1;
 868
 869         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
 870
 871         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
 872         sg = priv->sg_tx_p;
 873
 874         for (i = 0; i < num; i++, sg++) {
 875                 if (i == (num - 1))
 876                         sg_set_page(sg, virt_to_page(xmit->buf),
 877                                     rem, fifo_size * i);
 878                 else
 879                         sg_set_page(sg, virt_to_page(xmit->buf),
 880                                     size, fifo_size * i);
 881         }
 882
 883         sg = priv->sg_tx_p;
 884         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
 885         if (!nent) {
 886                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
 887                 return 0;
 888         }
 889         priv->nent = nent;
 890
 891         for (i = 0; i < nent; i++, sg++) {
 892                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
 893                               fifo_size * i;
 894                 sg_dma_address(sg) = (sg_dma_address(sg) &
 895                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
 896                 if (i == (nent - 1))
 897                         sg_dma_len(sg) = rem;
 898                 else
 899                         sg_dma_len(sg) = size;
 900         }
 901
 902         desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
 903                                         priv->sg_tx_p, nent, DMA_TO_DEVICE,
 904                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 905         if (!desc) {
 906                 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
 907                         __func__);
 908                 return 0;
 909         }
 910         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
 911         priv->desc_tx = desc;
 912         desc->callback = pch_dma_tx_complete;
 913         desc->callback_param = priv;
 914
 915         desc->tx_submit(desc);
 916
 917         dma_async_issue_pending(priv->chan_tx);
 918
 919         return PCH_UART_HANDLED_TX_INT;
 920 }
 921
 922 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
 923 {
 924         u8 fcr = ioread8(priv->membase + UART_FCR);
 925
 926         /* Reset FIFO */
 927         fcr |= UART_FCR_CLEAR_RCVR;
 928         iowrite8(fcr, priv->membase + UART_FCR);
 929
 930         if (lsr & PCH_UART_LSR_ERR)
 931                 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
 932
 933         if (lsr & UART_LSR_FE)
 934                 dev_err(&priv->pdev->dev, "Framing Error\n");
 935
 936         if (lsr & UART_LSR_PE)
 937                 dev_err(&priv->pdev->dev, "Parity Error\n");
 938
 939         if (lsr & UART_LSR_OE)
 940                 dev_err(&priv->pdev->dev, "Overrun Error\n");
 941 }
 942
 943 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
 944 {
 945         struct eg20t_port *priv = dev_id;
 946         unsigned int handled;
 947         u8 lsr;
 948         int ret = 0;
 949         unsigned int iid;
 950         unsigned long flags;
 951
 952         spin_lock_irqsave(&priv->port.lock, flags);
 953         handled = 0;
 954         while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
 955                 switch (iid) {
 956                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
 957                         lsr = pch_uart_hal_get_line_status(priv);
 958                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
 959                                                 UART_LSR_PE | UART_LSR_OE)) {
 960                                 pch_uart_err_ir(priv, lsr);
 961                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
 962                         }
 963                         break;
 964                 case PCH_UART_IID_RDR:  /* Received Data Ready */
 965                         if (priv->use_dma) {
 966                                 pch_uart_hal_disable_interrupt(priv,
 967                                                         PCH_UART_HAL_RX_INT);
 968                                 ret = dma_handle_rx(priv);
 969                                 if (!ret)
 970                                         pch_uart_hal_enable_interrupt(priv,
 971                                                         PCH_UART_HAL_RX_INT);
 972                         } else {
 973                                 ret = handle_rx(priv);
 974                         }
 975                         break;
 976                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
 977                                                    (FIFO Timeout) */
 978                         ret = handle_rx_to(priv);
 979                         break;
 980                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
 981                                                    Empty */
 982                         if (priv->use_dma)
 983                                 ret = dma_handle_tx(priv);
 984                         else
 985                                 ret = handle_tx(priv);
 986                         break;
 987                 case PCH_UART_IID_MS:   /* Modem Status */
 988                         ret = PCH_UART_HANDLED_MS_INT;
 989                         break;
 990                 default:        /* Never junp to this label */
 991                         dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
 992                                 iid, jiffies);
 993                         ret = -1;
 994                         break;
 995                 }
 996                 handled |= (unsigned int)ret;
 997         }
 998         if (handled == 0 && iid <= 1) {
 999                 if (priv->int_dis_flag)
1000                         priv->int_dis_flag = 0;
1001         }
1002
1003         spin_unlock_irqrestore(&priv->port.lock, flags);
1004         return IRQ_RETVAL(handled);
1005 }
1006
1007 /* This function tests whether the transmitter fifo and shifter for the port
1008                                                 described by 'port' is empty. */
1009 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1010 {
1011         struct eg20t_port *priv;
1012         int ret;
1013         priv = container_of(port, struct eg20t_port, port);
1014         if (priv->tx_empty)
1015                 ret = TIOCSER_TEMT;
1016         else
1017                 ret = 0;
1018
1019         return ret;
1020 }
1021
1022 /* Returns the current state of modem control inputs. */
1023 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1024 {
1025         struct eg20t_port *priv;
1026         u8 modem;
1027         unsigned int ret = 0;
1028
1029         priv = container_of(port, struct eg20t_port, port);
1030         modem = pch_uart_hal_get_modem(priv);
1031
1032         if (modem & UART_MSR_DCD)
1033                 ret |= TIOCM_CAR;
1034
1035         if (modem & UART_MSR_RI)
1036                 ret |= TIOCM_RNG;
1037
1038         if (modem & UART_MSR_DSR)
1039                 ret |= TIOCM_DSR;
1040
1041         if (modem & UART_MSR_CTS)
1042                 ret |= TIOCM_CTS;
1043
1044         return ret;
1045 }
1046
1047 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1048 {
1049         u32 mcr = 0;
1050         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1051
1052         if (mctrl & TIOCM_DTR)
1053                 mcr |= UART_MCR_DTR;
1054         if (mctrl & TIOCM_RTS)
1055                 mcr |= UART_MCR_RTS;
1056         if (mctrl & TIOCM_LOOP)
1057                 mcr |= UART_MCR_LOOP;
1058
1059         if (priv->mcr & UART_MCR_AFE)
1060                 mcr |= UART_MCR_AFE;
1061
1062         if (mctrl)
1063                 iowrite8(mcr, priv->membase + UART_MCR);
1064 }
1065
1066 static void pch_uart_stop_tx(struct uart_port *port)
1067 {
1068         struct eg20t_port *priv;
1069         priv = container_of(port, struct eg20t_port, port);
1070         priv->start_tx = 0;
1071         priv->tx_dma_use = 0;
1072 }
1073
1074 static void pch_uart_start_tx(struct uart_port *port)
1075 {
1076         struct eg20t_port *priv;
1077
1078         priv = container_of(port, struct eg20t_port, port);
1079
1080         if (priv->use_dma) {
1081                 if (priv->tx_dma_use) {
1082                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1083                                 __func__);
1084                         return;
1085                 }
1086         }
1087
1088         priv->start_tx = 1;
1089         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1090 }
1091
1092 static void pch_uart_stop_rx(struct uart_port *port)
1093 {
1094         struct eg20t_port *priv;
1095         priv = container_of(port, struct eg20t_port, port);
1096         priv->start_rx = 0;
1097         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
1098         priv->int_dis_flag = 1;
1099 }
1100
1101 /* Enable the modem status interrupts. */
1102 static void pch_uart_enable_ms(struct uart_port *port)
1103 {
1104         struct eg20t_port *priv;
1105         priv = container_of(port, struct eg20t_port, port);
1106         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1107 }
1108
1109 /* Control the transmission of a break signal. */
1110 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1111 {
1112         struct eg20t_port *priv;
1113         unsigned long flags;
1114
1115         priv = container_of(port, struct eg20t_port, port);
1116         spin_lock_irqsave(&port->lock, flags);
1117         pch_uart_hal_set_break(priv, ctl);
1118         spin_unlock_irqrestore(&port->lock, flags);
1119 }
1120
1121 /* Grab any interrupt resources and initialise any low level driver state. */
1122 static int pch_uart_startup(struct uart_port *port)
1123 {
1124         struct eg20t_port *priv;
1125         int ret;
1126         int fifo_size;
1127         int trigger_level;
1128
1129         priv = container_of(port, struct eg20t_port, port);
1130         priv->tx_empty = 1;
1131
1132         if (port->uartclk)
1133                 priv->base_baud = port->uartclk;
1134         else
1135                 port->uartclk = priv->base_baud;
1136
1137         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1138         ret = pch_uart_hal_set_line(priv, default_baud,
1139                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1140                               PCH_UART_HAL_STB1);
1141         if (ret)
1142                 return ret;
1143
1144         switch (priv->fifo_size) {
1145         case 256:
1146                 fifo_size = PCH_UART_HAL_FIFO256;
1147                 break;
1148         case 64:
1149                 fifo_size = PCH_UART_HAL_FIFO64;
1150                 break;
1151         case 16:
1152                 fifo_size = PCH_UART_HAL_FIFO16;
1153         case 1:
1154         default:
1155                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1156                 break;
1157         }
1158
1159         switch (priv->trigger) {
1160         case PCH_UART_HAL_TRIGGER1:
1161                 trigger_level = 1;
1162                 break;
1163         case PCH_UART_HAL_TRIGGER_L:
1164                 trigger_level = priv->fifo_size / 4;
1165                 break;
1166         case PCH_UART_HAL_TRIGGER_M:
1167                 trigger_level = priv->fifo_size / 2;
1168                 break;
1169         case PCH_UART_HAL_TRIGGER_H:
1170         default:
1171                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1172                 break;
1173         }
1174
1175         priv->trigger_level = trigger_level;
1176         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1177                                     fifo_size, priv->trigger);
1178         if (ret < 0)
1179                 return ret;
1180
1181         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1182                         KBUILD_MODNAME, priv);
1183         if (ret < 0)
1184                 return ret;
1185
1186         if (priv->use_dma)
1187                 pch_request_dma(port);
1188
1189         priv->start_rx = 1;
1190         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1191         uart_update_timeout(port, CS8, default_baud);
1192
1193         return 0;
1194 }
1195
1196 static void pch_uart_shutdown(struct uart_port *port)
1197 {
1198         struct eg20t_port *priv;
1199         int ret;
1200
1201         priv = container_of(port, struct eg20t_port, port);
1202         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1203         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1204         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1205                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1206         if (ret)
1207                 dev_err(priv->port.dev,
1208                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1209
1210         if (priv->use_dma_flag)
1211                 pch_free_dma(port);
1212
1213         free_irq(priv->port.irq, priv);
1214 }
1215
1216 /* Change the port parameters, including word length, parity, stop
1217  *bits.  Update read_status_mask and ignore_status_mask to indicate
1218  *the types of events we are interested in receiving.  */
1219 static void pch_uart_set_termios(struct uart_port *port,
1220                                  struct ktermios *termios, struct ktermios *old)
1221 {
1222         int baud;
1223         int rtn;
1224         unsigned int parity, bits, stb;
1225         struct eg20t_port *priv;
1226         unsigned long flags;
1227
1228         priv = container_of(port, struct eg20t_port, port);
1229         switch (termios->c_cflag & CSIZE) {
1230         case CS5:
1231                 bits = PCH_UART_HAL_5BIT;
1232                 break;
1233         case CS6:
1234                 bits = PCH_UART_HAL_6BIT;
1235                 break;
1236         case CS7:
1237                 bits = PCH_UART_HAL_7BIT;
1238                 break;
1239         default:                /* CS8 */
1240                 bits = PCH_UART_HAL_8BIT;
1241                 break;
1242         }
1243         if (termios->c_cflag & CSTOPB)
1244                 stb = PCH_UART_HAL_STB2;
1245         else
1246                 stb = PCH_UART_HAL_STB1;
1247
1248         if (termios->c_cflag & PARENB) {
1249                 if (!(termios->c_cflag & PARODD))
1250                         parity = PCH_UART_HAL_PARITY_ODD;
1251                 else
1252                         parity = PCH_UART_HAL_PARITY_EVEN;
1253
1254         } else {
1255                 parity = PCH_UART_HAL_PARITY_NONE;
1256         }
1257
1258         /* Only UART0 has auto hardware flow function */
1259         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1260                 priv->mcr |= UART_MCR_AFE;
1261         else
1262                 priv->mcr &= ~UART_MCR_AFE;
1263
1264         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1265
1266         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1267
1268         spin_lock_irqsave(&port->lock, flags);
1269
1270         uart_update_timeout(port, termios->c_cflag, baud);
1271         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1272         if (rtn)
1273                 goto out;
1274
1275         /* Don't rewrite B0 */
1276         if (tty_termios_baud_rate(termios))
1277                 tty_termios_encode_baud_rate(termios, baud, baud);
1278
1279 out:
1280         spin_unlock_irqrestore(&port->lock, flags);
1281 }
1282
1283 static const char *pch_uart_type(struct uart_port *port)
1284 {
1285         return KBUILD_MODNAME;
1286 }
1287
1288 static void pch_uart_release_port(struct uart_port *port)
1289 {
1290         struct eg20t_port *priv;
1291
1292         priv = container_of(port, struct eg20t_port, port);
1293         pci_iounmap(priv->pdev, priv->membase);
1294         pci_release_regions(priv->pdev);
1295 }
1296
1297 static int pch_uart_request_port(struct uart_port *port)
1298 {
1299         struct eg20t_port *priv;
1300         int ret;
1301         void __iomem *membase;
1302
1303         priv = container_of(port, struct eg20t_port, port);
1304         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1305         if (ret < 0)
1306                 return -EBUSY;
1307
1308         membase = pci_iomap(priv->pdev, 1, 0);
1309         if (!membase) {
1310                 pci_release_regions(priv->pdev);
1311                 return -EBUSY;
1312         }
1313         priv->membase = port->membase = membase;
1314
1315         return 0;
1316 }
1317
1318 static void pch_uart_config_port(struct uart_port *port, int type)
1319 {
1320         struct eg20t_port *priv;
1321
1322         priv = container_of(port, struct eg20t_port, port);
1323         if (type & UART_CONFIG_TYPE) {
1324                 port->type = priv->port_type;
1325                 pch_uart_request_port(port);
1326         }
1327 }
1328
1329 static int pch_uart_verify_port(struct uart_port *port,
1330                                 struct serial_struct *serinfo)
1331 {
1332         struct eg20t_port *priv;
1333
1334         priv = container_of(port, struct eg20t_port, port);
1335         if (serinfo->flags & UPF_LOW_LATENCY) {
1336                 dev_info(priv->port.dev,
1337                         "PCH UART : Use PIO Mode (without DMA)\n");
1338                 priv->use_dma = 0;
1339                 serinfo->flags &= ~UPF_LOW_LATENCY;
1340         } else {
1341 #ifndef CONFIG_PCH_DMA
1342                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1343                         __func__);
1344                 return -EOPNOTSUPP;
1345 #endif
1346                 priv->use_dma = 1;
1347                 priv->use_dma_flag = 1;
1348                 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1349         }
1350
1351         return 0;
1352 }
1353
1354 static struct uart_ops pch_uart_ops = {
1355         .tx_empty = pch_uart_tx_empty,
1356         .set_mctrl = pch_uart_set_mctrl,
1357         .get_mctrl = pch_uart_get_mctrl,
1358         .stop_tx = pch_uart_stop_tx,
1359         .start_tx = pch_uart_start_tx,
1360         .stop_rx = pch_uart_stop_rx,
1361         .enable_ms = pch_uart_enable_ms,
1362         .break_ctl = pch_uart_break_ctl,
1363         .startup = pch_uart_startup,
1364         .shutdown = pch_uart_shutdown,
1365         .set_termios = pch_uart_set_termios,
1366 /*      .pm             = pch_uart_pm,          Not supported yet */
1367 /*      .set_wake       = pch_uart_set_wake,    Not supported yet */
1368         .type = pch_uart_type,
1369         .release_port = pch_uart_release_port,
1370         .request_port = pch_uart_request_port,
1371         .config_port = pch_uart_config_port,
1372         .verify_port = pch_uart_verify_port
1373 };
1374
1375 static struct uart_driver pch_uart_driver = {
1376         .owner = THIS_MODULE,
1377         .driver_name = KBUILD_MODNAME,
1378         .dev_name = PCH_UART_DRIVER_DEVICE,
1379         .major = 0,
1380         .minor = 0,
1381         .nr = PCH_UART_NR,
1382 };
1383
1384 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1385                                              const struct pci_device_id *id)
1386 {
1387         struct eg20t_port *priv;
1388         int ret;
1389         unsigned int iobase;
1390         unsigned int mapbase;
1391         unsigned char *rxbuf;
1392         int fifosize, base_baud;
1393         int port_type;
1394         struct pch_uart_driver_data *board;
1395
1396         board = &drv_dat[id->driver_data];
1397         port_type = board->port_type;
1398
1399         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1400         if (priv == NULL)
1401                 goto init_port_alloc_err;
1402
1403         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1404         if (!rxbuf)
1405                 goto init_port_free_txbuf;
1406
1407         base_baud = 1843200; /* 1.8432MHz */
1408
1409         /* quirk for CM-iTC board */
1410         if (strstr(dmi_get_system_info(DMI_BOARD_NAME), "CM-iTC"))
1411                 base_baud = 192000000; /* 192.0MHz */
1412
1413         switch (port_type) {
1414         case PORT_UNKNOWN:
1415                 fifosize = 256; /* EG20T/ML7213: UART0 */
1416                 break;
1417         case PORT_8250:
1418                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1419                 break;
1420         default:
1421                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1422                 goto init_port_hal_free;
1423         }
1424
1425         iobase = pci_resource_start(pdev, 0);
1426         mapbase = pci_resource_start(pdev, 1);
1427         priv->mapbase = mapbase;
1428         priv->iobase = iobase;
1429         priv->pdev = pdev;
1430         priv->tx_empty = 1;
1431         priv->rxbuf.buf = rxbuf;
1432         priv->rxbuf.size = PAGE_SIZE;
1433
1434         priv->fifo_size = fifosize;
1435         priv->base_baud = base_baud;
1436         priv->port_type = PORT_MAX_8250 + port_type + 1;
1437         priv->port.dev = &pdev->dev;
1438         priv->port.iobase = iobase;
1439         priv->port.membase = NULL;
1440         priv->port.mapbase = mapbase;
1441         priv->port.irq = pdev->irq;
1442         priv->port.iotype = UPIO_PORT;
1443         priv->port.ops = &pch_uart_ops;
1444         priv->port.flags = UPF_BOOT_AUTOCONF;
1445         priv->port.fifosize = fifosize;
1446         priv->port.line = board->line_no;
1447         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1448
1449         spin_lock_init(&priv->port.lock);
1450
1451         pci_set_drvdata(pdev, priv);
1452         pch_uart_hal_request(pdev, fifosize, base_baud);
1453
1454         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1455         if (ret < 0)
1456                 goto init_port_hal_free;
1457
1458         return priv;
1459
1460 init_port_hal_free:
1461         free_page((unsigned long)rxbuf);
1462 init_port_free_txbuf:
1463         kfree(priv);
1464 init_port_alloc_err:
1465
1466         return NULL;
1467 }
1468
1469 static void pch_uart_exit_port(struct eg20t_port *priv)
1470 {
1471         uart_remove_one_port(&pch_uart_driver, &priv->port);
1472         pci_set_drvdata(priv->pdev, NULL);
1473         free_page((unsigned long)priv->rxbuf.buf);
1474 }
1475
1476 static void pch_uart_pci_remove(struct pci_dev *pdev)
1477 {
1478         struct eg20t_port *priv;
1479
1480         priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1481         pch_uart_exit_port(priv);
1482         pci_disable_device(pdev);
1483         kfree(priv);
1484         return;
1485 }
1486 #ifdef CONFIG_PM
1487 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1488 {
1489         struct eg20t_port *priv = pci_get_drvdata(pdev);
1490
1491         uart_suspend_port(&pch_uart_driver, &priv->port);
1492
1493         pci_save_state(pdev);
1494         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1495         return 0;
1496 }
1497
1498 static int pch_uart_pci_resume(struct pci_dev *pdev)
1499 {
1500         struct eg20t_port *priv = pci_get_drvdata(pdev);
1501         int ret;
1502
1503         pci_set_power_state(pdev, PCI_D0);
1504         pci_restore_state(pdev);
1505
1506         ret = pci_enable_device(pdev);
1507         if (ret) {
1508                 dev_err(&pdev->dev,
1509                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1510                 return ret;
1511         }
1512
1513         uart_resume_port(&pch_uart_driver, &priv->port);
1514
1515         return 0;
1516 }
1517 #else
1518 #define pch_uart_pci_suspend NULL
1519 #define pch_uart_pci_resume NULL
1520 #endif
1521
1522 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1523         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1524          .driver_data = pch_et20t_uart0},
1525         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1526          .driver_data = pch_et20t_uart1},
1527         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1528          .driver_data = pch_et20t_uart2},
1529         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1530          .driver_data = pch_et20t_uart3},
1531         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1532          .driver_data = pch_ml7213_uart0},
1533         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1534          .driver_data = pch_ml7213_uart1},
1535         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1536          .driver_data = pch_ml7213_uart2},
1537         {0,},
1538 };
1539
1540 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1541                                         const struct pci_device_id *id)
1542 {
1543         int ret;
1544         struct eg20t_port *priv;
1545
1546         ret = pci_enable_device(pdev);
1547         if (ret < 0)
1548                 goto probe_error;
1549
1550         priv = pch_uart_init_port(pdev, id);
1551         if (!priv) {
1552                 ret = -EBUSY;
1553                 goto probe_disable_device;
1554         }
1555         pci_set_drvdata(pdev, priv);
1556
1557         return ret;
1558
1559 probe_disable_device:
1560         pci_disable_device(pdev);
1561 probe_error:
1562         return ret;
1563 }
1564
1565 static struct pci_driver pch_uart_pci_driver = {
1566         .name = "pch_uart",
1567         .id_table = pch_uart_pci_id,
1568         .probe = pch_uart_pci_probe,
1569         .remove = __devexit_p(pch_uart_pci_remove),
1570         .suspend = pch_uart_pci_suspend,
1571         .resume = pch_uart_pci_resume,
1572 };
1573
1574 static int __init pch_uart_module_init(void)
1575 {
1576         int ret;
1577
1578         /* register as UART driver */
1579         ret = uart_register_driver(&pch_uart_driver);
1580         if (ret < 0)
1581                 return ret;
1582
1583         /* register as PCI driver */
1584         ret = pci_register_driver(&pch_uart_pci_driver);
1585         if (ret < 0)
1586                 uart_unregister_driver(&pch_uart_driver);
1587
1588         return ret;
1589 }
1590 module_init(pch_uart_module_init);
1591
1592 static void __exit pch_uart_module_exit(void)
1593 {
1594         pci_unregister_driver(&pch_uart_pci_driver);
1595         uart_unregister_driver(&pch_uart_driver);
1596 }
1597 module_exit(pch_uart_module_exit);
1598
1599 MODULE_LICENSE("GPL v2");
1600 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1601 module_param(default_baud, uint, S_IRUGO);