2 * Driver for msm7k serial device and console
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 # define SUPPORT_SYSRQ
22 #include <linux/atomic.h>
23 #include <linux/hrtimer.h>
24 #include <linux/module.h>
26 #include <linux/ioport.h>
27 #include <linux/irq.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/clk.h>
35 #include <linux/platform_device.h>
36 #include <linux/delay.h>
38 #include <linux/of_device.h>
40 #include "msm_serial.h"
43 struct uart_port uart;
48 void __iomem *gsbi_base;
50 unsigned int old_snap_state;
53 static inline void wait_for_xmitr(struct uart_port *port)
55 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
56 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
60 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
63 static void msm_stop_tx(struct uart_port *port)
65 struct msm_port *msm_port = UART_TO_MSM(port);
67 msm_port->imr &= ~UART_IMR_TXLEV;
68 msm_write(port, msm_port->imr, UART_IMR);
71 static void msm_start_tx(struct uart_port *port)
73 struct msm_port *msm_port = UART_TO_MSM(port);
75 msm_port->imr |= UART_IMR_TXLEV;
76 msm_write(port, msm_port->imr, UART_IMR);
79 static void msm_stop_rx(struct uart_port *port)
81 struct msm_port *msm_port = UART_TO_MSM(port);
83 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
84 msm_write(port, msm_port->imr, UART_IMR);
87 static void msm_enable_ms(struct uart_port *port)
89 struct msm_port *msm_port = UART_TO_MSM(port);
91 msm_port->imr |= UART_IMR_DELTA_CTS;
92 msm_write(port, msm_port->imr, UART_IMR);
95 static void handle_rx_dm(struct uart_port *port, unsigned int misr)
97 struct tty_port *tport = &port->state->port;
100 struct msm_port *msm_port = UART_TO_MSM(port);
102 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
103 port->icount.overrun++;
104 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
105 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
108 if (misr & UART_IMR_RXSTALE) {
109 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
110 msm_port->old_snap_state;
111 msm_port->old_snap_state = 0;
113 count = 4 * (msm_read(port, UART_RFWR));
114 msm_port->old_snap_state += count;
117 /* TODO: Precise error reporting */
119 port->icount.rx += count;
124 sr = msm_read(port, UART_SR);
125 if ((sr & UART_SR_RX_READY) == 0) {
126 msm_port->old_snap_state -= count;
129 c = msm_read(port, UARTDM_RF);
130 if (sr & UART_SR_RX_BREAK) {
132 if (uart_handle_break(port))
134 } else if (sr & UART_SR_PAR_FRAME_ERR)
135 port->icount.frame++;
137 /* TODO: handle sysrq */
138 tty_insert_flip_string(tport, (char *)&c,
139 (count > 4) ? 4 : count);
143 tty_flip_buffer_push(tport);
144 if (misr & (UART_IMR_RXSTALE))
145 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
146 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
147 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
150 static void handle_rx(struct uart_port *port)
152 struct tty_port *tport = &port->state->port;
156 * Handle overrun. My understanding of the hardware is that overrun
157 * is not tied to the RX buffer, so we handle the case out of band.
159 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
160 port->icount.overrun++;
161 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
162 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
165 /* and now the main RX loop */
166 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
168 char flag = TTY_NORMAL;
170 c = msm_read(port, UART_RF);
172 if (sr & UART_SR_RX_BREAK) {
174 if (uart_handle_break(port))
176 } else if (sr & UART_SR_PAR_FRAME_ERR) {
177 port->icount.frame++;
182 /* Mask conditions we're ignorning. */
183 sr &= port->read_status_mask;
185 if (sr & UART_SR_RX_BREAK) {
187 } else if (sr & UART_SR_PAR_FRAME_ERR) {
191 if (!uart_handle_sysrq_char(port, c))
192 tty_insert_flip_char(tport, c, flag);
195 tty_flip_buffer_push(tport);
198 static void reset_dm_count(struct uart_port *port, int count)
200 wait_for_xmitr(port);
201 msm_write(port, count, UARTDM_NCF_TX);
202 msm_read(port, UARTDM_NCF_TX);
205 static void handle_tx(struct uart_port *port)
207 struct circ_buf *xmit = &port->state->xmit;
208 struct msm_port *msm_port = UART_TO_MSM(port);
209 unsigned int tx_count, num_chars;
210 unsigned int tf_pointer = 0;
212 tx_count = uart_circ_chars_pending(xmit);
213 tx_count = min3(tx_count, (unsigned int)UART_XMIT_SIZE - xmit->tail,
217 if (msm_port->is_uartdm)
218 reset_dm_count(port, tx_count + 1);
220 msm_write(port, port->x_char,
221 msm_port->is_uartdm ? UARTDM_TF : UART_TF);
224 } else if (tx_count && msm_port->is_uartdm) {
225 reset_dm_count(port, tx_count);
228 while (tf_pointer < tx_count) {
231 unsigned int *bf = (unsigned int *)&buf;
233 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
236 if (msm_port->is_uartdm)
237 num_chars = min(tx_count - tf_pointer, sizeof(buf));
241 for (i = 0; i < num_chars; i++) {
242 buf[i] = xmit->buf[xmit->tail + i];
246 msm_write(port, *bf, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
247 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
248 tf_pointer += num_chars;
251 /* disable tx interrupts if nothing more to send */
252 if (uart_circ_empty(xmit))
255 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
256 uart_write_wakeup(port);
259 static void handle_delta_cts(struct uart_port *port)
261 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
263 wake_up_interruptible(&port->state->port.delta_msr_wait);
266 static irqreturn_t msm_irq(int irq, void *dev_id)
268 struct uart_port *port = dev_id;
269 struct msm_port *msm_port = UART_TO_MSM(port);
272 spin_lock(&port->lock);
273 misr = msm_read(port, UART_MISR);
274 msm_write(port, 0, UART_IMR); /* disable interrupt */
276 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
277 if (msm_port->is_uartdm)
278 handle_rx_dm(port, misr);
282 if (misr & UART_IMR_TXLEV)
284 if (misr & UART_IMR_DELTA_CTS)
285 handle_delta_cts(port);
287 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
288 spin_unlock(&port->lock);
293 static unsigned int msm_tx_empty(struct uart_port *port)
295 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
298 static unsigned int msm_get_mctrl(struct uart_port *port)
300 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
304 static void msm_reset(struct uart_port *port)
306 /* reset everything */
307 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
308 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
309 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
310 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
311 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
312 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
315 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
318 mr = msm_read(port, UART_MR1);
320 if (!(mctrl & TIOCM_RTS)) {
321 mr &= ~UART_MR1_RX_RDY_CTL;
322 msm_write(port, mr, UART_MR1);
323 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
325 mr |= UART_MR1_RX_RDY_CTL;
326 msm_write(port, mr, UART_MR1);
330 static void msm_break_ctl(struct uart_port *port, int break_ctl)
333 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
335 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
338 struct msm_baud_map {
344 static const struct msm_baud_map *
345 msm_find_best_baud(struct uart_port *port, unsigned int baud)
347 unsigned int i, divisor;
348 const struct msm_baud_map *entry;
349 static const struct msm_baud_map table[] = {
368 divisor = uart_get_divisor(port, baud);
370 for (i = 0, entry = table; i < ARRAY_SIZE(table); i++, entry++)
371 if (entry->divisor <= divisor)
374 return entry; /* Default to smallest divider */
377 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
379 unsigned int rxstale, watermark;
380 struct msm_port *msm_port = UART_TO_MSM(port);
381 const struct msm_baud_map *entry;
383 entry = msm_find_best_baud(port, baud);
385 if (msm_port->is_uartdm)
386 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
388 msm_write(port, entry->code, UART_CSR);
390 /* RX stale watermark */
391 rxstale = entry->rxstale;
392 watermark = UART_IPR_STALE_LSB & rxstale;
393 watermark |= UART_IPR_RXSTALE_LAST;
394 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
395 msm_write(port, watermark, UART_IPR);
397 /* set RX watermark */
398 watermark = (port->fifosize * 3) / 4;
399 msm_write(port, watermark, UART_RFWR);
401 /* set TX watermark */
402 msm_write(port, 10, UART_TFWR);
404 if (msm_port->is_uartdm) {
405 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
406 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
407 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
414 static void msm_init_clock(struct uart_port *port)
416 struct msm_port *msm_port = UART_TO_MSM(port);
418 clk_prepare_enable(msm_port->clk);
419 if (!IS_ERR(msm_port->pclk))
420 clk_prepare_enable(msm_port->pclk);
421 msm_serial_set_mnd_regs(port);
424 static int msm_startup(struct uart_port *port)
426 struct msm_port *msm_port = UART_TO_MSM(port);
427 unsigned int data, rfr_level;
430 snprintf(msm_port->name, sizeof(msm_port->name),
431 "msm_serial%d", port->line);
433 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
434 msm_port->name, port);
438 msm_init_clock(port);
440 if (likely(port->fifosize > 12))
441 rfr_level = port->fifosize - 12;
443 rfr_level = port->fifosize;
445 /* set automatic RFR level */
446 data = msm_read(port, UART_MR1);
447 data &= ~UART_MR1_AUTO_RFR_LEVEL1;
448 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
449 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
450 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
451 msm_write(port, data, UART_MR1);
453 /* make sure that RXSTALE count is non-zero */
454 data = msm_read(port, UART_IPR);
455 if (unlikely(!data)) {
456 data |= UART_IPR_RXSTALE_LAST;
457 data |= UART_IPR_STALE_LSB;
458 msm_write(port, data, UART_IPR);
462 if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) {
463 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
465 data = UART_CR_TX_ENABLE;
468 data |= UART_CR_RX_ENABLE;
469 msm_write(port, data, UART_CR); /* enable TX & RX */
471 /* Make sure IPR is not 0 to start with*/
472 if (msm_port->is_uartdm)
473 msm_write(port, UART_IPR_STALE_LSB, UART_IPR);
475 /* turn on RX and CTS interrupts */
476 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
477 UART_IMR_CURRENT_CTS;
479 if (msm_port->is_uartdm) {
480 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
481 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
482 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
485 msm_write(port, msm_port->imr, UART_IMR);
489 static void msm_shutdown(struct uart_port *port)
491 struct msm_port *msm_port = UART_TO_MSM(port);
494 msm_write(port, 0, UART_IMR); /* disable interrupts */
496 clk_disable_unprepare(msm_port->clk);
498 free_irq(port->irq, port);
501 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
502 struct ktermios *old)
505 unsigned int baud, mr;
507 spin_lock_irqsave(&port->lock, flags);
509 /* calculate and set baud rate */
510 baud = uart_get_baud_rate(port, termios, old, 300, 115200);
511 baud = msm_set_baud_rate(port, baud);
512 if (tty_termios_baud_rate(termios))
513 tty_termios_encode_baud_rate(termios, baud, baud);
515 /* calculate parity */
516 mr = msm_read(port, UART_MR2);
517 mr &= ~UART_MR2_PARITY_MODE;
518 if (termios->c_cflag & PARENB) {
519 if (termios->c_cflag & PARODD)
520 mr |= UART_MR2_PARITY_MODE_ODD;
521 else if (termios->c_cflag & CMSPAR)
522 mr |= UART_MR2_PARITY_MODE_SPACE;
524 mr |= UART_MR2_PARITY_MODE_EVEN;
527 /* calculate bits per char */
528 mr &= ~UART_MR2_BITS_PER_CHAR;
529 switch (termios->c_cflag & CSIZE) {
531 mr |= UART_MR2_BITS_PER_CHAR_5;
534 mr |= UART_MR2_BITS_PER_CHAR_6;
537 mr |= UART_MR2_BITS_PER_CHAR_7;
541 mr |= UART_MR2_BITS_PER_CHAR_8;
545 /* calculate stop bits */
546 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
547 if (termios->c_cflag & CSTOPB)
548 mr |= UART_MR2_STOP_BIT_LEN_TWO;
550 mr |= UART_MR2_STOP_BIT_LEN_ONE;
552 /* set parity, bits per char, and stop bit */
553 msm_write(port, mr, UART_MR2);
555 /* calculate and set hardware flow control */
556 mr = msm_read(port, UART_MR1);
557 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
558 if (termios->c_cflag & CRTSCTS) {
559 mr |= UART_MR1_CTS_CTL;
560 mr |= UART_MR1_RX_RDY_CTL;
562 msm_write(port, mr, UART_MR1);
564 /* Configure status bits to ignore based on termio flags. */
565 port->read_status_mask = 0;
566 if (termios->c_iflag & INPCK)
567 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
568 if (termios->c_iflag & (BRKINT | PARMRK))
569 port->read_status_mask |= UART_SR_RX_BREAK;
571 uart_update_timeout(port, termios->c_cflag, baud);
573 spin_unlock_irqrestore(&port->lock, flags);
576 static const char *msm_type(struct uart_port *port)
581 static void msm_release_port(struct uart_port *port)
583 struct platform_device *pdev = to_platform_device(port->dev);
584 struct msm_port *msm_port = UART_TO_MSM(port);
585 struct resource *uart_resource;
586 struct resource *gsbi_resource;
587 resource_size_t size;
589 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
590 if (unlikely(!uart_resource))
592 size = resource_size(uart_resource);
594 release_mem_region(port->mapbase, size);
595 iounmap(port->membase);
596 port->membase = NULL;
598 if (msm_port->gsbi_base) {
599 writel_relaxed(GSBI_PROTOCOL_IDLE,
600 msm_port->gsbi_base + GSBI_CONTROL);
602 gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
603 if (unlikely(!gsbi_resource))
606 size = resource_size(gsbi_resource);
607 release_mem_region(gsbi_resource->start, size);
608 iounmap(msm_port->gsbi_base);
609 msm_port->gsbi_base = NULL;
613 static int msm_request_port(struct uart_port *port)
615 struct msm_port *msm_port = UART_TO_MSM(port);
616 struct platform_device *pdev = to_platform_device(port->dev);
617 struct resource *uart_resource;
618 struct resource *gsbi_resource;
619 resource_size_t size;
622 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
623 if (unlikely(!uart_resource))
626 size = resource_size(uart_resource);
628 if (!request_mem_region(port->mapbase, size, "msm_serial"))
631 port->membase = ioremap(port->mapbase, size);
632 if (!port->membase) {
634 goto fail_release_port;
637 gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
638 /* Is this a GSBI-based port? */
640 size = resource_size(gsbi_resource);
642 if (!request_mem_region(gsbi_resource->start, size,
645 goto fail_release_port_membase;
648 msm_port->gsbi_base = ioremap(gsbi_resource->start, size);
649 if (!msm_port->gsbi_base) {
651 goto fail_release_gsbi;
658 release_mem_region(gsbi_resource->start, size);
659 fail_release_port_membase:
660 iounmap(port->membase);
662 release_mem_region(port->mapbase, size);
666 static void msm_config_port(struct uart_port *port, int flags)
668 struct msm_port *msm_port = UART_TO_MSM(port);
670 if (flags & UART_CONFIG_TYPE) {
671 port->type = PORT_MSM;
672 ret = msm_request_port(port);
676 if (msm_port->is_uartdm)
677 writel_relaxed(GSBI_PROTOCOL_UART,
678 msm_port->gsbi_base + GSBI_CONTROL);
681 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
683 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
685 if (unlikely(port->irq != ser->irq))
690 static void msm_power(struct uart_port *port, unsigned int state,
691 unsigned int oldstate)
693 struct msm_port *msm_port = UART_TO_MSM(port);
697 clk_prepare_enable(msm_port->clk);
698 if (!IS_ERR(msm_port->pclk))
699 clk_prepare_enable(msm_port->pclk);
702 clk_disable_unprepare(msm_port->clk);
703 if (!IS_ERR(msm_port->pclk))
704 clk_disable_unprepare(msm_port->pclk);
707 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
711 static struct uart_ops msm_uart_pops = {
712 .tx_empty = msm_tx_empty,
713 .set_mctrl = msm_set_mctrl,
714 .get_mctrl = msm_get_mctrl,
715 .stop_tx = msm_stop_tx,
716 .start_tx = msm_start_tx,
717 .stop_rx = msm_stop_rx,
718 .enable_ms = msm_enable_ms,
719 .break_ctl = msm_break_ctl,
720 .startup = msm_startup,
721 .shutdown = msm_shutdown,
722 .set_termios = msm_set_termios,
724 .release_port = msm_release_port,
725 .request_port = msm_request_port,
726 .config_port = msm_config_port,
727 .verify_port = msm_verify_port,
731 static struct msm_port msm_uart_ports[] = {
735 .ops = &msm_uart_pops,
736 .flags = UPF_BOOT_AUTOCONF,
744 .ops = &msm_uart_pops,
745 .flags = UPF_BOOT_AUTOCONF,
753 .ops = &msm_uart_pops,
754 .flags = UPF_BOOT_AUTOCONF,
761 #define UART_NR ARRAY_SIZE(msm_uart_ports)
763 static inline struct uart_port *get_port_from_line(unsigned int line)
765 return &msm_uart_ports[line].uart;
768 #ifdef CONFIG_SERIAL_MSM_CONSOLE
770 static void msm_console_putchar(struct uart_port *port, int c)
772 struct msm_port *msm_port = UART_TO_MSM(port);
774 if (msm_port->is_uartdm)
775 reset_dm_count(port, 1);
777 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
779 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
782 static void msm_console_write(struct console *co, const char *s,
785 struct uart_port *port;
786 struct msm_port *msm_port;
788 BUG_ON(co->index < 0 || co->index >= UART_NR);
790 port = get_port_from_line(co->index);
791 msm_port = UART_TO_MSM(port);
793 spin_lock(&port->lock);
794 uart_console_write(port, s, count, msm_console_putchar);
795 spin_unlock(&port->lock);
798 static int __init msm_console_setup(struct console *co, char *options)
800 struct uart_port *port;
801 struct msm_port *msm_port;
802 int baud, flow, bits, parity;
804 if (unlikely(co->index >= UART_NR || co->index < 0))
807 port = get_port_from_line(co->index);
808 msm_port = UART_TO_MSM(port);
810 if (unlikely(!port->membase))
813 msm_init_clock(port);
816 uart_parse_options(options, &baud, &parity, &bits, &flow);
821 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
824 if (baud < 300 || baud > 115200)
826 msm_set_baud_rate(port, baud);
830 if (msm_port->is_uartdm) {
831 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
832 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
835 printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
837 return uart_set_options(port, co, baud, parity, bits, flow);
840 static struct uart_driver msm_uart_driver;
842 static struct console msm_console = {
844 .write = msm_console_write,
845 .device = uart_console_device,
846 .setup = msm_console_setup,
847 .flags = CON_PRINTBUFFER,
849 .data = &msm_uart_driver,
852 #define MSM_CONSOLE (&msm_console)
855 #define MSM_CONSOLE NULL
858 static struct uart_driver msm_uart_driver = {
859 .owner = THIS_MODULE,
860 .driver_name = "msm_serial",
861 .dev_name = "ttyMSM",
866 static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
868 static int __init msm_serial_probe(struct platform_device *pdev)
870 struct msm_port *msm_port;
871 struct resource *resource;
872 struct uart_port *port;
876 pdev->id = atomic_inc_return(&msm_uart_next_id) - 1;
878 if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
881 printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id);
883 port = get_port_from_line(pdev->id);
884 port->dev = &pdev->dev;
885 msm_port = UART_TO_MSM(port);
887 if (platform_get_resource(pdev, IORESOURCE_MEM, 1))
888 msm_port->is_uartdm = 1;
890 msm_port->is_uartdm = 0;
892 if (msm_port->is_uartdm) {
893 msm_port->clk = devm_clk_get(&pdev->dev, "gsbi_uart_clk");
894 msm_port->pclk = devm_clk_get(&pdev->dev, "gsbi_pclk");
896 msm_port->clk = devm_clk_get(&pdev->dev, "uart_clk");
897 msm_port->pclk = ERR_PTR(-ENOENT);
900 if (IS_ERR(msm_port->clk))
901 return PTR_ERR(msm_port->clk);
903 if (msm_port->is_uartdm) {
904 if (IS_ERR(msm_port->pclk))
905 return PTR_ERR(msm_port->pclk);
907 clk_set_rate(msm_port->clk, 1843200);
910 port->uartclk = clk_get_rate(msm_port->clk);
911 printk(KERN_INFO "uartclk = %d\n", port->uartclk);
914 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
915 if (unlikely(!resource))
917 port->mapbase = resource->start;
919 irq = platform_get_irq(pdev, 0);
920 if (unlikely(irq < 0))
924 platform_set_drvdata(pdev, port);
926 return uart_add_one_port(&msm_uart_driver, port);
929 static int msm_serial_remove(struct platform_device *pdev)
931 struct uart_port *port = platform_get_drvdata(pdev);
933 uart_remove_one_port(&msm_uart_driver, port);
938 static struct of_device_id msm_match_table[] = {
939 { .compatible = "qcom,msm-uart" },
943 static struct platform_driver msm_platform_driver = {
944 .remove = msm_serial_remove,
946 .name = "msm_serial",
947 .owner = THIS_MODULE,
948 .of_match_table = msm_match_table,
952 static int __init msm_serial_init(void)
956 ret = uart_register_driver(&msm_uart_driver);
960 ret = platform_driver_probe(&msm_platform_driver, msm_serial_probe);
962 uart_unregister_driver(&msm_uart_driver);
964 printk(KERN_INFO "msm_serial: driver initialized\n");
969 static void __exit msm_serial_exit(void)
971 #ifdef CONFIG_SERIAL_MSM_CONSOLE
972 unregister_console(&msm_console);
974 platform_driver_unregister(&msm_platform_driver);
975 uart_unregister_driver(&msm_uart_driver);
978 module_init(msm_serial_init);
979 module_exit(msm_serial_exit);
981 MODULE_AUTHOR("Robert Love <rlove@google.com>");
982 MODULE_DESCRIPTION("Driver for msm7x serial device");
983 MODULE_LICENSE("GPL");