drivers/tty/serial/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/8250_pci.h>
  22 #include <linux/bitops.h>
  23
  24 #include <asm/byteorder.h>
  25 #include <asm/io.h>
  26
  27 #include "8250.h"
  28
  29 #undef SERIAL_DEBUG_PCI
  30
  31 /*
  32  * init function returns:
  33  *  > 0 - number of ports
  34  *  = 0 - use board->num_ports
  35  *  < 0 - error
  36  */
  37 struct pci_serial_quirk {
  38         u32     vendor;
  39         u32     device;
  40         u32     subvendor;
  41         u32     subdevice;
  42         int     (*probe)(struct pci_dev *dev);
  43         int     (*init)(struct pci_dev *dev);
  44         int     (*setup)(struct serial_private *,
  45                          const struct pciserial_board *,
  46                          struct uart_port *, int);
  47         void    (*exit)(struct pci_dev *dev);
  48 };
  49
  50 #define PCI_NUM_BAR_RESOURCES   6
  51
  52 struct serial_private {
  53         struct pci_dev          *dev;
  54         unsigned int            nr;
  55         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  56         struct pci_serial_quirk *quirk;
  57         int                     line[0];
  58 };
  59
  60 static int pci_default_setup(struct serial_private*,
  61           const struct pciserial_board*, struct uart_port*, int);
  62
  63 static void moan_device(const char *str, struct pci_dev *dev)
  64 {
  65         printk(KERN_WARNING
  66                "%s: %s\n"
  67                "Please send the output of lspci -vv, this\n"
  68                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  69                "manufacturer and name of serial board or\n"
  70                "modem board to rmk+serial@arm.linux.org.uk.\n",
  71                pci_name(dev), str, dev->vendor, dev->device,
  72                dev->subsystem_vendor, dev->subsystem_device);
  73 }
  74
  75 static int
  76 setup_port(struct serial_private *priv, struct uart_port *port,
  77            int bar, int offset, int regshift)
  78 {
  79         struct pci_dev *dev = priv->dev;
  80         unsigned long base, len;
  81
  82         if (bar >= PCI_NUM_BAR_RESOURCES)
  83                 return -EINVAL;
  84
  85         base = pci_resource_start(dev, bar);
  86
  87         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  88                 len =  pci_resource_len(dev, bar);
  89
  90                 if (!priv->remapped_bar[bar])
  91                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  92                 if (!priv->remapped_bar[bar])
  93                         return -ENOMEM;
  94
  95                 port->iotype = UPIO_MEM;
  96                 port->iobase = 0;
  97                 port->mapbase = base + offset;
  98                 port->membase = priv->remapped_bar[bar] + offset;
  99                 port->regshift = regshift;
 100         } else {
 101                 port->iotype = UPIO_PORT;
 102                 port->iobase = base + offset;
 103                 port->mapbase = 0;
 104                 port->membase = NULL;
 105                 port->regshift = 0;
 106         }
 107         return 0;
 108 }
 109
 110 /*
 111  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 112  */
 113 static int addidata_apci7800_setup(struct serial_private *priv,
 114                                 const struct pciserial_board *board,
 115                                 struct uart_port *port, int idx)
 116 {
 117         unsigned int bar = 0, offset = board->first_offset;
 118         bar = FL_GET_BASE(board->flags);
 119
 120         if (idx < 2) {
 121                 offset += idx * board->uart_offset;
 122         } else if ((idx >= 2) && (idx < 4)) {
 123                 bar += 1;
 124                 offset += ((idx - 2) * board->uart_offset);
 125         } else if ((idx >= 4) && (idx < 6)) {
 126                 bar += 2;
 127                 offset += ((idx - 4) * board->uart_offset);
 128         } else if (idx >= 6) {
 129                 bar += 3;
 130                 offset += ((idx - 6) * board->uart_offset);
 131         }
 132
 133         return setup_port(priv, port, bar, offset, board->reg_shift);
 134 }
 135
 136 /*
 137  * AFAVLAB uses a different mixture of BARs and offsets
 138  * Not that ugly ;) -- HW
 139  */
 140 static int
 141 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 142               struct uart_port *port, int idx)
 143 {
 144         unsigned int bar, offset = board->first_offset;
 145
 146         bar = FL_GET_BASE(board->flags);
 147         if (idx < 4)
 148                 bar += idx;
 149         else {
 150                 bar = 4;
 151                 offset += (idx - 4) * board->uart_offset;
 152         }
 153
 154         return setup_port(priv, port, bar, offset, board->reg_shift);
 155 }
 156
 157 /*
 158  * HP's Remote Management Console.  The Diva chip came in several
 159  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 160  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 161  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 162  * one Diva chip, but it has been expanded to 5 UARTs.
 163  */
 164 static int pci_hp_diva_init(struct pci_dev *dev)
 165 {
 166         int rc = 0;
 167
 168         switch (dev->subsystem_device) {
 169         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 170         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 171         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 172         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 173                 rc = 3;
 174                 break;
 175         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 176                 rc = 2;
 177                 break;
 178         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 179                 rc = 4;
 180                 break;
 181         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 182         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 183                 rc = 1;
 184                 break;
 185         }
 186
 187         return rc;
 188 }
 189
 190 /*
 191  * HP's Diva chip puts the 4th/5th serial port further out, and
 192  * some serial ports are supposed to be hidden on certain models.
 193  */
 194 static int
 195 pci_hp_diva_setup(struct serial_private *priv,
 196                 const struct pciserial_board *board,
 197                 struct uart_port *port, int idx)
 198 {
 199         unsigned int offset = board->first_offset;
 200         unsigned int bar = FL_GET_BASE(board->flags);
 201
 202         switch (priv->dev->subsystem_device) {
 203         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 204                 if (idx == 3)
 205                         idx++;
 206                 break;
 207         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 208                 if (idx > 0)
 209                         idx++;
 210                 if (idx > 2)
 211                         idx++;
 212                 break;
 213         }
 214         if (idx > 2)
 215                 offset = 0x18;
 216
 217         offset += idx * board->uart_offset;
 218
 219         return setup_port(priv, port, bar, offset, board->reg_shift);
 220 }
 221
 222 /*
 223  * Added for EKF Intel i960 serial boards
 224  */
 225 static int pci_inteli960ni_init(struct pci_dev *dev)
 226 {
 227         unsigned long oldval;
 228
 229         if (!(dev->subsystem_device & 0x1000))
 230                 return -ENODEV;
 231
 232         /* is firmware started? */
 233         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 234         if (oldval == 0x00001000L) { /* RESET value */
 235                 printk(KERN_DEBUG "Local i960 firmware missing");
 236                 return -ENODEV;
 237         }
 238         return 0;
 239 }
 240
 241 /*
 242  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 243  * that the card interrupt be explicitly enabled or disabled.  This
 244  * seems to be mainly needed on card using the PLX which also use I/O
 245  * mapped memory.
 246  */
 247 static int pci_plx9050_init(struct pci_dev *dev)
 248 {
 249         u8 irq_config;
 250         void __iomem *p;
 251
 252         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 253                 moan_device("no memory in bar 0", dev);
 254                 return 0;
 255         }
 256
 257         irq_config = 0x41;
 258         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 259             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 260                 irq_config = 0x43;
 261
 262         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 263             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 264                 /*
 265                  * As the megawolf cards have the int pins active
 266                  * high, and have 2 UART chips, both ints must be
 267                  * enabled on the 9050. Also, the UARTS are set in
 268                  * 16450 mode by default, so we have to enable the
 269                  * 16C950 'enhanced' mode so that we can use the
 270                  * deep FIFOs
 271                  */
 272                 irq_config = 0x5b;
 273         /*
 274          * enable/disable interrupts
 275          */
 276         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 277         if (p == NULL)
 278                 return -ENOMEM;
 279         writel(irq_config, p + 0x4c);
 280
 281         /*
 282          * Read the register back to ensure that it took effect.
 283          */
 284         readl(p + 0x4c);
 285         iounmap(p);
 286
 287         return 0;
 288 }
 289
 290 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 291 {
 292         u8 __iomem *p;
 293
 294         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 295                 return;
 296
 297         /*
 298          * disable interrupts
 299          */
 300         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 301         if (p != NULL) {
 302                 writel(0, p + 0x4c);
 303
 304                 /*
 305                  * Read the register back to ensure that it took effect.
 306                  */
 307                 readl(p + 0x4c);
 308                 iounmap(p);
 309         }
 310 }
 311
 312 #define NI8420_INT_ENABLE_REG   0x38
 313 #define NI8420_INT_ENABLE_BIT   0x2000
 314
 315 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
 316 {
 317         void __iomem *p;
 318         unsigned long base, len;
 319         unsigned int bar = 0;
 320
 321         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 322                 moan_device("no memory in bar", dev);
 323                 return;
 324         }
 325
 326         base = pci_resource_start(dev, bar);
 327         len =  pci_resource_len(dev, bar);
 328         p = ioremap_nocache(base, len);
 329         if (p == NULL)
 330                 return;
 331
 332         /* Disable the CPU Interrupt */
 333         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 334                p + NI8420_INT_ENABLE_REG);
 335         iounmap(p);
 336 }
 337
 338
 339 /* MITE registers */
 340 #define MITE_IOWBSR1    0xc4
 341 #define MITE_IOWCR1     0xf4
 342 #define MITE_LCIMR1     0x08
 343 #define MITE_LCIMR2     0x10
 344
 345 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 346
 347 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
 348 {
 349         void __iomem *p;
 350         unsigned long base, len;
 351         unsigned int bar = 0;
 352
 353         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 354                 moan_device("no memory in bar", dev);
 355                 return;
 356         }
 357
 358         base = pci_resource_start(dev, bar);
 359         len =  pci_resource_len(dev, bar);
 360         p = ioremap_nocache(base, len);
 361         if (p == NULL)
 362                 return;
 363
 364         /* Disable the CPU Interrupt */
 365         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 366         iounmap(p);
 367 }
 368
 369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 370 static int
 371 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 372                 struct uart_port *port, int idx)
 373 {
 374         unsigned int bar, offset = board->first_offset;
 375
 376         bar = 0;
 377
 378         if (idx < 4) {
 379                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 380                 offset += idx * board->uart_offset;
 381         } else if (idx < 8) {
 382                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 383                 offset += idx * board->uart_offset + 0xC00;
 384         } else /* we have only 8 ports on PMC-OCTALPRO */
 385                 return 1;
 386
 387         return setup_port(priv, port, bar, offset, board->reg_shift);
 388 }
 389
 390 /*
 391 * This does initialization for PMC OCTALPRO cards:
 392 * maps the device memory, resets the UARTs (needed, bc
 393 * if the module is removed and inserted again, the card
 394 * is in the sleep mode) and enables global interrupt.
 395 */
 396
 397 /* global control register offset for SBS PMC-OctalPro */
 398 #define OCT_REG_CR_OFF          0x500
 399
 400 static int sbs_init(struct pci_dev *dev)
 401 {
 402         u8 __iomem *p;
 403
 404         p = pci_ioremap_bar(dev, 0);
 405
 406         if (p == NULL)
 407                 return -ENOMEM;
 408         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 409         writeb(0x10, p + OCT_REG_CR_OFF);
 410         udelay(50);
 411         writeb(0x0, p + OCT_REG_CR_OFF);
 412
 413         /* Set bit-2 (INTENABLE) of Control Register */
 414         writeb(0x4, p + OCT_REG_CR_OFF);
 415         iounmap(p);
 416
 417         return 0;
 418 }
 419
 420 /*
 421  * Disables the global interrupt of PMC-OctalPro
 422  */
 423
 424 static void __devexit sbs_exit(struct pci_dev *dev)
 425 {
 426         u8 __iomem *p;
 427
 428         p = pci_ioremap_bar(dev, 0);
 429         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 430         if (p != NULL)
 431                 writeb(0, p + OCT_REG_CR_OFF);
 432         iounmap(p);
 433 }
 434
 435 /*
 436  * SIIG serial cards have an PCI interface chip which also controls
 437  * the UART clocking frequency. Each UART can be clocked independently
 438  * (except cards equipped with 4 UARTs) and initial clocking settings
 439  * are stored in the EEPROM chip. It can cause problems because this
 440  * version of serial driver doesn't support differently clocked UART's
 441  * on single PCI card. To prevent this, initialization functions set
 442  * high frequency clocking for all UART's on given card. It is safe (I
 443  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 444  * with other OSes (like M$ DOS).
 445  *
 446  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 447  *
 448  * There is two family of SIIG serial cards with different PCI
 449  * interface chip and different configuration methods:
 450  *     - 10x cards have control registers in IO and/or memory space;
 451  *     - 20x cards have control registers in standard PCI configuration space.
 452  *
 453  * Note: all 10x cards have PCI device ids 0x10..
 454  *       all 20x cards have PCI device ids 0x20..
 455  *
 456  * There are also Quartet Serial cards which use Oxford Semiconductor
 457  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 458  *
 459  * Note: some SIIG cards are probed by the parport_serial object.
 460  */
 461
 462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 464
 465 static int pci_siig10x_init(struct pci_dev *dev)
 466 {
 467         u16 data;
 468         void __iomem *p;
 469
 470         switch (dev->device & 0xfff8) {
 471         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 472                 data = 0xffdf;
 473                 break;
 474         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 475                 data = 0xf7ff;
 476                 break;
 477         default:                        /* 1S1P, 4S */
 478                 data = 0xfffb;
 479                 break;
 480         }
 481
 482         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 483         if (p == NULL)
 484                 return -ENOMEM;
 485
 486         writew(readw(p + 0x28) & data, p + 0x28);
 487         readw(p + 0x28);
 488         iounmap(p);
 489         return 0;
 490 }
 491
 492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 494
 495 static int pci_siig20x_init(struct pci_dev *dev)
 496 {
 497         u8 data;
 498
 499         /* Change clock frequency for the first UART. */
 500         pci_read_config_byte(dev, 0x6f, &data);
 501         pci_write_config_byte(dev, 0x6f, data & 0xef);
 502
 503         /* If this card has 2 UART, we have to do the same with second UART. */
 504         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 505             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 506                 pci_read_config_byte(dev, 0x73, &data);
 507                 pci_write_config_byte(dev, 0x73, data & 0xef);
 508         }
 509         return 0;
 510 }
 511
 512 static int pci_siig_init(struct pci_dev *dev)
 513 {
 514         unsigned int type = dev->device & 0xff00;
 515
 516         if (type == 0x1000)
 517                 return pci_siig10x_init(dev);
 518         else if (type == 0x2000)
 519                 return pci_siig20x_init(dev);
 520
 521         moan_device("Unknown SIIG card", dev);
 522         return -ENODEV;
 523 }
 524
 525 static int pci_siig_setup(struct serial_private *priv,
 526                           const struct pciserial_board *board,
 527                           struct uart_port *port, int idx)
 528 {
 529         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 530
 531         if (idx > 3) {
 532                 bar = 4;
 533                 offset = (idx - 4) * 8;
 534         }
 535
 536         return setup_port(priv, port, bar, offset, 0);
 537 }
 538
 539 /*
 540  * Timedia has an explosion of boards, and to avoid the PCI table from
 541  * growing *huge*, we use this function to collapse some 70 entries
 542  * in the PCI table into one, for sanity's and compactness's sake.
 543  */
 544 static const unsigned short timedia_single_port[] = {
 545         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 546 };
 547
 548 static const unsigned short timedia_dual_port[] = {
 549         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 550         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 551         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 552         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 553         0xD079, 0
 554 };
 555
 556 static const unsigned short timedia_quad_port[] = {
 557         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 558         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 559         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 560         0xB157, 0
 561 };
 562
 563 static const unsigned short timedia_eight_port[] = {
 564         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 565         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 566 };
 567
 568 static const struct timedia_struct {
 569         int num;
 570         const unsigned short *ids;
 571 } timedia_data[] = {
 572         { 1, timedia_single_port },
 573         { 2, timedia_dual_port },
 574         { 4, timedia_quad_port },
 575         { 8, timedia_eight_port }
 576 };
 577
 578 /*
 579  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 580  * listing them individually, this driver merely grabs them all with
 581  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 582  * and should be left free to be claimed by parport_serial instead.
 583  */
 584 static int pci_timedia_probe(struct pci_dev *dev)
 585 {
 586         /*
 587          * Check the third digit of the subdevice ID
 588          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 589          */
 590         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 591                 dev_info(&dev->dev,
 592                         "ignoring Timedia subdevice %04x for parport_serial\n",
 593                         dev->subsystem_device);
 594                 return -ENODEV;
 595         }
 596
 597         return 0;
 598 }
 599
 600 static int pci_timedia_init(struct pci_dev *dev)
 601 {
 602         const unsigned short *ids;
 603         int i, j;
 604
 605         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 606                 ids = timedia_data[i].ids;
 607                 for (j = 0; ids[j]; j++)
 608                         if (dev->subsystem_device == ids[j])
 609                                 return timedia_data[i].num;
 610         }
 611         return 0;
 612 }
 613
 614 /*
 615  * Timedia/SUNIX uses a mixture of BARs and offsets
 616  * Ugh, this is ugly as all hell --- TYT
 617  */
 618 static int
 619 pci_timedia_setup(struct serial_private *priv,
 620                   const struct pciserial_board *board,
 621                   struct uart_port *port, int idx)
 622 {
 623         unsigned int bar = 0, offset = board->first_offset;
 624
 625         switch (idx) {
 626         case 0:
 627                 bar = 0;
 628                 break;
 629         case 1:
 630                 offset = board->uart_offset;
 631                 bar = 0;
 632                 break;
 633         case 2:
 634                 bar = 1;
 635                 break;
 636         case 3:
 637                 offset = board->uart_offset;
 638                 /* FALLTHROUGH */
 639         case 4: /* BAR 2 */
 640         case 5: /* BAR 3 */
 641         case 6: /* BAR 4 */
 642         case 7: /* BAR 5 */
 643                 bar = idx - 2;
 644         }
 645
 646         return setup_port(priv, port, bar, offset, board->reg_shift);
 647 }
 648
 649 /*
 650  * Some Titan cards are also a little weird
 651  */
 652 static int
 653 titan_400l_800l_setup(struct serial_private *priv,
 654                       const struct pciserial_board *board,
 655                       struct uart_port *port, int idx)
 656 {
 657         unsigned int bar, offset = board->first_offset;
 658
 659         switch (idx) {
 660         case 0:
 661                 bar = 1;
 662                 break;
 663         case 1:
 664                 bar = 2;
 665                 break;
 666         default:
 667                 bar = 4;
 668                 offset = (idx - 2) * board->uart_offset;
 669         }
 670
 671         return setup_port(priv, port, bar, offset, board->reg_shift);
 672 }
 673
 674 static int pci_xircom_init(struct pci_dev *dev)
 675 {
 676         msleep(100);
 677         return 0;
 678 }
 679
 680 static int pci_ni8420_init(struct pci_dev *dev)
 681 {
 682         void __iomem *p;
 683         unsigned long base, len;
 684         unsigned int bar = 0;
 685
 686         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 687                 moan_device("no memory in bar", dev);
 688                 return 0;
 689         }
 690
 691         base = pci_resource_start(dev, bar);
 692         len =  pci_resource_len(dev, bar);
 693         p = ioremap_nocache(base, len);
 694         if (p == NULL)
 695                 return -ENOMEM;
 696
 697         /* Enable CPU Interrupt */
 698         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 699                p + NI8420_INT_ENABLE_REG);
 700
 701         iounmap(p);
 702         return 0;
 703 }
 704
 705 #define MITE_IOWBSR1_WSIZE      0xa
 706 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 707 #define MITE_IOWBSR1_WENAB      (1 << 7)
 708 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 709 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 710 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 711
 712 static int pci_ni8430_init(struct pci_dev *dev)
 713 {
 714         void __iomem *p;
 715         unsigned long base, len;
 716         u32 device_window;
 717         unsigned int bar = 0;
 718
 719         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 720                 moan_device("no memory in bar", dev);
 721                 return 0;
 722         }
 723
 724         base = pci_resource_start(dev, bar);
 725         len =  pci_resource_len(dev, bar);
 726         p = ioremap_nocache(base, len);
 727         if (p == NULL)
 728                 return -ENOMEM;
 729
 730         /* Set device window address and size in BAR0 */
 731         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 732                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 733         writel(device_window, p + MITE_IOWBSR1);
 734
 735         /* Set window access to go to RAMSEL IO address space */
 736         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 737                p + MITE_IOWCR1);
 738
 739         /* Enable IO Bus Interrupt 0 */
 740         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 741
 742         /* Enable CPU Interrupt */
 743         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 744
 745         iounmap(p);
 746         return 0;
 747 }
 748
 749 /* UART Port Control Register */
 750 #define NI8430_PORTCON  0x0f
 751 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 752
 753 static int
 754 pci_ni8430_setup(struct serial_private *priv,
 755                  const struct pciserial_board *board,
 756                  struct uart_port *port, int idx)
 757 {
 758         void __iomem *p;
 759         unsigned long base, len;
 760         unsigned int bar, offset = board->first_offset;
 761
 762         if (idx >= board->num_ports)
 763                 return 1;
 764
 765         bar = FL_GET_BASE(board->flags);
 766         offset += idx * board->uart_offset;
 767
 768         base = pci_resource_start(priv->dev, bar);
 769         len =  pci_resource_len(priv->dev, bar);
 770         p = ioremap_nocache(base, len);
 771
 772         /* enable the transceiver */
 773         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 774                p + offset + NI8430_PORTCON);
 775
 776         iounmap(p);
 777
 778         return setup_port(priv, port, bar, offset, board->reg_shift);
 779 }
 780
 781 static int pci_netmos_9900_setup(struct serial_private *priv,
 782                                 const struct pciserial_board *board,
 783                                 struct uart_port *port, int idx)
 784 {
 785         unsigned int bar;
 786
 787         if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
 788                 /* netmos apparently orders BARs by datasheet layout, so serial
 789                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 790                  */
 791                 bar = 3 * idx;
 792
 793                 return setup_port(priv, port, bar, 0, board->reg_shift);
 794         } else {
 795                 return pci_default_setup(priv, board, port, idx);
 796         }
 797 }
 798
 799 /* the 99xx series comes with a range of device IDs and a variety
 800  * of capabilities:
 801  *
 802  * 9900 has varying capabilities and can cascade to sub-controllers
 803  *   (cascading should be purely internal)
 804  * 9904 is hardwired with 4 serial ports
 805  * 9912 and 9922 are hardwired with 2 serial ports
 806  */
 807 static int pci_netmos_9900_numports(struct pci_dev *dev)
 808 {
 809         unsigned int c = dev->class;
 810         unsigned int pi;
 811         unsigned short sub_serports;
 812
 813         pi = (c & 0xff);
 814
 815         if (pi == 2) {
 816                 return 1;
 817         } else if ((pi == 0) &&
 818                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 819                 /* two possibilities: 0x30ps encodes number of parallel and
 820                  * serial ports, or 0x1000 indicates *something*. This is not
 821                  * immediately obvious, since the 2s1p+4s configuration seems
 822                  * to offer all functionality on functions 0..2, while still
 823                  * advertising the same function 3 as the 4s+2s1p config.
 824                  */
 825                 sub_serports = dev->subsystem_device & 0xf;
 826                 if (sub_serports > 0) {
 827                         return sub_serports;
 828                 } else {
 829                         printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 830                         return 0;
 831                 }
 832         }
 833
 834         moan_device("unknown NetMos/Mostech program interface", dev);
 835         return 0;
 836 }
 837
 838 static int pci_netmos_init(struct pci_dev *dev)
 839 {
 840         /* subdevice 0x00PS means <P> parallel, <S> serial */
 841         unsigned int num_serial = dev->subsystem_device & 0xf;
 842
 843         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 844                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 845                 return 0;
 846
 847         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 848                         dev->subsystem_device == 0x0299)
 849                 return 0;
 850
 851         switch (dev->device) { /* FALLTHROUGH on all */
 852                 case PCI_DEVICE_ID_NETMOS_9904:
 853                 case PCI_DEVICE_ID_NETMOS_9912:
 854                 case PCI_DEVICE_ID_NETMOS_9922:
 855                 case PCI_DEVICE_ID_NETMOS_9900:
 856                         num_serial = pci_netmos_9900_numports(dev);
 857                         break;
 858
 859                 default:
 860                         if (num_serial == 0 ) {
 861                                 moan_device("unknown NetMos/Mostech device", dev);
 862                         }
 863         }
 864
 865         if (num_serial == 0)
 866                 return -ENODEV;
 867
 868         return num_serial;
 869 }
 870
 871 /*
 872  * These chips are available with optionally one parallel port and up to
 873  * two serial ports. Unfortunately they all have the same product id.
 874  *
 875  * Basic configuration is done over a region of 32 I/O ports. The base
 876  * ioport is called INTA or INTC, depending on docs/other drivers.
 877  *
 878  * The region of the 32 I/O ports is configured in POSIO0R...
 879  */
 880
 881 /* registers */
 882 #define ITE_887x_MISCR          0x9c
 883 #define ITE_887x_INTCBAR        0x78
 884 #define ITE_887x_UARTBAR        0x7c
 885 #define ITE_887x_PS0BAR         0x10
 886 #define ITE_887x_POSIO0         0x60
 887
 888 /* I/O space size */
 889 #define ITE_887x_IOSIZE         32
 890 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 891 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 892 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 893 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 894 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 895 #define ITE_887x_POSIO_SPEED            (3 << 29)
 896 /* enable IO_Space bit */
 897 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 898
 899 static int pci_ite887x_init(struct pci_dev *dev)
 900 {
 901         /* inta_addr are the configuration addresses of the ITE */
 902         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 903                                                         0x200, 0x280, 0 };
 904         int ret, i, type;
 905         struct resource *iobase = NULL;
 906         u32 miscr, uartbar, ioport;
 907
 908         /* search for the base-ioport */
 909         i = 0;
 910         while (inta_addr[i] && iobase == NULL) {
 911                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 912                                                                 "ite887x");
 913                 if (iobase != NULL) {
 914                         /* write POSIO0R - speed | size | ioport */
 915                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 916                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 917                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 918                         /* write INTCBAR - ioport */
 919                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 920                                                                 inta_addr[i]);
 921                         ret = inb(inta_addr[i]);
 922                         if (ret != 0xff) {
 923                                 /* ioport connected */
 924                                 break;
 925                         }
 926                         release_region(iobase->start, ITE_887x_IOSIZE);
 927                         iobase = NULL;
 928                 }
 929                 i++;
 930         }
 931
 932         if (!inta_addr[i]) {
 933                 printk(KERN_ERR "ite887x: could not find iobase\n");
 934                 return -ENODEV;
 935         }
 936
 937         /* start of undocumented type checking (see parport_pc.c) */
 938         type = inb(iobase->start + 0x18) & 0x0f;
 939
 940         switch (type) {
 941         case 0x2:       /* ITE8871 (1P) */
 942         case 0xa:       /* ITE8875 (1P) */
 943                 ret = 0;
 944                 break;
 945         case 0xe:       /* ITE8872 (2S1P) */
 946                 ret = 2;
 947                 break;
 948         case 0x6:       /* ITE8873 (1S) */
 949                 ret = 1;
 950                 break;
 951         case 0x8:       /* ITE8874 (2S) */
 952                 ret = 2;
 953                 break;
 954         default:
 955                 moan_device("Unknown ITE887x", dev);
 956                 ret = -ENODEV;
 957         }
 958
 959         /* configure all serial ports */
 960         for (i = 0; i < ret; i++) {
 961                 /* read the I/O port from the device */
 962                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 963                                                                 &ioport);
 964                 ioport &= 0x0000FF00;   /* the actual base address */
 965                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 966                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 967                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 968
 969                 /* write the ioport to the UARTBAR */
 970                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 971                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 972                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 973                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 974
 975                 /* get current config */
 976                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 977                 /* disable interrupts (UARTx_Routing[3:0]) */
 978                 miscr &= ~(0xf << (12 - 4 * i));
 979                 /* activate the UART (UARTx_En) */
 980                 miscr |= 1 << (23 - i);
 981                 /* write new config with activated UART */
 982                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 983         }
 984
 985         if (ret <= 0) {
 986                 /* the device has no UARTs if we get here */
 987                 release_region(iobase->start, ITE_887x_IOSIZE);
 988         }
 989
 990         return ret;
 991 }
 992
 993 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
 994 {
 995         u32 ioport;
 996         /* the ioport is bit 0-15 in POSIO0R */
 997         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 998         ioport &= 0xffff;
 999         release_region(ioport, ITE_887x_IOSIZE);
1000 }
1001
1002 /*
1003  * Oxford Semiconductor Inc.
1004  * Check that device is part of the Tornado range of devices, then determine
1005  * the number of ports available on the device.
1006  */
1007 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008 {
1009         u8 __iomem *p;
1010         unsigned long deviceID;
1011         unsigned int  number_uarts = 0;
1012
1013         /* OxSemi Tornado devices are all 0xCxxx */
1014         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015             (dev->device & 0xF000) != 0xC000)
1016                 return 0;
1017
1018         p = pci_iomap(dev, 0, 5);
1019         if (p == NULL)
1020                 return -ENOMEM;
1021
1022         deviceID = ioread32(p);
1023         /* Tornado device */
1024         if (deviceID == 0x07000200) {
1025                 number_uarts = ioread8(p + 4);
1026                 printk(KERN_DEBUG
1027                         "%d ports detected on Oxford PCI Express device\n",
1028                                                                 number_uarts);
1029         }
1030         pci_iounmap(dev, p);
1031         return number_uarts;
1032 }
1033
1034 static int
1035 pci_default_setup(struct serial_private *priv,
1036                   const struct pciserial_board *board,
1037                   struct uart_port *port, int idx)
1038 {
1039         unsigned int bar, offset = board->first_offset, maxnr;
1040
1041         bar = FL_GET_BASE(board->flags);
1042         if (board->flags & FL_BASE_BARS)
1043                 bar += idx;
1044         else
1045                 offset += idx * board->uart_offset;
1046
1047         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1048                 (board->reg_shift + 3);
1049
1050         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1051                 return 1;
1052
1053         return setup_port(priv, port, bar, offset, board->reg_shift);
1054 }
1055
1056 static int
1057 ce4100_serial_setup(struct serial_private *priv,
1058                   const struct pciserial_board *board,
1059                   struct uart_port *port, int idx)
1060 {
1061         int ret;
1062
1063         ret = setup_port(priv, port, 0, 0, board->reg_shift);
1064         port->iotype = UPIO_MEM32;
1065         port->type = PORT_XSCALE;
1066         port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1067         port->regshift = 2;
1068
1069         return ret;
1070 }
1071
1072 static int
1073 pci_omegapci_setup(struct serial_private *priv,
1074                       const struct pciserial_board *board,
1075                       struct uart_port *port, int idx)
1076 {
1077         return setup_port(priv, port, 2, idx * 8, 0);
1078 }
1079
1080 static int
1081 pci_brcm_trumanage_setup(struct serial_private *priv,
1082                          const struct pciserial_board *board,
1083                          struct uart_port *port, int idx)
1084 {
1085         int ret = pci_default_setup(priv, board, port, idx);
1086
1087         port->type = PORT_BRCM_TRUMANAGE;
1088         port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1089         return ret;
1090 }
1091
1092 static int skip_tx_en_setup(struct serial_private *priv,
1093                         const struct pciserial_board *board,
1094                         struct uart_port *port, int idx)
1095 {
1096         port->flags |= UPF_NO_TXEN_TEST;
1097         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1098                           "[%04x:%04x] subsystem [%04x:%04x]\n",
1099                           priv->dev->vendor,
1100                           priv->dev->device,
1101                           priv->dev->subsystem_vendor,
1102                           priv->dev->subsystem_device);
1103
1104         return pci_default_setup(priv, board, port, idx);
1105 }
1106
1107 static int pci_eg20t_init(struct pci_dev *dev)
1108 {
1109 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1110         return -ENODEV;
1111 #else
1112         return 0;
1113 #endif
1114 }
1115
1116 static int
1117 pci_xr17c154_setup(struct serial_private *priv,
1118                   const struct pciserial_board *board,
1119                   struct uart_port *port, int idx)
1120 {
1121         port->flags |= UPF_EXAR_EFR;
1122         return pci_default_setup(priv, board, port, idx);
1123 }
1124
1125 /* This should be in linux/pci_ids.h */
1126 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1127 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1128 #define PCI_DEVICE_ID_OCTPRO            0x0001
1129 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1130 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1131 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1132 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1133 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1134 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1135 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1136 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1137 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1138 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1139 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1140 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1141 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1142 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1143 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1144 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1145 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1146 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1147 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1148 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1149 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1150 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1151 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1152 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1153 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1154
1155 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1156 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1157
1158 /*
1159  * Master list of serial port init/setup/exit quirks.
1160  * This does not describe the general nature of the port.
1161  * (ie, baud base, number and location of ports, etc)
1162  *
1163  * This list is ordered alphabetically by vendor then device.
1164  * Specific entries must come before more generic entries.
1165  */
1166 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1167         /*
1168         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1169         */
1170         {
1171                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
1172                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1173                 .subvendor      = PCI_ANY_ID,
1174                 .subdevice      = PCI_ANY_ID,
1175                 .setup          = addidata_apci7800_setup,
1176         },
1177         /*
1178          * AFAVLAB cards - these may be called via parport_serial
1179          *  It is not clear whether this applies to all products.
1180          */
1181         {
1182                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1183                 .device         = PCI_ANY_ID,
1184                 .subvendor      = PCI_ANY_ID,
1185                 .subdevice      = PCI_ANY_ID,
1186                 .setup          = afavlab_setup,
1187         },
1188         /*
1189          * HP Diva
1190          */
1191         {
1192                 .vendor         = PCI_VENDOR_ID_HP,
1193                 .device         = PCI_DEVICE_ID_HP_DIVA,
1194                 .subvendor      = PCI_ANY_ID,
1195                 .subdevice      = PCI_ANY_ID,
1196                 .init           = pci_hp_diva_init,
1197                 .setup          = pci_hp_diva_setup,
1198         },
1199         /*
1200          * Intel
1201          */
1202         {
1203                 .vendor         = PCI_VENDOR_ID_INTEL,
1204                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1205                 .subvendor      = 0xe4bf,
1206                 .subdevice      = PCI_ANY_ID,
1207                 .init           = pci_inteli960ni_init,
1208                 .setup          = pci_default_setup,
1209         },
1210         {
1211                 .vendor         = PCI_VENDOR_ID_INTEL,
1212                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1213                 .subvendor      = PCI_ANY_ID,
1214                 .subdevice      = PCI_ANY_ID,
1215                 .setup          = skip_tx_en_setup,
1216         },
1217         {
1218                 .vendor         = PCI_VENDOR_ID_INTEL,
1219                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1220                 .subvendor      = PCI_ANY_ID,
1221                 .subdevice      = PCI_ANY_ID,
1222                 .setup          = skip_tx_en_setup,
1223         },
1224         {
1225                 .vendor         = PCI_VENDOR_ID_INTEL,
1226                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1227                 .subvendor      = PCI_ANY_ID,
1228                 .subdevice      = PCI_ANY_ID,
1229                 .setup          = skip_tx_en_setup,
1230         },
1231         {
1232                 .vendor         = PCI_VENDOR_ID_INTEL,
1233                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1234                 .subvendor      = PCI_ANY_ID,
1235                 .subdevice      = PCI_ANY_ID,
1236                 .setup          = ce4100_serial_setup,
1237         },
1238         /*
1239          * ITE
1240          */
1241         {
1242                 .vendor         = PCI_VENDOR_ID_ITE,
1243                 .device         = PCI_DEVICE_ID_ITE_8872,
1244                 .subvendor      = PCI_ANY_ID,
1245                 .subdevice      = PCI_ANY_ID,
1246                 .init           = pci_ite887x_init,
1247                 .setup          = pci_default_setup,
1248                 .exit           = __devexit_p(pci_ite887x_exit),
1249         },
1250         /*
1251          * National Instruments
1252          */
1253         {
1254                 .vendor         = PCI_VENDOR_ID_NI,
1255                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1256                 .subvendor      = PCI_ANY_ID,
1257                 .subdevice      = PCI_ANY_ID,
1258                 .init           = pci_ni8420_init,
1259                 .setup          = pci_default_setup,
1260                 .exit           = __devexit_p(pci_ni8420_exit),
1261         },
1262         {
1263                 .vendor         = PCI_VENDOR_ID_NI,
1264                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1265                 .subvendor      = PCI_ANY_ID,
1266                 .subdevice      = PCI_ANY_ID,
1267                 .init           = pci_ni8420_init,
1268                 .setup          = pci_default_setup,
1269                 .exit           = __devexit_p(pci_ni8420_exit),
1270         },
1271         {
1272                 .vendor         = PCI_VENDOR_ID_NI,
1273                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1274                 .subvendor      = PCI_ANY_ID,
1275                 .subdevice      = PCI_ANY_ID,
1276                 .init           = pci_ni8420_init,
1277                 .setup          = pci_default_setup,
1278                 .exit           = __devexit_p(pci_ni8420_exit),
1279         },
1280         {
1281                 .vendor         = PCI_VENDOR_ID_NI,
1282                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1283                 .subvendor      = PCI_ANY_ID,
1284                 .subdevice      = PCI_ANY_ID,
1285                 .init           = pci_ni8420_init,
1286                 .setup          = pci_default_setup,
1287                 .exit           = __devexit_p(pci_ni8420_exit),
1288         },
1289         {
1290                 .vendor         = PCI_VENDOR_ID_NI,
1291                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1292                 .subvendor      = PCI_ANY_ID,
1293                 .subdevice      = PCI_ANY_ID,
1294                 .init           = pci_ni8420_init,
1295                 .setup          = pci_default_setup,
1296                 .exit           = __devexit_p(pci_ni8420_exit),
1297         },
1298         {
1299                 .vendor         = PCI_VENDOR_ID_NI,
1300                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1301                 .subvendor      = PCI_ANY_ID,
1302                 .subdevice      = PCI_ANY_ID,
1303                 .init           = pci_ni8420_init,
1304                 .setup          = pci_default_setup,
1305                 .exit           = __devexit_p(pci_ni8420_exit),
1306         },
1307         {
1308                 .vendor         = PCI_VENDOR_ID_NI,
1309                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1310                 .subvendor      = PCI_ANY_ID,
1311                 .subdevice      = PCI_ANY_ID,
1312                 .init           = pci_ni8420_init,
1313                 .setup          = pci_default_setup,
1314                 .exit           = __devexit_p(pci_ni8420_exit),
1315         },
1316         {
1317                 .vendor         = PCI_VENDOR_ID_NI,
1318                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1319                 .subvendor      = PCI_ANY_ID,
1320                 .subdevice      = PCI_ANY_ID,
1321                 .init           = pci_ni8420_init,
1322                 .setup          = pci_default_setup,
1323                 .exit           = __devexit_p(pci_ni8420_exit),
1324         },
1325         {
1326                 .vendor         = PCI_VENDOR_ID_NI,
1327                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1328                 .subvendor      = PCI_ANY_ID,
1329                 .subdevice      = PCI_ANY_ID,
1330                 .init           = pci_ni8420_init,
1331                 .setup          = pci_default_setup,
1332                 .exit           = __devexit_p(pci_ni8420_exit),
1333         },
1334         {
1335                 .vendor         = PCI_VENDOR_ID_NI,
1336                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1337                 .subvendor      = PCI_ANY_ID,
1338                 .subdevice      = PCI_ANY_ID,
1339                 .init           = pci_ni8420_init,
1340                 .setup          = pci_default_setup,
1341                 .exit           = __devexit_p(pci_ni8420_exit),
1342         },
1343         {
1344                 .vendor         = PCI_VENDOR_ID_NI,
1345                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1346                 .subvendor      = PCI_ANY_ID,
1347                 .subdevice      = PCI_ANY_ID,
1348                 .init           = pci_ni8420_init,
1349                 .setup          = pci_default_setup,
1350                 .exit           = __devexit_p(pci_ni8420_exit),
1351         },
1352         {
1353                 .vendor         = PCI_VENDOR_ID_NI,
1354                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1355                 .subvendor      = PCI_ANY_ID,
1356                 .subdevice      = PCI_ANY_ID,
1357                 .init           = pci_ni8420_init,
1358                 .setup          = pci_default_setup,
1359                 .exit           = __devexit_p(pci_ni8420_exit),
1360         },
1361         {
1362                 .vendor         = PCI_VENDOR_ID_NI,
1363                 .device         = PCI_ANY_ID,
1364                 .subvendor      = PCI_ANY_ID,
1365                 .subdevice      = PCI_ANY_ID,
1366                 .init           = pci_ni8430_init,
1367                 .setup          = pci_ni8430_setup,
1368                 .exit           = __devexit_p(pci_ni8430_exit),
1369         },
1370         /*
1371          * Panacom
1372          */
1373         {
1374                 .vendor         = PCI_VENDOR_ID_PANACOM,
1375                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1376                 .subvendor      = PCI_ANY_ID,
1377                 .subdevice      = PCI_ANY_ID,
1378                 .init           = pci_plx9050_init,
1379                 .setup          = pci_default_setup,
1380                 .exit           = __devexit_p(pci_plx9050_exit),
1381         },
1382         {
1383                 .vendor         = PCI_VENDOR_ID_PANACOM,
1384                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1385                 .subvendor      = PCI_ANY_ID,
1386                 .subdevice      = PCI_ANY_ID,
1387                 .init           = pci_plx9050_init,
1388                 .setup          = pci_default_setup,
1389                 .exit           = __devexit_p(pci_plx9050_exit),
1390         },
1391         /*
1392          * PLX
1393          */
1394         {
1395                 .vendor         = PCI_VENDOR_ID_PLX,
1396                 .device         = PCI_DEVICE_ID_PLX_9030,
1397                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1398                 .subdevice      = PCI_ANY_ID,
1399                 .setup          = pci_default_setup,
1400         },
1401         {
1402                 .vendor         = PCI_VENDOR_ID_PLX,
1403                 .device         = PCI_DEVICE_ID_PLX_9050,
1404                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1405                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1406                 .init           = pci_plx9050_init,
1407                 .setup          = pci_default_setup,
1408                 .exit           = __devexit_p(pci_plx9050_exit),
1409         },
1410         {
1411                 .vendor         = PCI_VENDOR_ID_PLX,
1412                 .device         = PCI_DEVICE_ID_PLX_9050,
1413                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1414                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1415                 .init           = pci_plx9050_init,
1416                 .setup          = pci_default_setup,
1417                 .exit           = __devexit_p(pci_plx9050_exit),
1418         },
1419         {
1420                 .vendor         = PCI_VENDOR_ID_PLX,
1421                 .device         = PCI_DEVICE_ID_PLX_9050,
1422                 .subvendor      = PCI_VENDOR_ID_PLX,
1423                 .subdevice      = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1424                 .init           = pci_plx9050_init,
1425                 .setup          = pci_default_setup,
1426                 .exit           = __devexit_p(pci_plx9050_exit),
1427         },
1428         {
1429                 .vendor         = PCI_VENDOR_ID_PLX,
1430                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1431                 .subvendor      = PCI_VENDOR_ID_PLX,
1432                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1433                 .init           = pci_plx9050_init,
1434                 .setup          = pci_default_setup,
1435                 .exit           = __devexit_p(pci_plx9050_exit),
1436         },
1437         /*
1438          * SBS Technologies, Inc., PMC-OCTALPRO 232
1439          */
1440         {
1441                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1442                 .device         = PCI_DEVICE_ID_OCTPRO,
1443                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1444                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1445                 .init           = sbs_init,
1446                 .setup          = sbs_setup,
1447                 .exit           = __devexit_p(sbs_exit),
1448         },
1449         /*
1450          * SBS Technologies, Inc., PMC-OCTALPRO 422
1451          */
1452         {
1453                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1454                 .device         = PCI_DEVICE_ID_OCTPRO,
1455                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1456                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1457                 .init           = sbs_init,
1458                 .setup          = sbs_setup,
1459                 .exit           = __devexit_p(sbs_exit),
1460         },
1461         /*
1462          * SBS Technologies, Inc., P-Octal 232
1463          */
1464         {
1465                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1466                 .device         = PCI_DEVICE_ID_OCTPRO,
1467                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1468                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1469                 .init           = sbs_init,
1470                 .setup          = sbs_setup,
1471                 .exit           = __devexit_p(sbs_exit),
1472         },
1473         /*
1474          * SBS Technologies, Inc., P-Octal 422
1475          */
1476         {
1477                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1478                 .device         = PCI_DEVICE_ID_OCTPRO,
1479                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1480                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1481                 .init           = sbs_init,
1482                 .setup          = sbs_setup,
1483                 .exit           = __devexit_p(sbs_exit),
1484         },
1485         /*
1486          * SIIG cards - these may be called via parport_serial
1487          */
1488         {
1489                 .vendor         = PCI_VENDOR_ID_SIIG,
1490                 .device         = PCI_ANY_ID,
1491                 .subvendor      = PCI_ANY_ID,
1492                 .subdevice      = PCI_ANY_ID,
1493                 .init           = pci_siig_init,
1494                 .setup          = pci_siig_setup,
1495         },
1496         /*
1497          * Titan cards
1498          */
1499         {
1500                 .vendor         = PCI_VENDOR_ID_TITAN,
1501                 .device         = PCI_DEVICE_ID_TITAN_400L,
1502                 .subvendor      = PCI_ANY_ID,
1503                 .subdevice      = PCI_ANY_ID,
1504                 .setup          = titan_400l_800l_setup,
1505         },
1506         {
1507                 .vendor         = PCI_VENDOR_ID_TITAN,
1508                 .device         = PCI_DEVICE_ID_TITAN_800L,
1509                 .subvendor      = PCI_ANY_ID,
1510                 .subdevice      = PCI_ANY_ID,
1511                 .setup          = titan_400l_800l_setup,
1512         },
1513         /*
1514          * Timedia cards
1515          */
1516         {
1517                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1518                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1519                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1520                 .subdevice      = PCI_ANY_ID,
1521                 .probe          = pci_timedia_probe,
1522                 .init           = pci_timedia_init,
1523                 .setup          = pci_timedia_setup,
1524         },
1525         {
1526                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1527                 .device         = PCI_ANY_ID,
1528                 .subvendor      = PCI_ANY_ID,
1529                 .subdevice      = PCI_ANY_ID,
1530                 .setup          = pci_timedia_setup,
1531         },
1532         /*
1533          * Exar cards
1534          */
1535         {
1536                 .vendor = PCI_VENDOR_ID_EXAR,
1537                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1538                 .subvendor      = PCI_ANY_ID,
1539                 .subdevice      = PCI_ANY_ID,
1540                 .setup          = pci_xr17c154_setup,
1541         },
1542         {
1543                 .vendor = PCI_VENDOR_ID_EXAR,
1544                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1545                 .subvendor      = PCI_ANY_ID,
1546                 .subdevice      = PCI_ANY_ID,
1547                 .setup          = pci_xr17c154_setup,
1548         },
1549         {
1550                 .vendor = PCI_VENDOR_ID_EXAR,
1551                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1552                 .subvendor      = PCI_ANY_ID,
1553                 .subdevice      = PCI_ANY_ID,
1554                 .setup          = pci_xr17c154_setup,
1555         },
1556         /*
1557          * Xircom cards
1558          */
1559         {
1560                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1561                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1562                 .subvendor      = PCI_ANY_ID,
1563                 .subdevice      = PCI_ANY_ID,
1564                 .init           = pci_xircom_init,
1565                 .setup          = pci_default_setup,
1566         },
1567         /*
1568          * Netmos cards - these may be called via parport_serial
1569          */
1570         {
1571                 .vendor         = PCI_VENDOR_ID_NETMOS,
1572                 .device         = PCI_ANY_ID,
1573                 .subvendor      = PCI_ANY_ID,
1574                 .subdevice      = PCI_ANY_ID,
1575                 .init           = pci_netmos_init,
1576                 .setup          = pci_netmos_9900_setup,
1577         },
1578         /*
1579          * For Oxford Semiconductor Tornado based devices
1580          */
1581         {
1582                 .vendor         = PCI_VENDOR_ID_OXSEMI,
1583                 .device         = PCI_ANY_ID,
1584                 .subvendor      = PCI_ANY_ID,
1585                 .subdevice      = PCI_ANY_ID,
1586                 .init           = pci_oxsemi_tornado_init,
1587                 .setup          = pci_default_setup,
1588         },
1589         {
1590                 .vendor         = PCI_VENDOR_ID_MAINPINE,
1591                 .device         = PCI_ANY_ID,
1592                 .subvendor      = PCI_ANY_ID,
1593                 .subdevice      = PCI_ANY_ID,
1594                 .init           = pci_oxsemi_tornado_init,
1595                 .setup          = pci_default_setup,
1596         },
1597         {
1598                 .vendor         = PCI_VENDOR_ID_DIGI,
1599                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1600                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
1601                 .subdevice              = PCI_ANY_ID,
1602                 .init                   = pci_oxsemi_tornado_init,
1603                 .setup          = pci_default_setup,
1604         },
1605         {
1606                 .vendor         = PCI_VENDOR_ID_INTEL,
1607                 .device         = 0x8811,
1608                 .subvendor      = PCI_ANY_ID,
1609                 .subdevice      = PCI_ANY_ID,
1610                 .init           = pci_eg20t_init,
1611                 .setup          = pci_default_setup,
1612         },
1613         {
1614                 .vendor         = PCI_VENDOR_ID_INTEL,
1615                 .device         = 0x8812,
1616                 .subvendor      = PCI_ANY_ID,
1617                 .subdevice      = PCI_ANY_ID,
1618                 .init           = pci_eg20t_init,
1619                 .setup          = pci_default_setup,
1620         },
1621         {
1622                 .vendor         = PCI_VENDOR_ID_INTEL,
1623                 .device         = 0x8813,
1624                 .subvendor      = PCI_ANY_ID,
1625                 .subdevice      = PCI_ANY_ID,
1626                 .init           = pci_eg20t_init,
1627                 .setup          = pci_default_setup,
1628         },
1629         {
1630                 .vendor         = PCI_VENDOR_ID_INTEL,
1631                 .device         = 0x8814,
1632                 .subvendor      = PCI_ANY_ID,
1633                 .subdevice      = PCI_ANY_ID,
1634                 .init           = pci_eg20t_init,
1635                 .setup          = pci_default_setup,
1636         },
1637         {
1638                 .vendor         = 0x10DB,
1639                 .device         = 0x8027,
1640                 .subvendor      = PCI_ANY_ID,
1641                 .subdevice      = PCI_ANY_ID,
1642                 .init           = pci_eg20t_init,
1643                 .setup          = pci_default_setup,
1644         },
1645         {
1646                 .vendor         = 0x10DB,
1647                 .device         = 0x8028,
1648                 .subvendor      = PCI_ANY_ID,
1649                 .subdevice      = PCI_ANY_ID,
1650                 .init           = pci_eg20t_init,
1651                 .setup          = pci_default_setup,
1652         },
1653         {
1654                 .vendor         = 0x10DB,
1655                 .device         = 0x8029,
1656                 .subvendor      = PCI_ANY_ID,
1657                 .subdevice      = PCI_ANY_ID,
1658                 .init           = pci_eg20t_init,
1659                 .setup          = pci_default_setup,
1660         },
1661         {
1662                 .vendor         = 0x10DB,
1663                 .device         = 0x800C,
1664                 .subvendor      = PCI_ANY_ID,
1665                 .subdevice      = PCI_ANY_ID,
1666                 .init           = pci_eg20t_init,
1667                 .setup          = pci_default_setup,
1668         },
1669         {
1670                 .vendor         = 0x10DB,
1671                 .device         = 0x800D,
1672                 .subvendor      = PCI_ANY_ID,
1673                 .subdevice      = PCI_ANY_ID,
1674                 .init           = pci_eg20t_init,
1675                 .setup          = pci_default_setup,
1676         },
1677         /*
1678          * Cronyx Omega PCI (PLX-chip based)
1679          */
1680         {
1681                 .vendor         = PCI_VENDOR_ID_PLX,
1682                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1683                 .subvendor      = PCI_ANY_ID,
1684                 .subdevice      = PCI_ANY_ID,
1685                 .setup          = pci_omegapci_setup,
1686          },
1687         /*
1688          * Broadcom TruManage (NetXtreme)
1689          */
1690         {
1691                 .vendor         = PCI_VENDOR_ID_BROADCOM,
1692                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
1693                 .subvendor      = PCI_ANY_ID,
1694                 .subdevice      = PCI_ANY_ID,
1695                 .setup          = pci_brcm_trumanage_setup,
1696         },
1697
1698         /*
1699          * Default "match everything" terminator entry
1700          */
1701         {
1702                 .vendor         = PCI_ANY_ID,
1703                 .device         = PCI_ANY_ID,
1704                 .subvendor      = PCI_ANY_ID,
1705                 .subdevice      = PCI_ANY_ID,
1706                 .setup          = pci_default_setup,
1707         }
1708 };
1709
1710 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1711 {
1712         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1713 }
1714
1715 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1716 {
1717         struct pci_serial_quirk *quirk;
1718
1719         for (quirk = pci_serial_quirks; ; quirk++)
1720                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1721                     quirk_id_matches(quirk->device, dev->device) &&
1722                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1723                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1724                         break;
1725         return quirk;
1726 }
1727
1728 static inline int get_pci_irq(struct pci_dev *dev,
1729                                 const struct pciserial_board *board)
1730 {
1731         if (board->flags & FL_NOIRQ)
1732                 return 0;
1733         else
1734                 return dev->irq;
1735 }
1736
1737 /*
1738  * This is the configuration table for all of the PCI serial boards
1739  * which we support.  It is directly indexed by the pci_board_num_t enum
1740  * value, which is encoded in the pci_device_id PCI probe table's
1741  * driver_data member.
1742  *
1743  * The makeup of these names are:
1744  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1745  *
1746  *  bn          = PCI BAR number
1747  *  bt          = Index using PCI BARs
1748  *  n           = number of serial ports
1749  *  baud        = baud rate
1750  *  offsetinhex = offset for each sequential port (in hex)
1751  *
1752  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1753  *
1754  * Please note: in theory if n = 1, _bt infix should make no difference.
1755  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1756  */
1757 enum pci_board_num_t {
1758         pbn_default = 0,
1759
1760         pbn_b0_1_115200,
1761         pbn_b0_2_115200,
1762         pbn_b0_4_115200,
1763         pbn_b0_5_115200,
1764         pbn_b0_8_115200,
1765
1766         pbn_b0_1_921600,
1767         pbn_b0_2_921600,
1768         pbn_b0_4_921600,
1769
1770         pbn_b0_2_1130000,
1771
1772         pbn_b0_4_1152000,
1773
1774         pbn_b0_2_1843200,
1775         pbn_b0_4_1843200,
1776
1777         pbn_b0_2_1843200_200,
1778         pbn_b0_4_1843200_200,
1779         pbn_b0_8_1843200_200,
1780
1781         pbn_b0_1_4000000,
1782
1783         pbn_b0_bt_1_115200,
1784         pbn_b0_bt_2_115200,
1785         pbn_b0_bt_4_115200,
1786         pbn_b0_bt_8_115200,
1787
1788         pbn_b0_bt_1_460800,
1789         pbn_b0_bt_2_460800,
1790         pbn_b0_bt_4_460800,
1791
1792         pbn_b0_bt_1_921600,
1793         pbn_b0_bt_2_921600,
1794         pbn_b0_bt_4_921600,
1795         pbn_b0_bt_8_921600,
1796
1797         pbn_b1_1_115200,
1798         pbn_b1_2_115200,
1799         pbn_b1_4_115200,
1800         pbn_b1_8_115200,
1801         pbn_b1_16_115200,
1802
1803         pbn_b1_1_921600,
1804         pbn_b1_2_921600,
1805         pbn_b1_4_921600,
1806         pbn_b1_8_921600,
1807
1808         pbn_b1_2_1250000,
1809
1810         pbn_b1_bt_1_115200,
1811         pbn_b1_bt_2_115200,
1812         pbn_b1_bt_4_115200,
1813
1814         pbn_b1_bt_2_921600,
1815
1816         pbn_b1_1_1382400,
1817         pbn_b1_2_1382400,
1818         pbn_b1_4_1382400,
1819         pbn_b1_8_1382400,
1820
1821         pbn_b2_1_115200,
1822         pbn_b2_2_115200,
1823         pbn_b2_4_115200,
1824         pbn_b2_8_115200,
1825
1826         pbn_b2_1_460800,
1827         pbn_b2_4_460800,
1828         pbn_b2_8_460800,
1829         pbn_b2_16_460800,
1830
1831         pbn_b2_1_921600,
1832         pbn_b2_4_921600,
1833         pbn_b2_8_921600,
1834
1835         pbn_b2_8_1152000,
1836
1837         pbn_b2_bt_1_115200,
1838         pbn_b2_bt_2_115200,
1839         pbn_b2_bt_4_115200,
1840
1841         pbn_b2_bt_2_921600,
1842         pbn_b2_bt_4_921600,
1843
1844         pbn_b3_2_115200,
1845         pbn_b3_4_115200,
1846         pbn_b3_8_115200,
1847
1848         pbn_b4_bt_2_921600,
1849         pbn_b4_bt_4_921600,
1850         pbn_b4_bt_8_921600,
1851
1852         /*
1853          * Board-specific versions.
1854          */
1855         pbn_panacom,
1856         pbn_panacom2,
1857         pbn_panacom4,
1858         pbn_exsys_4055,
1859         pbn_plx_romulus,
1860         pbn_oxsemi,
1861         pbn_oxsemi_1_4000000,
1862         pbn_oxsemi_2_4000000,
1863         pbn_oxsemi_4_4000000,
1864         pbn_oxsemi_8_4000000,
1865         pbn_intel_i960,
1866         pbn_sgi_ioc3,
1867         pbn_computone_4,
1868         pbn_computone_6,
1869         pbn_computone_8,
1870         pbn_sbsxrsio,
1871         pbn_exar_XR17C152,
1872         pbn_exar_XR17C154,
1873         pbn_exar_XR17C158,
1874         pbn_exar_ibm_saturn,
1875         pbn_pasemi_1682M,
1876         pbn_ni8430_2,
1877         pbn_ni8430_4,
1878         pbn_ni8430_8,
1879         pbn_ni8430_16,
1880         pbn_ADDIDATA_PCIe_1_3906250,
1881         pbn_ADDIDATA_PCIe_2_3906250,
1882         pbn_ADDIDATA_PCIe_4_3906250,
1883         pbn_ADDIDATA_PCIe_8_3906250,
1884         pbn_ce4100_1_115200,
1885         pbn_omegapci,
1886         pbn_NETMOS9900_2s_115200,
1887         pbn_brcm_trumanage,
1888 };
1889
1890 /*
1891  * uart_offset - the space between channels
1892  * reg_shift   - describes how the UART registers are mapped
1893  *               to PCI memory by the card.
1894  * For example IER register on SBS, Inc. PMC-OctPro is located at
1895  * offset 0x10 from the UART base, while UART_IER is defined as 1
1896  * in include/linux/serial_reg.h,
1897  * see first lines of serial_in() and serial_out() in 8250.c
1898 */
1899
1900 static struct pciserial_board pci_boards[] __devinitdata = {
1901         [pbn_default] = {
1902                 .flags          = FL_BASE0,
1903                 .num_ports      = 1,
1904                 .base_baud      = 115200,
1905                 .uart_offset    = 8,
1906         },
1907         [pbn_b0_1_115200] = {
1908                 .flags          = FL_BASE0,
1909                 .num_ports      = 1,
1910                 .base_baud      = 115200,
1911                 .uart_offset    = 8,
1912         },
1913         [pbn_b0_2_115200] = {
1914                 .flags          = FL_BASE0,
1915                 .num_ports      = 2,
1916                 .base_baud      = 115200,
1917                 .uart_offset    = 8,
1918         },
1919         [pbn_b0_4_115200] = {
1920                 .flags          = FL_BASE0,
1921                 .num_ports      = 4,
1922                 .base_baud      = 115200,
1923                 .uart_offset    = 8,
1924         },
1925         [pbn_b0_5_115200] = {
1926                 .flags          = FL_BASE0,
1927                 .num_ports      = 5,
1928                 .base_baud      = 115200,
1929                 .uart_offset    = 8,
1930         },
1931         [pbn_b0_8_115200] = {
1932                 .flags          = FL_BASE0,
1933                 .num_ports      = 8,
1934                 .base_baud      = 115200,
1935                 .uart_offset    = 8,
1936         },
1937         [pbn_b0_1_921600] = {
1938                 .flags          = FL_BASE0,
1939                 .num_ports      = 1,
1940                 .base_baud      = 921600,
1941                 .uart_offset    = 8,
1942         },
1943         [pbn_b0_2_921600] = {
1944                 .flags          = FL_BASE0,
1945                 .num_ports      = 2,
1946                 .base_baud      = 921600,
1947                 .uart_offset    = 8,
1948         },
1949         [pbn_b0_4_921600] = {
1950                 .flags          = FL_BASE0,
1951                 .num_ports      = 4,
1952                 .base_baud      = 921600,
1953                 .uart_offset    = 8,
1954         },
1955
1956         [pbn_b0_2_1130000] = {
1957                 .flags          = FL_BASE0,
1958                 .num_ports      = 2,
1959                 .base_baud      = 1130000,
1960                 .uart_offset    = 8,
1961         },
1962
1963         [pbn_b0_4_1152000] = {
1964                 .flags          = FL_BASE0,
1965                 .num_ports      = 4,
1966                 .base_baud      = 1152000,
1967                 .uart_offset    = 8,
1968         },
1969
1970         [pbn_b0_2_1843200] = {
1971                 .flags          = FL_BASE0,
1972                 .num_ports      = 2,
1973                 .base_baud      = 1843200,
1974                 .uart_offset    = 8,
1975         },
1976         [pbn_b0_4_1843200] = {
1977                 .flags          = FL_BASE0,
1978                 .num_ports      = 4,
1979                 .base_baud      = 1843200,
1980                 .uart_offset    = 8,
1981         },
1982
1983         [pbn_b0_2_1843200_200] = {
1984                 .flags          = FL_BASE0,
1985                 .num_ports      = 2,
1986                 .base_baud      = 1843200,
1987                 .uart_offset    = 0x200,
1988         },
1989         [pbn_b0_4_1843200_200] = {
1990                 .flags          = FL_BASE0,
1991                 .num_ports      = 4,
1992                 .base_baud      = 1843200,
1993                 .uart_offset    = 0x200,
1994         },
1995         [pbn_b0_8_1843200_200] = {
1996                 .flags          = FL_BASE0,
1997                 .num_ports      = 8,
1998                 .base_baud      = 1843200,
1999                 .uart_offset    = 0x200,
2000         },
2001         [pbn_b0_1_4000000] = {
2002                 .flags          = FL_BASE0,
2003                 .num_ports      = 1,
2004                 .base_baud      = 4000000,
2005                 .uart_offset    = 8,
2006         },
2007
2008         [pbn_b0_bt_1_115200] = {
2009                 .flags          = FL_BASE0|FL_BASE_BARS,
2010                 .num_ports      = 1,
2011                 .base_baud      = 115200,
2012                 .uart_offset    = 8,
2013         },
2014         [pbn_b0_bt_2_115200] = {
2015                 .flags          = FL_BASE0|FL_BASE_BARS,
2016                 .num_ports      = 2,
2017                 .base_baud      = 115200,
2018                 .uart_offset    = 8,
2019         },
2020         [pbn_b0_bt_4_115200] = {
2021                 .flags          = FL_BASE0|FL_BASE_BARS,
2022                 .num_ports      = 4,
2023                 .base_baud      = 115200,
2024                 .uart_offset    = 8,
2025         },
2026         [pbn_b0_bt_8_115200] = {
2027                 .flags          = FL_BASE0|FL_BASE_BARS,
2028                 .num_ports      = 8,
2029                 .base_baud      = 115200,
2030                 .uart_offset    = 8,
2031         },
2032
2033         [pbn_b0_bt_1_460800] = {
2034                 .flags          = FL_BASE0|FL_BASE_BARS,
2035                 .num_ports      = 1,
2036                 .base_baud      = 460800,
2037                 .uart_offset    = 8,
2038         },
2039         [pbn_b0_bt_2_460800] = {
2040                 .flags          = FL_BASE0|FL_BASE_BARS,
2041                 .num_ports      = 2,
2042                 .base_baud      = 460800,
2043                 .uart_offset    = 8,
2044         },
2045         [pbn_b0_bt_4_460800] = {
2046                 .flags          = FL_BASE0|FL_BASE_BARS,
2047                 .num_ports      = 4,
2048                 .base_baud      = 460800,
2049                 .uart_offset    = 8,
2050         },
2051
2052         [pbn_b0_bt_1_921600] = {
2053                 .flags          = FL_BASE0|FL_BASE_BARS,
2054                 .num_ports      = 1,
2055                 .base_baud      = 921600,
2056                 .uart_offset    = 8,
2057         },
2058         [pbn_b0_bt_2_921600] = {
2059                 .flags          = FL_BASE0|FL_BASE_BARS,
2060                 .num_ports      = 2,
2061                 .base_baud      = 921600,
2062                 .uart_offset    = 8,
2063         },
2064         [pbn_b0_bt_4_921600] = {
2065                 .flags          = FL_BASE0|FL_BASE_BARS,
2066                 .num_ports      = 4,
2067                 .base_baud      = 921600,
2068                 .uart_offset    = 8,
2069         },
2070         [pbn_b0_bt_8_921600] = {
2071                 .flags          = FL_BASE0|FL_BASE_BARS,
2072                 .num_ports      = 8,
2073                 .base_baud      = 921600,
2074                 .uart_offset    = 8,
2075         },
2076
2077         [pbn_b1_1_115200] = {
2078                 .flags          = FL_BASE1,
2079                 .num_ports      = 1,
2080                 .base_baud      = 115200,
2081                 .uart_offset    = 8,
2082         },
2083         [pbn_b1_2_115200] = {
2084                 .flags          = FL_BASE1,
2085                 .num_ports      = 2,
2086                 .base_baud      = 115200,
2087                 .uart_offset    = 8,
2088         },
2089         [pbn_b1_4_115200] = {
2090                 .flags          = FL_BASE1,
2091                 .num_ports      = 4,
2092                 .base_baud      = 115200,
2093                 .uart_offset    = 8,
2094         },
2095         [pbn_b1_8_115200] = {
2096                 .flags          = FL_BASE1,
2097                 .num_ports      = 8,
2098                 .base_baud      = 115200,
2099                 .uart_offset    = 8,
2100         },
2101         [pbn_b1_16_115200] = {
2102                 .flags          = FL_BASE1,
2103                 .num_ports      = 16,
2104                 .base_baud      = 115200,
2105                 .uart_offset    = 8,
2106         },
2107
2108         [pbn_b1_1_921600] = {
2109                 .flags          = FL_BASE1,
2110                 .num_ports      = 1,
2111                 .base_baud      = 921600,
2112                 .uart_offset    = 8,
2113         },
2114         [pbn_b1_2_921600] = {
2115                 .flags          = FL_BASE1,
2116                 .num_ports      = 2,
2117                 .base_baud      = 921600,
2118                 .uart_offset    = 8,
2119         },
2120         [pbn_b1_4_921600] = {
2121                 .flags          = FL_BASE1,
2122                 .num_ports      = 4,
2123                 .base_baud      = 921600,
2124                 .uart_offset    = 8,
2125         },
2126         [pbn_b1_8_921600] = {
2127                 .flags          = FL_BASE1,
2128                 .num_ports      = 8,
2129                 .base_baud      = 921600,
2130                 .uart_offset    = 8,
2131         },
2132         [pbn_b1_2_1250000] = {
2133                 .flags          = FL_BASE1,
2134                 .num_ports      = 2,
2135                 .base_baud      = 1250000,
2136                 .uart_offset    = 8,
2137         },
2138
2139         [pbn_b1_bt_1_115200] = {
2140                 .flags          = FL_BASE1|FL_BASE_BARS,
2141                 .num_ports      = 1,
2142                 .base_baud      = 115200,
2143                 .uart_offset    = 8,
2144         },
2145         [pbn_b1_bt_2_115200] = {
2146                 .flags          = FL_BASE1|FL_BASE_BARS,
2147                 .num_ports      = 2,
2148                 .base_baud      = 115200,
2149                 .uart_offset    = 8,
2150         },
2151         [pbn_b1_bt_4_115200] = {
2152                 .flags          = FL_BASE1|FL_BASE_BARS,
2153                 .num_ports      = 4,
2154                 .base_baud      = 115200,
2155                 .uart_offset    = 8,
2156         },
2157
2158         [pbn_b1_bt_2_921600] = {
2159                 .flags          = FL_BASE1|FL_BASE_BARS,
2160                 .num_ports      = 2,
2161                 .base_baud      = 921600,
2162                 .uart_offset    = 8,
2163         },
2164
2165         [pbn_b1_1_1382400] = {
2166                 .flags          = FL_BASE1,
2167                 .num_ports      = 1,
2168                 .base_baud      = 1382400,
2169                 .uart_offset    = 8,
2170         },
2171         [pbn_b1_2_1382400] = {
2172                 .flags          = FL_BASE1,
2173                 .num_ports      = 2,
2174                 .base_baud      = 1382400,
2175                 .uart_offset    = 8,
2176         },
2177         [pbn_b1_4_1382400] = {
2178                 .flags          = FL_BASE1,
2179                 .num_ports      = 4,
2180                 .base_baud      = 1382400,
2181                 .uart_offset    = 8,
2182         },
2183         [pbn_b1_8_1382400] = {
2184                 .flags          = FL_BASE1,
2185                 .num_ports      = 8,
2186                 .base_baud      = 1382400,
2187                 .uart_offset    = 8,
2188         },
2189
2190         [pbn_b2_1_115200] = {
2191                 .flags          = FL_BASE2,
2192                 .num_ports      = 1,
2193                 .base_baud      = 115200,
2194                 .uart_offset    = 8,
2195         },
2196         [pbn_b2_2_115200] = {
2197                 .flags          = FL_BASE2,
2198                 .num_ports      = 2,
2199                 .base_baud      = 115200,
2200                 .uart_offset    = 8,
2201         },
2202         [pbn_b2_4_115200] = {
2203                 .flags          = FL_BASE2,
2204                 .num_ports      = 4,
2205                 .base_baud      = 115200,
2206                 .uart_offset    = 8,
2207         },
2208         [pbn_b2_8_115200] = {
2209                 .flags          = FL_BASE2,
2210                 .num_ports      = 8,
2211                 .base_baud      = 115200,
2212                 .uart_offset    = 8,
2213         },
2214
2215         [pbn_b2_1_460800] = {
2216                 .flags          = FL_BASE2,
2217                 .num_ports      = 1,
2218                 .base_baud      = 460800,
2219                 .uart_offset    = 8,
2220         },
2221         [pbn_b2_4_460800] = {
2222                 .flags          = FL_BASE2,
2223                 .num_ports      = 4,
2224                 .base_baud      = 460800,
2225                 .uart_offset    = 8,
2226         },
2227         [pbn_b2_8_460800] = {
2228                 .flags          = FL_BASE2,
2229                 .num_ports      = 8,
2230                 .base_baud      = 460800,
2231                 .uart_offset    = 8,
2232         },
2233         [pbn_b2_16_460800] = {
2234                 .flags          = FL_BASE2,
2235                 .num_ports      = 16,
2236                 .base_baud      = 460800,
2237                 .uart_offset    = 8,
2238          },
2239
2240         [pbn_b2_1_921600] = {
2241                 .flags          = FL_BASE2,
2242                 .num_ports      = 1,
2243                 .base_baud      = 921600,
2244                 .uart_offset    = 8,
2245         },
2246         [pbn_b2_4_921600] = {
2247                 .flags          = FL_BASE2,
2248                 .num_ports      = 4,
2249                 .base_baud      = 921600,
2250                 .uart_offset    = 8,
2251         },
2252         [pbn_b2_8_921600] = {
2253                 .flags          = FL_BASE2,
2254                 .num_ports      = 8,
2255                 .base_baud      = 921600,
2256                 .uart_offset    = 8,
2257         },
2258
2259         [pbn_b2_8_1152000] = {
2260                 .flags          = FL_BASE2,
2261                 .num_ports      = 8,
2262                 .base_baud      = 1152000,
2263                 .uart_offset    = 8,
2264         },
2265
2266         [pbn_b2_bt_1_115200] = {
2267                 .flags          = FL_BASE2|FL_BASE_BARS,
2268                 .num_ports      = 1,
2269                 .base_baud      = 115200,
2270                 .uart_offset    = 8,
2271         },
2272         [pbn_b2_bt_2_115200] = {
2273                 .flags          = FL_BASE2|FL_BASE_BARS,
2274                 .num_ports      = 2,
2275                 .base_baud      = 115200,
2276                 .uart_offset    = 8,
2277         },
2278         [pbn_b2_bt_4_115200] = {
2279                 .flags          = FL_BASE2|FL_BASE_BARS,
2280                 .num_ports      = 4,
2281                 .base_baud      = 115200,
2282                 .uart_offset    = 8,
2283         },
2284
2285         [pbn_b2_bt_2_921600] = {
2286                 .flags          = FL_BASE2|FL_BASE_BARS,
2287                 .num_ports      = 2,
2288                 .base_baud      = 921600,
2289                 .uart_offset    = 8,
2290         },
2291         [pbn_b2_bt_4_921600] = {
2292                 .flags          = FL_BASE2|FL_BASE_BARS,
2293                 .num_ports      = 4,
2294                 .base_baud      = 921600,
2295                 .uart_offset    = 8,
2296         },
2297
2298         [pbn_b3_2_115200] = {
2299                 .flags          = FL_BASE3,
2300                 .num_ports      = 2,
2301                 .base_baud      = 115200,
2302                 .uart_offset    = 8,
2303         },
2304         [pbn_b3_4_115200] = {
2305                 .flags          = FL_BASE3,
2306                 .num_ports      = 4,
2307                 .base_baud      = 115200,
2308                 .uart_offset    = 8,
2309         },
2310         [pbn_b3_8_115200] = {
2311                 .flags          = FL_BASE3,
2312                 .num_ports      = 8,
2313                 .base_baud      = 115200,
2314                 .uart_offset    = 8,
2315         },
2316
2317         [pbn_b4_bt_2_921600] = {
2318                 .flags          = FL_BASE4,
2319                 .num_ports      = 2,
2320                 .base_baud      = 921600,
2321                 .uart_offset    = 8,
2322         },
2323         [pbn_b4_bt_4_921600] = {
2324                 .flags          = FL_BASE4,
2325                 .num_ports      = 4,
2326                 .base_baud      = 921600,
2327                 .uart_offset    = 8,
2328         },
2329         [pbn_b4_bt_8_921600] = {
2330                 .flags          = FL_BASE4,
2331                 .num_ports      = 8,
2332                 .base_baud      = 921600,
2333                 .uart_offset    = 8,
2334         },
2335
2336         /*
2337          * Entries following this are board-specific.
2338          */
2339
2340         /*
2341          * Panacom - IOMEM
2342          */
2343         [pbn_panacom] = {
2344                 .flags          = FL_BASE2,
2345                 .num_ports      = 2,
2346                 .base_baud      = 921600,
2347                 .uart_offset    = 0x400,
2348                 .reg_shift      = 7,
2349         },
2350         [pbn_panacom2] = {
2351                 .flags          = FL_BASE2|FL_BASE_BARS,
2352                 .num_ports      = 2,
2353                 .base_baud      = 921600,
2354                 .uart_offset    = 0x400,
2355                 .reg_shift      = 7,
2356         },
2357         [pbn_panacom4] = {
2358                 .flags          = FL_BASE2|FL_BASE_BARS,
2359                 .num_ports      = 4,
2360                 .base_baud      = 921600,
2361                 .uart_offset    = 0x400,
2362                 .reg_shift      = 7,
2363         },
2364
2365         [pbn_exsys_4055] = {
2366                 .flags          = FL_BASE2,
2367                 .num_ports      = 4,
2368                 .base_baud      = 115200,
2369                 .uart_offset    = 8,
2370         },
2371
2372         /* I think this entry is broken - the first_offset looks wrong --rmk */
2373         [pbn_plx_romulus] = {
2374                 .flags          = FL_BASE2,
2375                 .num_ports      = 4,
2376                 .base_baud      = 921600,
2377                 .uart_offset    = 8 << 2,
2378                 .reg_shift      = 2,
2379                 .first_offset   = 0x03,
2380         },
2381
2382         /*
2383          * This board uses the size of PCI Base region 0 to
2384          * signal now many ports are available
2385          */
2386         [pbn_oxsemi] = {
2387                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2388                 .num_ports      = 32,
2389                 .base_baud      = 115200,
2390                 .uart_offset    = 8,
2391         },
2392         [pbn_oxsemi_1_4000000] = {
2393                 .flags          = FL_BASE0,
2394                 .num_ports      = 1,
2395                 .base_baud      = 4000000,
2396                 .uart_offset    = 0x200,
2397                 .first_offset   = 0x1000,
2398         },
2399         [pbn_oxsemi_2_4000000] = {
2400                 .flags          = FL_BASE0,
2401                 .num_ports      = 2,
2402                 .base_baud      = 4000000,
2403                 .uart_offset    = 0x200,
2404                 .first_offset   = 0x1000,
2405         },
2406         [pbn_oxsemi_4_4000000] = {
2407                 .flags          = FL_BASE0,
2408                 .num_ports      = 4,
2409                 .base_baud      = 4000000,
2410                 .uart_offset    = 0x200,
2411                 .first_offset   = 0x1000,
2412         },
2413         [pbn_oxsemi_8_4000000] = {
2414                 .flags          = FL_BASE0,
2415                 .num_ports      = 8,
2416                 .base_baud      = 4000000,
2417                 .uart_offset    = 0x200,
2418                 .first_offset   = 0x1000,
2419         },
2420
2421
2422         /*
2423          * EKF addition for i960 Boards form EKF with serial port.
2424          * Max 256 ports.
2425          */
2426         [pbn_intel_i960] = {
2427                 .flags          = FL_BASE0,
2428                 .num_ports      = 32,
2429                 .base_baud      = 921600,
2430                 .uart_offset    = 8 << 2,
2431                 .reg_shift      = 2,
2432                 .first_offset   = 0x10000,
2433         },
2434         [pbn_sgi_ioc3] = {
2435                 .flags          = FL_BASE0|FL_NOIRQ,
2436                 .num_ports      = 1,
2437                 .base_baud      = 458333,
2438                 .uart_offset    = 8,
2439                 .reg_shift      = 0,
2440                 .first_offset   = 0x20178,
2441         },
2442
2443         /*
2444          * Computone - uses IOMEM.
2445          */
2446         [pbn_computone_4] = {
2447                 .flags          = FL_BASE0,
2448                 .num_ports      = 4,
2449                 .base_baud      = 921600,
2450                 .uart_offset    = 0x40,
2451                 .reg_shift      = 2,
2452                 .first_offset   = 0x200,
2453         },
2454         [pbn_computone_6] = {
2455                 .flags          = FL_BASE0,
2456                 .num_ports      = 6,
2457                 .base_baud      = 921600,
2458                 .uart_offset    = 0x40,
2459                 .reg_shift      = 2,
2460                 .first_offset   = 0x200,
2461         },
2462         [pbn_computone_8] = {
2463                 .flags          = FL_BASE0,
2464                 .num_ports      = 8,
2465                 .base_baud      = 921600,
2466                 .uart_offset    = 0x40,
2467                 .reg_shift      = 2,
2468                 .first_offset   = 0x200,
2469         },
2470         [pbn_sbsxrsio] = {
2471                 .flags          = FL_BASE0,
2472                 .num_ports      = 8,
2473                 .base_baud      = 460800,
2474                 .uart_offset    = 256,
2475                 .reg_shift      = 4,
2476         },
2477         /*
2478          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2479          *  Only basic 16550A support.
2480          *  XR17C15[24] are not tested, but they should work.
2481          */
2482         [pbn_exar_XR17C152] = {
2483                 .flags          = FL_BASE0,
2484                 .num_ports      = 2,
2485                 .base_baud      = 921600,
2486                 .uart_offset    = 0x200,
2487         },
2488         [pbn_exar_XR17C154] = {
2489                 .flags          = FL_BASE0,
2490                 .num_ports      = 4,
2491                 .base_baud      = 921600,
2492                 .uart_offset    = 0x200,
2493         },
2494         [pbn_exar_XR17C158] = {
2495                 .flags          = FL_BASE0,
2496                 .num_ports      = 8,
2497                 .base_baud      = 921600,
2498                 .uart_offset    = 0x200,
2499         },
2500         [pbn_exar_ibm_saturn] = {
2501                 .flags          = FL_BASE0,
2502                 .num_ports      = 1,
2503                 .base_baud      = 921600,
2504                 .uart_offset    = 0x200,
2505         },
2506
2507         /*
2508          * PA Semi PWRficient PA6T-1682M on-chip UART
2509          */
2510         [pbn_pasemi_1682M] = {
2511                 .flags          = FL_BASE0,
2512                 .num_ports      = 1,
2513                 .base_baud      = 8333333,
2514         },
2515         /*
2516          * National Instruments 843x
2517          */
2518         [pbn_ni8430_16] = {
2519                 .flags          = FL_BASE0,
2520                 .num_ports      = 16,
2521                 .base_baud      = 3686400,
2522                 .uart_offset    = 0x10,
2523                 .first_offset   = 0x800,
2524         },
2525         [pbn_ni8430_8] = {
2526                 .flags          = FL_BASE0,
2527                 .num_ports      = 8,
2528                 .base_baud      = 3686400,
2529                 .uart_offset    = 0x10,
2530                 .first_offset   = 0x800,
2531         },
2532         [pbn_ni8430_4] = {
2533                 .flags          = FL_BASE0,
2534                 .num_ports      = 4,
2535                 .base_baud      = 3686400,
2536                 .uart_offset    = 0x10,
2537                 .first_offset   = 0x800,
2538         },
2539         [pbn_ni8430_2] = {
2540                 .flags          = FL_BASE0,
2541                 .num_ports      = 2,
2542                 .base_baud      = 3686400,
2543                 .uart_offset    = 0x10,
2544                 .first_offset   = 0x800,
2545         },
2546         /*
2547          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2548          */
2549         [pbn_ADDIDATA_PCIe_1_3906250] = {
2550                 .flags          = FL_BASE0,
2551                 .num_ports      = 1,
2552                 .base_baud      = 3906250,
2553                 .uart_offset    = 0x200,
2554                 .first_offset   = 0x1000,
2555         },
2556         [pbn_ADDIDATA_PCIe_2_3906250] = {
2557                 .flags          = FL_BASE0,
2558                 .num_ports      = 2,
2559                 .base_baud      = 3906250,
2560                 .uart_offset    = 0x200,
2561                 .first_offset   = 0x1000,
2562         },
2563         [pbn_ADDIDATA_PCIe_4_3906250] = {
2564                 .flags          = FL_BASE0,
2565                 .num_ports      = 4,
2566                 .base_baud      = 3906250,
2567                 .uart_offset    = 0x200,
2568                 .first_offset   = 0x1000,
2569         },
2570         [pbn_ADDIDATA_PCIe_8_3906250] = {
2571                 .flags          = FL_BASE0,
2572                 .num_ports      = 8,
2573                 .base_baud      = 3906250,
2574                 .uart_offset    = 0x200,
2575                 .first_offset   = 0x1000,
2576         },
2577         [pbn_ce4100_1_115200] = {
2578                 .flags          = FL_BASE0,
2579                 .num_ports      = 1,
2580                 .base_baud      = 921600,
2581                 .reg_shift      = 2,
2582         },
2583         [pbn_omegapci] = {
2584                 .flags          = FL_BASE0,
2585                 .num_ports      = 8,
2586                 .base_baud      = 115200,
2587                 .uart_offset    = 0x200,
2588         },
2589         [pbn_NETMOS9900_2s_115200] = {
2590                 .flags          = FL_BASE0,
2591                 .num_ports      = 2,
2592                 .base_baud      = 115200,
2593         },
2594         [pbn_brcm_trumanage] = {
2595                 .flags          = FL_BASE0,
2596                 .num_ports      = 1,
2597                 .reg_shift      = 2,
2598                 .base_baud      = 115200,
2599         },
2600 };
2601
2602 static const struct pci_device_id softmodem_blacklist[] = {
2603         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2604         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2605         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2606 };
2607
2608 /*
2609  * Given a complete unknown PCI device, try to use some heuristics to
2610  * guess what the configuration might be, based on the pitiful PCI
2611  * serial specs.  Returns 0 on success, 1 on failure.
2612  */
2613 static int __devinit
2614 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2615 {
2616         const struct pci_device_id *blacklist;
2617         int num_iomem, num_port, first_port = -1, i;
2618
2619         /*
2620          * If it is not a communications device or the programming
2621          * interface is greater than 6, give up.
2622          *
2623          * (Should we try to make guesses for multiport serial devices
2624          * later?)
2625          */
2626         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2627              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2628             (dev->class & 0xff) > 6)
2629                 return -ENODEV;
2630
2631         /*
2632          * Do not access blacklisted devices that are known not to
2633          * feature serial ports.
2634          */
2635         for (blacklist = softmodem_blacklist;
2636              blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2637              blacklist++) {
2638                 if (dev->vendor == blacklist->vendor &&
2639                     dev->device == blacklist->device)
2640                         return -ENODEV;
2641         }
2642
2643         num_iomem = num_port = 0;
2644         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2645                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2646                         num_port++;
2647                         if (first_port == -1)
2648                                 first_port = i;
2649                 }
2650                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2651                         num_iomem++;
2652         }
2653
2654         /*
2655          * If there is 1 or 0 iomem regions, and exactly one port,
2656          * use it.  We guess the number of ports based on the IO
2657          * region size.
2658          */
2659         if (num_iomem <= 1 && num_port == 1) {
2660                 board->flags = first_port;
2661                 board->num_ports = pci_resource_len(dev, first_port) / 8;
2662                 return 0;
2663         }
2664
2665         /*
2666          * Now guess if we've got a board which indexes by BARs.
2667          * Each IO BAR should be 8 bytes, and they should follow
2668          * consecutively.
2669          */
2670         first_port = -1;
2671         num_port = 0;
2672         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2673                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2674                     pci_resource_len(dev, i) == 8 &&
2675                     (first_port == -1 || (first_port + num_port) == i)) {
2676                         num_port++;
2677                         if (first_port == -1)
2678                                 first_port = i;
2679                 }
2680         }
2681
2682         if (num_port > 1) {
2683                 board->flags = first_port | FL_BASE_BARS;
2684                 board->num_ports = num_port;
2685                 return 0;
2686         }
2687
2688         return -ENODEV;
2689 }
2690
2691 static inline int
2692 serial_pci_matches(const struct pciserial_board *board,
2693                    const struct pciserial_board *guessed)
2694 {
2695         return
2696             board->num_ports == guessed->num_ports &&
2697             board->base_baud == guessed->base_baud &&
2698             board->uart_offset == guessed->uart_offset &&
2699             board->reg_shift == guessed->reg_shift &&
2700             board->first_offset == guessed->first_offset;
2701 }
2702
2703 struct serial_private *
2704 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2705 {
2706         struct uart_port serial_port;
2707         struct serial_private *priv;
2708         struct pci_serial_quirk *quirk;
2709         int rc, nr_ports, i;
2710
2711         nr_ports = board->num_ports;
2712
2713         /*
2714          * Find an init and setup quirks.
2715          */
2716         quirk = find_quirk(dev);
2717
2718         /*
2719          * Run the new-style initialization function.
2720          * The initialization function returns:
2721          *  <0  - error
2722          *   0  - use board->num_ports
2723          *  >0  - number of ports
2724          */
2725         if (quirk->init) {
2726                 rc = quirk->init(dev);
2727                 if (rc < 0) {
2728                         priv = ERR_PTR(rc);
2729                         goto err_out;
2730                 }
2731                 if (rc)
2732                         nr_ports = rc;
2733         }
2734
2735         priv = kzalloc(sizeof(struct serial_private) +
2736                        sizeof(unsigned int) * nr_ports,
2737                        GFP_KERNEL);
2738         if (!priv) {
2739                 priv = ERR_PTR(-ENOMEM);
2740                 goto err_deinit;
2741         }
2742
2743         priv->dev = dev;
2744         priv->quirk = quirk;
2745
2746         memset(&serial_port, 0, sizeof(struct uart_port));
2747         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2748         serial_port.uartclk = board->base_baud * 16;
2749         serial_port.irq = get_pci_irq(dev, board);
2750         serial_port.dev = &dev->dev;
2751
2752         for (i = 0; i < nr_ports; i++) {
2753                 if (quirk->setup(priv, board, &serial_port, i))
2754                         break;
2755
2756 #ifdef SERIAL_DEBUG_PCI
2757                 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2758                        serial_port.iobase, serial_port.irq, serial_port.iotype);
2759 #endif
2760
2761                 priv->line[i] = serial8250_register_port(&serial_port);
2762                 if (priv->line[i] < 0) {
2763                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2764                         break;
2765                 }
2766         }
2767         priv->nr = i;
2768         return priv;
2769
2770 err_deinit:
2771         if (quirk->exit)
2772                 quirk->exit(dev);
2773 err_out:
2774         return priv;
2775 }
2776 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2777
2778 void pciserial_remove_ports(struct serial_private *priv)
2779 {
2780         struct pci_serial_quirk *quirk;
2781         int i;
2782
2783         for (i = 0; i < priv->nr; i++)
2784                 serial8250_unregister_port(priv->line[i]);
2785
2786         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2787                 if (priv->remapped_bar[i])
2788                         iounmap(priv->remapped_bar[i]);
2789                 priv->remapped_bar[i] = NULL;
2790         }
2791
2792         /*
2793          * Find the exit quirks.
2794          */
2795         quirk = find_quirk(priv->dev);
2796         if (quirk->exit)
2797                 quirk->exit(priv->dev);
2798
2799         kfree(priv);
2800 }
2801 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2802
2803 void pciserial_suspend_ports(struct serial_private *priv)
2804 {
2805         int i;
2806
2807         for (i = 0; i < priv->nr; i++)
2808                 if (priv->line[i] >= 0)
2809                         serial8250_suspend_port(priv->line[i]);
2810 }
2811 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2812
2813 void pciserial_resume_ports(struct serial_private *priv)
2814 {
2815         int i;
2816
2817         /*
2818          * Ensure that the board is correctly configured.
2819          */
2820         if (priv->quirk->init)
2821                 priv->quirk->init(priv->dev);
2822
2823         for (i = 0; i < priv->nr; i++)
2824                 if (priv->line[i] >= 0)
2825                         serial8250_resume_port(priv->line[i]);
2826 }
2827 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2828
2829 /*
2830  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
2831  * to the arrangement of serial ports on a PCI card.
2832  */
2833 static int __devinit
2834 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2835 {
2836         struct pci_serial_quirk *quirk;
2837         struct serial_private *priv;
2838         const struct pciserial_board *board;
2839         struct pciserial_board tmp;
2840         int rc;
2841
2842         quirk = find_quirk(dev);
2843         if (quirk->probe) {
2844                 rc = quirk->probe(dev);
2845                 if (rc)
2846                         return rc;
2847         }
2848
2849         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2850                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2851                         ent->driver_data);
2852                 return -EINVAL;
2853         }
2854
2855         board = &pci_boards[ent->driver_data];
2856
2857         rc = pci_enable_device(dev);
2858         pci_save_state(dev);
2859         if (rc)
2860                 return rc;
2861
2862         if (ent->driver_data == pbn_default) {
2863                 /*
2864                  * Use a copy of the pci_board entry for this;
2865                  * avoid changing entries in the table.
2866                  */
2867                 memcpy(&tmp, board, sizeof(struct pciserial_board));
2868                 board = &tmp;
2869
2870                 /*
2871                  * We matched one of our class entries.  Try to
2872                  * determine the parameters of this board.
2873                  */
2874                 rc = serial_pci_guess_board(dev, &tmp);
2875                 if (rc)
2876                         goto disable;
2877         } else {
2878                 /*
2879                  * We matched an explicit entry.  If we are able to
2880                  * detect this boards settings with our heuristic,
2881                  * then we no longer need this entry.
2882                  */
2883                 memcpy(&tmp, &pci_boards[pbn_default],
2884                        sizeof(struct pciserial_board));
2885                 rc = serial_pci_guess_board(dev, &tmp);
2886                 if (rc == 0 && serial_pci_matches(board, &tmp))
2887                         moan_device("Redundant entry in serial pci_table.",
2888                                     dev);
2889         }
2890
2891         priv = pciserial_init_ports(dev, board);
2892         if (!IS_ERR(priv)) {
2893                 pci_set_drvdata(dev, priv);
2894                 return 0;
2895         }
2896
2897         rc = PTR_ERR(priv);
2898
2899  disable:
2900         pci_disable_device(dev);
2901         return rc;
2902 }
2903
2904 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2905 {
2906         struct serial_private *priv = pci_get_drvdata(dev);
2907
2908         pci_set_drvdata(dev, NULL);
2909
2910         pciserial_remove_ports(priv);
2911
2912         pci_disable_device(dev);
2913 }
2914
2915 #ifdef CONFIG_PM
2916 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2917 {
2918         struct serial_private *priv = pci_get_drvdata(dev);
2919
2920         if (priv)
2921                 pciserial_suspend_ports(priv);
2922
2923         pci_save_state(dev);
2924         pci_set_power_state(dev, pci_choose_state(dev, state));
2925         return 0;
2926 }
2927
2928 static int pciserial_resume_one(struct pci_dev *dev)
2929 {
2930         int err;
2931         struct serial_private *priv = pci_get_drvdata(dev);
2932
2933         pci_set_power_state(dev, PCI_D0);
2934         pci_restore_state(dev);
2935
2936         if (priv) {
2937                 /*
2938                  * The device may have been disabled.  Re-enable it.
2939                  */
2940                 err = pci_enable_device(dev);
2941                 /* FIXME: We cannot simply error out here */
2942                 if (err)
2943                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2944                 pciserial_resume_ports(priv);
2945         }
2946         return 0;
2947 }
2948 #endif
2949
2950 static struct pci_device_id serial_pci_tbl[] = {
2951         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2952         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2953                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2954                 pbn_b2_8_921600 },
2955         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2956                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2957                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2958                 pbn_b1_8_1382400 },
2959         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2960                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2961                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2962                 pbn_b1_4_1382400 },
2963         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2964                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2965                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2966                 pbn_b1_2_1382400 },
2967         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2968                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2969                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2970                 pbn_b1_8_1382400 },
2971         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2972                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2973                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2974                 pbn_b1_4_1382400 },
2975         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2976                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2977                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2978                 pbn_b1_2_1382400 },
2979         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2980                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2981                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2982                 pbn_b1_8_921600 },
2983         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2984                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2985                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2986                 pbn_b1_8_921600 },
2987         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2988                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2989                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2990                 pbn_b1_4_921600 },
2991         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2992                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2993                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2994                 pbn_b1_4_921600 },
2995         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2996                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2997                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2998                 pbn_b1_2_921600 },
2999         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3000                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3001                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3002                 pbn_b1_8_921600 },
3003         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3004                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3005                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3006                 pbn_b1_8_921600 },
3007         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3008                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3009                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3010                 pbn_b1_4_921600 },
3011         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3012                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3013                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3014                 pbn_b1_2_1250000 },
3015         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3016                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3017                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3018                 pbn_b0_2_1843200 },
3019         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3020                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3021                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3022                 pbn_b0_4_1843200 },
3023         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3024                 PCI_VENDOR_ID_AFAVLAB,
3025                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3026                 pbn_b0_4_1152000 },
3027         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3028                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3029                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3030                 pbn_b0_2_1843200_200 },
3031         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3032                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3033                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3034                 pbn_b0_4_1843200_200 },
3035         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3036                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3037                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3038                 pbn_b0_8_1843200_200 },
3039         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3040                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3041                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3042                 pbn_b0_2_1843200_200 },
3043         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3044                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3045                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3046                 pbn_b0_4_1843200_200 },
3047         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3048                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3049                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3050                 pbn_b0_8_1843200_200 },
3051         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3052                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3053                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3054                 pbn_b0_2_1843200_200 },
3055         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3056                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3057                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3058                 pbn_b0_4_1843200_200 },
3059         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3060                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3061                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3062                 pbn_b0_8_1843200_200 },
3063         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3064                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3065                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3066                 pbn_b0_2_1843200_200 },
3067         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3068                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3069                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3070                 pbn_b0_4_1843200_200 },
3071         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3072                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3073                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3074                 pbn_b0_8_1843200_200 },
3075         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3076                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3077                 0, 0, pbn_exar_ibm_saturn },
3078
3079         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3080                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3081                 pbn_b2_bt_1_115200 },
3082         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3083                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3084                 pbn_b2_bt_2_115200 },
3085         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3086                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3087                 pbn_b2_bt_4_115200 },
3088         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3089                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3090                 pbn_b2_bt_2_115200 },
3091         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3092                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3093                 pbn_b2_bt_4_115200 },
3094         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3095                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3096                 pbn_b2_8_115200 },
3097         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3098                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3099                 pbn_b2_8_460800 },
3100         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3101                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3102                 pbn_b2_8_115200 },
3103
3104         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3105                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3106                 pbn_b2_bt_2_115200 },
3107         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3108                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3109                 pbn_b2_bt_2_921600 },
3110         /*
3111          * VScom SPCOM800, from sl@s.pl
3112          */
3113         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3114                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3115                 pbn_b2_8_921600 },
3116         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3117                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3118                 pbn_b2_4_921600 },
3119         /* Unknown card - subdevice 0x1584 */
3120         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3121                 PCI_VENDOR_ID_PLX,
3122                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3123                 pbn_b0_4_115200 },
3124         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3125                 PCI_SUBVENDOR_ID_KEYSPAN,
3126                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3127                 pbn_panacom },
3128         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3129                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3130                 pbn_panacom4 },
3131         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3132                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3133                 pbn_panacom2 },
3134         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3135                 PCI_VENDOR_ID_ESDGMBH,
3136                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3137                 pbn_b2_4_115200 },
3138         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3139                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3140                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3141                 pbn_b2_4_460800 },
3142         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3143                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3144                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3145                 pbn_b2_8_460800 },
3146         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3147                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3148                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3149                 pbn_b2_16_460800 },
3150         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3151                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3152                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3153                 pbn_b2_16_460800 },
3154         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3155                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3156                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3157                 pbn_b2_4_460800 },
3158         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3159                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3160                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3161                 pbn_b2_8_460800 },
3162         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3163                 PCI_SUBVENDOR_ID_EXSYS,
3164                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3165                 pbn_exsys_4055 },
3166         /*
3167          * Megawolf Romulus PCI Serial Card, from Mike Hudson
3168          * (Exoray@isys.ca)
3169          */
3170         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3171                 0x10b5, 0x106a, 0, 0,
3172                 pbn_plx_romulus },
3173         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3174                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3175                 pbn_b1_4_115200 },
3176         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3177                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3178                 pbn_b1_2_115200 },
3179         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3180                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3181                 pbn_b1_8_115200 },
3182         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3183                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3184                 pbn_b1_8_115200 },
3185         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3186                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3187                 0, 0,
3188                 pbn_b0_4_921600 },
3189         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3190                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3191                 0, 0,
3192                 pbn_b0_4_1152000 },
3193         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
3194                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3195                 pbn_b0_bt_2_921600 },
3196
3197                 /*
3198                  * The below card is a little controversial since it is the
3199                  * subject of a PCI vendor/device ID clash.  (See
3200                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3201                  * For now just used the hex ID 0x950a.
3202                  */
3203         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3204                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
3205                 0, 0, pbn_b0_2_115200 },
3206         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3207                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
3208                 0, 0, pbn_b0_2_115200 },
3209         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3210                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3211                 pbn_b0_2_1130000 },
3212         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3213                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3214                 pbn_b0_1_921600 },
3215         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3216                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3217                 pbn_b0_4_115200 },
3218         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3219                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3220                 pbn_b0_bt_2_921600 },
3221         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3222                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3223                 pbn_b2_8_1152000 },
3224
3225         /*
3226          * Oxford Semiconductor Inc. Tornado PCI express device range.
3227          */
3228         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
3229                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3230                 pbn_b0_1_4000000 },
3231         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
3232                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3233                 pbn_b0_1_4000000 },
3234         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
3235                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3236                 pbn_oxsemi_1_4000000 },
3237         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
3238                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3239                 pbn_oxsemi_1_4000000 },
3240         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
3241                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3242                 pbn_b0_1_4000000 },
3243         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
3244                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3245                 pbn_b0_1_4000000 },
3246         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
3247                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3248                 pbn_oxsemi_1_4000000 },
3249         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
3250                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3251                 pbn_oxsemi_1_4000000 },
3252         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
3253                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3254                 pbn_b0_1_4000000 },
3255         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
3256                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3257                 pbn_b0_1_4000000 },
3258         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
3259                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3260                 pbn_b0_1_4000000 },
3261         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
3262                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3263                 pbn_b0_1_4000000 },
3264         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
3265                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3266                 pbn_oxsemi_2_4000000 },
3267         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
3268                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3269                 pbn_oxsemi_2_4000000 },
3270         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
3271                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3272                 pbn_oxsemi_4_4000000 },
3273         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
3274                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3275                 pbn_oxsemi_4_4000000 },
3276         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
3277                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3278                 pbn_oxsemi_8_4000000 },
3279         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
3280                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3281                 pbn_oxsemi_8_4000000 },
3282         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
3283                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3284                 pbn_oxsemi_1_4000000 },
3285         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
3286                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3287                 pbn_oxsemi_1_4000000 },
3288         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
3289                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3290                 pbn_oxsemi_1_4000000 },
3291         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
3292                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3293                 pbn_oxsemi_1_4000000 },
3294         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
3295                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3296                 pbn_oxsemi_1_4000000 },
3297         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
3298                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3299                 pbn_oxsemi_1_4000000 },
3300         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
3301                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3302                 pbn_oxsemi_1_4000000 },
3303         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
3304                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3305                 pbn_oxsemi_1_4000000 },
3306         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
3307                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3308                 pbn_oxsemi_1_4000000 },
3309         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
3310                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3311                 pbn_oxsemi_1_4000000 },
3312         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
3313                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3314                 pbn_oxsemi_1_4000000 },
3315         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
3316                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3317                 pbn_oxsemi_1_4000000 },
3318         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
3319                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3320                 pbn_oxsemi_1_4000000 },
3321         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
3322                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3323                 pbn_oxsemi_1_4000000 },
3324         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
3325                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3326                 pbn_oxsemi_1_4000000 },
3327         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
3328                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3329                 pbn_oxsemi_1_4000000 },
3330         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
3331                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3332                 pbn_oxsemi_1_4000000 },
3333         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
3334                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3335                 pbn_oxsemi_1_4000000 },
3336         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
3337                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3338                 pbn_oxsemi_1_4000000 },
3339         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
3340                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3341                 pbn_oxsemi_1_4000000 },
3342         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
3343                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3344                 pbn_oxsemi_1_4000000 },
3345         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
3346                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3347                 pbn_oxsemi_1_4000000 },
3348         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
3349                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3350                 pbn_oxsemi_1_4000000 },
3351         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
3352                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3353                 pbn_oxsemi_1_4000000 },
3354         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
3355                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3356                 pbn_oxsemi_1_4000000 },
3357         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
3358                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3359                 pbn_oxsemi_1_4000000 },
3360         /*
3361          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3362          */
3363         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3364                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3365                 pbn_oxsemi_1_4000000 },
3366         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3367                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3368                 pbn_oxsemi_2_4000000 },
3369         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3370                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3371                 pbn_oxsemi_4_4000000 },
3372         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3373                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3374                 pbn_oxsemi_8_4000000 },
3375
3376         /*
3377          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3378          */
3379         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3380                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3381                 pbn_oxsemi_2_4000000 },
3382
3383         /*
3384          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3385          * from skokodyn@yahoo.com
3386          */
3387         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3388                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3389                 pbn_sbsxrsio },
3390         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3391                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3392                 pbn_sbsxrsio },
3393         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3394                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3395                 pbn_sbsxrsio },
3396         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3397                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3398                 pbn_sbsxrsio },
3399
3400         /*
3401          * Digitan DS560-558, from jimd@esoft.com
3402          */
3403         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3404                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3405                 pbn_b1_1_115200 },
3406
3407         /*
3408          * Titan Electronic cards
3409          *  The 400L and 800L have a custom setup quirk.
3410          */
3411         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3412                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3413                 pbn_b0_1_921600 },
3414         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3415                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3416                 pbn_b0_2_921600 },
3417         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3418                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3419                 pbn_b0_4_921600 },
3420         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3421                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3422                 pbn_b0_4_921600 },
3423         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3424                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3425                 pbn_b1_1_921600 },
3426         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3427                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3428                 pbn_b1_bt_2_921600 },
3429         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3430                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3431                 pbn_b0_bt_4_921600 },
3432         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3433                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3434                 pbn_b0_bt_8_921600 },
3435         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3436                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3437                 pbn_b4_bt_2_921600 },
3438         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3439                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3440                 pbn_b4_bt_4_921600 },
3441         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3442                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3443                 pbn_b4_bt_8_921600 },
3444         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3445                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3446                 pbn_b0_4_921600 },
3447         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3448                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3449                 pbn_b0_4_921600 },
3450         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3451                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3452                 pbn_b0_4_921600 },
3453         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3454                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3455                 pbn_oxsemi_1_4000000 },
3456         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3457                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3458                 pbn_oxsemi_2_4000000 },
3459         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3460                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3461                 pbn_oxsemi_4_4000000 },
3462         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3463                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3464                 pbn_oxsemi_8_4000000 },
3465         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3466                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3467                 pbn_oxsemi_2_4000000 },
3468         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3469                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3470                 pbn_oxsemi_2_4000000 },
3471
3472         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3473                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3474                 pbn_b2_1_460800 },
3475         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3476                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3477                 pbn_b2_1_460800 },
3478         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3479                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3480                 pbn_b2_1_460800 },
3481         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3482                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3483                 pbn_b2_bt_2_921600 },
3484         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3485                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3486                 pbn_b2_bt_2_921600 },
3487         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3488                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3489                 pbn_b2_bt_2_921600 },
3490         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3491                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3492                 pbn_b2_bt_4_921600 },
3493         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3494                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3495                 pbn_b2_bt_4_921600 },
3496         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3497                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3498                 pbn_b2_bt_4_921600 },
3499         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3500                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3501                 pbn_b0_1_921600 },
3502         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3503                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3504                 pbn_b0_1_921600 },
3505         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3506                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3507                 pbn_b0_1_921600 },
3508         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3509                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3510                 pbn_b0_bt_2_921600 },
3511         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3512                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3513                 pbn_b0_bt_2_921600 },
3514         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3515                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3516                 pbn_b0_bt_2_921600 },
3517         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3518                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3519                 pbn_b0_bt_4_921600 },
3520         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3521                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3522                 pbn_b0_bt_4_921600 },
3523         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3524                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3525                 pbn_b0_bt_4_921600 },
3526         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3527                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3528                 pbn_b0_bt_8_921600 },
3529         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3530                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3531                 pbn_b0_bt_8_921600 },
3532         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3533                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3534                 pbn_b0_bt_8_921600 },
3535
3536         /*
3537          * Computone devices submitted by Doug McNash dmcnash@computone.com
3538          */
3539         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3540                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3541                 0, 0, pbn_computone_4 },
3542         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3543                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3544                 0, 0, pbn_computone_8 },
3545         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3546                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3547                 0, 0, pbn_computone_6 },
3548
3549         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3550                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3551                 pbn_oxsemi },
3552         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3553                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3554                 pbn_b0_bt_1_921600 },
3555
3556         /*
3557          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3558          */
3559         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3560                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3561                 pbn_b0_bt_8_115200 },
3562         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3563                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3564                 pbn_b0_bt_8_115200 },
3565
3566         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3567                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3568                 pbn_b0_bt_2_115200 },
3569         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3570                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3571                 pbn_b0_bt_2_115200 },
3572         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3573                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3574                 pbn_b0_bt_2_115200 },
3575         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3576                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3577                 pbn_b0_bt_2_115200 },
3578         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3579                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3580                 pbn_b0_bt_2_115200 },
3581         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3582                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3583                 pbn_b0_bt_4_460800 },
3584         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3585                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3586                 pbn_b0_bt_4_460800 },
3587         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3588                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3589                 pbn_b0_bt_2_460800 },
3590         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3591                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3592                 pbn_b0_bt_2_460800 },
3593         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3594                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3595                 pbn_b0_bt_2_460800 },
3596         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3597                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3598                 pbn_b0_bt_1_115200 },
3599         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3600                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3601                 pbn_b0_bt_1_460800 },
3602
3603         /*
3604          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3605          * Cards are identified by their subsystem vendor IDs, which
3606          * (in hex) match the model number.
3607          *
3608          * Note that JC140x are RS422/485 cards which require ox950
3609          * ACR = 0x10, and as such are not currently fully supported.
3610          */
3611         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3612                 0x1204, 0x0004, 0, 0,
3613                 pbn_b0_4_921600 },
3614         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3615                 0x1208, 0x0004, 0, 0,
3616                 pbn_b0_4_921600 },
3617 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3618                 0x1402, 0x0002, 0, 0,
3619                 pbn_b0_2_921600 }, */
3620 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3621                 0x1404, 0x0004, 0, 0,
3622                 pbn_b0_4_921600 }, */
3623         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3624                 0x1208, 0x0004, 0, 0,
3625                 pbn_b0_4_921600 },
3626
3627         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3628                 0x1204, 0x0004, 0, 0,
3629                 pbn_b0_4_921600 },
3630         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3631                 0x1208, 0x0004, 0, 0,
3632                 pbn_b0_4_921600 },
3633         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3634                 0x1208, 0x0004, 0, 0,
3635                 pbn_b0_4_921600 },
3636         /*
3637          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3638          */
3639         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3640                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3641                 pbn_b1_1_1382400 },
3642
3643         /*
3644          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3645          */
3646         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3647                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3648                 pbn_b1_1_1382400 },
3649
3650         /*
3651          * RAStel 2 port modem, gerg@moreton.com.au
3652          */
3653         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3654                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3655                 pbn_b2_bt_2_115200 },
3656
3657         /*
3658          * EKF addition for i960 Boards form EKF with serial port
3659          */
3660         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3661                 0xE4BF, PCI_ANY_ID, 0, 0,
3662                 pbn_intel_i960 },
3663
3664         /*
3665          * Xircom Cardbus/Ethernet combos
3666          */
3667         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3668                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3669                 pbn_b0_1_115200 },
3670         /*
3671          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3672          */
3673         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3674                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3675                 pbn_b0_1_115200 },
3676
3677         /*
3678          * Untested PCI modems, sent in from various folks...
3679          */
3680
3681         /*
3682          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3683          */
3684         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
3685                 0x1048, 0x1500, 0, 0,
3686                 pbn_b1_1_115200 },
3687
3688         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3689                 0xFF00, 0, 0, 0,
3690                 pbn_sgi_ioc3 },
3691
3692         /*
3693          * HP Diva card
3694          */
3695         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3696                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3697                 pbn_b1_1_115200 },
3698         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3699                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3700                 pbn_b0_5_115200 },
3701         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3702                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3703                 pbn_b2_1_115200 },
3704
3705         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3706                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3707                 pbn_b3_2_115200 },
3708         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3709                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3710                 pbn_b3_4_115200 },
3711         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3712                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3713                 pbn_b3_8_115200 },
3714
3715         /*
3716          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3717          */
3718         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3719                 PCI_ANY_ID, PCI_ANY_ID,
3720                 0,
3721                 0, pbn_exar_XR17C152 },
3722         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3723                 PCI_ANY_ID, PCI_ANY_ID,
3724                 0,
3725                 0, pbn_exar_XR17C154 },
3726         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3727                 PCI_ANY_ID, PCI_ANY_ID,
3728                 0,
3729                 0, pbn_exar_XR17C158 },
3730
3731         /*
3732          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3733          */
3734         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3735                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3736                 pbn_b0_1_115200 },
3737         /*
3738          * ITE
3739          */
3740         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3741                 PCI_ANY_ID, PCI_ANY_ID,
3742                 0, 0,
3743                 pbn_b1_bt_1_115200 },
3744
3745         /*
3746          * IntaShield IS-200
3747          */
3748         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3749                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
3750                 pbn_b2_2_115200 },
3751         /*
3752          * IntaShield IS-400
3753          */
3754         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3755                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
3756                 pbn_b2_4_115200 },
3757         /*
3758          * Perle PCI-RAS cards
3759          */
3760         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3761                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3762                 0, 0, pbn_b2_4_921600 },
3763         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3764                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3765                 0, 0, pbn_b2_8_921600 },
3766
3767         /*
3768          * Mainpine series cards: Fairly standard layout but fools
3769          * parts of the autodetect in some cases and uses otherwise
3770          * unmatched communications subclasses in the PCI Express case
3771          */
3772
3773         {       /* RockForceDUO */
3774                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3775                 PCI_VENDOR_ID_MAINPINE, 0x0200,
3776                 0, 0, pbn_b0_2_115200 },
3777         {       /* RockForceQUATRO */
3778                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3779                 PCI_VENDOR_ID_MAINPINE, 0x0300,
3780                 0, 0, pbn_b0_4_115200 },
3781         {       /* RockForceDUO+ */
3782                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3783                 PCI_VENDOR_ID_MAINPINE, 0x0400,
3784                 0, 0, pbn_b0_2_115200 },
3785         {       /* RockForceQUATRO+ */
3786                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3787                 PCI_VENDOR_ID_MAINPINE, 0x0500,
3788                 0, 0, pbn_b0_4_115200 },
3789         {       /* RockForce+ */
3790                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3791                 PCI_VENDOR_ID_MAINPINE, 0x0600,
3792                 0, 0, pbn_b0_2_115200 },
3793         {       /* RockForce+ */
3794                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3795                 PCI_VENDOR_ID_MAINPINE, 0x0700,
3796                 0, 0, pbn_b0_4_115200 },
3797         {       /* RockForceOCTO+ */
3798                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3799                 PCI_VENDOR_ID_MAINPINE, 0x0800,
3800                 0, 0, pbn_b0_8_115200 },
3801         {       /* RockForceDUO+ */
3802                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3803                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3804                 0, 0, pbn_b0_2_115200 },
3805         {       /* RockForceQUARTRO+ */
3806                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3807                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3808                 0, 0, pbn_b0_4_115200 },
3809         {       /* RockForceOCTO+ */
3810                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3811                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3812                 0, 0, pbn_b0_8_115200 },
3813         {       /* RockForceD1 */
3814                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3815                 PCI_VENDOR_ID_MAINPINE, 0x2000,
3816                 0, 0, pbn_b0_1_115200 },
3817         {       /* RockForceF1 */
3818                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3819                 PCI_VENDOR_ID_MAINPINE, 0x2100,
3820                 0, 0, pbn_b0_1_115200 },
3821         {       /* RockForceD2 */
3822                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3823                 PCI_VENDOR_ID_MAINPINE, 0x2200,
3824                 0, 0, pbn_b0_2_115200 },
3825         {       /* RockForceF2 */
3826                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3827                 PCI_VENDOR_ID_MAINPINE, 0x2300,
3828                 0, 0, pbn_b0_2_115200 },
3829         {       /* RockForceD4 */
3830                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3831                 PCI_VENDOR_ID_MAINPINE, 0x2400,
3832                 0, 0, pbn_b0_4_115200 },
3833         {       /* RockForceF4 */
3834                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3835                 PCI_VENDOR_ID_MAINPINE, 0x2500,
3836                 0, 0, pbn_b0_4_115200 },
3837         {       /* RockForceD8 */
3838                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3839                 PCI_VENDOR_ID_MAINPINE, 0x2600,
3840                 0, 0, pbn_b0_8_115200 },
3841         {       /* RockForceF8 */
3842                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3843                 PCI_VENDOR_ID_MAINPINE, 0x2700,
3844                 0, 0, pbn_b0_8_115200 },
3845         {       /* IQ Express D1 */
3846                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3847                 PCI_VENDOR_ID_MAINPINE, 0x3000,
3848                 0, 0, pbn_b0_1_115200 },
3849         {       /* IQ Express F1 */
3850                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3851                 PCI_VENDOR_ID_MAINPINE, 0x3100,
3852                 0, 0, pbn_b0_1_115200 },
3853         {       /* IQ Express D2 */
3854                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3855                 PCI_VENDOR_ID_MAINPINE, 0x3200,
3856                 0, 0, pbn_b0_2_115200 },
3857         {       /* IQ Express F2 */
3858                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3859                 PCI_VENDOR_ID_MAINPINE, 0x3300,
3860                 0, 0, pbn_b0_2_115200 },
3861         {       /* IQ Express D4 */
3862                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3863                 PCI_VENDOR_ID_MAINPINE, 0x3400,
3864                 0, 0, pbn_b0_4_115200 },
3865         {       /* IQ Express F4 */
3866                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3867                 PCI_VENDOR_ID_MAINPINE, 0x3500,
3868                 0, 0, pbn_b0_4_115200 },
3869         {       /* IQ Express D8 */
3870                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3871                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3872                 0, 0, pbn_b0_8_115200 },
3873         {       /* IQ Express F8 */
3874                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3875                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3876                 0, 0, pbn_b0_8_115200 },
3877
3878
3879         /*
3880          * PA Semi PA6T-1682M on-chip UART
3881          */
3882         {       PCI_VENDOR_ID_PASEMI, 0xa004,
3883                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3884                 pbn_pasemi_1682M },
3885
3886         /*
3887          * National Instruments
3888          */
3889         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3890                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3891                 pbn_b1_16_115200 },
3892         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3893                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3894                 pbn_b1_8_115200 },
3895         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3896                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3897                 pbn_b1_bt_4_115200 },
3898         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3899                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3900                 pbn_b1_bt_2_115200 },
3901         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3902                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3903                 pbn_b1_bt_4_115200 },
3904         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3905                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3906                 pbn_b1_bt_2_115200 },
3907         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3908                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3909                 pbn_b1_16_115200 },
3910         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3911                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3912                 pbn_b1_8_115200 },
3913         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3914                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3915                 pbn_b1_bt_4_115200 },
3916         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3917                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3918                 pbn_b1_bt_2_115200 },
3919         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3920                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3921                 pbn_b1_bt_4_115200 },
3922         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3923                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3924                 pbn_b1_bt_2_115200 },
3925         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3926                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3927                 pbn_ni8430_2 },
3928         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3929                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3930                 pbn_ni8430_2 },
3931         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3932                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3933                 pbn_ni8430_4 },
3934         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3935                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3936                 pbn_ni8430_4 },
3937         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3938                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3939                 pbn_ni8430_8 },
3940         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3941                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3942                 pbn_ni8430_8 },
3943         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3944                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3945                 pbn_ni8430_16 },
3946         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3947                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3948                 pbn_ni8430_16 },
3949         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3950                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3951                 pbn_ni8430_2 },
3952         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3953                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3954                 pbn_ni8430_2 },
3955         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3956                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3957                 pbn_ni8430_4 },
3958         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3959                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3960                 pbn_ni8430_4 },
3961
3962         /*
3963         * ADDI-DATA GmbH communication cards <info@addi-data.com>
3964         */
3965         {       PCI_VENDOR_ID_ADDIDATA,
3966                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3967                 PCI_ANY_ID,
3968                 PCI_ANY_ID,
3969                 0,
3970                 0,
3971                 pbn_b0_4_115200 },
3972
3973         {       PCI_VENDOR_ID_ADDIDATA,
3974                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3975                 PCI_ANY_ID,
3976                 PCI_ANY_ID,
3977                 0,
3978                 0,
3979                 pbn_b0_2_115200 },
3980
3981         {       PCI_VENDOR_ID_ADDIDATA,
3982                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3983                 PCI_ANY_ID,
3984                 PCI_ANY_ID,
3985                 0,
3986                 0,
3987                 pbn_b0_1_115200 },
3988
3989         {       PCI_VENDOR_ID_ADDIDATA_OLD,
3990                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3991                 PCI_ANY_ID,
3992                 PCI_ANY_ID,
3993                 0,
3994                 0,
3995                 pbn_b1_8_115200 },
3996
3997         {       PCI_VENDOR_ID_ADDIDATA,
3998                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3999                 PCI_ANY_ID,
4000                 PCI_ANY_ID,
4001                 0,
4002                 0,
4003                 pbn_b0_4_115200 },
4004
4005         {       PCI_VENDOR_ID_ADDIDATA,
4006                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4007                 PCI_ANY_ID,
4008                 PCI_ANY_ID,
4009                 0,
4010                 0,
4011                 pbn_b0_2_115200 },
4012
4013         {       PCI_VENDOR_ID_ADDIDATA,
4014                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4015                 PCI_ANY_ID,
4016                 PCI_ANY_ID,
4017                 0,
4018                 0,
4019                 pbn_b0_1_115200 },
4020
4021         {       PCI_VENDOR_ID_ADDIDATA,
4022                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4023                 PCI_ANY_ID,
4024                 PCI_ANY_ID,
4025                 0,
4026                 0,
4027                 pbn_b0_4_115200 },
4028
4029         {       PCI_VENDOR_ID_ADDIDATA,
4030                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4031                 PCI_ANY_ID,
4032                 PCI_ANY_ID,
4033                 0,
4034                 0,
4035                 pbn_b0_2_115200 },
4036
4037         {       PCI_VENDOR_ID_ADDIDATA,
4038                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4039                 PCI_ANY_ID,
4040                 PCI_ANY_ID,
4041                 0,
4042                 0,
4043                 pbn_b0_1_115200 },
4044
4045         {       PCI_VENDOR_ID_ADDIDATA,
4046                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4047                 PCI_ANY_ID,
4048                 PCI_ANY_ID,
4049                 0,
4050                 0,
4051                 pbn_b0_8_115200 },
4052
4053         {       PCI_VENDOR_ID_ADDIDATA,
4054                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4055                 PCI_ANY_ID,
4056                 PCI_ANY_ID,
4057                 0,
4058                 0,
4059                 pbn_ADDIDATA_PCIe_4_3906250 },
4060
4061         {       PCI_VENDOR_ID_ADDIDATA,
4062                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4063                 PCI_ANY_ID,
4064                 PCI_ANY_ID,
4065                 0,
4066                 0,
4067                 pbn_ADDIDATA_PCIe_2_3906250 },
4068
4069         {       PCI_VENDOR_ID_ADDIDATA,
4070                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4071                 PCI_ANY_ID,
4072                 PCI_ANY_ID,
4073                 0,
4074                 0,
4075                 pbn_ADDIDATA_PCIe_1_3906250 },
4076
4077         {       PCI_VENDOR_ID_ADDIDATA,
4078                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4079                 PCI_ANY_ID,
4080                 PCI_ANY_ID,
4081                 0,
4082                 0,
4083                 pbn_ADDIDATA_PCIe_8_3906250 },
4084
4085         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4086                 PCI_VENDOR_ID_IBM, 0x0299,
4087                 0, 0, pbn_b0_bt_2_115200 },
4088
4089         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4090                 0xA000, 0x1000,
4091                 0, 0, pbn_b0_1_115200 },
4092
4093         /* the 9901 is a rebranded 9912 */
4094         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4095                 0xA000, 0x1000,
4096                 0, 0, pbn_b0_1_115200 },
4097
4098         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4099                 0xA000, 0x1000,
4100                 0, 0, pbn_b0_1_115200 },
4101
4102         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4103                 0xA000, 0x1000,
4104                 0, 0, pbn_b0_1_115200 },
4105
4106         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4107                 0xA000, 0x1000,
4108                 0, 0, pbn_b0_1_115200 },
4109
4110         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4111                 0xA000, 0x3002,
4112                 0, 0, pbn_NETMOS9900_2s_115200 },
4113
4114         /*
4115          * Best Connectivity and Rosewill PCI Multi I/O cards
4116          */
4117
4118         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4119                 0xA000, 0x1000,
4120                 0, 0, pbn_b0_1_115200 },
4121
4122         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4123                 0xA000, 0x3002,
4124                 0, 0, pbn_b0_bt_2_115200 },
4125
4126         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4127                 0xA000, 0x3004,
4128                 0, 0, pbn_b0_bt_4_115200 },
4129         /* Intel CE4100 */
4130         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4131                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
4132                 pbn_ce4100_1_115200 },
4133
4134         /*
4135          * Cronyx Omega PCI
4136          */
4137         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4138                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4139                 pbn_omegapci },
4140
4141         /*
4142          * Broadcom TruManage
4143          */
4144         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
4145                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4146                 pbn_brcm_trumanage },
4147
4148         /*
4149          * These entries match devices with class COMMUNICATION_SERIAL,
4150          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4151          */
4152         {       PCI_ANY_ID, PCI_ANY_ID,
4153                 PCI_ANY_ID, PCI_ANY_ID,
4154                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4155                 0xffff00, pbn_default },
4156         {       PCI_ANY_ID, PCI_ANY_ID,
4157                 PCI_ANY_ID, PCI_ANY_ID,
4158                 PCI_CLASS_COMMUNICATION_MODEM << 8,
4159                 0xffff00, pbn_default },
4160         {       PCI_ANY_ID, PCI_ANY_ID,
4161                 PCI_ANY_ID, PCI_ANY_ID,
4162                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4163                 0xffff00, pbn_default },
4164         { 0, }
4165 };
4166
4167 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4168                                                 pci_channel_state_t state)
4169 {
4170         struct serial_private *priv = pci_get_drvdata(dev);
4171
4172         if (state == pci_channel_io_perm_failure)
4173                 return PCI_ERS_RESULT_DISCONNECT;
4174
4175         if (priv)
4176                 pciserial_suspend_ports(priv);
4177
4178         pci_disable_device(dev);
4179
4180         return PCI_ERS_RESULT_NEED_RESET;
4181 }
4182
4183 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4184 {
4185         int rc;
4186
4187         rc = pci_enable_device(dev);
4188
4189         if (rc)
4190                 return PCI_ERS_RESULT_DISCONNECT;
4191
4192         pci_restore_state(dev);
4193         pci_save_state(dev);
4194
4195         return PCI_ERS_RESULT_RECOVERED;
4196 }
4197
4198 static void serial8250_io_resume(struct pci_dev *dev)
4199 {
4200         struct serial_private *priv = pci_get_drvdata(dev);
4201
4202         if (priv)
4203                 pciserial_resume_ports(priv);
4204 }
4205
4206 static struct pci_error_handlers serial8250_err_handler = {
4207         .error_detected = serial8250_io_error_detected,
4208         .slot_reset = serial8250_io_slot_reset,
4209         .resume = serial8250_io_resume,
4210 };
4211
4212 static struct pci_driver serial_pci_driver = {
4213         .name           = "serial",
4214         .probe          = pciserial_init_one,
4215         .remove         = __devexit_p(pciserial_remove_one),
4216 #ifdef CONFIG_PM
4217         .suspend        = pciserial_suspend_one,
4218         .resume         = pciserial_resume_one,
4219 #endif
4220         .id_table       = serial_pci_tbl,
4221         .err_handler    = &serial8250_err_handler,
4222 };
4223
4224 static int __init serial8250_pci_init(void)
4225 {
4226         return pci_register_driver(&serial_pci_driver);
4227 }
4228
4229 static void __exit serial8250_pci_exit(void)
4230 {
4231         pci_unregister_driver(&serial_pci_driver);
4232 }
4233
4234 module_init(serial8250_pci_init);
4235 module_exit(serial8250_pci_exit);
4236
4237 MODULE_LICENSE("GPL");
4238 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4239 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);