2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
4 * Copyright (C) 2011 Samsung Electronics
5 * Donggeun Kim <dg77.kim@samsung.com>
6 * Amit Daniel Kachhap <amit.kachhap@linaro.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/clk.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/platform_device.h>
32 #include <linux/regulator/consumer.h>
34 #include "exynos_thermal_common.h"
35 #include "exynos_tmu.h"
36 #include "exynos_tmu_data.h"
39 * struct exynos_tmu_data : A structure to hold the private data of the TMU
41 * @id: identifier of the one instance of the TMU controller.
42 * @pdata: pointer to the tmu platform/configuration data
43 * @base: base address of the single instance of the TMU controller.
44 * @base_second: base address of the common registers of the TMU controller.
45 * @irq: irq number of the TMU controller.
46 * @soc: id of the SOC type.
47 * @irq_work: pointer to the irq work structure.
48 * @lock: lock to implement synchronization.
49 * @clk: pointer to the clock structure.
50 * @clk_sec: pointer to the clock structure for accessing the base_second.
51 * @temp_error1: fused value of the first point trim.
52 * @temp_error2: fused value of the second point trim.
53 * @regulator: pointer to the TMU regulator structure.
54 * @reg_conf: pointer to structure to register with core thermal.
56 struct exynos_tmu_data {
58 struct exynos_tmu_platform_data *pdata;
60 void __iomem *base_second;
63 struct work_struct irq_work;
65 struct clk *clk, *clk_sec;
66 u8 temp_error1, temp_error2;
67 struct regulator *regulator;
68 struct thermal_sensor_conf *reg_conf;
72 * TMU treats temperature as a mapped temperature code.
73 * The temperature is converted differently depending on the calibration type.
75 static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
77 struct exynos_tmu_platform_data *pdata = data->pdata;
80 switch (pdata->cal_type) {
81 case TYPE_TWO_POINT_TRIMMING:
82 temp_code = (temp - pdata->first_point_trim) *
83 (data->temp_error2 - data->temp_error1) /
84 (pdata->second_point_trim - pdata->first_point_trim) +
87 case TYPE_ONE_POINT_TRIMMING:
88 temp_code = temp + data->temp_error1 - pdata->first_point_trim;
91 temp_code = temp + pdata->default_temp_offset;
99 * Calculate a temperature value from a temperature code.
100 * The unit of the temperature is degree Celsius.
102 static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
104 struct exynos_tmu_platform_data *pdata = data->pdata;
107 switch (pdata->cal_type) {
108 case TYPE_TWO_POINT_TRIMMING:
109 temp = (temp_code - data->temp_error1) *
110 (pdata->second_point_trim - pdata->first_point_trim) /
111 (data->temp_error2 - data->temp_error1) +
112 pdata->first_point_trim;
114 case TYPE_ONE_POINT_TRIMMING:
115 temp = temp_code - data->temp_error1 + pdata->first_point_trim;
118 temp = temp_code - pdata->default_temp_offset;
125 static void exynos_tmu_clear_irqs(struct exynos_tmu_data *data)
127 const struct exynos_tmu_registers *reg = data->pdata->registers;
128 unsigned int val_irq;
130 val_irq = readl(data->base + reg->tmu_intstat);
132 * Clear the interrupts. Please note that the documentation for
133 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly
134 * states that INTCLEAR register has a different placing of bits
135 * responsible for FALL IRQs than INTSTAT register. Exynos5420
136 * and Exynos5440 documentation is correct (Exynos4210 doesn't
137 * support FALL IRQs at all).
139 writel(val_irq, data->base + reg->tmu_intclear);
142 static int exynos_tmu_initialize(struct platform_device *pdev)
144 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
145 struct exynos_tmu_platform_data *pdata = data->pdata;
146 const struct exynos_tmu_registers *reg = pdata->registers;
147 unsigned int status, trim_info = 0, con, ctrl;
148 unsigned int rising_threshold = 0, falling_threshold = 0;
149 int ret = 0, threshold_code, i;
151 mutex_lock(&data->lock);
152 clk_enable(data->clk);
153 if (!IS_ERR(data->clk_sec))
154 clk_enable(data->clk_sec);
156 if (TMU_SUPPORTS(pdata, READY_STATUS)) {
157 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
164 if (TMU_SUPPORTS(pdata, TRIM_RELOAD)) {
165 if (data->soc == SOC_ARCH_EXYNOS3250) {
166 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1);
167 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
168 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1);
170 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2);
171 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
172 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2);
175 /* Save trimming info in order to perform calibration */
176 if (data->soc == SOC_ARCH_EXYNOS5440) {
178 * For exynos5440 soc triminfo value is swapped between TMU0 and
179 * TMU2, so the below logic is needed.
183 trim_info = readl(data->base +
184 EXYNOS5440_EFUSE_SWAP_OFFSET + EXYNOS5440_TMU_S0_7_TRIM);
187 trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM);
190 trim_info = readl(data->base -
191 EXYNOS5440_EFUSE_SWAP_OFFSET + EXYNOS5440_TMU_S0_7_TRIM);
194 /* On exynos5420 the triminfo register is in the shared space */
195 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
196 trim_info = readl(data->base_second +
197 EXYNOS_TMU_REG_TRIMINFO);
199 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
201 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
202 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
203 EXYNOS_TMU_TEMP_MASK);
205 if (!data->temp_error1 ||
206 (pdata->min_efuse_value > data->temp_error1) ||
207 (data->temp_error1 > pdata->max_efuse_value))
208 data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
210 if (!data->temp_error2)
212 (pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
213 EXYNOS_TMU_TEMP_MASK;
215 rising_threshold = readl(data->base + reg->threshold_th0);
217 if (data->soc == SOC_ARCH_EXYNOS4210) {
218 /* Write temperature code for threshold */
219 threshold_code = temp_to_code(data, pdata->threshold);
220 writeb(threshold_code,
221 data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
222 for (i = 0; i < pdata->non_hw_trigger_levels; i++)
223 writeb(pdata->trigger_levels[i], data->base +
224 reg->threshold_th0 + i * sizeof(reg->threshold_th0));
226 exynos_tmu_clear_irqs(data);
228 /* Write temperature code for rising and falling threshold */
229 for (i = 0; i < pdata->non_hw_trigger_levels; i++) {
230 threshold_code = temp_to_code(data,
231 pdata->trigger_levels[i]);
232 rising_threshold &= ~(0xff << 8 * i);
233 rising_threshold |= threshold_code << 8 * i;
234 if (pdata->threshold_falling) {
235 threshold_code = temp_to_code(data,
236 pdata->trigger_levels[i] -
237 pdata->threshold_falling);
238 falling_threshold |= threshold_code << 8 * i;
242 writel(rising_threshold,
243 data->base + reg->threshold_th0);
244 writel(falling_threshold,
245 data->base + reg->threshold_th1);
247 exynos_tmu_clear_irqs(data);
249 /* if last threshold limit is also present */
250 i = pdata->max_trigger_level - 1;
251 if (pdata->trigger_levels[i] &&
252 (pdata->trigger_type[i] == HW_TRIP)) {
253 threshold_code = temp_to_code(data,
254 pdata->trigger_levels[i]);
255 if (i == EXYNOS_MAX_TRIGGER_PER_REG - 1) {
256 /* 1-4 level to be assigned in th0 reg */
257 rising_threshold &= ~(0xff << 8 * i);
258 rising_threshold |= threshold_code << 8 * i;
259 writel(rising_threshold,
260 data->base + reg->threshold_th0);
261 } else if (i == EXYNOS_MAX_TRIGGER_PER_REG) {
262 /* 5th level to be assigned in th2 reg */
264 threshold_code << reg->threshold_th3_l0_shift;
265 writel(rising_threshold,
266 data->base + reg->threshold_th2);
268 con = readl(data->base + reg->tmu_ctrl);
269 con |= (1 << reg->therm_trip_en_shift);
270 writel(con, data->base + reg->tmu_ctrl);
273 /*Clear the PMIN in the common TMU register*/
274 if (reg->tmu_pmin && !data->id)
275 writel(0, data->base_second + reg->tmu_pmin);
277 clk_disable(data->clk);
278 mutex_unlock(&data->lock);
279 if (!IS_ERR(data->clk_sec))
280 clk_disable(data->clk_sec);
285 static void exynos_tmu_control(struct platform_device *pdev, bool on)
287 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
288 struct exynos_tmu_platform_data *pdata = data->pdata;
289 const struct exynos_tmu_registers *reg = pdata->registers;
290 unsigned int con, interrupt_en;
292 mutex_lock(&data->lock);
293 clk_enable(data->clk);
295 con = readl(data->base + reg->tmu_ctrl);
298 con |= (pdata->test_mux << EXYNOS4412_MUX_ADDR_SHIFT);
300 con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT);
301 con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
303 con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
304 con |= (pdata->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
306 if (pdata->noise_cancel_mode) {
307 con &= ~(reg->therm_trip_mode_mask <<
308 reg->therm_trip_mode_shift);
309 con |= (pdata->noise_cancel_mode << reg->therm_trip_mode_shift);
313 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
315 pdata->trigger_enable[3] << reg->inten_rise3_shift |
316 pdata->trigger_enable[2] << reg->inten_rise2_shift |
317 pdata->trigger_enable[1] << reg->inten_rise1_shift |
318 pdata->trigger_enable[0] << reg->inten_rise0_shift;
319 if (TMU_SUPPORTS(pdata, FALLING_TRIP))
321 interrupt_en << reg->inten_fall0_shift;
323 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
324 interrupt_en = 0; /* Disable all interrupts */
326 writel(interrupt_en, data->base + reg->tmu_inten);
327 writel(con, data->base + reg->tmu_ctrl);
329 clk_disable(data->clk);
330 mutex_unlock(&data->lock);
333 static int exynos_tmu_read(struct exynos_tmu_data *data)
335 struct exynos_tmu_platform_data *pdata = data->pdata;
336 const struct exynos_tmu_registers *reg = pdata->registers;
340 mutex_lock(&data->lock);
341 clk_enable(data->clk);
343 temp_code = readb(data->base + reg->tmu_cur_temp);
345 if (data->soc == SOC_ARCH_EXYNOS4210)
346 /* temp_code should range between 75 and 175 */
347 if (temp_code < 75 || temp_code > 175) {
352 temp = code_to_temp(data, temp_code);
354 clk_disable(data->clk);
355 mutex_unlock(&data->lock);
360 #ifdef CONFIG_THERMAL_EMULATION
361 static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
363 struct exynos_tmu_data *data = drv_data;
364 struct exynos_tmu_platform_data *pdata = data->pdata;
365 const struct exynos_tmu_registers *reg = pdata->registers;
369 if (!TMU_SUPPORTS(pdata, EMULATION))
372 if (temp && temp < MCELSIUS)
375 mutex_lock(&data->lock);
376 clk_enable(data->clk);
378 val = readl(data->base + reg->emul_con);
383 if (TMU_SUPPORTS(pdata, EMUL_TIME)) {
384 val &= ~(EXYNOS_EMUL_TIME_MASK << reg->emul_time_shift);
385 val |= (EXYNOS_EMUL_TIME << reg->emul_time_shift);
387 val &= ~(EXYNOS_EMUL_DATA_MASK << reg->emul_temp_shift);
388 val |= (temp_to_code(data, temp) << reg->emul_temp_shift) |
391 val &= ~EXYNOS_EMUL_ENABLE;
394 writel(val, data->base + reg->emul_con);
396 clk_disable(data->clk);
397 mutex_unlock(&data->lock);
403 static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
405 #endif/*CONFIG_THERMAL_EMULATION*/
407 static void exynos_tmu_work(struct work_struct *work)
409 struct exynos_tmu_data *data = container_of(work,
410 struct exynos_tmu_data, irq_work);
411 struct exynos_tmu_platform_data *pdata = data->pdata;
412 const struct exynos_tmu_registers *reg = pdata->registers;
413 unsigned int val_type;
415 if (!IS_ERR(data->clk_sec))
416 clk_enable(data->clk_sec);
417 /* Find which sensor generated this interrupt */
418 if (reg->tmu_irqstatus) {
419 val_type = readl(data->base_second + reg->tmu_irqstatus);
420 if (!((val_type >> data->id) & 0x1))
423 if (!IS_ERR(data->clk_sec))
424 clk_disable(data->clk_sec);
426 exynos_report_trigger(data->reg_conf);
427 mutex_lock(&data->lock);
428 clk_enable(data->clk);
430 /* TODO: take action based on particular interrupt */
431 exynos_tmu_clear_irqs(data);
433 clk_disable(data->clk);
434 mutex_unlock(&data->lock);
436 enable_irq(data->irq);
439 static irqreturn_t exynos_tmu_irq(int irq, void *id)
441 struct exynos_tmu_data *data = id;
443 disable_irq_nosync(irq);
444 schedule_work(&data->irq_work);
449 static const struct of_device_id exynos_tmu_match[] = {
451 .compatible = "samsung,exynos3250-tmu",
452 .data = (void *)EXYNOS3250_TMU_DRV_DATA,
455 .compatible = "samsung,exynos4210-tmu",
456 .data = (void *)EXYNOS4210_TMU_DRV_DATA,
459 .compatible = "samsung,exynos4412-tmu",
460 .data = (void *)EXYNOS4412_TMU_DRV_DATA,
463 .compatible = "samsung,exynos5250-tmu",
464 .data = (void *)EXYNOS5250_TMU_DRV_DATA,
467 .compatible = "samsung,exynos5260-tmu",
468 .data = (void *)EXYNOS5260_TMU_DRV_DATA,
471 .compatible = "samsung,exynos5420-tmu",
472 .data = (void *)EXYNOS5420_TMU_DRV_DATA,
475 .compatible = "samsung,exynos5420-tmu-ext-triminfo",
476 .data = (void *)EXYNOS5420_TMU_DRV_DATA,
479 .compatible = "samsung,exynos5440-tmu",
480 .data = (void *)EXYNOS5440_TMU_DRV_DATA,
484 MODULE_DEVICE_TABLE(of, exynos_tmu_match);
486 static inline struct exynos_tmu_platform_data *exynos_get_driver_data(
487 struct platform_device *pdev, int id)
489 struct exynos_tmu_init_data *data_table;
490 struct exynos_tmu_platform_data *tmu_data;
491 const struct of_device_id *match;
493 match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
496 data_table = (struct exynos_tmu_init_data *) match->data;
497 if (!data_table || id >= data_table->tmu_count)
499 tmu_data = data_table->tmu_data;
500 return (struct exynos_tmu_platform_data *) (tmu_data + id);
503 static int exynos_map_dt_data(struct platform_device *pdev)
505 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
506 struct exynos_tmu_platform_data *pdata;
510 if (!data || !pdev->dev.of_node)
514 * Try enabling the regulator if found
515 * TODO: Add regulator as an SOC feature, so that regulator enable
516 * is a compulsory call.
518 data->regulator = devm_regulator_get(&pdev->dev, "vtmu");
519 if (!IS_ERR(data->regulator)) {
520 ret = regulator_enable(data->regulator);
522 dev_err(&pdev->dev, "failed to enable vtmu\n");
526 dev_info(&pdev->dev, "Regulator node (vtmu) not found\n");
529 data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl");
533 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
534 if (data->irq <= 0) {
535 dev_err(&pdev->dev, "failed to get IRQ\n");
539 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
540 dev_err(&pdev->dev, "failed to get Resource 0\n");
544 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
546 dev_err(&pdev->dev, "Failed to ioremap memory\n");
547 return -EADDRNOTAVAIL;
550 pdata = exynos_get_driver_data(pdev, data->id);
552 dev_err(&pdev->dev, "No platform init data supplied.\n");
557 * Check if the TMU shares some registers and then try to map the
558 * memory of common registers.
560 if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
563 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
564 dev_err(&pdev->dev, "failed to get Resource 1\n");
568 data->base_second = devm_ioremap(&pdev->dev, res.start,
569 resource_size(&res));
570 if (!data->base_second) {
571 dev_err(&pdev->dev, "Failed to ioremap memory\n");
578 static int exynos_tmu_probe(struct platform_device *pdev)
580 struct exynos_tmu_data *data;
581 struct exynos_tmu_platform_data *pdata;
582 struct thermal_sensor_conf *sensor_conf;
585 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
590 platform_set_drvdata(pdev, data);
591 mutex_init(&data->lock);
593 ret = exynos_map_dt_data(pdev);
599 INIT_WORK(&data->irq_work, exynos_tmu_work);
601 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
602 if (IS_ERR(data->clk)) {
603 dev_err(&pdev->dev, "Failed to get clock\n");
604 return PTR_ERR(data->clk);
607 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
608 if (IS_ERR(data->clk_sec)) {
609 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
610 dev_err(&pdev->dev, "Failed to get triminfo clock\n");
611 return PTR_ERR(data->clk_sec);
614 ret = clk_prepare(data->clk_sec);
616 dev_err(&pdev->dev, "Failed to get clock\n");
621 ret = clk_prepare(data->clk);
623 dev_err(&pdev->dev, "Failed to get clock\n");
627 if (pdata->type == SOC_ARCH_EXYNOS3250 ||
628 pdata->type == SOC_ARCH_EXYNOS4210 ||
629 pdata->type == SOC_ARCH_EXYNOS4412 ||
630 pdata->type == SOC_ARCH_EXYNOS5250 ||
631 pdata->type == SOC_ARCH_EXYNOS5260 ||
632 pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO ||
633 pdata->type == SOC_ARCH_EXYNOS5440)
634 data->soc = pdata->type;
637 dev_err(&pdev->dev, "Platform not supported\n");
641 ret = exynos_tmu_initialize(pdev);
643 dev_err(&pdev->dev, "Failed to initialize TMU\n");
647 exynos_tmu_control(pdev, true);
649 /* Allocate a structure to register with the exynos core thermal */
650 sensor_conf = devm_kzalloc(&pdev->dev,
651 sizeof(struct thermal_sensor_conf), GFP_KERNEL);
656 sprintf(sensor_conf->name, "therm_zone%d", data->id);
657 sensor_conf->read_temperature = (int (*)(void *))exynos_tmu_read;
658 sensor_conf->write_emul_temp =
659 (int (*)(void *, unsigned long))exynos_tmu_set_emulation;
660 sensor_conf->driver_data = data;
661 sensor_conf->trip_data.trip_count = pdata->trigger_enable[0] +
662 pdata->trigger_enable[1] + pdata->trigger_enable[2]+
663 pdata->trigger_enable[3];
665 for (i = 0; i < sensor_conf->trip_data.trip_count; i++) {
666 sensor_conf->trip_data.trip_val[i] =
667 pdata->threshold + pdata->trigger_levels[i];
668 sensor_conf->trip_data.trip_type[i] =
669 pdata->trigger_type[i];
672 sensor_conf->trip_data.trigger_falling = pdata->threshold_falling;
674 sensor_conf->cooling_data.freq_clip_count = pdata->freq_tab_count;
675 for (i = 0; i < pdata->freq_tab_count; i++) {
676 sensor_conf->cooling_data.freq_data[i].freq_clip_max =
677 pdata->freq_tab[i].freq_clip_max;
678 sensor_conf->cooling_data.freq_data[i].temp_level =
679 pdata->freq_tab[i].temp_level;
681 sensor_conf->dev = &pdev->dev;
682 /* Register the sensor with thermal management interface */
683 ret = exynos_register_thermal(sensor_conf);
685 dev_err(&pdev->dev, "Failed to register thermal interface\n");
688 data->reg_conf = sensor_conf;
690 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
691 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data);
693 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
699 clk_unprepare(data->clk);
701 if (!IS_ERR(data->clk_sec))
702 clk_unprepare(data->clk_sec);
706 static int exynos_tmu_remove(struct platform_device *pdev)
708 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
710 exynos_unregister_thermal(data->reg_conf);
712 exynos_tmu_control(pdev, false);
714 clk_unprepare(data->clk);
715 if (!IS_ERR(data->clk_sec))
716 clk_unprepare(data->clk_sec);
718 if (!IS_ERR(data->regulator))
719 regulator_disable(data->regulator);
724 #ifdef CONFIG_PM_SLEEP
725 static int exynos_tmu_suspend(struct device *dev)
727 exynos_tmu_control(to_platform_device(dev), false);
732 static int exynos_tmu_resume(struct device *dev)
734 struct platform_device *pdev = to_platform_device(dev);
736 exynos_tmu_initialize(pdev);
737 exynos_tmu_control(pdev, true);
742 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
743 exynos_tmu_suspend, exynos_tmu_resume);
744 #define EXYNOS_TMU_PM (&exynos_tmu_pm)
746 #define EXYNOS_TMU_PM NULL
749 static struct platform_driver exynos_tmu_driver = {
751 .name = "exynos-tmu",
752 .owner = THIS_MODULE,
754 .of_match_table = exynos_tmu_match,
756 .probe = exynos_tmu_probe,
757 .remove = exynos_tmu_remove,
760 module_platform_driver(exynos_tmu_driver);
762 MODULE_DESCRIPTION("EXYNOS TMU Driver");
763 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
764 MODULE_LICENSE("GPL");
765 MODULE_ALIAS("platform:exynos-tmu");