drivers/staging/xgifb/vb_init.c

   1 #include <linux/delay.h> /* udelay */
   2 #include <linux/vmalloc.h>
   3
   4 #include "XGIfb.h"
   5 #include "vb_def.h"
   6 #include "vb_util.h"
   7 #include "vb_setmode.h"
   8
   9 static const unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
  10         { 2, 13, 9, 64, 0x45},
  11         { 2, 12, 9, 32, 0x35},
  12         { 2, 12, 8, 16, 0x31},
  13         { 2, 11, 8,  8, 0x21} };
  14
  15 static const unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
  16         { 2, 14, 11, 128, 0x5D},
  17         { 2, 14, 10, 64, 0x59},
  18         { 2, 13, 11, 64, 0x4D},
  19         { 2, 14,  9, 32, 0x55},
  20         { 2, 13, 10, 32, 0x49},
  21         { 2, 12, 11, 32, 0x3D},
  22         { 2, 14,  8, 16, 0x51},
  23         { 2, 13,  9, 16, 0x45},
  24         { 2, 12, 10, 16, 0x39},
  25         { 2, 13,  8,  8, 0x41},
  26         { 2, 12,  9,  8, 0x35},
  27         { 2, 12,  8,  4, 0x31} };
  28
  29 #define XGIFB_ROM_SIZE  65536
  30
  31 static unsigned char
  32 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
  33                        struct vb_device_info *pVBInfo)
  34 {
  35         unsigned char data, temp;
  36
  37         if (HwDeviceExtension->jChipType < XG20) {
  38                 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
  39                         data = *pVBInfo->pSoftSetting & 0x07;
  40                         return data;
  41                 } else {
  42                         data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
  43                         if (data == 0)
  44                                 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
  45                                        0x02) >> 1;
  46                         return data;
  47                 }
  48         } else if (HwDeviceExtension->jChipType == XG27) {
  49                 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
  50                         data = *pVBInfo->pSoftSetting & 0x07;
  51                         return data;
  52                 }
  53                 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
  54                 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
  55                 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
  56                         data = 0; /* DDR */
  57                 else
  58                         data = 1; /* DDRII */
  59                 return data;
  60         } else if (HwDeviceExtension->jChipType == XG21) {
  61                 /* Independent GPIO control */
  62                 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
  63                 udelay(800);
  64                 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
  65                 /* GPIOF 0:DVI 1:DVO */
  66                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
  67                 /* HOTPLUG_SUPPORT */
  68                 /* for current XG20 & XG21, GPIOH is floating, driver will
  69                  * fix DDR temporarily */
  70                 if (temp & 0x01) /* DVI read GPIOH */
  71                         data = 1; /* DDRII */
  72                 else
  73                         data = 0; /* DDR */
  74                 /* ~HOTPLUG_SUPPORT */
  75                 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
  76                 return data;
  77         } else {
  78                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
  79
  80                 if (data == 1)
  81                         data++;
  82
  83                 return data;
  84         }
  85 }
  86
  87 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
  88                                  struct vb_device_info *pVBInfo)
  89 {
  90         xgifb_reg_set(P3c4, 0x18, 0x01);
  91         xgifb_reg_set(P3c4, 0x19, 0x20);
  92         xgifb_reg_set(P3c4, 0x16, 0x00);
  93         xgifb_reg_set(P3c4, 0x16, 0x80);
  94
  95         if (*pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C) { /* Samsung F Die */
  96                 mdelay(3);
  97                 xgifb_reg_set(P3c4, 0x18, 0x00);
  98                 xgifb_reg_set(P3c4, 0x19, 0x20);
  99                 xgifb_reg_set(P3c4, 0x16, 0x00);
 100                 xgifb_reg_set(P3c4, 0x16, 0x80);
 101         }
 102
 103         udelay(60);
 104         xgifb_reg_set(P3c4,
 105                       0x18,
 106                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 107         xgifb_reg_set(P3c4, 0x19, 0x01);
 108         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[0]);
 109         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[1]);
 110         mdelay(1);
 111         xgifb_reg_set(P3c4, 0x1B, 0x03);
 112         udelay(500);
 113         xgifb_reg_set(P3c4,
 114                       0x18,
 115                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 116         xgifb_reg_set(P3c4, 0x19, 0x00);
 117         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[2]);
 118         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[3]);
 119         xgifb_reg_set(P3c4, 0x1B, 0x00);
 120 }
 121
 122 static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
 123                 struct vb_device_info *pVBInfo)
 124 {
 125
 126         xgifb_reg_set(pVBInfo->P3c4,
 127                       0x28,
 128                       pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
 129         xgifb_reg_set(pVBInfo->P3c4,
 130                       0x29,
 131                       pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
 132         xgifb_reg_set(pVBInfo->P3c4,
 133                       0x2A,
 134                       pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
 135
 136         xgifb_reg_set(pVBInfo->P3c4,
 137                       0x2E,
 138                       pVBInfo->ECLKData[pVBInfo->ram_type].SR2E);
 139         xgifb_reg_set(pVBInfo->P3c4,
 140                       0x2F,
 141                       pVBInfo->ECLKData[pVBInfo->ram_type].SR2F);
 142         xgifb_reg_set(pVBInfo->P3c4,
 143                       0x30,
 144                       pVBInfo->ECLKData[pVBInfo->ram_type].SR30);
 145
 146         /* [Vicent] 2004/07/07,
 147          * When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
 148         /* [Hsuan] 2004/08/20,
 149          * Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz,
 150          * Set SR32 D[1:0] = 10b */
 151         if (HwDeviceExtension->jChipType == XG42) {
 152                 if ((pVBInfo->MCLKData[pVBInfo->ram_type].SR28 == 0x1C) &&
 153                     (pVBInfo->MCLKData[pVBInfo->ram_type].SR29 == 0x01) &&
 154                     (((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x1C) &&
 155                       (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01)) ||
 156                      ((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x22) &&
 157                       (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01))))
 158                         xgifb_reg_set(pVBInfo->P3c4,
 159                                       0x32,
 160                                       ((unsigned char) xgifb_reg_get(
 161                                           pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
 162         }
 163 }
 164
 165 static void XGINew_DDRII_Bootup_XG27(
 166                         struct xgi_hw_device_info *HwDeviceExtension,
 167                         unsigned long P3c4, struct vb_device_info *pVBInfo)
 168 {
 169         unsigned long P3d4 = P3c4 + 0x10;
 170         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 171         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 172
 173         /* Set Double Frequency */
 174         /* xgifb_reg_set(P3d4, 0x97, 0x11); *//* CR97 */
 175         xgifb_reg_set(P3d4, 0x97, *pVBInfo->pXGINew_CR97); /* CR97 */
 176
 177         udelay(200);
 178
 179         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
 180         xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
 181         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 182         udelay(15);
 183         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 184         udelay(15);
 185
 186         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
 187         xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
 188         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 189         udelay(15);
 190         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 191         udelay(15);
 192
 193         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
 194         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 195         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 196         udelay(30);
 197         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 198         udelay(15);
 199
 200         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
 201         xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
 202         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 203         udelay(30);
 204         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 205         xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
 206         /* udelay(15); */
 207
 208         xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
 209         udelay(60);
 210         xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
 211
 212         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
 213         xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
 214         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 215
 216         udelay(30);
 217         xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
 218         udelay(15);
 219
 220         xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
 221         xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
 222         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 223         udelay(30);
 224         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 225         udelay(15);
 226
 227         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
 228         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 229         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 230         udelay(30);
 231         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 232         udelay(15);
 233
 234         /* Set SR1B refresh control 000:close; 010:open */
 235         xgifb_reg_set(P3c4, 0x1B, 0x04);
 236         udelay(200);
 237
 238 }
 239
 240 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
 241                 unsigned long P3c4, struct vb_device_info *pVBInfo)
 242 {
 243         unsigned long P3d4 = P3c4 + 0x10;
 244
 245         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 246         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 247
 248         xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
 249
 250         udelay(200);
 251         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
 252         xgifb_reg_set(P3c4, 0x19, 0x80);
 253         xgifb_reg_set(P3c4, 0x16, 0x05);
 254         xgifb_reg_set(P3c4, 0x16, 0x85);
 255
 256         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
 257         xgifb_reg_set(P3c4, 0x19, 0xC0);
 258         xgifb_reg_set(P3c4, 0x16, 0x05);
 259         xgifb_reg_set(P3c4, 0x16, 0x85);
 260
 261         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
 262         xgifb_reg_set(P3c4, 0x19, 0x40);
 263         xgifb_reg_set(P3c4, 0x16, 0x05);
 264         xgifb_reg_set(P3c4, 0x16, 0x85);
 265
 266         /* xgifb_reg_set(P3c4, 0x18, 0x52); */ /* MRS1 */
 267         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 268         xgifb_reg_set(P3c4, 0x19, 0x02);
 269         xgifb_reg_set(P3c4, 0x16, 0x05);
 270         xgifb_reg_set(P3c4, 0x16, 0x85);
 271
 272         udelay(15);
 273         xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
 274         udelay(30);
 275         xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
 276         udelay(100);
 277
 278         /* xgifb_reg_set(P3c4 ,0x18, 0x52); */ /* MRS2 */
 279         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 280         xgifb_reg_set(P3c4, 0x19, 0x00);
 281         xgifb_reg_set(P3c4, 0x16, 0x05);
 282         xgifb_reg_set(P3c4, 0x16, 0x85);
 283
 284         udelay(200);
 285 }
 286
 287 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
 288                                   struct vb_device_info *pVBInfo)
 289 {
 290         xgifb_reg_set(P3c4, 0x18, 0x01);
 291         xgifb_reg_set(P3c4, 0x19, 0x40);
 292         xgifb_reg_set(P3c4, 0x16, 0x00);
 293         xgifb_reg_set(P3c4, 0x16, 0x80);
 294         udelay(60);
 295
 296         xgifb_reg_set(P3c4, 0x18, 0x00);
 297         xgifb_reg_set(P3c4, 0x19, 0x40);
 298         xgifb_reg_set(P3c4, 0x16, 0x00);
 299         xgifb_reg_set(P3c4, 0x16, 0x80);
 300         udelay(60);
 301         xgifb_reg_set(P3c4,
 302                       0x18,
 303                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 304         /* xgifb_reg_set(P3c4, 0x18, 0x31); */
 305         xgifb_reg_set(P3c4, 0x19, 0x01);
 306         xgifb_reg_set(P3c4, 0x16, 0x03);
 307         xgifb_reg_set(P3c4, 0x16, 0x83);
 308         mdelay(1);
 309         xgifb_reg_set(P3c4, 0x1B, 0x03);
 310         udelay(500);
 311         /* xgifb_reg_set(P3c4, 0x18, 0x31); */
 312         xgifb_reg_set(P3c4,
 313                       0x18,
 314                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 315         xgifb_reg_set(P3c4, 0x19, 0x00);
 316         xgifb_reg_set(P3c4, 0x16, 0x03);
 317         xgifb_reg_set(P3c4, 0x16, 0x83);
 318         xgifb_reg_set(P3c4, 0x1B, 0x00);
 319 }
 320
 321 static void XGINew_DDR1x_DefaultRegister(
 322                 struct xgi_hw_device_info *HwDeviceExtension,
 323                 unsigned long Port, struct vb_device_info *pVBInfo)
 324 {
 325         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 326
 327         if (HwDeviceExtension->jChipType >= XG20) {
 328                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 329                 xgifb_reg_set(P3d4,
 330                               0x82,
 331                               pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
 332                 xgifb_reg_set(P3d4,
 333                               0x85,
 334                               pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 335                 xgifb_reg_set(P3d4,
 336                               0x86,
 337                               pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
 338
 339                 xgifb_reg_set(P3d4, 0x98, 0x01);
 340                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 341
 342                 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
 343         } else {
 344                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 345
 346                 switch (HwDeviceExtension->jChipType) {
 347                 case XG42:
 348                         /* CR82 */
 349                         xgifb_reg_set(P3d4,
 350                                       0x82,
 351                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 352                         /* CR85 */
 353                         xgifb_reg_set(P3d4,
 354                                       0x85,
 355                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 356                         /* CR86 */
 357                         xgifb_reg_set(P3d4,
 358                                       0x86,
 359                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 360                         break;
 361                 default:
 362                         xgifb_reg_set(P3d4, 0x82, 0x88);
 363                         xgifb_reg_set(P3d4, 0x86, 0x00);
 364                         /* Insert read command for delay */
 365                         xgifb_reg_get(P3d4, 0x86);
 366                         xgifb_reg_set(P3d4, 0x86, 0x88);
 367                         xgifb_reg_get(P3d4, 0x86);
 368                         xgifb_reg_set(P3d4,
 369                                       0x86,
 370                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 371                         xgifb_reg_set(P3d4, 0x82, 0x77);
 372                         xgifb_reg_set(P3d4, 0x85, 0x00);
 373
 374                         /* Insert read command for delay */
 375                         xgifb_reg_get(P3d4, 0x85);
 376                         xgifb_reg_set(P3d4, 0x85, 0x88);
 377
 378                         /* Insert read command for delay */
 379                         xgifb_reg_get(P3d4, 0x85);
 380                         /* CR85 */
 381                         xgifb_reg_set(P3d4,
 382                                       0x85,
 383                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 384                         /* CR82 */
 385                         xgifb_reg_set(P3d4,
 386                                       0x82,
 387                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 388                         break;
 389                 }
 390
 391                 xgifb_reg_set(P3d4, 0x97, 0x00);
 392                 xgifb_reg_set(P3d4, 0x98, 0x01);
 393                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 394                 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
 395         }
 396 }
 397
 398 static void XGINew_DDR2_DefaultRegister(
 399                 struct xgi_hw_device_info *HwDeviceExtension,
 400                 unsigned long Port, struct vb_device_info *pVBInfo)
 401 {
 402         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 403
 404         /* keep following setting sequence, each setting in
 405          * the same reg insert idle */
 406         xgifb_reg_set(P3d4, 0x82, 0x77);
 407         xgifb_reg_set(P3d4, 0x86, 0x00);
 408         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 409         xgifb_reg_set(P3d4, 0x86, 0x88);
 410         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 411         /* CR86 */
 412         xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
 413         xgifb_reg_set(P3d4, 0x82, 0x77);
 414         xgifb_reg_set(P3d4, 0x85, 0x00);
 415         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 416         xgifb_reg_set(P3d4, 0x85, 0x88);
 417         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 418         xgifb_reg_set(P3d4,
 419                       0x85,
 420                       pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 421         if (HwDeviceExtension->jChipType == XG27)
 422                 /* CR82 */
 423                 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
 424         else
 425                 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
 426
 427         xgifb_reg_set(P3d4, 0x98, 0x01);
 428         xgifb_reg_set(P3d4, 0x9A, 0x02);
 429         if (HwDeviceExtension->jChipType == XG27)
 430                 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
 431         else
 432                 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
 433 }
 434
 435 static void XGINew_SetDRAMDefaultRegister340(
 436                 struct xgi_hw_device_info *HwDeviceExtension,
 437                 unsigned long Port, struct vb_device_info *pVBInfo)
 438 {
 439         unsigned char temp, temp1, temp2, temp3, i, j, k;
 440
 441         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 442
 443         xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
 444         xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
 445         xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
 446         xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
 447
 448         temp2 = 0;
 449         for (i = 0; i < 4; i++) {
 450                 /* CR6B DQS fine tune delay */
 451                 temp = pVBInfo->CR6B[pVBInfo->ram_type][i];
 452                 for (j = 0; j < 4; j++) {
 453                         temp1 = ((temp >> (2 * j)) & 0x03) << 2;
 454                         temp2 |= temp1;
 455                         xgifb_reg_set(P3d4, 0x6B, temp2);
 456                         /* Insert read command for delay */
 457                         xgifb_reg_get(P3d4, 0x6B);
 458                         temp2 &= 0xF0;
 459                         temp2 += 0x10;
 460                 }
 461         }
 462
 463         temp2 = 0;
 464         for (i = 0; i < 4; i++) {
 465                 /* CR6E DQM fine tune delay */
 466                 temp = pVBInfo->CR6E[pVBInfo->ram_type][i];
 467                 for (j = 0; j < 4; j++) {
 468                         temp1 = ((temp >> (2 * j)) & 0x03) << 2;
 469                         temp2 |= temp1;
 470                         xgifb_reg_set(P3d4, 0x6E, temp2);
 471                         /* Insert read command for delay */
 472                         xgifb_reg_get(P3d4, 0x6E);
 473                         temp2 &= 0xF0;
 474                         temp2 += 0x10;
 475                 }
 476         }
 477
 478         temp3 = 0;
 479         for (k = 0; k < 4; k++) {
 480                 /* CR6E_D[1:0] select channel */
 481                 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
 482                 temp2 = 0;
 483                 for (i = 0; i < 8; i++) {
 484                         /* CR6F DQ fine tune delay */
 485                         temp = pVBInfo->CR6F[pVBInfo->ram_type][8 * k + i];
 486                         for (j = 0; j < 4; j++) {
 487                                 temp1 = (temp >> (2 * j)) & 0x03;
 488                                 temp2 |= temp1;
 489                                 xgifb_reg_set(P3d4, 0x6F, temp2);
 490                                 /* Insert read command for delay */
 491                                 xgifb_reg_get(P3d4, 0x6F);
 492                                 temp2 &= 0xF8;
 493                                 temp2 += 0x08;
 494                         }
 495                 }
 496                 temp3 += 0x01;
 497         }
 498
 499         xgifb_reg_set(P3d4,
 500                       0x80,
 501                       pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
 502         xgifb_reg_set(P3d4,
 503                       0x81,
 504                       pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
 505
 506         temp2 = 0x80;
 507         /* CR89 terminator type select */
 508         temp = pVBInfo->CR89[pVBInfo->ram_type][0];
 509         for (j = 0; j < 4; j++) {
 510                 temp1 = (temp >> (2 * j)) & 0x03;
 511                 temp2 |= temp1;
 512                 xgifb_reg_set(P3d4, 0x89, temp2);
 513                 xgifb_reg_get(P3d4, 0x89); /* Insert read command for delay */
 514                 temp2 &= 0xF0;
 515                 temp2 += 0x10;
 516         }
 517
 518         temp = pVBInfo->CR89[pVBInfo->ram_type][1];
 519         temp1 = temp & 0x03;
 520         temp2 |= temp1;
 521         xgifb_reg_set(P3d4, 0x89, temp2);
 522
 523         temp = pVBInfo->CR40[3][pVBInfo->ram_type];
 524         temp1 = temp & 0x0F;
 525         temp2 = (temp >> 4) & 0x07;
 526         temp3 = temp & 0x80;
 527         xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
 528         xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
 529         xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
 530         xgifb_reg_set(P3d4,
 531                       0x41,
 532                       pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
 533
 534         if (HwDeviceExtension->jChipType == XG27)
 535                 xgifb_reg_set(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
 536
 537         for (j = 0; j <= 6; j++) /* CR90 - CR96 */
 538                 xgifb_reg_set(P3d4, (0x90 + j),
 539                                 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
 540
 541         for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
 542                 xgifb_reg_set(P3d4, (0xC3 + j),
 543                                 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
 544
 545         for (j = 0; j < 2; j++) /* CR8A - CR8B */
 546                 xgifb_reg_set(P3d4, (0x8A + j),
 547                                 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
 548
 549         if (HwDeviceExtension->jChipType == XG42)
 550                 xgifb_reg_set(P3d4, 0x8C, 0x87);
 551
 552         xgifb_reg_set(P3d4,
 553                       0x59,
 554                       pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
 555
 556         xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
 557         xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
 558         xgifb_reg_set(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */
 559         if (pVBInfo->ram_type) {
 560                 /* xgifb_reg_set(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */
 561                 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
 562                 if (HwDeviceExtension->jChipType == XG27)
 563                         xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
 564
 565         } else {
 566                 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
 567         }
 568         xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
 569
 570         temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 571         if (temp == 0) {
 572                 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 573         } else {
 574                 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
 575                 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 576         }
 577         xgifb_reg_set(P3c4,
 578                       0x1B,
 579                       pVBInfo->SR15[3][pVBInfo->ram_type]); /* SR1B */
 580 }
 581
 582 static void XGINew_SetDRAMSizingType(int index,
 583                 const unsigned short DRAMTYPE_TABLE[][5],
 584                 struct vb_device_info *pVBInfo)
 585 {
 586         unsigned short data;
 587
 588         data = DRAMTYPE_TABLE[index][4];
 589         xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, data);
 590         udelay(15);
 591         /* should delay 50 ns */
 592 }
 593
 594 static unsigned short XGINew_SetDRAMSizeReg(int index,
 595                 const unsigned short DRAMTYPE_TABLE[][5],
 596                 struct vb_device_info *pVBInfo)
 597 {
 598         unsigned short data = 0, memsize = 0;
 599         int RankSize;
 600         unsigned char ChannelNo;
 601
 602         RankSize = DRAMTYPE_TABLE[index][3] * pVBInfo->ram_bus / 32;
 603         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 604         data &= 0x80;
 605
 606         if (data == 0x80)
 607                 RankSize *= 2;
 608
 609         data = 0;
 610
 611         if (pVBInfo->ram_channel == 3)
 612                 ChannelNo = 4;
 613         else
 614                 ChannelNo = pVBInfo->ram_channel;
 615
 616         if (ChannelNo * RankSize <= 256) {
 617                 while ((RankSize >>= 1) > 0)
 618                         data += 0x10;
 619
 620                 memsize = data >> 4;
 621
 622                 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
 623                 xgifb_reg_set(pVBInfo->P3c4,
 624                               0x14,
 625                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 626                                (data & 0xF0));
 627
 628                 /* data |= pVBInfo->ram_channel << 2; */
 629                 /* data |= (pVBInfo->ram_bus / 64) << 1; */
 630                 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
 631
 632                 /* should delay */
 633                 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
 634         }
 635         return memsize;
 636 }
 637
 638 static unsigned short XGINew_SetDRAMSize20Reg(int index,
 639                 const unsigned short DRAMTYPE_TABLE[][5],
 640                 struct vb_device_info *pVBInfo)
 641 {
 642         unsigned short data = 0, memsize = 0;
 643         int RankSize;
 644         unsigned char ChannelNo;
 645
 646         RankSize = DRAMTYPE_TABLE[index][3] * pVBInfo->ram_bus / 8;
 647         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 648         data &= 0x80;
 649
 650         if (data == 0x80)
 651                 RankSize *= 2;
 652
 653         data = 0;
 654
 655         if (pVBInfo->ram_channel == 3)
 656                 ChannelNo = 4;
 657         else
 658                 ChannelNo = pVBInfo->ram_channel;
 659
 660         if (ChannelNo * RankSize <= 256) {
 661                 while ((RankSize >>= 1) > 0)
 662                         data += 0x10;
 663
 664                 memsize = data >> 4;
 665
 666                 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
 667                 xgifb_reg_set(pVBInfo->P3c4,
 668                               0x14,
 669                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 670                                 (data & 0xF0));
 671                 udelay(15);
 672
 673                 /* data |= pVBInfo->ram_channel << 2; */
 674                 /* data |= (pVBInfo->ram_bus / 64) << 1; */
 675                 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
 676
 677                 /* should delay */
 678                 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
 679         }
 680         return memsize;
 681 }
 682
 683 static int XGINew_ReadWriteRest(unsigned short StopAddr,
 684                 unsigned short StartAddr, struct vb_device_info *pVBInfo)
 685 {
 686         int i;
 687         unsigned long Position = 0;
 688         void __iomem *fbaddr = pVBInfo->FBAddr;
 689
 690         writel(Position, fbaddr + Position);
 691
 692         for (i = StartAddr; i <= StopAddr; i++) {
 693                 Position = 1 << i;
 694                 writel(Position, fbaddr + Position);
 695         }
 696
 697         udelay(500); /* [Vicent] 2004/04/16.
 698                         Fix #1759 Memory Size error in Multi-Adapter. */
 699
 700         Position = 0;
 701
 702         if (readl(fbaddr + Position) != Position)
 703                 return 0;
 704
 705         for (i = StartAddr; i <= StopAddr; i++) {
 706                 Position = 1 << i;
 707                 if (readl(fbaddr + Position) != Position)
 708                         return 0;
 709         }
 710         return 1;
 711 }
 712
 713 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
 714 {
 715         unsigned char data;
 716
 717         data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 718
 719         if ((data & 0x10) == 0) {
 720                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
 721                 data = (data & 0x02) >> 1;
 722                 return data;
 723         } else {
 724                 return data & 0x01;
 725         }
 726 }
 727
 728 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
 729                 struct vb_device_info *pVBInfo)
 730 {
 731         unsigned char data;
 732
 733         switch (HwDeviceExtension->jChipType) {
 734         case XG20:
 735         case XG21:
 736                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 737                 data = data & 0x01;
 738                 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
 739
 740                 if (data == 0) { /* Single_32_16 */
 741
 742                         if ((HwDeviceExtension->ulVideoMemorySize - 1)
 743                                         > 0x1000000) {
 744
 745                                 pVBInfo->ram_bus = 32; /* 32 bits */
 746                                 /* 22bit + 2 rank + 32bit */
 747                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 748                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 749                                 udelay(15);
 750
 751                                 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 752                                         return;
 753
 754                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 755                                     0x800000) {
 756                                         /* 22bit + 1 rank + 32bit */
 757                                         xgifb_reg_set(pVBInfo->P3c4,
 758                                                       0x13,
 759                                                       0x31);
 760                                         xgifb_reg_set(pVBInfo->P3c4,
 761                                                       0x14,
 762                                                       0x42);
 763                                         udelay(15);
 764
 765                                         if (XGINew_ReadWriteRest(23,
 766                                                                  23,
 767                                                                  pVBInfo) == 1)
 768                                                 return;
 769                                 }
 770                         }
 771
 772                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 773                             0x800000) {
 774                                 pVBInfo->ram_bus = 16; /* 16 bits */
 775                                 /* 22bit + 2 rank + 16bit */
 776                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 777                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 778                                 udelay(15);
 779
 780                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 781                                         return;
 782                                 else
 783                                         xgifb_reg_set(pVBInfo->P3c4,
 784                                                       0x13,
 785                                                       0x31);
 786                                 udelay(15);
 787                         }
 788
 789                 } else { /* Dual_16_8 */
 790                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 791                             0x800000) {
 792                                 pVBInfo->ram_bus = 16; /* 16 bits */
 793                                 /* (0x31:12x8x2) 22bit + 2 rank */
 794                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 795                                 /* 0x41:16Mx16 bit*/
 796                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 797                                 udelay(15);
 798
 799                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 800                                         return;
 801
 802                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 803                                     0x400000) {
 804                                         /* (0x31:12x8x2) 22bit + 1 rank */
 805                                         xgifb_reg_set(pVBInfo->P3c4,
 806                                                       0x13,
 807                                                       0x31);
 808                                         /* 0x31:8Mx16 bit*/
 809                                         xgifb_reg_set(pVBInfo->P3c4,
 810                                                       0x14,
 811                                                       0x31);
 812                                         udelay(15);
 813
 814                                         if (XGINew_ReadWriteRest(22,
 815                                                                  22,
 816                                                                  pVBInfo) == 1)
 817                                                 return;
 818                                 }
 819                         }
 820
 821                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 822                             0x400000) {
 823                                 pVBInfo->ram_bus = 8; /* 8 bits */
 824                                 /* (0x31:12x8x2) 22bit + 2 rank */
 825                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 826                                 /* 0x30:8Mx8 bit*/
 827                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 828                                 udelay(15);
 829
 830                                 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
 831                                         return;
 832                                 else /* (0x31:12x8x2) 22bit + 1 rank */
 833                                         xgifb_reg_set(pVBInfo->P3c4,
 834                                                       0x13,
 835                                                       0x31);
 836                                 udelay(15);
 837                         }
 838                 }
 839                 break;
 840
 841         case XG27:
 842                 pVBInfo->ram_bus = 16; /* 16 bits */
 843                 pVBInfo->ram_channel = 1; /* Single channel */
 844                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
 845                 break;
 846         case XG42:
 847                 /*
 848                  XG42 SR14 D[3] Reserve
 849                  D[2] = 1, Dual Channel
 850                  = 0, Single Channel
 851
 852                  It's Different from Other XG40 Series.
 853                  */
 854                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
 855                         pVBInfo->ram_bus = 32; /* 32 bits */
 856                         pVBInfo->ram_channel = 2; /* 2 Channel */
 857                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 858                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
 859
 860                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 861                                 return;
 862
 863                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 864                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
 865                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 866                                 return;
 867
 868                         pVBInfo->ram_channel = 1; /* Single Channel */
 869                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 870                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
 871
 872                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 873                                 return;
 874                         else {
 875                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 876                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 877                         }
 878                 } else { /* DDR */
 879                         pVBInfo->ram_bus = 64; /* 64 bits */
 880                         pVBInfo->ram_channel = 1; /* 1 channels */
 881                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 882                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 883
 884                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 885                                 return;
 886                         else {
 887                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 888                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
 889                         }
 890                 }
 891
 892                 break;
 893
 894         default: /* XG40 */
 895
 896                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
 897                         pVBInfo->ram_bus = 32; /* 32 bits */
 898                         pVBInfo->ram_channel = 3;
 899                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 900                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
 901
 902                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
 903                                 return;
 904
 905                         pVBInfo->ram_channel = 2; /* 2 channels */
 906                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
 907
 908                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 909                                 return;
 910
 911                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 912                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
 913
 914                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
 915                                 pVBInfo->ram_channel = 3; /* 4 channels */
 916                         } else {
 917                                 pVBInfo->ram_channel = 2; /* 2 channels */
 918                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
 919                         }
 920                 } else { /* DDR */
 921                         pVBInfo->ram_bus = 64; /* 64 bits */
 922                         pVBInfo->ram_channel = 2; /* 2 channels */
 923                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 924                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
 925
 926                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
 927                                 return;
 928                         } else {
 929                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 930                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
 931                         }
 932                 }
 933                 break;
 934         }
 935 }
 936
 937 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
 938                 struct vb_device_info *pVBInfo)
 939 {
 940         int i;
 941         unsigned short memsize, addr;
 942
 943         xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
 944         xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
 945         XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
 946
 947         if (HwDeviceExtension->jChipType >= XG20) {
 948                 for (i = 0; i < 12; i++) {
 949                         XGINew_SetDRAMSizingType(i,
 950                                                  XGINew_DDRDRAM_TYPE20,
 951                                                  pVBInfo);
 952                         memsize = XGINew_SetDRAMSize20Reg(i,
 953                                                           XGINew_DDRDRAM_TYPE20,
 954                                                           pVBInfo);
 955                         if (memsize == 0)
 956                                 continue;
 957
 958                         addr = memsize + (pVBInfo->ram_channel - 2) + 20;
 959                         if ((HwDeviceExtension->ulVideoMemorySize - 1) <
 960                             (unsigned long) (1 << addr))
 961                                 continue;
 962
 963                         if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1)
 964                                 return 1;
 965                 }
 966         } else {
 967                 for (i = 0; i < 4; i++) {
 968                         XGINew_SetDRAMSizingType(i,
 969                                                  XGINew_DDRDRAM_TYPE340,
 970                                                  pVBInfo);
 971                         memsize = XGINew_SetDRAMSizeReg(i,
 972                                                         XGINew_DDRDRAM_TYPE340,
 973                                                         pVBInfo);
 974
 975                         if (memsize == 0)
 976                                 continue;
 977
 978                         addr = memsize + (pVBInfo->ram_channel - 2) + 20;
 979                         if ((HwDeviceExtension->ulVideoMemorySize - 1) <
 980                             (unsigned long) (1 << addr))
 981                                 continue;
 982
 983                         if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1)
 984                                 return 1;
 985                 }
 986         }
 987         return 0;
 988 }
 989
 990 static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
 991                 struct xgi_hw_device_info *HwDeviceExtension,
 992                 struct vb_device_info *pVBInfo)
 993 {
 994         unsigned short data;
 995
 996         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
 997
 998         XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
 999
1000         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1001         /* disable read cache */
1002         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
1003         XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
1004
1005         /* data = xgifb_reg_get(pVBInfo->P3c4, 0x1); */
1006         /* data |= 0x20 ; */
1007         /* xgifb_reg_set(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
1008         XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
1009         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1010         /* enable read cache */
1011         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
1012 }
1013
1014 static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
1015 {
1016         void __iomem *rom_address;
1017         u8 *rom_copy;
1018
1019         rom_address = pci_map_rom(dev, rom_size);
1020         if (rom_address == NULL)
1021                 return NULL;
1022
1023         rom_copy = vzalloc(XGIFB_ROM_SIZE);
1024         if (rom_copy == NULL)
1025                 goto done;
1026
1027         *rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
1028         memcpy_fromio(rom_copy, rom_address, *rom_size);
1029
1030 done:
1031         pci_unmap_rom(dev, rom_address);
1032         return rom_copy;
1033 }
1034
1035 static void xgifb_read_vbios(struct pci_dev *pdev,
1036                               struct vb_device_info *pVBInfo)
1037 {
1038         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1039         u8 *vbios;
1040         unsigned long i;
1041         unsigned char j;
1042         struct XGI21_LVDSCapStruct *lvds;
1043         size_t vbios_size;
1044         int entry;
1045
1046         if (xgifb_info->chip != XG21)
1047                 return;
1048         pVBInfo->IF_DEF_LVDS = 0;
1049         vbios = xgifb_copy_rom(pdev, &vbios_size);
1050         if (vbios == NULL) {
1051                 dev_err(&pdev->dev, "video BIOS not available\n");
1052                 return;
1053         }
1054         if (vbios_size <= 0x65)
1055                 goto error;
1056         /*
1057          * The user can ignore the LVDS bit in the BIOS and force the display
1058          * type.
1059          */
1060         if (!(vbios[0x65] & 0x1) &&
1061             (!xgifb_info->display2_force ||
1062              xgifb_info->display2 != XGIFB_DISP_LCD)) {
1063                 vfree(vbios);
1064                 return;
1065         }
1066         if (vbios_size <= 0x317)
1067                 goto error;
1068         i = vbios[0x316] | (vbios[0x317] << 8);
1069         if (vbios_size <= i - 1)
1070                 goto error;
1071         j = vbios[i - 1];
1072         if (j == 0)
1073                 goto error;
1074         if (j == 0xff)
1075                 j = 1;
1076         /*
1077          * Read the LVDS table index scratch register set by the BIOS.
1078          */
1079         entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
1080         if (entry >= j)
1081                 entry = 0;
1082         i += entry * 25;
1083         lvds = &xgifb_info->lvds_data;
1084         if (vbios_size <= i + 24)
1085                 goto error;
1086         lvds->LVDS_Capability   = vbios[i]      | (vbios[i + 1] << 8);
1087         lvds->LVDSHT            = vbios[i + 2]  | (vbios[i + 3] << 8);
1088         lvds->LVDSVT            = vbios[i + 4]  | (vbios[i + 5] << 8);
1089         lvds->LVDSHDE           = vbios[i + 6]  | (vbios[i + 7] << 8);
1090         lvds->LVDSVDE           = vbios[i + 8]  | (vbios[i + 9] << 8);
1091         lvds->LVDSHFP           = vbios[i + 10] | (vbios[i + 11] << 8);
1092         lvds->LVDSVFP           = vbios[i + 12] | (vbios[i + 13] << 8);
1093         lvds->LVDSHSYNC         = vbios[i + 14] | (vbios[i + 15] << 8);
1094         lvds->LVDSVSYNC         = vbios[i + 16] | (vbios[i + 17] << 8);
1095         lvds->VCLKData1         = vbios[i + 18];
1096         lvds->VCLKData2         = vbios[i + 19];
1097         lvds->PSC_S1            = vbios[i + 20];
1098         lvds->PSC_S2            = vbios[i + 21];
1099         lvds->PSC_S3            = vbios[i + 22];
1100         lvds->PSC_S4            = vbios[i + 23];
1101         lvds->PSC_S5            = vbios[i + 24];
1102         vfree(vbios);
1103         pVBInfo->IF_DEF_LVDS = 1;
1104         return;
1105 error:
1106         dev_err(&pdev->dev, "video BIOS corrupted\n");
1107         vfree(vbios);
1108 }
1109
1110 static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
1111                 struct vb_device_info *pVBInfo)
1112 {
1113         unsigned short tempbx = 0, temp, tempcx, CR3CData;
1114
1115         temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
1116
1117         if (temp & Monitor1Sense)
1118                 tempbx |= ActiveCRT1;
1119         if (temp & LCDSense)
1120                 tempbx |= ActiveLCD;
1121         if (temp & Monitor2Sense)
1122                 tempbx |= ActiveCRT2;
1123         if (temp & TVSense) {
1124                 tempbx |= ActiveTV;
1125                 if (temp & AVIDEOSense)
1126                         tempbx |= (ActiveAVideo << 8);
1127                 if (temp & SVIDEOSense)
1128                         tempbx |= (ActiveSVideo << 8);
1129                 if (temp & SCARTSense)
1130                         tempbx |= (ActiveSCART << 8);
1131                 if (temp & HiTVSense)
1132                         tempbx |= (ActiveHiTV << 8);
1133                 if (temp & YPbPrSense)
1134                         tempbx |= (ActiveYPbPr << 8);
1135         }
1136
1137         tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1138         tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
1139
1140         if (tempbx & tempcx) {
1141                 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
1142                 if (!(CR3CData & DisplayDeviceFromCMOS)) {
1143                         tempcx = 0x1FF0;
1144                         if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1145                                 tempbx = 0x1FF0;
1146                 }
1147         } else {
1148                 tempcx = 0x1FF0;
1149                 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1150                         tempbx = 0x1FF0;
1151         }
1152
1153         tempbx &= tempcx;
1154         xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1155         xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
1156 }
1157
1158 static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1159                 struct vb_device_info *pVBInfo)
1160 {
1161         unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
1162
1163         temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1164         temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
1165         temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
1166
1167         if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1168                 if (temp & ActiveCRT2)
1169                         tempcl = SetCRT2ToRAMDAC;
1170         }
1171
1172         if (temp & ActiveLCD) {
1173                 tempcl |= SetCRT2ToLCD;
1174                 if (temp & DriverMode) {
1175                         if (temp & ActiveTV) {
1176                                 tempch = SetToLCDA | EnableDualEdge;
1177                                 temp ^= SetCRT2ToLCD;
1178
1179                                 if ((temp >> 8) & ActiveAVideo)
1180                                         tempcl |= SetCRT2ToAVIDEO;
1181                                 if ((temp >> 8) & ActiveSVideo)
1182                                         tempcl |= SetCRT2ToSVIDEO;
1183                                 if ((temp >> 8) & ActiveSCART)
1184                                         tempcl |= SetCRT2ToSCART;
1185
1186                                 if (pVBInfo->IF_DEF_HiVision == 1) {
1187                                         if ((temp >> 8) & ActiveHiTV)
1188                                                 tempcl |= SetCRT2ToHiVision;
1189                                 }
1190
1191                                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1192                                         if ((temp >> 8) & ActiveYPbPr)
1193                                                 tempch |= SetYPbPr;
1194                                 }
1195                         }
1196                 }
1197         } else {
1198                 if ((temp >> 8) & ActiveAVideo)
1199                         tempcl |= SetCRT2ToAVIDEO;
1200                 if ((temp >> 8) & ActiveSVideo)
1201                         tempcl |= SetCRT2ToSVIDEO;
1202                 if ((temp >> 8) & ActiveSCART)
1203                         tempcl |= SetCRT2ToSCART;
1204
1205                 if (pVBInfo->IF_DEF_HiVision == 1) {
1206                         if ((temp >> 8) & ActiveHiTV)
1207                                 tempcl |= SetCRT2ToHiVision;
1208                 }
1209
1210                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1211                         if ((temp >> 8) & ActiveYPbPr)
1212                                 tempch |= SetYPbPr;
1213                 }
1214         }
1215
1216         tempcl |= SetSimuScanMode;
1217         if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1218                         || (temp & ActiveCRT2)))
1219                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1220         if ((temp & ActiveLCD) && (temp & ActiveTV))
1221                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1222         xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1223
1224         CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1225         CR31Data &= ~(SetNotSimuMode >> 8);
1226         if (!(temp & ActiveCRT1))
1227                 CR31Data |= (SetNotSimuMode >> 8);
1228         CR31Data &= ~(DisableCRT2Display >> 8);
1229         if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1230                 CR31Data |= (DisableCRT2Display >> 8);
1231         xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1232
1233         CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1234         CR38Data &= ~SetYPbPr;
1235         CR38Data |= tempch;
1236         xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1237
1238 }
1239
1240 static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1241                                                         *HwDeviceExtension,
1242                                       struct vb_device_info *pVBInfo)
1243 {
1244         unsigned short temp;
1245
1246         /* add lcd sense */
1247         if (HwDeviceExtension->ulCRT2LCDType == LCD_UNKNOWN) {
1248                 return 0;
1249         } else {
1250                 temp = (unsigned short) HwDeviceExtension->ulCRT2LCDType;
1251                 switch (HwDeviceExtension->ulCRT2LCDType) {
1252                 case LCD_INVALID:
1253                 case LCD_800x600:
1254                 case LCD_1024x768:
1255                 case LCD_1280x1024:
1256                         break;
1257
1258                 case LCD_640x480:
1259                 case LCD_1024x600:
1260                 case LCD_1152x864:
1261                 case LCD_1280x960:
1262                 case LCD_1152x768:
1263                         temp = 0;
1264                         break;
1265
1266                 case LCD_1400x1050:
1267                 case LCD_1280x768:
1268                 case LCD_1600x1200:
1269                         break;
1270
1271                 case LCD_1920x1440:
1272                 case LCD_2048x1536:
1273                         temp = 0;
1274                         break;
1275
1276                 default:
1277                         break;
1278                 }
1279                 xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1280                 return 1;
1281         }
1282 }
1283
1284 static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1285                 struct vb_device_info *pVBInfo)
1286 {
1287         unsigned char Temp;
1288
1289 #if 1
1290         if (pVBInfo->IF_DEF_LVDS) { /* For XG21 LVDS */
1291                 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1292                 /* LVDS on chip */
1293                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1294         } else {
1295 #endif
1296                 /* Enable GPIOA/B read  */
1297                 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1298                 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1299                 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1300                         XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
1301                         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1302                         /* Enable read GPIOF */
1303                         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1304                         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
1305                         if (!Temp)
1306                                 xgifb_reg_and_or(pVBInfo->P3d4,
1307                                                  0x38,
1308                                                  ~0xE0,
1309                                                  0x80); /* TMDS on chip */
1310                         else
1311                                 xgifb_reg_and_or(pVBInfo->P3d4,
1312                                                  0x38,
1313                                                  ~0xE0,
1314                                                  0xA0); /* Only DVO on chip */
1315                         /* Disable read GPIOF */
1316                         xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1317                 }
1318 #if 1
1319         }
1320 #endif
1321 }
1322
1323 static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1324                 struct vb_device_info *pVBInfo)
1325 {
1326         unsigned char Temp, bCR4A;
1327
1328         pVBInfo->IF_DEF_LVDS = 0;
1329         bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1330         /* Enable GPIOA/B/C read  */
1331         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1332         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1333         xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1334
1335         if (Temp <= 0x02) {
1336                 /* LVDS setting */
1337                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1338                 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1339         } else {
1340                 /* TMDS/DVO setting */
1341                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1342         }
1343         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1344
1345 }
1346
1347 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1348 {
1349         unsigned char CR38, CR4A, temp;
1350
1351         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1352         /* enable GPIOE read */
1353         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1354         CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1355         temp = 0;
1356         if ((CR38 & 0xE0) > 0x80) {
1357                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1358                 temp &= 0x08;
1359                 temp >>= 3;
1360         }
1361
1362         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1363
1364         return temp;
1365 }
1366
1367 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1368 {
1369         unsigned char CR4A, temp;
1370
1371         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1372         /* enable GPIOA/B/C read */
1373         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1374         temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1375         if (temp <= 2)
1376                 temp &= 0x03;
1377         else
1378                 temp = ((temp & 0x04) >> 1) || ((~temp) & 0x01);
1379
1380         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1381
1382         return temp;
1383 }
1384
1385 unsigned char XGIInitNew(struct pci_dev *pdev)
1386 {
1387         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1388         struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1389         struct vb_device_info VBINF;
1390         struct vb_device_info *pVBInfo = &VBINF;
1391         unsigned char i, temp = 0, temp1;
1392         /* VBIOSVersion[5]; */
1393
1394         /* unsigned long j, k; */
1395
1396         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1397
1398         pVBInfo->BaseAddr = xgifb_info->vga_base;
1399
1400         /* Newdebugcode(0x99); */
1401
1402         if (pVBInfo->FBAddr == NULL) {
1403                 printk("\n pVBInfo->FBAddr == 0 ");
1404                 return 0;
1405         }
1406         printk("1");
1407         if (pVBInfo->BaseAddr == 0) {
1408                 printk("\npVBInfo->BaseAddr == 0 ");
1409                 return 0;
1410         }
1411         printk("2");
1412
1413         outb(0x67, (pVBInfo->BaseAddr + 0x12)); /* 3c2 <- 67 ,ynlai */
1414
1415         pVBInfo->ISXPDOS = 0;
1416         printk("3");
1417
1418         printk("4");
1419
1420         /* VBIOSVersion[4] = 0x0; */
1421
1422         /* 09/07/99 modify by domao */
1423
1424         pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
1425         pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
1426         pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
1427         pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
1428         pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
1429         pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
1430         pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
1431         pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
1432         pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
1433         pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
1434         pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
1435         pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
1436         pVBInfo->Part1Port = pVBInfo->BaseAddr + SIS_CRT2_PORT_04;
1437         pVBInfo->Part2Port = pVBInfo->BaseAddr + SIS_CRT2_PORT_10;
1438         pVBInfo->Part3Port = pVBInfo->BaseAddr + SIS_CRT2_PORT_12;
1439         pVBInfo->Part4Port = pVBInfo->BaseAddr + SIS_CRT2_PORT_14;
1440         pVBInfo->Part5Port = pVBInfo->BaseAddr + SIS_CRT2_PORT_14 + 2;
1441         printk("5");
1442
1443         if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
1444                 /* Run XGI_GetVBType before InitTo330Pointer */
1445                 XGI_GetVBType(pVBInfo);
1446
1447         InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1448
1449         xgifb_read_vbios(pdev, pVBInfo);
1450
1451         /* 1.Openkey */
1452         xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1453         printk("6");
1454
1455         /* GetXG21Sense (GPIO) */
1456         if (HwDeviceExtension->jChipType == XG21)
1457                 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
1458
1459         if (HwDeviceExtension->jChipType == XG27)
1460                 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1461
1462         printk("7");
1463
1464         /* 2.Reset Extended register */
1465
1466         for (i = 0x06; i < 0x20; i++)
1467                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1468
1469         for (i = 0x21; i <= 0x27; i++)
1470                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1471
1472         /* for(i = 0x06; i <= 0x27; i++) */
1473         /* xgifb_reg_set(pVBInfo->P3c4, i, 0); */
1474
1475         printk("8");
1476
1477         for (i = 0x31; i <= 0x3B; i++)
1478                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1479         printk("9");
1480
1481         /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
1482         if (HwDeviceExtension->jChipType == XG42)
1483                 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1484
1485         /* for (i = 0x30; i <= 0x3F; i++) */
1486         /* xgifb_reg_set(pVBInfo->P3d4, i, 0); */
1487
1488         for (i = 0x79; i <= 0x7C; i++)
1489                 xgifb_reg_set(pVBInfo->P3d4, i, 0); /* shampoo 0208 */
1490
1491         printk("10");
1492
1493         if (HwDeviceExtension->jChipType >= XG20)
1494                 xgifb_reg_set(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
1495
1496         /* 3.SetMemoryClock
1497
1498         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1499         */
1500
1501         printk("11");
1502
1503         /* 4.SetDefExt1Regs begin */
1504         xgifb_reg_set(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
1505         if (HwDeviceExtension->jChipType == XG27) {
1506                 xgifb_reg_set(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
1507                 xgifb_reg_set(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
1508         }
1509         xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1510         xgifb_reg_set(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
1511         /* xgifb_reg_set(pVBInfo->P3c4, 0x20, 0x20); */
1512         /* alan, 2001/6/26 Frame buffer can read/write SR20 */
1513         xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1514         /* Hsuan, 2006/01/01 H/W request for slow corner chip */
1515         xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1516         if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
1517                 xgifb_reg_set(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
1518
1519         /* SR11 = 0x0F; */
1520         /* xgifb_reg_set(pVBInfo->P3c4, 0x11, SR11); */
1521
1522         printk("12");
1523
1524         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1525                 u32 Temp;
1526
1527                 /* Set AGP Rate */
1528                 /*
1529                 temp1 = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
1530                 temp1 &= 0x02;
1531                 if (temp1 == 0x02) {
1532                         outl(0x80000000, 0xcf8);
1533                         ChipsetID = inl(0x0cfc);
1534                         outl(0x8000002C, 0xcf8);
1535                         VendorID = inl(0x0cfc);
1536                         VendorID &= 0x0000FFFF;
1537                         outl(0x8001002C, 0xcf8);
1538                         GraphicVendorID = inl(0x0cfc);
1539                         GraphicVendorID &= 0x0000FFFF;
1540
1541                         if (ChipsetID == 0x7301039)
1542                                 xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x09);
1543
1544                         ChipsetID &= 0x0000FFFF;
1545
1546                         if ((ChipsetID == 0x700E) ||
1547                             (ChipsetID == 0x1022) ||
1548                             (ChipsetID == 0x1106) ||
1549                             (ChipsetID == 0x10DE)) {
1550                                 if (ChipsetID == 0x1106) {
1551                                         if ((VendorID == 0x1019) &&
1552                                             (GraphicVendorID == 0x1019))
1553                                                 xgifb_reg_set(pVBInfo->P3d4,
1554                                                               0x5F,
1555                                                               0x0D);
1556                                         else
1557                                                 xgifb_reg_set(pVBInfo->P3d4,
1558                                                               0x5F,
1559                                                               0x0B);
1560                                 } else {
1561                                         xgifb_reg_set(pVBInfo->P3d4,
1562                                                       0x5F,
1563                                                       0x0B);
1564                                 }
1565                         }
1566                 }
1567                 */
1568
1569                 printk("13");
1570
1571                 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1572                 for (i = 0x47; i <= 0x4C; i++)
1573                         xgifb_reg_set(pVBInfo->P3d4,
1574                                       i,
1575                                       pVBInfo->AGPReg[i - 0x47]);
1576
1577                 for (i = 0x70; i <= 0x71; i++)
1578                         xgifb_reg_set(pVBInfo->P3d4,
1579                                       i,
1580                                       pVBInfo->AGPReg[6 + i - 0x70]);
1581
1582                 for (i = 0x74; i <= 0x77; i++)
1583                         xgifb_reg_set(pVBInfo->P3d4,
1584                                       i,
1585                                       pVBInfo->AGPReg[8 + i - 0x74]);
1586                 /* Set AGP customize registers (in SetDefAGPRegs) End */
1587                 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
1588                 /*        outl(0x80000000, 0xcf8); */
1589                 /*        ChipsetID = inl(0x0cfc); */
1590                 /*        if (ChipsetID == 0x25308086) */
1591                 /*            xgifb_reg_set(pVBInfo->P3d4, 0x77, 0xF0); */
1592
1593                 pci_read_config_dword(pdev, 0x50, &Temp);
1594                 Temp >>= 20;
1595                 Temp &= 0xF;
1596
1597                 if (Temp == 1)
1598                         xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1599                 printk("14");
1600         } /* != XG20 */
1601
1602         /* Set PCI */
1603         xgifb_reg_set(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
1604         xgifb_reg_set(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
1605         xgifb_reg_set(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
1606         printk("15");
1607
1608         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1609                 /* Set VB */
1610                 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
1611                 /* alan, disable VideoCapture */
1612                 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1613                 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1614                 /* chk if BCLK>=100MHz */
1615                 temp1 = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1616                 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
1617
1618                 xgifb_reg_set(pVBInfo->Part1Port,
1619                               0x02,
1620                               (*pVBInfo->pCRT2Data_1_2));
1621
1622                 printk("16");
1623
1624                 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1625         } /* != XG20 */
1626
1627         xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1628
1629         if ((HwDeviceExtension->jChipType == XG42) &&
1630             XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1631                 /* Not DDR */
1632                 xgifb_reg_set(pVBInfo->P3c4,
1633                               0x31,
1634                               (*pVBInfo->pSR31 & 0x3F) | 0x40);
1635                 xgifb_reg_set(pVBInfo->P3c4,
1636                               0x32,
1637                               (*pVBInfo->pSR32 & 0xFC) | 0x01);
1638         } else {
1639                 xgifb_reg_set(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
1640                 xgifb_reg_set(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
1641         }
1642         xgifb_reg_set(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
1643         printk("17");
1644
1645         /*
1646          SetPowerConsume (HwDeviceExtension, pVBInfo->P3c4);    */
1647
1648         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1649                 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1650                         if (pVBInfo->IF_DEF_LVDS == 0) {
1651                                 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1652                                 xgifb_reg_set(pVBInfo->Part4Port,
1653                                               0x0D,
1654                                               *pVBInfo->pCRT2Data_4_D);
1655                                 xgifb_reg_set(pVBInfo->Part4Port,
1656                                               0x0E,
1657                                               *pVBInfo->pCRT2Data_4_E);
1658                                 xgifb_reg_set(pVBInfo->Part4Port,
1659                                               0x10,
1660                                               *pVBInfo->pCRT2Data_4_10);
1661                                 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1662                         }
1663
1664                         XGI_LockCRT2(HwDeviceExtension, pVBInfo);
1665                 }
1666         } /* != XG20 */
1667         printk("18");
1668
1669         printk("181");
1670
1671         printk("182");
1672
1673         XGI_SenseCRT1(pVBInfo);
1674
1675         printk("183");
1676         /* XGINew_DetectMonitor(HwDeviceExtension); */
1677         if (HwDeviceExtension->jChipType == XG21) {
1678                 printk("186");
1679
1680                 xgifb_reg_and_or(pVBInfo->P3d4,
1681                                  0x32,
1682                                  ~Monitor1Sense,
1683                                  Monitor1Sense); /* Z9 default has CRT */
1684                 temp = GetXG21FPBits(pVBInfo);
1685                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1686                 printk("187");
1687
1688         }
1689         if (HwDeviceExtension->jChipType == XG27) {
1690                 xgifb_reg_and_or(pVBInfo->P3d4,
1691                                  0x32,
1692                                  ~Monitor1Sense,
1693                                  Monitor1Sense); /* Z9 default has CRT */
1694                 temp = GetXG27FPBits(pVBInfo);
1695                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1696         }
1697         printk("19");
1698
1699         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1700
1701         XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1702                                          pVBInfo->P3d4,
1703                                          pVBInfo);
1704
1705         printk("20");
1706         XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
1707         printk("21");
1708
1709         printk("22");
1710
1711         /* SetDefExt2Regs begin */
1712         /*
1713         AGP = 1;
1714         temp = (unsigned char) xgifb_reg_get(pVBInfo->P3c4, 0x3A);
1715         temp &= 0x30;
1716         if (temp == 0x30)
1717                 AGP = 0;
1718
1719         if (AGP == 0)
1720                 *pVBInfo->pSR21 &= 0xEF;
1721
1722         xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1723         if (AGP == 1)
1724                 *pVBInfo->pSR22 &= 0x20;
1725         xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
1726         */
1727         /* base = 0x80000000; */
1728         /* OutPortLong(0xcf8, base); */
1729         /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
1730         /* if (Temp == 0x1039) { */
1731         xgifb_reg_set(pVBInfo->P3c4,
1732                       0x22,
1733                       (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
1734         /* } else { */
1735         /*      xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
1736         /* } */
1737
1738         xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1739
1740         printk("23");
1741
1742         XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1743         XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
1744
1745         printk("24");
1746
1747         xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1748         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x31);
1749         printk("25");
1750
1751         return 1;
1752 } /* end of init */