drivers/staging/xgifb/vb_init.c

   1 #include <linux/types.h>
   2 #include <linux/delay.h> /* udelay */
   3 #include <linux/pci.h>
   4
   5 #include "vgatypes.h"
   6 #include "XGIfb.h"
   7
   8 #include "vb_def.h"
   9 #include "vb_struct.h"
  10 #include "vb_util.h"
  11 #include "vb_setmode.h"
  12 #include "vb_init.h"
  13 #include "vb_ext.h"
  14
  15
  16 #include <linux/io.h>
  17
  18 static const unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
  19         { 2, 13, 9, 64, 0x45},
  20         { 2, 12, 9, 32, 0x35},
  21         { 2, 12, 8, 16, 0x31},
  22         { 2, 11, 8,  8, 0x21} };
  23
  24 static const unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
  25         { 2, 14, 11, 128, 0x5D},
  26         { 2, 14, 10, 64, 0x59},
  27         { 2, 13, 11, 64, 0x4D},
  28         { 2, 14,  9, 32, 0x55},
  29         { 2, 13, 10, 32, 0x49},
  30         { 2, 12, 11, 32, 0x3D},
  31         { 2, 14,  8, 16, 0x51},
  32         { 2, 13,  9, 16, 0x45},
  33         { 2, 12, 10, 16, 0x39},
  34         { 2, 13,  8,  8, 0x41},
  35         { 2, 12,  9,  8, 0x35},
  36         { 2, 12,  8,  4, 0x31} };
  37
  38 static unsigned char
  39 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
  40                        struct vb_device_info *pVBInfo)
  41 {
  42         unsigned char data, temp;
  43
  44         if (HwDeviceExtension->jChipType < XG20) {
  45                 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
  46                         data = *pVBInfo->pSoftSetting & 0x07;
  47                         return data;
  48                 } else {
  49                         data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
  50                         if (data == 0)
  51                                 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
  52                                        0x02) >> 1;
  53                         return data;
  54                 }
  55         } else if (HwDeviceExtension->jChipType == XG27) {
  56                 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
  57                         data = *pVBInfo->pSoftSetting & 0x07;
  58                         return data;
  59                 }
  60                 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
  61                 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
  62                 if ((temp & 0x88) == 0x80)
  63                         data = 0; /* DDR */
  64                 else
  65                         data = 1; /* DDRII */
  66                 return data;
  67         } else if (HwDeviceExtension->jChipType == XG21) {
  68                 /* Independent GPIO control */
  69                 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
  70                 udelay(800);
  71                 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
  72                 /* GPIOF 0:DVI 1:DVO */
  73                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
  74                 /* HOTPLUG_SUPPORT */
  75                 /* for current XG20 & XG21, GPIOH is floating, driver will
  76                  * fix DDR temporarily */
  77                 if (temp & 0x01) /* DVI read GPIOH */
  78                         data = 1; /* DDRII */
  79                 else
  80                         data = 0; /* DDR */
  81                 /* ~HOTPLUG_SUPPORT */
  82                 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
  83                 return data;
  84         } else {
  85                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
  86
  87                 if (data == 1)
  88                         data++;
  89
  90                 return data;
  91         }
  92 }
  93
  94 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
  95                                  struct vb_device_info *pVBInfo)
  96 {
  97         xgifb_reg_set(P3c4, 0x18, 0x01);
  98         xgifb_reg_set(P3c4, 0x19, 0x20);
  99         xgifb_reg_set(P3c4, 0x16, 0x00);
 100         xgifb_reg_set(P3c4, 0x16, 0x80);
 101
 102         if (*pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C) { /* Samsung F Die */
 103                 mdelay(3);
 104                 xgifb_reg_set(P3c4, 0x18, 0x00);
 105                 xgifb_reg_set(P3c4, 0x19, 0x20);
 106                 xgifb_reg_set(P3c4, 0x16, 0x00);
 107                 xgifb_reg_set(P3c4, 0x16, 0x80);
 108         }
 109
 110         udelay(60);
 111         xgifb_reg_set(P3c4,
 112                       0x18,
 113                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 114         xgifb_reg_set(P3c4, 0x19, 0x01);
 115         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[0]);
 116         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[1]);
 117         mdelay(1);
 118         xgifb_reg_set(P3c4, 0x1B, 0x03);
 119         udelay(500);
 120         xgifb_reg_set(P3c4,
 121                       0x18,
 122                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 123         xgifb_reg_set(P3c4, 0x19, 0x00);
 124         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[2]);
 125         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[3]);
 126         xgifb_reg_set(P3c4, 0x1B, 0x00);
 127 }
 128
 129 static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
 130                 struct vb_device_info *pVBInfo)
 131 {
 132
 133         xgifb_reg_set(pVBInfo->P3c4,
 134                       0x28,
 135                       pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
 136         xgifb_reg_set(pVBInfo->P3c4,
 137                       0x29,
 138                       pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
 139         xgifb_reg_set(pVBInfo->P3c4,
 140                       0x2A,
 141                       pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
 142
 143         xgifb_reg_set(pVBInfo->P3c4,
 144                       0x2E,
 145                       pVBInfo->ECLKData[pVBInfo->ram_type].SR2E);
 146         xgifb_reg_set(pVBInfo->P3c4,
 147                       0x2F,
 148                       pVBInfo->ECLKData[pVBInfo->ram_type].SR2F);
 149         xgifb_reg_set(pVBInfo->P3c4,
 150                       0x30,
 151                       pVBInfo->ECLKData[pVBInfo->ram_type].SR30);
 152
 153         /* [Vicent] 2004/07/07,
 154          * When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
 155         /* [Hsuan] 2004/08/20,
 156          * Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz,
 157          * Set SR32 D[1:0] = 10b */
 158         if (HwDeviceExtension->jChipType == XG42) {
 159                 if ((pVBInfo->MCLKData[pVBInfo->ram_type].SR28 == 0x1C) &&
 160                     (pVBInfo->MCLKData[pVBInfo->ram_type].SR29 == 0x01) &&
 161                     (((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x1C) &&
 162                       (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01)) ||
 163                      ((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x22) &&
 164                       (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01))))
 165                         xgifb_reg_set(pVBInfo->P3c4,
 166                                       0x32,
 167                                       ((unsigned char) xgifb_reg_get(
 168                                           pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
 169         }
 170 }
 171
 172 static void XGINew_DDRII_Bootup_XG27(
 173                         struct xgi_hw_device_info *HwDeviceExtension,
 174                         unsigned long P3c4, struct vb_device_info *pVBInfo)
 175 {
 176         unsigned long P3d4 = P3c4 + 0x10;
 177         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 178         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 179
 180         /* Set Double Frequency */
 181         /* xgifb_reg_set(P3d4, 0x97, 0x11); *//* CR97 */
 182         xgifb_reg_set(P3d4, 0x97, *pVBInfo->pXGINew_CR97); /* CR97 */
 183
 184         udelay(200);
 185
 186         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
 187         xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
 188         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 189         udelay(15);
 190         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 191         udelay(15);
 192
 193         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
 194         xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
 195         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 196         udelay(15);
 197         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 198         udelay(15);
 199
 200         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
 201         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 202         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 203         udelay(30);
 204         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 205         udelay(15);
 206
 207         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
 208         xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
 209         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 210         udelay(30);
 211         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 212         xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
 213         /* udelay(15); */
 214
 215         xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
 216         udelay(60);
 217         xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
 218
 219         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
 220         xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
 221         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 222
 223         udelay(30);
 224         xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
 225         udelay(15);
 226
 227         xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
 228         xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
 229         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 230         udelay(30);
 231         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 232         udelay(15);
 233
 234         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
 235         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 236         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 237         udelay(30);
 238         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 239         udelay(15);
 240
 241         /* Set SR1B refresh control 000:close; 010:open */
 242         xgifb_reg_set(P3c4, 0x1B, 0x04);
 243         udelay(200);
 244
 245 }
 246
 247 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
 248                 unsigned long P3c4, struct vb_device_info *pVBInfo)
 249 {
 250         unsigned long P3d4 = P3c4 + 0x10;
 251
 252         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 253         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 254
 255         xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
 256
 257         udelay(200);
 258         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
 259         xgifb_reg_set(P3c4, 0x19, 0x80);
 260         xgifb_reg_set(P3c4, 0x16, 0x05);
 261         xgifb_reg_set(P3c4, 0x16, 0x85);
 262
 263         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
 264         xgifb_reg_set(P3c4, 0x19, 0xC0);
 265         xgifb_reg_set(P3c4, 0x16, 0x05);
 266         xgifb_reg_set(P3c4, 0x16, 0x85);
 267
 268         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
 269         xgifb_reg_set(P3c4, 0x19, 0x40);
 270         xgifb_reg_set(P3c4, 0x16, 0x05);
 271         xgifb_reg_set(P3c4, 0x16, 0x85);
 272
 273         /* xgifb_reg_set(P3c4, 0x18, 0x52); */ /* MRS1 */
 274         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 275         xgifb_reg_set(P3c4, 0x19, 0x02);
 276         xgifb_reg_set(P3c4, 0x16, 0x05);
 277         xgifb_reg_set(P3c4, 0x16, 0x85);
 278
 279         udelay(15);
 280         xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
 281         udelay(30);
 282         xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
 283         udelay(100);
 284
 285         /* xgifb_reg_set(P3c4 ,0x18, 0x52); */ /* MRS2 */
 286         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 287         xgifb_reg_set(P3c4, 0x19, 0x00);
 288         xgifb_reg_set(P3c4, 0x16, 0x05);
 289         xgifb_reg_set(P3c4, 0x16, 0x85);
 290
 291         udelay(200);
 292 }
 293
 294 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
 295                                   struct vb_device_info *pVBInfo)
 296 {
 297         xgifb_reg_set(P3c4, 0x18, 0x01);
 298         xgifb_reg_set(P3c4, 0x19, 0x40);
 299         xgifb_reg_set(P3c4, 0x16, 0x00);
 300         xgifb_reg_set(P3c4, 0x16, 0x80);
 301         udelay(60);
 302
 303         xgifb_reg_set(P3c4, 0x18, 0x00);
 304         xgifb_reg_set(P3c4, 0x19, 0x40);
 305         xgifb_reg_set(P3c4, 0x16, 0x00);
 306         xgifb_reg_set(P3c4, 0x16, 0x80);
 307         udelay(60);
 308         xgifb_reg_set(P3c4,
 309                       0x18,
 310                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 311         /* xgifb_reg_set(P3c4, 0x18, 0x31); */
 312         xgifb_reg_set(P3c4, 0x19, 0x01);
 313         xgifb_reg_set(P3c4, 0x16, 0x03);
 314         xgifb_reg_set(P3c4, 0x16, 0x83);
 315         mdelay(1);
 316         xgifb_reg_set(P3c4, 0x1B, 0x03);
 317         udelay(500);
 318         /* xgifb_reg_set(P3c4, 0x18, 0x31); */
 319         xgifb_reg_set(P3c4,
 320                       0x18,
 321                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 322         xgifb_reg_set(P3c4, 0x19, 0x00);
 323         xgifb_reg_set(P3c4, 0x16, 0x03);
 324         xgifb_reg_set(P3c4, 0x16, 0x83);
 325         xgifb_reg_set(P3c4, 0x1B, 0x00);
 326 }
 327
 328 static void XGINew_DDR1x_DefaultRegister(
 329                 struct xgi_hw_device_info *HwDeviceExtension,
 330                 unsigned long Port, struct vb_device_info *pVBInfo)
 331 {
 332         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 333
 334         if (HwDeviceExtension->jChipType >= XG20) {
 335                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 336                 xgifb_reg_set(P3d4,
 337                               0x82,
 338                               pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
 339                 xgifb_reg_set(P3d4,
 340                               0x85,
 341                               pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 342                 xgifb_reg_set(P3d4,
 343                               0x86,
 344                               pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
 345
 346                 xgifb_reg_set(P3d4, 0x98, 0x01);
 347                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 348
 349                 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
 350         } else {
 351                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 352
 353                 switch (HwDeviceExtension->jChipType) {
 354                 case XG41:
 355                 case XG42:
 356                         /* CR82 */
 357                         xgifb_reg_set(P3d4,
 358                                       0x82,
 359                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 360                         /* CR85 */
 361                         xgifb_reg_set(P3d4,
 362                                       0x85,
 363                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 364                         /* CR86 */
 365                         xgifb_reg_set(P3d4,
 366                                       0x86,
 367                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 368                         break;
 369                 default:
 370                         xgifb_reg_set(P3d4, 0x82, 0x88);
 371                         xgifb_reg_set(P3d4, 0x86, 0x00);
 372                         /* Insert read command for delay */
 373                         xgifb_reg_get(P3d4, 0x86);
 374                         xgifb_reg_set(P3d4, 0x86, 0x88);
 375                         xgifb_reg_get(P3d4, 0x86);
 376                         xgifb_reg_set(P3d4,
 377                                       0x86,
 378                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 379                         xgifb_reg_set(P3d4, 0x82, 0x77);
 380                         xgifb_reg_set(P3d4, 0x85, 0x00);
 381
 382                         /* Insert read command for delay */
 383                         xgifb_reg_get(P3d4, 0x85);
 384                         xgifb_reg_set(P3d4, 0x85, 0x88);
 385
 386                         /* Insert read command for delay */
 387                         xgifb_reg_get(P3d4, 0x85);
 388                         /* CR85 */
 389                         xgifb_reg_set(P3d4,
 390                                       0x85,
 391                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 392                         /* CR82 */
 393                         xgifb_reg_set(P3d4,
 394                                       0x82,
 395                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 396                         break;
 397                 }
 398
 399                 xgifb_reg_set(P3d4, 0x97, 0x00);
 400                 xgifb_reg_set(P3d4, 0x98, 0x01);
 401                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 402                 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
 403         }
 404 }
 405
 406 static void XGINew_DDR2_DefaultRegister(
 407                 struct xgi_hw_device_info *HwDeviceExtension,
 408                 unsigned long Port, struct vb_device_info *pVBInfo)
 409 {
 410         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 411
 412         /* keep following setting sequence, each setting in
 413          * the same reg insert idle */
 414         xgifb_reg_set(P3d4, 0x82, 0x77);
 415         xgifb_reg_set(P3d4, 0x86, 0x00);
 416         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 417         xgifb_reg_set(P3d4, 0x86, 0x88);
 418         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 419         /* CR86 */
 420         xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
 421         xgifb_reg_set(P3d4, 0x82, 0x77);
 422         xgifb_reg_set(P3d4, 0x85, 0x00);
 423         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 424         xgifb_reg_set(P3d4, 0x85, 0x88);
 425         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 426         xgifb_reg_set(P3d4,
 427                       0x85,
 428                       pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 429         if (HwDeviceExtension->jChipType == XG27)
 430                 /* CR82 */
 431                 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
 432         else
 433                 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
 434
 435         xgifb_reg_set(P3d4, 0x98, 0x01);
 436         xgifb_reg_set(P3d4, 0x9A, 0x02);
 437         if (HwDeviceExtension->jChipType == XG27)
 438                 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
 439         else
 440                 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
 441 }
 442
 443 static void XGINew_SetDRAMDefaultRegister340(
 444                 struct xgi_hw_device_info *HwDeviceExtension,
 445                 unsigned long Port, struct vb_device_info *pVBInfo)
 446 {
 447         unsigned char temp, temp1, temp2, temp3, i, j, k;
 448
 449         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 450
 451         xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
 452         xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
 453         xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
 454         xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
 455
 456         temp2 = 0;
 457         for (i = 0; i < 4; i++) {
 458                 /* CR6B DQS fine tune delay */
 459                 temp = pVBInfo->CR6B[pVBInfo->ram_type][i];
 460                 for (j = 0; j < 4; j++) {
 461                         temp1 = ((temp >> (2 * j)) & 0x03) << 2;
 462                         temp2 |= temp1;
 463                         xgifb_reg_set(P3d4, 0x6B, temp2);
 464                         /* Insert read command for delay */
 465                         xgifb_reg_get(P3d4, 0x6B);
 466                         temp2 &= 0xF0;
 467                         temp2 += 0x10;
 468                 }
 469         }
 470
 471         temp2 = 0;
 472         for (i = 0; i < 4; i++) {
 473                 /* CR6E DQM fine tune delay */
 474                 temp = pVBInfo->CR6E[pVBInfo->ram_type][i];
 475                 for (j = 0; j < 4; j++) {
 476                         temp1 = ((temp >> (2 * j)) & 0x03) << 2;
 477                         temp2 |= temp1;
 478                         xgifb_reg_set(P3d4, 0x6E, temp2);
 479                         /* Insert read command for delay */
 480                         xgifb_reg_get(P3d4, 0x6E);
 481                         temp2 &= 0xF0;
 482                         temp2 += 0x10;
 483                 }
 484         }
 485
 486         temp3 = 0;
 487         for (k = 0; k < 4; k++) {
 488                 /* CR6E_D[1:0] select channel */
 489                 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
 490                 temp2 = 0;
 491                 for (i = 0; i < 8; i++) {
 492                         /* CR6F DQ fine tune delay */
 493                         temp = pVBInfo->CR6F[pVBInfo->ram_type][8 * k + i];
 494                         for (j = 0; j < 4; j++) {
 495                                 temp1 = (temp >> (2 * j)) & 0x03;
 496                                 temp2 |= temp1;
 497                                 xgifb_reg_set(P3d4, 0x6F, temp2);
 498                                 /* Insert read command for delay */
 499                                 xgifb_reg_get(P3d4, 0x6F);
 500                                 temp2 &= 0xF8;
 501                                 temp2 += 0x08;
 502                         }
 503                 }
 504                 temp3 += 0x01;
 505         }
 506
 507         xgifb_reg_set(P3d4,
 508                       0x80,
 509                       pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
 510         xgifb_reg_set(P3d4,
 511                       0x81,
 512                       pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
 513
 514         temp2 = 0x80;
 515         /* CR89 terminator type select */
 516         temp = pVBInfo->CR89[pVBInfo->ram_type][0];
 517         for (j = 0; j < 4; j++) {
 518                 temp1 = (temp >> (2 * j)) & 0x03;
 519                 temp2 |= temp1;
 520                 xgifb_reg_set(P3d4, 0x89, temp2);
 521                 xgifb_reg_get(P3d4, 0x89); /* Insert read command for delay */
 522                 temp2 &= 0xF0;
 523                 temp2 += 0x10;
 524         }
 525
 526         temp = pVBInfo->CR89[pVBInfo->ram_type][1];
 527         temp1 = temp & 0x03;
 528         temp2 |= temp1;
 529         xgifb_reg_set(P3d4, 0x89, temp2);
 530
 531         temp = pVBInfo->CR40[3][pVBInfo->ram_type];
 532         temp1 = temp & 0x0F;
 533         temp2 = (temp >> 4) & 0x07;
 534         temp3 = temp & 0x80;
 535         xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
 536         xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
 537         xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
 538         xgifb_reg_set(P3d4,
 539                       0x41,
 540                       pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
 541
 542         if (HwDeviceExtension->jChipType == XG27)
 543                 xgifb_reg_set(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
 544
 545         for (j = 0; j <= 6; j++) /* CR90 - CR96 */
 546                 xgifb_reg_set(P3d4, (0x90 + j),
 547                                 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
 548
 549         for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
 550                 xgifb_reg_set(P3d4, (0xC3 + j),
 551                                 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
 552
 553         for (j = 0; j < 2; j++) /* CR8A - CR8B */
 554                 xgifb_reg_set(P3d4, (0x8A + j),
 555                                 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
 556
 557         if ((HwDeviceExtension->jChipType == XG41) ||
 558             (HwDeviceExtension->jChipType == XG42))
 559                 xgifb_reg_set(P3d4, 0x8C, 0x87);
 560
 561         xgifb_reg_set(P3d4,
 562                       0x59,
 563                       pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
 564
 565         xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
 566         xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
 567         xgifb_reg_set(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */
 568         if (pVBInfo->ram_type) {
 569                 /* xgifb_reg_set(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */
 570                 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
 571                 if (HwDeviceExtension->jChipType == XG27)
 572                         xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
 573
 574         } else {
 575                 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
 576         }
 577         xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
 578
 579         temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 580         if (temp == 0) {
 581                 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 582         } else {
 583                 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
 584                 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 585         }
 586         xgifb_reg_set(P3c4,
 587                       0x1B,
 588                       pVBInfo->SR15[3][pVBInfo->ram_type]); /* SR1B */
 589 }
 590
 591 static void XGINew_SetDRAMSizingType(int index,
 592                 const unsigned short DRAMTYPE_TABLE[][5],
 593                 struct vb_device_info *pVBInfo)
 594 {
 595         unsigned short data;
 596
 597         data = DRAMTYPE_TABLE[index][4];
 598         xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, data);
 599         udelay(15);
 600         /* should delay 50 ns */
 601 }
 602
 603 static unsigned short XGINew_SetDRAMSizeReg(int index,
 604                 const unsigned short DRAMTYPE_TABLE[][5],
 605                 struct vb_device_info *pVBInfo)
 606 {
 607         unsigned short data = 0, memsize = 0;
 608         int RankSize;
 609         unsigned char ChannelNo;
 610
 611         RankSize = DRAMTYPE_TABLE[index][3] * pVBInfo->ram_bus / 32;
 612         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 613         data &= 0x80;
 614
 615         if (data == 0x80)
 616                 RankSize *= 2;
 617
 618         data = 0;
 619
 620         if (pVBInfo->ram_channel == 3)
 621                 ChannelNo = 4;
 622         else
 623                 ChannelNo = pVBInfo->ram_channel;
 624
 625         if (ChannelNo * RankSize <= 256) {
 626                 while ((RankSize >>= 1) > 0)
 627                         data += 0x10;
 628
 629                 memsize = data >> 4;
 630
 631                 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
 632                 xgifb_reg_set(pVBInfo->P3c4,
 633                               0x14,
 634                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 635                                (data & 0xF0));
 636
 637                 /* data |= pVBInfo->ram_channel << 2; */
 638                 /* data |= (pVBInfo->ram_bus / 64) << 1; */
 639                 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
 640
 641                 /* should delay */
 642                 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
 643         }
 644         return memsize;
 645 }
 646
 647 static unsigned short XGINew_SetDRAMSize20Reg(int index,
 648                 const unsigned short DRAMTYPE_TABLE[][5],
 649                 struct vb_device_info *pVBInfo)
 650 {
 651         unsigned short data = 0, memsize = 0;
 652         int RankSize;
 653         unsigned char ChannelNo;
 654
 655         RankSize = DRAMTYPE_TABLE[index][3] * pVBInfo->ram_bus / 8;
 656         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 657         data &= 0x80;
 658
 659         if (data == 0x80)
 660                 RankSize *= 2;
 661
 662         data = 0;
 663
 664         if (pVBInfo->ram_channel == 3)
 665                 ChannelNo = 4;
 666         else
 667                 ChannelNo = pVBInfo->ram_channel;
 668
 669         if (ChannelNo * RankSize <= 256) {
 670                 while ((RankSize >>= 1) > 0)
 671                         data += 0x10;
 672
 673                 memsize = data >> 4;
 674
 675                 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
 676                 xgifb_reg_set(pVBInfo->P3c4,
 677                               0x14,
 678                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 679                                 (data & 0xF0));
 680                 udelay(15);
 681
 682                 /* data |= pVBInfo->ram_channel << 2; */
 683                 /* data |= (pVBInfo->ram_bus / 64) << 1; */
 684                 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
 685
 686                 /* should delay */
 687                 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
 688         }
 689         return memsize;
 690 }
 691
 692 static int XGINew_ReadWriteRest(unsigned short StopAddr,
 693                 unsigned short StartAddr, struct vb_device_info *pVBInfo)
 694 {
 695         int i;
 696         unsigned long Position = 0;
 697         void __iomem *fbaddr = pVBInfo->FBAddr;
 698
 699         writel(Position, fbaddr + Position);
 700
 701         for (i = StartAddr; i <= StopAddr; i++) {
 702                 Position = 1 << i;
 703                 writel(Position, fbaddr + Position);
 704         }
 705
 706         udelay(500); /* [Vicent] 2004/04/16.
 707                         Fix #1759 Memory Size error in Multi-Adapter. */
 708
 709         Position = 0;
 710
 711         if (readl(fbaddr + Position) != Position)
 712                 return 0;
 713
 714         for (i = StartAddr; i <= StopAddr; i++) {
 715                 Position = 1 << i;
 716                 if (readl(fbaddr + Position) != Position)
 717                         return 0;
 718         }
 719         return 1;
 720 }
 721
 722 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
 723 {
 724         unsigned char data;
 725
 726         data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 727
 728         if ((data & 0x10) == 0) {
 729                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
 730                 data = (data & 0x02) >> 1;
 731                 return data;
 732         } else {
 733                 return data & 0x01;
 734         }
 735 }
 736
 737 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
 738                 struct vb_device_info *pVBInfo)
 739 {
 740         unsigned char data;
 741
 742         switch (HwDeviceExtension->jChipType) {
 743         case XG20:
 744         case XG21:
 745                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 746                 data = data & 0x01;
 747                 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
 748
 749                 if (data == 0) { /* Single_32_16 */
 750
 751                         if ((HwDeviceExtension->ulVideoMemorySize - 1)
 752                                         > 0x1000000) {
 753
 754                                 pVBInfo->ram_bus = 32; /* 32 bits */
 755                                 /* 22bit + 2 rank + 32bit */
 756                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 757                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 758                                 udelay(15);
 759
 760                                 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 761                                         return;
 762
 763                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 764                                     0x800000) {
 765                                         /* 22bit + 1 rank + 32bit */
 766                                         xgifb_reg_set(pVBInfo->P3c4,
 767                                                       0x13,
 768                                                       0x31);
 769                                         xgifb_reg_set(pVBInfo->P3c4,
 770                                                       0x14,
 771                                                       0x42);
 772                                         udelay(15);
 773
 774                                         if (XGINew_ReadWriteRest(23,
 775                                                                  23,
 776                                                                  pVBInfo) == 1)
 777                                                 return;
 778                                 }
 779                         }
 780
 781                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 782                             0x800000) {
 783                                 pVBInfo->ram_bus = 16; /* 16 bits */
 784                                 /* 22bit + 2 rank + 16bit */
 785                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 786                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 787                                 udelay(15);
 788
 789                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 790                                         return;
 791                                 else
 792                                         xgifb_reg_set(pVBInfo->P3c4,
 793                                                       0x13,
 794                                                       0x31);
 795                                 udelay(15);
 796                         }
 797
 798                 } else { /* Dual_16_8 */
 799                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 800                             0x800000) {
 801                                 pVBInfo->ram_bus = 16; /* 16 bits */
 802                                 /* (0x31:12x8x2) 22bit + 2 rank */
 803                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 804                                 /* 0x41:16Mx16 bit*/
 805                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 806                                 udelay(15);
 807
 808                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 809                                         return;
 810
 811                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 812                                     0x400000) {
 813                                         /* (0x31:12x8x2) 22bit + 1 rank */
 814                                         xgifb_reg_set(pVBInfo->P3c4,
 815                                                       0x13,
 816                                                       0x31);
 817                                         /* 0x31:8Mx16 bit*/
 818                                         xgifb_reg_set(pVBInfo->P3c4,
 819                                                       0x14,
 820                                                       0x31);
 821                                         udelay(15);
 822
 823                                         if (XGINew_ReadWriteRest(22,
 824                                                                  22,
 825                                                                  pVBInfo) == 1)
 826                                                 return;
 827                                 }
 828                         }
 829
 830                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 831                             0x400000) {
 832                                 pVBInfo->ram_bus = 8; /* 8 bits */
 833                                 /* (0x31:12x8x2) 22bit + 2 rank */
 834                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 835                                 /* 0x30:8Mx8 bit*/
 836                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 837                                 udelay(15);
 838
 839                                 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
 840                                         return;
 841                                 else /* (0x31:12x8x2) 22bit + 1 rank */
 842                                         xgifb_reg_set(pVBInfo->P3c4,
 843                                                       0x13,
 844                                                       0x31);
 845                                 udelay(15);
 846                         }
 847                 }
 848                 break;
 849
 850         case XG27:
 851                 pVBInfo->ram_bus = 16; /* 16 bits */
 852                 pVBInfo->ram_channel = 1; /* Single channel */
 853                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
 854                 break;
 855         case XG41:
 856                 if (XGINew_CheckFrequence(pVBInfo) == 1) {
 857                         pVBInfo->ram_bus = 32; /* 32 bits */
 858                         pVBInfo->ram_channel = 3; /* Quad Channel */
 859                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 860                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
 861
 862                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
 863                                 return;
 864
 865                         pVBInfo->ram_channel = 2; /* Dual channels */
 866                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
 867
 868                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 869                                 return;
 870
 871                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x49);
 872
 873                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 874                                 return;
 875
 876                         pVBInfo->ram_channel = 3;
 877                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 878                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
 879
 880                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 881                                 return;
 882
 883                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
 884
 885                         if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
 886                                 return;
 887                         else
 888                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x39);
 889                 } else { /* DDR */
 890                         pVBInfo->ram_bus = 64; /* 64 bits */
 891                         pVBInfo->ram_channel = 2; /* Dual channels */
 892                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 893                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
 894
 895                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
 896                                 return;
 897
 898                         pVBInfo->ram_channel = 1; /* Single channels */
 899                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 900
 901                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 902                                 return;
 903
 904                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x53);
 905
 906                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 907                                 return;
 908
 909                         pVBInfo->ram_channel = 2; /* Dual channels */
 910                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 911                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
 912
 913                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 914                                 return;
 915
 916                         pVBInfo->ram_channel = 1; /* Single channels */
 917                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
 918
 919                         if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
 920                                 return;
 921                         else
 922                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x43);
 923                 }
 924
 925                 break;
 926
 927         case XG42:
 928                 /*
 929                  XG42 SR14 D[3] Reserve
 930                  D[2] = 1, Dual Channel
 931                  = 0, Single Channel
 932
 933                  It's Different from Other XG40 Series.
 934                  */
 935                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
 936                         pVBInfo->ram_bus = 32; /* 32 bits */
 937                         pVBInfo->ram_channel = 2; /* 2 Channel */
 938                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 939                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
 940
 941                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 942                                 return;
 943
 944                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 945                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
 946                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 947                                 return;
 948
 949                         pVBInfo->ram_channel = 1; /* Single Channel */
 950                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 951                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
 952
 953                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 954                                 return;
 955                         else {
 956                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 957                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 958                         }
 959                 } else { /* DDR */
 960                         pVBInfo->ram_bus = 64; /* 64 bits */
 961                         pVBInfo->ram_channel = 1; /* 1 channels */
 962                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 963                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 964
 965                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 966                                 return;
 967                         else {
 968                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 969                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
 970                         }
 971                 }
 972
 973                 break;
 974
 975         default: /* XG40 */
 976
 977                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
 978                         pVBInfo->ram_bus = 32; /* 32 bits */
 979                         pVBInfo->ram_channel = 3;
 980                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 981                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
 982
 983                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
 984                                 return;
 985
 986                         pVBInfo->ram_channel = 2; /* 2 channels */
 987                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
 988
 989                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 990                                 return;
 991
 992                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 993                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
 994
 995                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
 996                                 pVBInfo->ram_channel = 3; /* 4 channels */
 997                         } else {
 998                                 pVBInfo->ram_channel = 2; /* 2 channels */
 999                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
1000                         }
1001                 } else { /* DDR */
1002                         pVBInfo->ram_bus = 64; /* 64 bits */
1003                         pVBInfo->ram_channel = 2; /* 2 channels */
1004                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
1005                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
1006
1007                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
1008                                 return;
1009                         } else {
1010                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
1011                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
1012                         }
1013                 }
1014                 break;
1015         }
1016 }
1017
1018 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
1019                 struct vb_device_info *pVBInfo)
1020 {
1021         int i;
1022         unsigned short memsize, addr;
1023
1024         xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
1025         xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
1026         XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
1027
1028         if (HwDeviceExtension->jChipType >= XG20) {
1029                 for (i = 0; i < 12; i++) {
1030                         XGINew_SetDRAMSizingType(i,
1031                                                  XGINew_DDRDRAM_TYPE20,
1032                                                  pVBInfo);
1033                         memsize = XGINew_SetDRAMSize20Reg(i,
1034                                                           XGINew_DDRDRAM_TYPE20,
1035                                                           pVBInfo);
1036                         if (memsize == 0)
1037                                 continue;
1038
1039                         addr = memsize + (pVBInfo->ram_channel - 2) + 20;
1040                         if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1041                             (unsigned long) (1 << addr))
1042                                 continue;
1043
1044                         if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1)
1045                                 return 1;
1046                 }
1047         } else {
1048                 for (i = 0; i < 4; i++) {
1049                         XGINew_SetDRAMSizingType(i,
1050                                                  XGINew_DDRDRAM_TYPE340,
1051                                                  pVBInfo);
1052                         memsize = XGINew_SetDRAMSizeReg(i,
1053                                                         XGINew_DDRDRAM_TYPE340,
1054                                                         pVBInfo);
1055
1056                         if (memsize == 0)
1057                                 continue;
1058
1059                         addr = memsize + (pVBInfo->ram_channel - 2) + 20;
1060                         if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1061                             (unsigned long) (1 << addr))
1062                                 continue;
1063
1064                         if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1)
1065                                 return 1;
1066                 }
1067         }
1068         return 0;
1069 }
1070
1071 static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
1072                 struct vb_device_info *pVBInfo)
1073 {
1074         unsigned short data;
1075
1076         pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1077         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1078
1079         XGISetModeNew(HwDeviceExtension, 0x2e);
1080
1081         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1082         /* disable read cache */
1083         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
1084         XGI_DisplayOff(HwDeviceExtension, pVBInfo);
1085
1086         /* data = xgifb_reg_get(pVBInfo->P3c4, 0x1); */
1087         /* data |= 0x20 ; */
1088         /* xgifb_reg_set(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
1089         XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
1090         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1091         /* enable read cache */
1092         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
1093 }
1094
1095 static void ReadVBIOSTablData(unsigned char ChipType,
1096                               struct vb_device_info *pVBInfo)
1097 {
1098         volatile unsigned char *pVideoMemory =
1099                 (unsigned char *) pVBInfo->ROMAddr;
1100         unsigned long i;
1101         unsigned char j, k;
1102         /* Volari customize data area end */
1103
1104         if (ChipType == XG21) {
1105                 pVBInfo->IF_DEF_LVDS = 0;
1106                 if (pVideoMemory[0x65] & 0x1) {
1107                         pVBInfo->IF_DEF_LVDS = 1;
1108                         i = pVideoMemory[0x316] | (pVideoMemory[0x317] << 8);
1109                         j = pVideoMemory[i - 1];
1110                         if (j != 0xff) {
1111                                 k = 0;
1112                                 do {
1113                                         pVBInfo->XG21_LVDSCapList[k].
1114                                                  LVDS_Capability
1115                                                 = pVideoMemory[i] |
1116                                                  (pVideoMemory[i + 1] << 8);
1117                                         pVBInfo->XG21_LVDSCapList[k].LVDSHT
1118                                                 = pVideoMemory[i + 2] |
1119                                                   (pVideoMemory[i + 3] << 8);
1120                                         pVBInfo->XG21_LVDSCapList[k].LVDSVT
1121                                                 = pVideoMemory[i + 4] |
1122                                                   (pVideoMemory[i + 5] << 8);
1123                                         pVBInfo->XG21_LVDSCapList[k].LVDSHDE
1124                                                 = pVideoMemory[i + 6] |
1125                                                   (pVideoMemory[i + 7] << 8);
1126                                         pVBInfo->XG21_LVDSCapList[k].LVDSVDE
1127                                                 = pVideoMemory[i + 8] |
1128                                                   (pVideoMemory[i + 9] << 8);
1129                                         pVBInfo->XG21_LVDSCapList[k].LVDSHFP
1130                                                 = pVideoMemory[i + 10] |
1131                                                   (pVideoMemory[i + 11] << 8);
1132                                         pVBInfo->XG21_LVDSCapList[k].LVDSVFP
1133                                                 = pVideoMemory[i + 12] |
1134                                                   (pVideoMemory[i + 13] << 8);
1135                                         pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC
1136                                                 = pVideoMemory[i + 14] |
1137                                                   (pVideoMemory[i + 15] << 8);
1138                                         pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC
1139                                                 = pVideoMemory[i + 16] |
1140                                                   (pVideoMemory[i + 17] << 8);
1141                                         pVBInfo->XG21_LVDSCapList[k].VCLKData1
1142                                                 = pVideoMemory[i + 18];
1143                                         pVBInfo->XG21_LVDSCapList[k].VCLKData2
1144                                                 = pVideoMemory[i + 19];
1145                                         pVBInfo->XG21_LVDSCapList[k].PSC_S1
1146                                                 = pVideoMemory[i + 20];
1147                                         pVBInfo->XG21_LVDSCapList[k].PSC_S2
1148                                                 = pVideoMemory[i + 21];
1149                                         pVBInfo->XG21_LVDSCapList[k].PSC_S3
1150                                                 = pVideoMemory[i + 22];
1151                                         pVBInfo->XG21_LVDSCapList[k].PSC_S4
1152                                                 = pVideoMemory[i + 23];
1153                                         pVBInfo->XG21_LVDSCapList[k].PSC_S5
1154                                                 = pVideoMemory[i + 24];
1155                                         i += 25;
1156                                         j--;
1157                                         k++;
1158                                 } while ((j > 0) &&
1159                                          (k < (sizeof(XGI21_LCDCapList) /
1160                                                sizeof(struct
1161                                                         XGI21_LVDSCapStruct))));
1162                         } else {
1163                                 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability
1164                                                 = pVideoMemory[i] |
1165                                                   (pVideoMemory[i + 1] << 8);
1166                                 pVBInfo->XG21_LVDSCapList[0].LVDSHT
1167                                                 = pVideoMemory[i + 2] |
1168                                                   (pVideoMemory[i + 3] << 8);
1169                                 pVBInfo->XG21_LVDSCapList[0].LVDSVT
1170                                                 = pVideoMemory[i + 4] |
1171                                                   (pVideoMemory[i + 5] << 8);
1172                                 pVBInfo->XG21_LVDSCapList[0].LVDSHDE
1173                                                 = pVideoMemory[i + 6] |
1174                                                   (pVideoMemory[i + 7] << 8);
1175                                 pVBInfo->XG21_LVDSCapList[0].LVDSVDE
1176                                                 = pVideoMemory[i + 8] |
1177                                                   (pVideoMemory[i + 9] << 8);
1178                                 pVBInfo->XG21_LVDSCapList[0].LVDSHFP
1179                                                 = pVideoMemory[i + 10] |
1180                                                   (pVideoMemory[i + 11] << 8);
1181                                 pVBInfo->XG21_LVDSCapList[0].LVDSVFP
1182                                                 = pVideoMemory[i + 12] |
1183                                                   (pVideoMemory[i + 13] << 8);
1184                                 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC
1185                                                 = pVideoMemory[i + 14] |
1186                                                   (pVideoMemory[i + 15] << 8);
1187                                 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC
1188                                                 = pVideoMemory[i + 16] |
1189                                                   (pVideoMemory[i + 17] << 8);
1190                                 pVBInfo->XG21_LVDSCapList[0].VCLKData1
1191                                                 = pVideoMemory[i + 18];
1192                                 pVBInfo->XG21_LVDSCapList[0].VCLKData2
1193                                                 = pVideoMemory[i + 19];
1194                                 pVBInfo->XG21_LVDSCapList[0].PSC_S1
1195                                                 = pVideoMemory[i + 20];
1196                                 pVBInfo->XG21_LVDSCapList[0].PSC_S2
1197                                                 = pVideoMemory[i + 21];
1198                                 pVBInfo->XG21_LVDSCapList[0].PSC_S3
1199                                                 = pVideoMemory[i + 22];
1200                                 pVBInfo->XG21_LVDSCapList[0].PSC_S4
1201                                                 = pVideoMemory[i + 23];
1202                                 pVBInfo->XG21_LVDSCapList[0].PSC_S5
1203                                                 = pVideoMemory[i + 24];
1204                         }
1205                 }
1206         }
1207 }
1208
1209 static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
1210                 struct vb_device_info *pVBInfo)
1211 {
1212         unsigned short tempbx = 0, temp, tempcx, CR3CData;
1213
1214         temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
1215
1216         if (temp & Monitor1Sense)
1217                 tempbx |= ActiveCRT1;
1218         if (temp & LCDSense)
1219                 tempbx |= ActiveLCD;
1220         if (temp & Monitor2Sense)
1221                 tempbx |= ActiveCRT2;
1222         if (temp & TVSense) {
1223                 tempbx |= ActiveTV;
1224                 if (temp & AVIDEOSense)
1225                         tempbx |= (ActiveAVideo << 8);
1226                 if (temp & SVIDEOSense)
1227                         tempbx |= (ActiveSVideo << 8);
1228                 if (temp & SCARTSense)
1229                         tempbx |= (ActiveSCART << 8);
1230                 if (temp & HiTVSense)
1231                         tempbx |= (ActiveHiTV << 8);
1232                 if (temp & YPbPrSense)
1233                         tempbx |= (ActiveYPbPr << 8);
1234         }
1235
1236         tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1237         tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
1238
1239         if (tempbx & tempcx) {
1240                 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
1241                 if (!(CR3CData & DisplayDeviceFromCMOS)) {
1242                         tempcx = 0x1FF0;
1243                         if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1244                                 tempbx = 0x1FF0;
1245                 }
1246         } else {
1247                 tempcx = 0x1FF0;
1248                 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1249                         tempbx = 0x1FF0;
1250         }
1251
1252         tempbx &= tempcx;
1253         xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1254         xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
1255 }
1256
1257 static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1258                 struct vb_device_info *pVBInfo)
1259 {
1260         unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
1261
1262         temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1263         temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
1264         temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
1265
1266         if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1267                 if (temp & ActiveCRT2)
1268                         tempcl = SetCRT2ToRAMDAC;
1269         }
1270
1271         if (temp & ActiveLCD) {
1272                 tempcl |= SetCRT2ToLCD;
1273                 if (temp & DriverMode) {
1274                         if (temp & ActiveTV) {
1275                                 tempch = SetToLCDA | EnableDualEdge;
1276                                 temp ^= SetCRT2ToLCD;
1277
1278                                 if ((temp >> 8) & ActiveAVideo)
1279                                         tempcl |= SetCRT2ToAVIDEO;
1280                                 if ((temp >> 8) & ActiveSVideo)
1281                                         tempcl |= SetCRT2ToSVIDEO;
1282                                 if ((temp >> 8) & ActiveSCART)
1283                                         tempcl |= SetCRT2ToSCART;
1284
1285                                 if (pVBInfo->IF_DEF_HiVision == 1) {
1286                                         if ((temp >> 8) & ActiveHiTV)
1287                                                 tempcl |= SetCRT2ToHiVisionTV;
1288                                 }
1289
1290                                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1291                                         if ((temp >> 8) & ActiveYPbPr)
1292                                                 tempch |= SetYPbPr;
1293                                 }
1294                         }
1295                 }
1296         } else {
1297                 if ((temp >> 8) & ActiveAVideo)
1298                         tempcl |= SetCRT2ToAVIDEO;
1299                 if ((temp >> 8) & ActiveSVideo)
1300                         tempcl |= SetCRT2ToSVIDEO;
1301                 if ((temp >> 8) & ActiveSCART)
1302                         tempcl |= SetCRT2ToSCART;
1303
1304                 if (pVBInfo->IF_DEF_HiVision == 1) {
1305                         if ((temp >> 8) & ActiveHiTV)
1306                                 tempcl |= SetCRT2ToHiVisionTV;
1307                 }
1308
1309                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1310                         if ((temp >> 8) & ActiveYPbPr)
1311                                 tempch |= SetYPbPr;
1312                 }
1313         }
1314
1315         tempcl |= SetSimuScanMode;
1316         if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1317                         || (temp & ActiveCRT2)))
1318                 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1319         if ((temp & ActiveLCD) && (temp & ActiveTV))
1320                 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1321         xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1322
1323         CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1324         CR31Data &= ~(SetNotSimuMode >> 8);
1325         if (!(temp & ActiveCRT1))
1326                 CR31Data |= (SetNotSimuMode >> 8);
1327         CR31Data &= ~(DisableCRT2Display >> 8);
1328         if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1329                 CR31Data |= (DisableCRT2Display >> 8);
1330         xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1331
1332         CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1333         CR38Data &= ~SetYPbPr;
1334         CR38Data |= tempch;
1335         xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1336
1337 }
1338
1339 static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1340                 struct vb_device_info *pVBInfo)
1341 {
1342         unsigned char Temp;
1343         volatile unsigned char *pVideoMemory =
1344                         (unsigned char *) pVBInfo->ROMAddr;
1345
1346         pVBInfo->IF_DEF_LVDS = 0;
1347
1348 #if 1
1349         if ((pVideoMemory[0x65] & 0x01)) { /* For XG21 LVDS */
1350                 pVBInfo->IF_DEF_LVDS = 1;
1351                 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1352                 /* LVDS on chip */
1353                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1354         } else {
1355 #endif
1356                 /* Enable GPIOA/B read  */
1357                 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1358                 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1359                 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1360                         XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
1361                         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1362                         /* Enable read GPIOF */
1363                         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1364                         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
1365                         if (!Temp)
1366                                 xgifb_reg_and_or(pVBInfo->P3d4,
1367                                                  0x38,
1368                                                  ~0xE0,
1369                                                  0x80); /* TMDS on chip */
1370                         else
1371                                 xgifb_reg_and_or(pVBInfo->P3d4,
1372                                                  0x38,
1373                                                  ~0xE0,
1374                                                  0xA0); /* Only DVO on chip */
1375                         /* Disable read GPIOF */
1376                         xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1377                 }
1378 #if 1
1379         }
1380 #endif
1381 }
1382
1383 static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1384                 struct vb_device_info *pVBInfo)
1385 {
1386         unsigned char Temp, bCR4A;
1387
1388         pVBInfo->IF_DEF_LVDS = 0;
1389         bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1390         /* Enable GPIOA/B/C read  */
1391         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1392         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1393         xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1394
1395         if (Temp <= 0x02) {
1396                 pVBInfo->IF_DEF_LVDS = 1;
1397                 /* LVDS setting */
1398                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1399                 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1400         } else {
1401                 /* TMDS/DVO setting */
1402                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1403         }
1404         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1405
1406 }
1407
1408 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1409 {
1410         unsigned char CR38, CR4A, temp;
1411
1412         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1413         /* enable GPIOE read */
1414         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1415         CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1416         temp = 0;
1417         if ((CR38 & 0xE0) > 0x80) {
1418                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1419                 temp &= 0x08;
1420                 temp >>= 3;
1421         }
1422
1423         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1424
1425         return temp;
1426 }
1427
1428 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1429 {
1430         unsigned char CR4A, temp;
1431
1432         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1433         /* enable GPIOA/B/C read */
1434         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1435         temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1436         if (temp <= 2)
1437                 temp &= 0x03;
1438         else
1439                 temp = ((temp & 0x04) >> 1) || ((~temp) & 0x01);
1440
1441         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1442
1443         return temp;
1444 }
1445
1446 unsigned char XGIInitNew(struct pci_dev *pdev)
1447 {
1448         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1449         struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1450         struct vb_device_info VBINF;
1451         struct vb_device_info *pVBInfo = &VBINF;
1452         unsigned char i, temp = 0, temp1;
1453         /* VBIOSVersion[5]; */
1454         volatile unsigned char *pVideoMemory;
1455
1456         /* unsigned long j, k; */
1457
1458         pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1459
1460         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1461
1462         pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
1463
1464         pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
1465
1466         /* Newdebugcode(0x99); */
1467
1468
1469         /* if (pVBInfo->ROMAddr == 0) */
1470         /* return(0); */
1471
1472         if (pVBInfo->FBAddr == NULL) {
1473                 printk("\n pVBInfo->FBAddr == 0 ");
1474                 return 0;
1475         }
1476         printk("1");
1477         if (pVBInfo->BaseAddr == 0) {
1478                 printk("\npVBInfo->BaseAddr == 0 ");
1479                 return 0;
1480         }
1481         printk("2");
1482
1483         outb(0x67, (pVBInfo->BaseAddr + 0x12)); /* 3c2 <- 67 ,ynlai */
1484
1485         pVBInfo->ISXPDOS = 0;
1486         printk("3");
1487
1488         printk("4");
1489
1490         /* VBIOSVersion[4] = 0x0; */
1491
1492         /* 09/07/99 modify by domao */
1493
1494         pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
1495         pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
1496         pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
1497         pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
1498         pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
1499         pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
1500         pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
1501         pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
1502         pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
1503         pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
1504         pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
1505         pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
1506         pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
1507         pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
1508         pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
1509         pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
1510         pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
1511         printk("5");
1512
1513         if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
1514                 /* Run XGI_GetVBType before InitTo330Pointer */
1515                 XGI_GetVBType(pVBInfo);
1516
1517         InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1518
1519         /* ReadVBIOSData */
1520         ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
1521
1522         /* 1.Openkey */
1523         xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1524         printk("6");
1525
1526         /* GetXG21Sense (GPIO) */
1527         if (HwDeviceExtension->jChipType == XG21)
1528                 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
1529
1530         if (HwDeviceExtension->jChipType == XG27)
1531                 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1532
1533         printk("7");
1534
1535         /* 2.Reset Extended register */
1536
1537         for (i = 0x06; i < 0x20; i++)
1538                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1539
1540         for (i = 0x21; i <= 0x27; i++)
1541                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1542
1543         /* for(i = 0x06; i <= 0x27; i++) */
1544         /* xgifb_reg_set(pVBInfo->P3c4, i, 0); */
1545
1546         printk("8");
1547
1548         for (i = 0x31; i <= 0x3B; i++)
1549                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1550         printk("9");
1551
1552         /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
1553         if (HwDeviceExtension->jChipType == XG42)
1554                 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1555
1556         /* for (i = 0x30; i <= 0x3F; i++) */
1557         /* xgifb_reg_set(pVBInfo->P3d4, i, 0); */
1558
1559         for (i = 0x79; i <= 0x7C; i++)
1560                 xgifb_reg_set(pVBInfo->P3d4, i, 0); /* shampoo 0208 */
1561
1562         printk("10");
1563
1564         if (HwDeviceExtension->jChipType >= XG20)
1565                 xgifb_reg_set(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
1566
1567         /* 3.SetMemoryClock
1568
1569         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1570         */
1571
1572         printk("11");
1573
1574         /* 4.SetDefExt1Regs begin */
1575         xgifb_reg_set(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
1576         if (HwDeviceExtension->jChipType == XG27) {
1577                 xgifb_reg_set(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
1578                 xgifb_reg_set(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
1579         }
1580         xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1581         xgifb_reg_set(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
1582         /* xgifb_reg_set(pVBInfo->P3c4, 0x20, 0x20); */
1583         /* alan, 2001/6/26 Frame buffer can read/write SR20 */
1584         xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1585         /* Hsuan, 2006/01/01 H/W request for slow corner chip */
1586         xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1587         if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
1588                 xgifb_reg_set(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
1589
1590         /* SR11 = 0x0F; */
1591         /* xgifb_reg_set(pVBInfo->P3c4, 0x11, SR11); */
1592
1593         printk("12");
1594
1595         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1596                 u32 Temp;
1597
1598                 /* Set AGP Rate */
1599                 /*
1600                 temp1 = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
1601                 temp1 &= 0x02;
1602                 if (temp1 == 0x02) {
1603                         outl(0x80000000, 0xcf8);
1604                         ChipsetID = inl(0x0cfc);
1605                         outl(0x8000002C, 0xcf8);
1606                         VendorID = inl(0x0cfc);
1607                         VendorID &= 0x0000FFFF;
1608                         outl(0x8001002C, 0xcf8);
1609                         GraphicVendorID = inl(0x0cfc);
1610                         GraphicVendorID &= 0x0000FFFF;
1611
1612                         if (ChipsetID == 0x7301039)
1613                                 xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x09);
1614
1615                         ChipsetID &= 0x0000FFFF;
1616
1617                         if ((ChipsetID == 0x700E) ||
1618                             (ChipsetID == 0x1022) ||
1619                             (ChipsetID == 0x1106) ||
1620                             (ChipsetID == 0x10DE)) {
1621                                 if (ChipsetID == 0x1106) {
1622                                         if ((VendorID == 0x1019) &&
1623                                             (GraphicVendorID == 0x1019))
1624                                                 xgifb_reg_set(pVBInfo->P3d4,
1625                                                               0x5F,
1626                                                               0x0D);
1627                                         else
1628                                                 xgifb_reg_set(pVBInfo->P3d4,
1629                                                               0x5F,
1630                                                               0x0B);
1631                                 } else {
1632                                         xgifb_reg_set(pVBInfo->P3d4,
1633                                                       0x5F,
1634                                                       0x0B);
1635                                 }
1636                         }
1637                 }
1638                 */
1639
1640                 printk("13");
1641
1642                 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1643                 for (i = 0x47; i <= 0x4C; i++)
1644                         xgifb_reg_set(pVBInfo->P3d4,
1645                                       i,
1646                                       pVBInfo->AGPReg[i - 0x47]);
1647
1648                 for (i = 0x70; i <= 0x71; i++)
1649                         xgifb_reg_set(pVBInfo->P3d4,
1650                                       i,
1651                                       pVBInfo->AGPReg[6 + i - 0x70]);
1652
1653                 for (i = 0x74; i <= 0x77; i++)
1654                         xgifb_reg_set(pVBInfo->P3d4,
1655                                       i,
1656                                       pVBInfo->AGPReg[8 + i - 0x74]);
1657                 /* Set AGP customize registers (in SetDefAGPRegs) End */
1658                 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
1659                 /*        outl(0x80000000, 0xcf8); */
1660                 /*        ChipsetID = inl(0x0cfc); */
1661                 /*        if (ChipsetID == 0x25308086) */
1662                 /*            xgifb_reg_set(pVBInfo->P3d4, 0x77, 0xF0); */
1663
1664                 pci_read_config_dword(pdev, 0x50, &Temp);
1665                 Temp >>= 20;
1666                 Temp &= 0xF;
1667
1668                 if (Temp == 1)
1669                         xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1670                 printk("14");
1671         } /* != XG20 */
1672
1673         /* Set PCI */
1674         xgifb_reg_set(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
1675         xgifb_reg_set(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
1676         xgifb_reg_set(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
1677         printk("15");
1678
1679         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1680                 /* Set VB */
1681                 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
1682                 /* alan, disable VideoCapture */
1683                 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1684                 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1685                 /* chk if BCLK>=100MHz */
1686                 temp1 = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1687                 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
1688
1689                 xgifb_reg_set(pVBInfo->Part1Port,
1690                               0x02,
1691                               (*pVBInfo->pCRT2Data_1_2));
1692
1693                 printk("16");
1694
1695                 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1696         } /* != XG20 */
1697
1698         xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1699
1700         if ((HwDeviceExtension->jChipType == XG42) &&
1701             XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1702                 /* Not DDR */
1703                 xgifb_reg_set(pVBInfo->P3c4,
1704                               0x31,
1705                               (*pVBInfo->pSR31 & 0x3F) | 0x40);
1706                 xgifb_reg_set(pVBInfo->P3c4,
1707                               0x32,
1708                               (*pVBInfo->pSR32 & 0xFC) | 0x01);
1709         } else {
1710                 xgifb_reg_set(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
1711                 xgifb_reg_set(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
1712         }
1713         xgifb_reg_set(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
1714         printk("17");
1715
1716         /*
1717          SetPowerConsume (HwDeviceExtension, pVBInfo->P3c4);    */
1718
1719         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1720                 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1721                         if (pVBInfo->IF_DEF_LVDS == 0) {
1722                                 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1723                                 xgifb_reg_set(pVBInfo->Part4Port,
1724                                               0x0D,
1725                                               *pVBInfo->pCRT2Data_4_D);
1726                                 xgifb_reg_set(pVBInfo->Part4Port,
1727                                               0x0E,
1728                                               *pVBInfo->pCRT2Data_4_E);
1729                                 xgifb_reg_set(pVBInfo->Part4Port,
1730                                               0x10,
1731                                               *pVBInfo->pCRT2Data_4_10);
1732                                 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1733                         }
1734
1735                         XGI_LockCRT2(HwDeviceExtension, pVBInfo);
1736                 }
1737         } /* != XG20 */
1738         printk("18");
1739
1740         printk("181");
1741
1742         printk("182");
1743
1744         XGI_SenseCRT1(pVBInfo);
1745
1746         printk("183");
1747         /* XGINew_DetectMonitor(HwDeviceExtension); */
1748         if (HwDeviceExtension->jChipType == XG21) {
1749                 printk("186");
1750
1751                 xgifb_reg_and_or(pVBInfo->P3d4,
1752                                  0x32,
1753                                  ~Monitor1Sense,
1754                                  Monitor1Sense); /* Z9 default has CRT */
1755                 temp = GetXG21FPBits(pVBInfo);
1756                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1757                 printk("187");
1758
1759         }
1760         if (HwDeviceExtension->jChipType == XG27) {
1761                 xgifb_reg_and_or(pVBInfo->P3d4,
1762                                  0x32,
1763                                  ~Monitor1Sense,
1764                                  Monitor1Sense); /* Z9 default has CRT */
1765                 temp = GetXG27FPBits(pVBInfo);
1766                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1767         }
1768         printk("19");
1769
1770         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1771
1772         XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1773                                          pVBInfo->P3d4,
1774                                          pVBInfo);
1775
1776         printk("20");
1777         XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo);
1778         printk("21");
1779
1780         printk("22");
1781
1782         /* SetDefExt2Regs begin */
1783         /*
1784         AGP = 1;
1785         temp = (unsigned char) xgifb_reg_get(pVBInfo->P3c4, 0x3A);
1786         temp &= 0x30;
1787         if (temp == 0x30)
1788                 AGP = 0;
1789
1790         if (AGP == 0)
1791                 *pVBInfo->pSR21 &= 0xEF;
1792
1793         xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1794         if (AGP == 1)
1795                 *pVBInfo->pSR22 &= 0x20;
1796         xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
1797         */
1798         /* base = 0x80000000; */
1799         /* OutPortLong(0xcf8, base); */
1800         /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
1801         /* if (Temp == 0x1039) { */
1802         xgifb_reg_set(pVBInfo->P3c4,
1803                       0x22,
1804                       (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
1805         /* } else { */
1806         /*      xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
1807         /* } */
1808
1809         xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1810
1811         printk("23");
1812
1813         XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1814         XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
1815
1816         printk("24");
1817
1818         xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1819         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x31);
1820         printk("25");
1821
1822         return 1;
1823 } /* end of init */