drivers/staging/vme/bridges/vme_ca91cx42.h

   1 /*
   2  * ca91c042.h
   3  *
   4  * Support for the Tundra Universe 1 and Universe II VME bridge chips
   5  *
   6  * Author: Tom Armistead
   7  * Updated by Ajit Prem
   8  * Copyright 2004 Motorola Inc.
   9  *
  10  * Further updated by Martyn Welch <martyn.welch@ge.com>
  11  * Copyright 2009 GE Intelligent Platforms Embedded Systems, Inc.
  12  *
  13  * Derived from ca91c042.h by Michael Wyrick
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  */
  20
  21 #ifndef _CA91CX42_H
  22 #define _CA91CX42_H
  23
  24 #ifndef PCI_VENDOR_ID_TUNDRA
  25 #define PCI_VENDOR_ID_TUNDRA 0x10e3
  26 #endif
  27
  28 #ifndef PCI_DEVICE_ID_TUNDRA_CA91C142
  29 #define PCI_DEVICE_ID_TUNDRA_CA91C142 0x0000
  30 #endif
  31
  32 /*
  33  *  Define the number of each that the CA91C142 supports.
  34  */
  35 #define CA91C142_MAX_MASTER             8       /* Max Master Windows */
  36 #define CA91C142_MAX_SLAVE              8       /* Max Slave Windows */
  37 #define CA91C142_MAX_DMA                1       /* Max DMA Controllers */
  38 #define CA91C142_MAX_MAILBOX            4       /* Max Mail Box registers */
  39
  40 /* See Page 2-77 in the Universe User Manual */
  41 struct ca91cx42_dma_descriptor {
  42         unsigned int dctl;      /* DMA Control */
  43         unsigned int dtbc;      /* Transfer Byte Count */
  44         unsigned int dlv;       /* PCI Address */
  45         unsigned int res1;      /* Reserved */
  46         unsigned int dva;       /* Vme Address */
  47         unsigned int res2;      /* Reserved */
  48         unsigned int dcpp;      /* Pointer to Numed Cmd Packet with rPN */
  49         unsigned int res3;      /* Reserved */
  50 };
  51
  52 struct ca91cx42_dma_entry {
  53         struct ca91cx42_dma_descriptor descriptor;
  54         struct list_head list;
  55 };
  56
  57 /* Universe Register Offsets */
  58 /* general PCI configuration registers */
  59 #define CA91CX42_PCI_ID         0x000
  60 #define CA91CX42_PCI_CSR        0x004
  61 #define CA91CX42_PCI_CLASS      0x008
  62 #define CA91CX42_PCI_MISC0      0x00C
  63 #define CA91CX42_PCI_BS         0x010
  64 #define CA91CX42_PCI_MISC1      0x03C
  65
  66 #define LSI0_CTL                0x0100
  67 #define LSI0_BS                 0x0104
  68 #define LSI0_BD                 0x0108
  69 #define LSI0_TO                 0x010C
  70
  71 #define LSI1_CTL                0x0114
  72 #define LSI1_BS                 0x0118
  73 #define LSI1_BD                 0x011C
  74 #define LSI1_TO                 0x0120
  75
  76 #define LSI2_CTL                0x0128
  77 #define LSI2_BS                 0x012C
  78 #define LSI2_BD                 0x0130
  79 #define LSI2_TO                 0x0134
  80
  81 #define LSI3_CTL                0x013C
  82 #define LSI3_BS                 0x0140
  83 #define LSI3_BD                 0x0144
  84 #define LSI3_TO                 0x0148
  85
  86 #define LSI4_CTL                0x01A0
  87 #define LSI4_BS                 0x01A4
  88 #define LSI4_BD                 0x01A8
  89 #define LSI4_TO                 0x01AC
  90
  91 #define LSI5_CTL                0x01B4
  92 #define LSI5_BS                 0x01B8
  93 #define LSI5_BD                 0x01BC
  94 #define LSI5_TO                 0x01C0
  95
  96 #define LSI6_CTL                0x01C8
  97 #define LSI6_BS                 0x01CC
  98 #define LSI6_BD                 0x01D0
  99 #define LSI6_TO                 0x01D4
 100
 101 #define LSI7_CTL                0x01DC
 102 #define LSI7_BS                 0x01E0
 103 #define LSI7_BD                 0x01E4
 104 #define LSI7_TO                 0x01E8
 105
 106 static const int CA91CX42_LSI_CTL[] = { LSI0_CTL, LSI1_CTL, LSI2_CTL, LSI3_CTL,
 107                                 LSI4_CTL, LSI5_CTL, LSI6_CTL, LSI7_CTL };
 108
 109 static const int CA91CX42_LSI_BS[] = { LSI0_BS, LSI1_BS, LSI2_BS, LSI3_BS,
 110                                 LSI4_BS, LSI5_BS, LSI6_BS, LSI7_BS };
 111
 112 static const int CA91CX42_LSI_BD[] = { LSI0_BD, LSI1_BD, LSI2_BD, LSI3_BD,
 113                                 LSI4_BD, LSI5_BD, LSI6_BD, LSI7_BD };
 114
 115 static const int CA91CX42_LSI_TO[] = { LSI0_TO, LSI1_TO, LSI2_TO, LSI3_TO,
 116                                 LSI4_TO, LSI5_TO, LSI6_TO, LSI7_TO };
 117
 118 #define SCYC_CTL                0x0170
 119 #define SCYC_ADDR               0x0174
 120 #define SCYC_EN                 0x0178
 121 #define SCYC_CMP                0x017C
 122 #define SCYC_SWP                0x0180
 123 #define LMISC                   0x0184
 124 #define SLSI                    0x0188
 125 #define L_CMDERR                0x018C
 126 #define LAERR                   0x0190
 127
 128 #define DCTL                    0x0200
 129 #define DTBC                    0x0204
 130 #define DLA                     0x0208
 131 #define DVA                     0x0210
 132 #define DCPP                    0x0218
 133 #define DGCS                    0x0220
 134 #define D_LLUE                  0x0224
 135
 136 #define LINT_EN                 0x0300
 137 #define LINT_STAT               0x0304
 138 #define LINT_MAP0               0x0308
 139 #define LINT_MAP1               0x030C
 140 #define VINT_EN                 0x0310
 141 #define VINT_STAT               0x0314
 142 #define VINT_MAP0               0x0318
 143 #define VINT_MAP1               0x031C
 144 #define STATID                  0x0320
 145
 146 #define V1_STATID               0x0324
 147 #define V2_STATID               0x0328
 148 #define V3_STATID               0x032C
 149 #define V4_STATID               0x0330
 150 #define V5_STATID               0x0334
 151 #define V6_STATID               0x0338
 152 #define V7_STATID               0x033C
 153
 154 static const int CA91CX42_V_STATID[8] = { 0, V1_STATID, V2_STATID, V3_STATID,
 155                                         V4_STATID, V5_STATID, V6_STATID,
 156                                         V7_STATID };
 157
 158 #define LINT_MAP2               0x0340
 159 #define VINT_MAP2               0x0344
 160
 161 #define MBOX0                   0x0348
 162 #define MBOX1                   0x034C
 163 #define MBOX2                   0x0350
 164 #define MBOX3                   0x0354
 165 #define SEMA0                   0x0358
 166 #define SEMA1                   0x035C
 167
 168 #define MAST_CTL                0x0400
 169 #define MISC_CTL                0x0404
 170 #define MISC_STAT               0x0408
 171 #define USER_AM                 0x040C
 172
 173 #define VSI0_CTL                0x0F00
 174 #define VSI0_BS                 0x0F04
 175 #define VSI0_BD                 0x0F08
 176 #define VSI0_TO                 0x0F0C
 177
 178 #define VSI1_CTL                0x0F14
 179 #define VSI1_BS                 0x0F18
 180 #define VSI1_BD                 0x0F1C
 181 #define VSI1_TO                 0x0F20
 182
 183 #define VSI2_CTL                0x0F28
 184 #define VSI2_BS                 0x0F2C
 185 #define VSI2_BD                 0x0F30
 186 #define VSI2_TO                 0x0F34
 187
 188 #define VSI3_CTL                0x0F3C
 189 #define VSI3_BS                 0x0F40
 190 #define VSI3_BD                 0x0F44
 191 #define VSI3_TO                 0x0F48
 192
 193 #define LM_CTL                  0x0F64
 194 #define LM_BS                   0x0F68
 195
 196 #define VRAI_CTL                0x0F70
 197
 198 #define VRAI_BS                 0x0F74
 199 #define VCSR_CTL                0x0F80
 200 #define VCSR_TO                 0x0F84
 201 #define V_AMERR                 0x0F88
 202 #define VAERR                   0x0F8C
 203
 204 #define VSI4_CTL                0x0F90
 205 #define VSI4_BS                 0x0F94
 206 #define VSI4_BD                 0x0F98
 207 #define VSI4_TO                 0x0F9C
 208
 209 #define VSI5_CTL                0x0FA4
 210 #define VSI5_BS                 0x0FA8
 211 #define VSI5_BD                 0x0FAC
 212 #define VSI5_TO                 0x0FB0
 213
 214 #define VSI6_CTL                0x0FB8
 215 #define VSI6_BS                 0x0FBC
 216 #define VSI6_BD                 0x0FC0
 217 #define VSI6_TO                 0x0FC4
 218
 219 #define VSI7_CTL                0x0FCC
 220 #define VSI7_BS                 0x0FD0
 221 #define VSI7_BD                 0x0FD4
 222 #define VSI7_TO                 0x0FD8
 223
 224 static const int CA91CX42_VSI_CTL[] = { VSI0_CTL, VSI1_CTL, VSI2_CTL, VSI3_CTL,
 225                                 VSI4_CTL, VSI5_CTL, VSI6_CTL, VSI7_CTL };
 226
 227 static const int CA91CX42_VSI_BS[] = { VSI0_BS, VSI1_BS, VSI2_BS, VSI3_BS,
 228                                 VSI4_BS, VSI5_BS, VSI6_BS, VSI7_BS };
 229
 230 static const int CA91CX42_VSI_BD[] = { VSI0_BD, VSI1_BD, VSI2_BD, VSI3_BD,
 231                                 VSI4_BD, VSI5_BD, VSI6_BD, VSI7_BD };
 232
 233 static const int CA91CX42_VSI_TO[] = { VSI0_TO, VSI1_TO, VSI2_TO, VSI3_TO,
 234                                 VSI4_TO, VSI5_TO, VSI6_TO, VSI7_TO };
 235
 236 #define VCSR_CLR                0x0FF4
 237 #define VCSR_SET                0x0FF8
 238 #define VCSR_BS                 0x0FFC
 239
 240 // DMA General Control/Status Register DGCS (0x220)
 241 // 32-24 ||  GO   | STOPR | HALTR |   0   || CHAIN |   0   |   0   |   0   ||
 242 // 23-16 ||              VON              ||             VOFF              ||
 243 // 15-08 ||  ACT  | STOP  | HALT  |   0   || DONE  | LERR  | VERR  | P_ERR ||
 244 // 07-00 ||   0   | INT_S | INT_H |   0   || I_DNE | I_LER | I_VER | I_PER ||
 245
 246 // VON - Length Per DMA VMEBus Transfer
 247 //  0000 = None
 248 //  0001 = 256 Bytes
 249 //  0010 = 512
 250 //  0011 = 1024
 251 //  0100 = 2048
 252 //  0101 = 4096
 253 //  0110 = 8192
 254 //  0111 = 16384
 255
 256 // VOFF - wait between DMA tenures
 257 //  0000 = 0    us
 258 //  0001 = 16
 259 //  0010 = 32
 260 //  0011 = 64
 261 //  0100 = 128
 262 //  0101 = 256
 263 //  0110 = 512
 264 //  0111 = 1024
 265
 266 /*
 267  * PCI Class Register
 268  * offset 008
 269  */
 270 #define CA91CX42_BM_PCI_CLASS_BASE          0xFF000000
 271 #define CA91CX42_OF_PCI_CLASS_BASE          24
 272 #define CA91CX42_BM_PCI_CLASS_SUB           0x00FF0000
 273 #define CA91CX42_OF_PCI_CLASS_SUB           16
 274 #define CA91CX42_BM_PCI_CLASS_PROG          0x0000FF00
 275 #define CA91CX42_OF_PCI_CLASS_PROG          8
 276 #define CA91CX42_BM_PCI_CLASS_RID           0x000000FF
 277 #define CA91CX42_OF_PCI_CLASS_RID           0
 278
 279 #define CA91CX42_OF_PCI_CLASS_RID_UNIVERSE_I 0
 280 #define CA91CX42_OF_PCI_CLASS_RID_UNIVERSE_II 1
 281
 282 /*
 283  * PCI Misc Register
 284  * offset 00C
 285  */
 286 #define CA91CX42_BM_PCI_MISC0_BISTC         0x80000000
 287 #define CA91CX42_BM_PCI_MISC0_SBIST         0x60000000
 288 #define CA91CX42_BM_PCI_MISC0_CCODE         0x0F000000
 289 #define CA91CX42_BM_PCI_MISC0_MFUNCT        0x00800000
 290 #define CA91CX42_BM_PCI_MISC0_LAYOUT        0x007F0000
 291 #define CA91CX42_BM_PCI_MISC0_LTIMER        0x0000FF00
 292 #define CA91CX42_OF_PCI_MISC0_LTIMER        8
 293
 294
 295 /*
 296  * LSI Control Register
 297  * offset  100
 298  */
 299 #define CA91CX42_LSI_CTL_EN             (1<<31)
 300 #define CA91CX42_LSI_CTL_PWEN           (1<<30)
 301
 302 #define CA91CX42_LSI_CTL_VDW_M          (3<<22)
 303 #define CA91CX42_LSI_CTL_VDW_D8         0
 304 #define CA91CX42_LSI_CTL_VDW_D16        (1<<22)
 305 #define CA91CX42_LSI_CTL_VDW_D32        (1<<23)
 306 #define CA91CX42_LSI_CTL_VDW_D64        (3<<22)
 307
 308 #define CA91CX42_LSI_CTL_VAS_M          (7<<16)
 309 #define CA91CX42_LSI_CTL_VAS_A16        0
 310 #define CA91CX42_LSI_CTL_VAS_A24        (1<<16)
 311 #define CA91CX42_LSI_CTL_VAS_A32        (1<<17)
 312 #define CA91CX42_LSI_CTL_VAS_CRCSR      (5<<16)
 313 #define CA91CX42_LSI_CTL_VAS_USER1      (3<<17)
 314 #define CA91CX42_LSI_CTL_VAS_USER2      (7<<16)
 315
 316 #define CA91CX42_LSI_CTL_PGM_M          (1<<14)
 317 #define CA91CX42_LSI_CTL_PGM_DATA       0
 318 #define CA91CX42_LSI_CTL_PGM_PGM        (1<<14)
 319
 320 #define CA91CX42_LSI_CTL_SUPER_M        (1<<12)
 321 #define CA91CX42_LSI_CTL_SUPER_NPRIV    0
 322 #define CA91CX42_LSI_CTL_SUPER_SUPR     (1<<12)
 323
 324 #define CA91CX42_LSI_CTL_VCT_M          (1<<8)
 325 #define CA91CX42_LSI_CTL_VCT_BLT        (1<<8)
 326 #define CA91CX42_LSI_CTL_VCT_MBLT       (1<<8)
 327 #define CA91CX42_LSI_CTL_LAS            (1<<0)
 328
 329
 330 /*
 331  * LMISC Register
 332  * offset  184
 333  */
 334 #define CA91CX42_BM_LMISC_CRT               0xF0000000
 335 #define CA91CX42_OF_LMISC_CRT               28
 336 #define CA91CX42_BM_LMISC_CWT               0x0F000000
 337 #define CA91CX42_OF_LMISC_CWT               24
 338
 339 /*
 340  * SLSI Register
 341  * offset  188
 342  */
 343 #define CA91CX42_BM_SLSI_EN                 0x80000000
 344 #define CA91CX42_BM_SLSI_PWEN               0x40000000
 345 #define CA91CX42_BM_SLSI_VDW                0x00F00000
 346 #define CA91CX42_OF_SLSI_VDW                20
 347 #define CA91CX42_BM_SLSI_PGM                0x0000F000
 348 #define CA91CX42_OF_SLSI_PGM                12
 349 #define CA91CX42_BM_SLSI_SUPER              0x00000F00
 350 #define CA91CX42_OF_SLSI_SUPER              8
 351 #define CA91CX42_BM_SLSI_BS                 0x000000F6
 352 #define CA91CX42_OF_SLSI_BS                 2
 353 #define CA91CX42_BM_SLSI_LAS                0x00000003
 354 #define CA91CX42_OF_SLSI_LAS                0
 355 #define CA91CX42_BM_SLSI_RESERVED           0x3F0F0000
 356
 357 /*
 358  * PCI Interrupt Enable Register
 359  * offset  300
 360  */
 361 #define CA91CX42_LINT_LM3               0x00800000
 362 #define CA91CX42_LINT_LM2               0x00400000
 363 #define CA91CX42_LINT_LM1               0x00200000
 364 #define CA91CX42_LINT_LM0               0x00100000
 365 #define CA91CX42_LINT_MBOX3             0x00080000
 366 #define CA91CX42_LINT_MBOX2             0x00040000
 367 #define CA91CX42_LINT_MBOX1             0x00020000
 368 #define CA91CX42_LINT_MBOX0             0x00010000
 369 #define CA91CX42_LINT_ACFAIL            0x00008000
 370 #define CA91CX42_LINT_SYSFAIL           0x00004000
 371 #define CA91CX42_LINT_SW_INT            0x00002000
 372 #define CA91CX42_LINT_SW_IACK           0x00001000
 373
 374 #define CA91CX42_LINT_VERR              0x00000400
 375 #define CA91CX42_LINT_LERR              0x00000200
 376 #define CA91CX42_LINT_DMA               0x00000100
 377 #define CA91CX42_LINT_VIRQ7             0x00000080
 378 #define CA91CX42_LINT_VIRQ6             0x00000040
 379 #define CA91CX42_LINT_VIRQ5             0x00000020
 380 #define CA91CX42_LINT_VIRQ4             0x00000010
 381 #define CA91CX42_LINT_VIRQ3             0x00000008
 382 #define CA91CX42_LINT_VIRQ2             0x00000004
 383 #define CA91CX42_LINT_VIRQ1             0x00000002
 384 #define CA91CX42_LINT_VOWN              0x00000001
 385
 386 static const int CA91CX42_LINT_VIRQ[] = { 0, CA91CX42_LINT_VIRQ1,
 387                                 CA91CX42_LINT_VIRQ2, CA91CX42_LINT_VIRQ3,
 388                                 CA91CX42_LINT_VIRQ4, CA91CX42_LINT_VIRQ5,
 389                                 CA91CX42_LINT_VIRQ6, CA91CX42_LINT_VIRQ7 };
 390
 391 #define CA91CX42_LINT_MBOX              0x000F0000
 392
 393 static const int CA91CX42_LINT_LM[] = { CA91CX42_LINT_LM0, CA91CX42_LINT_LM1,
 394                                         CA91CX42_LINT_LM2, CA91CX42_LINT_LM3 };
 395
 396 /*
 397  * MAST_CTL Register
 398  * offset  400
 399  */
 400 #define CA91CX42_BM_MAST_CTL_MAXRTRY        0xF0000000
 401 #define CA91CX42_OF_MAST_CTL_MAXRTRY        28
 402 #define CA91CX42_BM_MAST_CTL_PWON           0x0F000000
 403 #define CA91CX42_OF_MAST_CTL_PWON           24
 404 #define CA91CX42_BM_MAST_CTL_VRL            0x00C00000
 405 #define CA91CX42_OF_MAST_CTL_VRL            22
 406 #define CA91CX42_BM_MAST_CTL_VRM            0x00200000
 407 #define CA91CX42_BM_MAST_CTL_VREL           0x00100000
 408 #define CA91CX42_BM_MAST_CTL_VOWN           0x00080000
 409 #define CA91CX42_BM_MAST_CTL_VOWN_ACK       0x00040000
 410 #define CA91CX42_BM_MAST_CTL_PABS           0x00001000
 411 #define CA91CX42_BM_MAST_CTL_BUS_NO         0x0000000F
 412 #define CA91CX42_OF_MAST_CTL_BUS_NO         0
 413
 414 /*
 415  * MISC_CTL Register
 416  * offset  404
 417  */
 418 #define CA91CX42_MISC_CTL_VBTO           0xF0000000
 419 #define CA91CX42_MISC_CTL_VARB           0x04000000
 420 #define CA91CX42_MISC_CTL_VARBTO         0x03000000
 421 #define CA91CX42_MISC_CTL_SW_LRST        0x00800000
 422 #define CA91CX42_MISC_CTL_SW_SRST        0x00400000
 423 #define CA91CX42_MISC_CTL_BI             0x00100000
 424 #define CA91CX42_MISC_CTL_ENGBI          0x00080000
 425 #define CA91CX42_MISC_CTL_RESCIND        0x00040000
 426 #define CA91CX42_MISC_CTL_SYSCON         0x00020000
 427 #define CA91CX42_MISC_CTL_V64AUTO        0x00010000
 428 #define CA91CX42_MISC_CTL_RESERVED       0x0820FFFF
 429
 430 #define CA91CX42_OF_MISC_CTL_VARBTO         24
 431 #define CA91CX42_OF_MISC_CTL_VBTO           28
 432
 433 /*
 434  * MISC_STAT Register
 435  * offset  408
 436  */
 437 #define CA91CX42_BM_MISC_STAT_ENDIAN        0x80000000
 438 #define CA91CX42_BM_MISC_STAT_LCLSIZE       0x40000000
 439 #define CA91CX42_BM_MISC_STAT_DY4AUTO       0x08000000
 440 #define CA91CX42_BM_MISC_STAT_MYBBSY        0x00200000
 441 #define CA91CX42_BM_MISC_STAT_DY4DONE       0x00080000
 442 #define CA91CX42_BM_MISC_STAT_TXFE          0x00040000
 443 #define CA91CX42_BM_MISC_STAT_RXFE          0x00020000
 444 #define CA91CX42_BM_MISC_STAT_DY4AUTOID     0x0000FF00
 445 #define CA91CX42_OF_MISC_STAT_DY4AUTOID     8
 446
 447 /*
 448  * VSI Control Register
 449  * offset  F00
 450  */
 451 #define CA91CX42_VSI_CTL_EN             (1<<31)
 452 #define CA91CX42_VSI_CTL_PWEN           (1<<30)
 453 #define CA91CX42_VSI_CTL_PREN           (1<<29)
 454
 455 #define CA91CX42_VSI_CTL_PGM_M          (3<<22)
 456 #define CA91CX42_VSI_CTL_PGM_DATA       (1<<22)
 457 #define CA91CX42_VSI_CTL_PGM_PGM        (1<<23)
 458
 459 #define CA91CX42_VSI_CTL_SUPER_M        (3<<20)
 460 #define CA91CX42_VSI_CTL_SUPER_NPRIV    (1<<20)
 461 #define CA91CX42_VSI_CTL_SUPER_SUPR     (1<<21)
 462
 463 #define CA91CX42_VSI_CTL_VAS_M          (7<<16)
 464 #define CA91CX42_VSI_CTL_VAS_A16        0
 465 #define CA91CX42_VSI_CTL_VAS_A24        (1<<16)
 466 #define CA91CX42_VSI_CTL_VAS_A32        (1<<17)
 467 #define CA91CX42_VSI_CTL_VAS_USER1      (3<<17)
 468 #define CA91CX42_VSI_CTL_VAS_USER2      (7<<16)
 469
 470 #define CA91CX42_VSI_CTL_LD64EN         (1<<7)
 471 #define CA91CX42_VSI_CTL_LLRMW          (1<<6)
 472
 473 #define CA91CX42_VSI_CTL_LAS_M          (3<<0)
 474 #define CA91CX42_VSI_CTL_LAS_PCI_MS     0
 475 #define CA91CX42_VSI_CTL_LAS_PCI_IO     (1<<0)
 476 #define CA91CX42_VSI_CTL_LAS_PCI_CONF   (1<<1)
 477
 478 /*
 479  * VRAI_CTL Register
 480  * offset  F70
 481  */
 482 #define CA91CX42_BM_VRAI_CTL_EN             0x80000000
 483 #define CA91CX42_BM_VRAI_CTL_PGM            0x00C00000
 484 #define CA91CX42_OF_VRAI_CTL_PGM            22
 485 #define CA91CX42_BM_VRAI_CTL_SUPER          0x00300000
 486 #define CA91CX42_OF_VRAI_CTL_SUPER          20
 487 #define CA91CX42_BM_VRAI_CTL_VAS            0x00030000
 488 #define CA91CX42_OF_VRAI_CTL_VAS            16
 489
 490 /* VCSR_CTL Register
 491  * offset F80
 492  */
 493 #define CA91CX42_VCSR_CTL_EN            (1<<31)
 494
 495 #define CA91CX42_VCSR_CTL_LAS_M         (3<<0)
 496 #define CA91CX42_VCSR_CTL_LAS_PCI_MS    0
 497 #define CA91CX42_VCSR_CTL_LAS_PCI_IO    (1<<0)
 498 #define CA91CX42_VCSR_CTL_LAS_PCI_CONF  (1<<1)
 499
 500 /* VCSR_BS Register
 501  * offset FFC
 502  */
 503 #define CA91CX42_VCSR_BS_SLOT_M         (0x1F<<27)
 504
 505 #endif /* _CA91CX42_H */