drivers/staging/vme/bridges/vme_ca91cx42.c

   1 /*
   2  * Support for the Tundra Universe I/II VME-PCI Bridge Chips
   3  *
   4  * Author: Martyn Welch <martyn.welch@ge.com>
   5  * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
   6  *
   7  * Based on work by Tom Armistead and Ajit Prem
   8  * Copyright 2004 Motorola Inc.
   9  *
  10  * Derived from ca91c042.c by Michael Wyrick
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/mm.h>
  20 #include <linux/types.h>
  21 #include <linux/errno.h>
  22 #include <linux/pci.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/poll.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/sched.h>
  28 #include <linux/slab.h>
  29 #include <asm/time.h>
  30 #include <asm/io.h>
  31 #include <asm/uaccess.h>
  32
  33 #include "../vme.h"
  34 #include "../vme_bridge.h"
  35 #include "vme_ca91cx42.h"
  36
  37 static int __init ca91cx42_init(void);
  38 static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *);
  39 static void ca91cx42_remove(struct pci_dev *);
  40 static void __exit ca91cx42_exit(void);
  41
  42 /* Module parameters */
  43 static int geoid;
  44
  45 static char driver_name[] = "vme_ca91cx42";
  46
  47 static const struct pci_device_id ca91cx42_ids[] = {
  48         { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) },
  49         { },
  50 };
  51
  52 static struct pci_driver ca91cx42_driver = {
  53         .name = driver_name,
  54         .id_table = ca91cx42_ids,
  55         .probe = ca91cx42_probe,
  56         .remove = ca91cx42_remove,
  57 };
  58
  59 static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge)
  60 {
  61         wake_up(&(bridge->dma_queue));
  62
  63         return CA91CX42_LINT_DMA;
  64 }
  65
  66 static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat)
  67 {
  68         int i;
  69         u32 serviced = 0;
  70
  71         for (i = 0; i < 4; i++) {
  72                 if (stat & CA91CX42_LINT_LM[i]) {
  73                         /* We only enable interrupts if the callback is set */
  74                         bridge->lm_callback[i](i);
  75                         serviced |= CA91CX42_LINT_LM[i];
  76                 }
  77         }
  78
  79         return serviced;
  80 }
  81
  82 /* XXX This needs to be split into 4 queues */
  83 static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask)
  84 {
  85         wake_up(&(bridge->mbox_queue));
  86
  87         return CA91CX42_LINT_MBOX;
  88 }
  89
  90 static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge)
  91 {
  92         wake_up(&(bridge->iack_queue));
  93
  94         return CA91CX42_LINT_SW_IACK;
  95 }
  96
  97 static u32 ca91cx42_VERR_irqhandler(struct ca91cx42_driver *bridge)
  98 {
  99         int val;
 100
 101         val = ioread32(bridge->base + DGCS);
 102
 103         if (!(val & 0x00000800)) {
 104                 printk(KERN_ERR "ca91c042: ca91cx42_VERR_irqhandler DMA Read "
 105                         "Error DGCS=%08X\n", val);
 106         }
 107
 108         return CA91CX42_LINT_VERR;
 109 }
 110
 111 static u32 ca91cx42_LERR_irqhandler(struct ca91cx42_driver *bridge)
 112 {
 113         int val;
 114
 115         val = ioread32(bridge->base + DGCS);
 116
 117         if (!(val & 0x00000800)) {
 118                 printk(KERN_ERR "ca91c042: ca91cx42_LERR_irqhandler DMA Read "
 119                         "Error DGCS=%08X\n", val);
 120
 121         }
 122
 123         return CA91CX42_LINT_LERR;
 124 }
 125
 126
 127 static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge,
 128         int stat)
 129 {
 130         int vec, i, serviced = 0;
 131         struct ca91cx42_driver *bridge;
 132
 133         bridge = ca91cx42_bridge->driver_priv;
 134
 135
 136         for (i = 7; i > 0; i--) {
 137                 if (stat & (1 << i)) {
 138                         vec = ioread32(bridge->base +
 139                                 CA91CX42_V_STATID[i]) & 0xff;
 140
 141                         vme_irq_handler(ca91cx42_bridge, i, vec);
 142
 143                         serviced |= (1 << i);
 144                 }
 145         }
 146
 147         return serviced;
 148 }
 149
 150 static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr)
 151 {
 152         u32 stat, enable, serviced = 0;
 153         struct vme_bridge *ca91cx42_bridge;
 154         struct ca91cx42_driver *bridge;
 155
 156         ca91cx42_bridge = ptr;
 157
 158         bridge = ca91cx42_bridge->driver_priv;
 159
 160         enable = ioread32(bridge->base + LINT_EN);
 161         stat = ioread32(bridge->base + LINT_STAT);
 162
 163         /* Only look at unmasked interrupts */
 164         stat &= enable;
 165
 166         if (unlikely(!stat))
 167                 return IRQ_NONE;
 168
 169         if (stat & CA91CX42_LINT_DMA)
 170                 serviced |= ca91cx42_DMA_irqhandler(bridge);
 171         if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
 172                         CA91CX42_LINT_LM3))
 173                 serviced |= ca91cx42_LM_irqhandler(bridge, stat);
 174         if (stat & CA91CX42_LINT_MBOX)
 175                 serviced |= ca91cx42_MB_irqhandler(bridge, stat);
 176         if (stat & CA91CX42_LINT_SW_IACK)
 177                 serviced |= ca91cx42_IACK_irqhandler(bridge);
 178         if (stat & CA91CX42_LINT_VERR)
 179                 serviced |= ca91cx42_VERR_irqhandler(bridge);
 180         if (stat & CA91CX42_LINT_LERR)
 181                 serviced |= ca91cx42_LERR_irqhandler(bridge);
 182         if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 |
 183                         CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 |
 184                         CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 |
 185                         CA91CX42_LINT_VIRQ7))
 186                 serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat);
 187
 188         /* Clear serviced interrupts */
 189         iowrite32(stat, bridge->base + LINT_STAT);
 190
 191         return IRQ_HANDLED;
 192 }
 193
 194 static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge)
 195 {
 196         int result, tmp;
 197         struct pci_dev *pdev;
 198         struct ca91cx42_driver *bridge;
 199
 200         bridge = ca91cx42_bridge->driver_priv;
 201
 202         /* Need pdev */
 203         pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
 204
 205         /* Initialise list for VME bus errors */
 206         INIT_LIST_HEAD(&(ca91cx42_bridge->vme_errors));
 207
 208         mutex_init(&(ca91cx42_bridge->irq_mtx));
 209
 210         /* Disable interrupts from PCI to VME */
 211         iowrite32(0, bridge->base + VINT_EN);
 212
 213         /* Disable PCI interrupts */
 214         iowrite32(0, bridge->base + LINT_EN);
 215         /* Clear Any Pending PCI Interrupts */
 216         iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
 217
 218         result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED,
 219                         driver_name, ca91cx42_bridge);
 220         if (result) {
 221                 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
 222                        pdev->irq);
 223                 return result;
 224         }
 225
 226         /* Ensure all interrupts are mapped to PCI Interrupt 0 */
 227         iowrite32(0, bridge->base + LINT_MAP0);
 228         iowrite32(0, bridge->base + LINT_MAP1);
 229         iowrite32(0, bridge->base + LINT_MAP2);
 230
 231         /* Enable DMA, mailbox & LM Interrupts */
 232         tmp = CA91CX42_LINT_MBOX3 | CA91CX42_LINT_MBOX2 | CA91CX42_LINT_MBOX1 |
 233                 CA91CX42_LINT_MBOX0 | CA91CX42_LINT_SW_IACK |
 234                 CA91CX42_LINT_VERR | CA91CX42_LINT_LERR | CA91CX42_LINT_DMA;
 235
 236         iowrite32(tmp, bridge->base + LINT_EN);
 237
 238         return 0;
 239 }
 240
 241 static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge,
 242         struct pci_dev *pdev)
 243 {
 244         /* Disable interrupts from PCI to VME */
 245         iowrite32(0, bridge->base + VINT_EN);
 246
 247         /* Disable PCI interrupts */
 248         iowrite32(0, bridge->base + LINT_EN);
 249         /* Clear Any Pending PCI Interrupts */
 250         iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
 251
 252         free_irq(pdev->irq, pdev);
 253 }
 254
 255 /*
 256  * Set up an VME interrupt
 257  */
 258 void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level, int state,
 259         int sync)
 260
 261 {
 262         struct pci_dev *pdev;
 263         u32 tmp;
 264         struct ca91cx42_driver *bridge;
 265
 266         bridge = ca91cx42_bridge->driver_priv;
 267
 268         /* Enable IRQ level */
 269         tmp = ioread32(bridge->base + LINT_EN);
 270
 271         if (state == 0)
 272                 tmp &= ~CA91CX42_LINT_VIRQ[level];
 273         else
 274                 tmp |= CA91CX42_LINT_VIRQ[level];
 275
 276         iowrite32(tmp, bridge->base + LINT_EN);
 277
 278         if ((state == 0) && (sync != 0)) {
 279                 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev,
 280                         dev);
 281
 282                 synchronize_irq(pdev->irq);
 283         }
 284 }
 285
 286 int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level,
 287         int statid)
 288 {
 289         u32 tmp;
 290         struct ca91cx42_driver *bridge;
 291
 292         bridge = ca91cx42_bridge->driver_priv;
 293
 294         /* Universe can only generate even vectors */
 295         if (statid & 1)
 296                 return -EINVAL;
 297
 298         mutex_lock(&(bridge->vme_int));
 299
 300         tmp = ioread32(bridge->base + VINT_EN);
 301
 302         /* Set Status/ID */
 303         iowrite32(statid << 24, bridge->base + STATID);
 304
 305         /* Assert VMEbus IRQ */
 306         tmp = tmp | (1 << (level + 24));
 307         iowrite32(tmp, bridge->base + VINT_EN);
 308
 309         /* Wait for IACK */
 310         wait_event_interruptible(bridge->iack_queue, 0);
 311
 312         /* Return interrupt to low state */
 313         tmp = ioread32(bridge->base + VINT_EN);
 314         tmp = tmp & ~(1 << (level + 24));
 315         iowrite32(tmp, bridge->base + VINT_EN);
 316
 317         mutex_unlock(&(bridge->vme_int));
 318
 319         return 0;
 320 }
 321
 322 int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled,
 323         unsigned long long vme_base, unsigned long long size,
 324         dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
 325 {
 326         unsigned int i, addr = 0, granularity;
 327         unsigned int temp_ctl = 0;
 328         unsigned int vme_bound, pci_offset;
 329         struct ca91cx42_driver *bridge;
 330
 331         bridge = image->parent->driver_priv;
 332
 333         i = image->number;
 334
 335         switch (aspace) {
 336         case VME_A16:
 337                 addr |= CA91CX42_VSI_CTL_VAS_A16;
 338                 break;
 339         case VME_A24:
 340                 addr |= CA91CX42_VSI_CTL_VAS_A24;
 341                 break;
 342         case VME_A32:
 343                 addr |= CA91CX42_VSI_CTL_VAS_A32;
 344                 break;
 345         case VME_USER1:
 346                 addr |= CA91CX42_VSI_CTL_VAS_USER1;
 347                 break;
 348         case VME_USER2:
 349                 addr |= CA91CX42_VSI_CTL_VAS_USER2;
 350                 break;
 351         case VME_A64:
 352         case VME_CRCSR:
 353         case VME_USER3:
 354         case VME_USER4:
 355         default:
 356                 printk(KERN_ERR "Invalid address space\n");
 357                 return -EINVAL;
 358                 break;
 359         }
 360
 361         /*
 362          * Bound address is a valid address for the window, adjust
 363          * accordingly
 364          */
 365         vme_bound = vme_base + size;
 366         pci_offset = pci_base - vme_base;
 367
 368         if ((i == 0) || (i == 4))
 369                 granularity = 0x1000;
 370         else
 371                 granularity = 0x10000;
 372
 373         if (vme_base & (granularity - 1)) {
 374                 printk(KERN_ERR "Invalid VME base alignment\n");
 375                 return -EINVAL;
 376         }
 377         if (vme_bound & (granularity - 1)) {
 378                 printk(KERN_ERR "Invalid VME bound alignment\n");
 379                 return -EINVAL;
 380         }
 381         if (pci_offset & (granularity - 1)) {
 382                 printk(KERN_ERR "Invalid PCI Offset alignment\n");
 383                 return -EINVAL;
 384         }
 385
 386         /* Disable while we are mucking around */
 387         temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
 388         temp_ctl &= ~CA91CX42_VSI_CTL_EN;
 389         iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
 390
 391         /* Setup mapping */
 392         iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]);
 393         iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]);
 394         iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]);
 395
 396         /* Setup address space */
 397         temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M;
 398         temp_ctl |= addr;
 399
 400         /* Setup cycle types */
 401         temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M);
 402         if (cycle & VME_SUPER)
 403                 temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR;
 404         if (cycle & VME_USER)
 405                 temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV;
 406         if (cycle & VME_PROG)
 407                 temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM;
 408         if (cycle & VME_DATA)
 409                 temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA;
 410
 411         /* Write ctl reg without enable */
 412         iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
 413
 414         if (enabled)
 415                 temp_ctl |= CA91CX42_VSI_CTL_EN;
 416
 417         iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
 418
 419         return 0;
 420 }
 421
 422 int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled,
 423         unsigned long long *vme_base, unsigned long long *size,
 424         dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
 425 {
 426         unsigned int i, granularity = 0, ctl = 0;
 427         unsigned long long vme_bound, pci_offset;
 428         struct ca91cx42_driver *bridge;
 429
 430         bridge = image->parent->driver_priv;
 431
 432         i = image->number;
 433
 434         if ((i == 0) || (i == 4))
 435                 granularity = 0x1000;
 436         else
 437                 granularity = 0x10000;
 438
 439         /* Read Registers */
 440         ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
 441
 442         *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]);
 443         vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]);
 444         pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]);
 445
 446         *pci_base = (dma_addr_t)vme_base + pci_offset;
 447         *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
 448
 449         *enabled = 0;
 450         *aspace = 0;
 451         *cycle = 0;
 452
 453         if (ctl & CA91CX42_VSI_CTL_EN)
 454                 *enabled = 1;
 455
 456         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16)
 457                 *aspace = VME_A16;
 458         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24)
 459                 *aspace = VME_A24;
 460         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32)
 461                 *aspace = VME_A32;
 462         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1)
 463                 *aspace = VME_USER1;
 464         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2)
 465                 *aspace = VME_USER2;
 466
 467         if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR)
 468                 *cycle |= VME_SUPER;
 469         if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV)
 470                 *cycle |= VME_USER;
 471         if (ctl & CA91CX42_VSI_CTL_PGM_PGM)
 472                 *cycle |= VME_PROG;
 473         if (ctl & CA91CX42_VSI_CTL_PGM_DATA)
 474                 *cycle |= VME_DATA;
 475
 476         return 0;
 477 }
 478
 479 /*
 480  * Allocate and map PCI Resource
 481  */
 482 static int ca91cx42_alloc_resource(struct vme_master_resource *image,
 483         unsigned long long size)
 484 {
 485         unsigned long long existing_size;
 486         int retval = 0;
 487         struct pci_dev *pdev;
 488         struct vme_bridge *ca91cx42_bridge;
 489
 490         ca91cx42_bridge = image->parent;
 491
 492         /* Find pci_dev container of dev */
 493         if (ca91cx42_bridge->parent == NULL) {
 494                 printk(KERN_ERR "Dev entry NULL\n");
 495                 return -EINVAL;
 496         }
 497         pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
 498
 499         existing_size = (unsigned long long)(image->bus_resource.end -
 500                 image->bus_resource.start);
 501
 502         /* If the existing size is OK, return */
 503         if (existing_size == (size - 1))
 504                 return 0;
 505
 506         if (existing_size != 0) {
 507                 iounmap(image->kern_base);
 508                 image->kern_base = NULL;
 509                 if (image->bus_resource.name != NULL)
 510                         kfree(image->bus_resource.name);
 511                 release_resource(&(image->bus_resource));
 512                 memset(&(image->bus_resource), 0, sizeof(struct resource));
 513         }
 514
 515         if (image->bus_resource.name == NULL) {
 516                 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL);
 517                 if (image->bus_resource.name == NULL) {
 518                         printk(KERN_ERR "Unable to allocate memory for resource"
 519                                 " name\n");
 520                         retval = -ENOMEM;
 521                         goto err_name;
 522                 }
 523         }
 524
 525         sprintf((char *)image->bus_resource.name, "%s.%d",
 526                 ca91cx42_bridge->name, image->number);
 527
 528         image->bus_resource.start = 0;
 529         image->bus_resource.end = (unsigned long)size;
 530         image->bus_resource.flags = IORESOURCE_MEM;
 531
 532         retval = pci_bus_alloc_resource(pdev->bus,
 533                 &(image->bus_resource), size, size, PCIBIOS_MIN_MEM,
 534                 0, NULL, NULL);
 535         if (retval) {
 536                 printk(KERN_ERR "Failed to allocate mem resource for "
 537                         "window %d size 0x%lx start 0x%lx\n",
 538                         image->number, (unsigned long)size,
 539                         (unsigned long)image->bus_resource.start);
 540                 goto err_resource;
 541         }
 542
 543         image->kern_base = ioremap_nocache(
 544                 image->bus_resource.start, size);
 545         if (image->kern_base == NULL) {
 546                 printk(KERN_ERR "Failed to remap resource\n");
 547                 retval = -ENOMEM;
 548                 goto err_remap;
 549         }
 550
 551         return 0;
 552
 553         iounmap(image->kern_base);
 554         image->kern_base = NULL;
 555 err_remap:
 556         release_resource(&(image->bus_resource));
 557 err_resource:
 558         kfree(image->bus_resource.name);
 559         memset(&(image->bus_resource), 0, sizeof(struct resource));
 560 err_name:
 561         return retval;
 562 }
 563
 564 /*
 565  * Free and unmap PCI Resource
 566  */
 567 static void ca91cx42_free_resource(struct vme_master_resource *image)
 568 {
 569         iounmap(image->kern_base);
 570         image->kern_base = NULL;
 571         release_resource(&(image->bus_resource));
 572         kfree(image->bus_resource.name);
 573         memset(&(image->bus_resource), 0, sizeof(struct resource));
 574 }
 575
 576
 577 int ca91cx42_master_set(struct vme_master_resource *image, int enabled,
 578         unsigned long long vme_base, unsigned long long size,
 579         vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
 580 {
 581         int retval = 0;
 582         unsigned int i, granularity = 0;
 583         unsigned int temp_ctl = 0;
 584         unsigned long long pci_bound, vme_offset, pci_base;
 585         struct ca91cx42_driver *bridge;
 586
 587         bridge = image->parent->driver_priv;
 588
 589         i = image->number;
 590
 591         if ((i == 0) || (i == 4))
 592                 granularity = 0x1000;
 593         else
 594                 granularity = 0x10000;
 595
 596         /* Verify input data */
 597         if (vme_base & (granularity - 1)) {
 598                 printk(KERN_ERR "Invalid VME Window alignment\n");
 599                 retval = -EINVAL;
 600                 goto err_window;
 601         }
 602         if (size & (granularity - 1)) {
 603                 printk(KERN_ERR "Invalid VME Window alignment\n");
 604                 retval = -EINVAL;
 605                 goto err_window;
 606         }
 607
 608         spin_lock(&(image->lock));
 609
 610         /*
 611          * Let's allocate the resource here rather than further up the stack as
 612          * it avoids pushing loads of bus dependant stuff up the stack
 613          */
 614         retval = ca91cx42_alloc_resource(image, size);
 615         if (retval) {
 616                 spin_unlock(&(image->lock));
 617                 printk(KERN_ERR "Unable to allocate memory for resource "
 618                         "name\n");
 619                 retval = -ENOMEM;
 620                 goto err_res;
 621         }
 622
 623         pci_base = (unsigned long long)image->bus_resource.start;
 624
 625         /*
 626          * Bound address is a valid address for the window, adjust
 627          * according to window granularity.
 628          */
 629         pci_bound = pci_base + size;
 630         vme_offset = vme_base - pci_base;
 631
 632         /* Disable while we are mucking around */
 633         temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
 634         temp_ctl &= ~CA91CX42_LSI_CTL_EN;
 635         iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
 636
 637         /* Setup cycle types */
 638         temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M;
 639         if (cycle & VME_BLT)
 640                 temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT;
 641         if (cycle & VME_MBLT)
 642                 temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT;
 643
 644         /* Setup data width */
 645         temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M;
 646         switch (dwidth) {
 647         case VME_D8:
 648                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D8;
 649                 break;
 650         case VME_D16:
 651                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D16;
 652                 break;
 653         case VME_D32:
 654                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D32;
 655                 break;
 656         case VME_D64:
 657                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D64;
 658                 break;
 659         default:
 660                 spin_unlock(&(image->lock));
 661                 printk(KERN_ERR "Invalid data width\n");
 662                 retval = -EINVAL;
 663                 goto err_dwidth;
 664                 break;
 665         }
 666
 667         /* Setup address space */
 668         temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M;
 669         switch (aspace) {
 670         case VME_A16:
 671                 temp_ctl |= CA91CX42_LSI_CTL_VAS_A16;
 672                 break;
 673         case VME_A24:
 674                 temp_ctl |= CA91CX42_LSI_CTL_VAS_A24;
 675                 break;
 676         case VME_A32:
 677                 temp_ctl |= CA91CX42_LSI_CTL_VAS_A32;
 678                 break;
 679         case VME_CRCSR:
 680                 temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR;
 681                 break;
 682         case VME_USER1:
 683                 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1;
 684                 break;
 685         case VME_USER2:
 686                 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2;
 687                 break;
 688         case VME_A64:
 689         case VME_USER3:
 690         case VME_USER4:
 691         default:
 692                 spin_unlock(&(image->lock));
 693                 printk(KERN_ERR "Invalid address space\n");
 694                 retval = -EINVAL;
 695                 goto err_aspace;
 696                 break;
 697         }
 698
 699         temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M);
 700         if (cycle & VME_SUPER)
 701                 temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR;
 702         if (cycle & VME_PROG)
 703                 temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM;
 704
 705         /* Setup mapping */
 706         iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]);
 707         iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]);
 708         iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]);
 709
 710         /* Write ctl reg without enable */
 711         iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
 712
 713         if (enabled)
 714                 temp_ctl |= CA91CX42_LSI_CTL_EN;
 715
 716         iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
 717
 718         spin_unlock(&(image->lock));
 719         return 0;
 720
 721 err_aspace:
 722 err_dwidth:
 723         ca91cx42_free_resource(image);
 724 err_res:
 725 err_window:
 726         return retval;
 727 }
 728
 729 int __ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
 730         unsigned long long *vme_base, unsigned long long *size,
 731         vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
 732 {
 733         unsigned int i, ctl;
 734         unsigned long long pci_base, pci_bound, vme_offset;
 735         struct ca91cx42_driver *bridge;
 736
 737         bridge = image->parent->driver_priv;
 738
 739         i = image->number;
 740
 741         ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
 742
 743         pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]);
 744         vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]);
 745         pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]);
 746
 747         *vme_base = pci_base + vme_offset;
 748         *size = (unsigned long long)(pci_bound - pci_base);
 749
 750         *enabled = 0;
 751         *aspace = 0;
 752         *cycle = 0;
 753         *dwidth = 0;
 754
 755         if (ctl & CA91CX42_LSI_CTL_EN)
 756                 *enabled = 1;
 757
 758         /* Setup address space */
 759         switch (ctl & CA91CX42_LSI_CTL_VAS_M) {
 760         case CA91CX42_LSI_CTL_VAS_A16:
 761                 *aspace = VME_A16;
 762                 break;
 763         case CA91CX42_LSI_CTL_VAS_A24:
 764                 *aspace = VME_A24;
 765                 break;
 766         case CA91CX42_LSI_CTL_VAS_A32:
 767                 *aspace = VME_A32;
 768                 break;
 769         case CA91CX42_LSI_CTL_VAS_CRCSR:
 770                 *aspace = VME_CRCSR;
 771                 break;
 772         case CA91CX42_LSI_CTL_VAS_USER1:
 773                 *aspace = VME_USER1;
 774                 break;
 775         case CA91CX42_LSI_CTL_VAS_USER2:
 776                 *aspace = VME_USER2;
 777                 break;
 778         }
 779
 780         /* XXX Not sure howto check for MBLT */
 781         /* Setup cycle types */
 782         if (ctl & CA91CX42_LSI_CTL_VCT_BLT)
 783                 *cycle |= VME_BLT;
 784         else
 785                 *cycle |= VME_SCT;
 786
 787         if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR)
 788                 *cycle |= VME_SUPER;
 789         else
 790                 *cycle |= VME_USER;
 791
 792         if (ctl & CA91CX42_LSI_CTL_PGM_PGM)
 793                 *cycle = VME_PROG;
 794         else
 795                 *cycle = VME_DATA;
 796
 797         /* Setup data width */
 798         switch (ctl & CA91CX42_LSI_CTL_VDW_M) {
 799         case CA91CX42_LSI_CTL_VDW_D8:
 800                 *dwidth = VME_D8;
 801                 break;
 802         case CA91CX42_LSI_CTL_VDW_D16:
 803                 *dwidth = VME_D16;
 804                 break;
 805         case CA91CX42_LSI_CTL_VDW_D32:
 806                 *dwidth = VME_D32;
 807                 break;
 808         case CA91CX42_LSI_CTL_VDW_D64:
 809                 *dwidth = VME_D64;
 810                 break;
 811         }
 812
 813         return 0;
 814 }
 815
 816 int ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
 817         unsigned long long *vme_base, unsigned long long *size,
 818         vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
 819 {
 820         int retval;
 821
 822         spin_lock(&(image->lock));
 823
 824         retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace,
 825                 cycle, dwidth);
 826
 827         spin_unlock(&(image->lock));
 828
 829         return retval;
 830 }
 831
 832 ssize_t ca91cx42_master_read(struct vme_master_resource *image, void *buf,
 833         size_t count, loff_t offset)
 834 {
 835         ssize_t retval;
 836
 837         spin_lock(&(image->lock));
 838
 839         memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
 840         retval = count;
 841
 842         spin_unlock(&(image->lock));
 843
 844         return retval;
 845 }
 846
 847 ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf,
 848         size_t count, loff_t offset)
 849 {
 850         int retval = 0;
 851
 852         spin_lock(&(image->lock));
 853
 854         memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
 855         retval = count;
 856
 857         spin_unlock(&(image->lock));
 858
 859         return retval;
 860 }
 861
 862 unsigned int ca91cx42_master_rmw(struct vme_master_resource *image,
 863         unsigned int mask, unsigned int compare, unsigned int swap,
 864         loff_t offset)
 865 {
 866         u32 pci_addr, result;
 867         int i;
 868         struct ca91cx42_driver *bridge;
 869         struct device *dev;
 870
 871         bridge = image->parent->driver_priv;
 872         dev = image->parent->parent;
 873
 874         /* Find the PCI address that maps to the desired VME address */
 875         i = image->number;
 876
 877         /* Locking as we can only do one of these at a time */
 878         mutex_lock(&(bridge->vme_rmw));
 879
 880         /* Lock image */
 881         spin_lock(&(image->lock));
 882
 883         pci_addr = (u32)image->kern_base + offset;
 884
 885         /* Address must be 4-byte aligned */
 886         if (pci_addr & 0x3) {
 887                 dev_err(dev, "RMW Address not 4-byte aligned\n");
 888                 return -EINVAL;
 889         }
 890
 891         /* Ensure RMW Disabled whilst configuring */
 892         iowrite32(0, bridge->base + SCYC_CTL);
 893
 894         /* Configure registers */
 895         iowrite32(mask, bridge->base + SCYC_EN);
 896         iowrite32(compare, bridge->base + SCYC_CMP);
 897         iowrite32(swap, bridge->base + SCYC_SWP);
 898         iowrite32(pci_addr, bridge->base + SCYC_ADDR);
 899
 900         /* Enable RMW */
 901         iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL);
 902
 903         /* Kick process off with a read to the required address. */
 904         result = ioread32(image->kern_base + offset);
 905
 906         /* Disable RMW */
 907         iowrite32(0, bridge->base + SCYC_CTL);
 908
 909         spin_unlock(&(image->lock));
 910
 911         mutex_unlock(&(bridge->vme_rmw));
 912
 913         return result;
 914 }
 915
 916 int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src,
 917         struct vme_dma_attr *dest, size_t count)
 918 {
 919         struct ca91cx42_dma_entry *entry, *prev;
 920         struct vme_dma_pci *pci_attr;
 921         struct vme_dma_vme *vme_attr;
 922         dma_addr_t desc_ptr;
 923         int retval = 0;
 924
 925         /* XXX descriptor must be aligned on 64-bit boundaries */
 926         entry = (struct ca91cx42_dma_entry *)
 927                 kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL);
 928         if (entry == NULL) {
 929                 printk(KERN_ERR "Failed to allocate memory for dma resource "
 930                         "structure\n");
 931                 retval = -ENOMEM;
 932                 goto err_mem;
 933         }
 934
 935         /* Test descriptor alignment */
 936         if ((unsigned long)&(entry->descriptor) & CA91CX42_DCPP_M) {
 937                 printk("Descriptor not aligned to 16 byte boundary as "
 938                         "required: %p\n", &(entry->descriptor));
 939                 retval = -EINVAL;
 940                 goto err_align;
 941         }
 942
 943         memset(&(entry->descriptor), 0, sizeof(struct ca91cx42_dma_descriptor));
 944
 945         if (dest->type == VME_DMA_VME) {
 946                 entry->descriptor.dctl |= CA91CX42_DCTL_L2V;
 947                 vme_attr = (struct vme_dma_vme *)dest->private;
 948                 pci_attr = (struct vme_dma_pci *)src->private;
 949         } else {
 950                 vme_attr = (struct vme_dma_vme *)src->private;
 951                 pci_attr = (struct vme_dma_pci *)dest->private;
 952         }
 953
 954         /* Check we can do fullfill required attributes */
 955         if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 |
 956                 VME_USER2)) != 0) {
 957
 958                 printk(KERN_ERR "Unsupported cycle type\n");
 959                 retval = -EINVAL;
 960                 goto err_aspace;
 961         }
 962
 963         if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER |
 964                 VME_PROG | VME_DATA)) != 0) {
 965
 966                 printk(KERN_ERR "Unsupported cycle type\n");
 967                 retval = -EINVAL;
 968                 goto err_cycle;
 969         }
 970
 971         /* Check to see if we can fullfill source and destination */
 972         if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) ||
 973                 ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) {
 974
 975                 printk(KERN_ERR "Cannot perform transfer with this "
 976                         "source-destination combination\n");
 977                 retval = -EINVAL;
 978                 goto err_direct;
 979         }
 980
 981         /* Setup cycle types */
 982         if (vme_attr->cycle & VME_BLT)
 983                 entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT;
 984
 985         /* Setup data width */
 986         switch (vme_attr->dwidth) {
 987         case VME_D8:
 988                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8;
 989                 break;
 990         case VME_D16:
 991                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16;
 992                 break;
 993         case VME_D32:
 994                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32;
 995                 break;
 996         case VME_D64:
 997                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64;
 998                 break;
 999         default:
1000                 printk(KERN_ERR "Invalid data width\n");
1001                 return -EINVAL;
1002         }
1003
1004         /* Setup address space */
1005         switch (vme_attr->aspace) {
1006         case VME_A16:
1007                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16;
1008                 break;
1009         case VME_A24:
1010                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24;
1011                 break;
1012         case VME_A32:
1013                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32;
1014                 break;
1015         case VME_USER1:
1016                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1;
1017                 break;
1018         case VME_USER2:
1019                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2;
1020                 break;
1021         default:
1022                 printk(KERN_ERR "Invalid address space\n");
1023                 return -EINVAL;
1024                 break;
1025         }
1026
1027         if (vme_attr->cycle & VME_SUPER)
1028                 entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR;
1029         if (vme_attr->cycle & VME_PROG)
1030                 entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM;
1031
1032         entry->descriptor.dtbc = count;
1033         entry->descriptor.dla = pci_attr->address;
1034         entry->descriptor.dva = vme_attr->address;
1035         entry->descriptor.dcpp = CA91CX42_DCPP_NULL;
1036
1037         /* Add to list */
1038         list_add_tail(&(entry->list), &(list->entries));
1039
1040         /* Fill out previous descriptors "Next Address" */
1041         if (entry->list.prev != &(list->entries)) {
1042                 prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry,
1043                         list);
1044                 /* We need the bus address for the pointer */
1045                 desc_ptr = virt_to_bus(&(entry->descriptor));
1046                 prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M;
1047         }
1048
1049         return 0;
1050
1051 err_cycle:
1052 err_aspace:
1053 err_direct:
1054 err_align:
1055         kfree(entry);
1056 err_mem:
1057         return retval;
1058 }
1059
1060 static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge)
1061 {
1062         u32 tmp;
1063         struct ca91cx42_driver *bridge;
1064
1065         bridge = ca91cx42_bridge->driver_priv;
1066
1067         tmp = ioread32(bridge->base + DGCS);
1068
1069         if (tmp & CA91CX42_DGCS_ACT)
1070                 return 0;
1071         else
1072                 return 1;
1073 }
1074
1075 int ca91cx42_dma_list_exec(struct vme_dma_list *list)
1076 {
1077         struct vme_dma_resource *ctrlr;
1078         struct ca91cx42_dma_entry *entry;
1079         int retval = 0;
1080         dma_addr_t bus_addr;
1081         u32 val;
1082
1083         struct ca91cx42_driver *bridge;
1084
1085         ctrlr = list->parent;
1086
1087         bridge = ctrlr->parent->driver_priv;
1088
1089         mutex_lock(&(ctrlr->mtx));
1090
1091         if (!(list_empty(&(ctrlr->running)))) {
1092                 /*
1093                  * XXX We have an active DMA transfer and currently haven't
1094                  *     sorted out the mechanism for "pending" DMA transfers.
1095                  *     Return busy.
1096                  */
1097                 /* Need to add to pending here */
1098                 mutex_unlock(&(ctrlr->mtx));
1099                 return -EBUSY;
1100         } else {
1101                 list_add(&(list->list), &(ctrlr->running));
1102         }
1103
1104         /* Get first bus address and write into registers */
1105         entry = list_first_entry(&(list->entries), struct ca91cx42_dma_entry,
1106                 list);
1107
1108         bus_addr = virt_to_bus(&(entry->descriptor));
1109
1110         mutex_unlock(&(ctrlr->mtx));
1111
1112         iowrite32(0, bridge->base + DTBC);
1113         iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP);
1114
1115         /* Start the operation */
1116         val = ioread32(bridge->base + DGCS);
1117
1118         /* XXX Could set VMEbus On and Off Counters here */
1119         val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M);
1120
1121         val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT |
1122                 CA91CX42_DGCS_DONE | CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1123                 CA91CX42_DGCS_PERR);
1124
1125         iowrite32(val, bridge->base + DGCS);
1126
1127         val |= CA91CX42_DGCS_GO;
1128
1129         iowrite32(val, bridge->base + DGCS);
1130
1131         wait_event_interruptible(bridge->dma_queue,
1132                 ca91cx42_dma_busy(ctrlr->parent));
1133
1134         /*
1135          * Read status register, this register is valid until we kick off a
1136          * new transfer.
1137          */
1138         val = ioread32(bridge->base + DGCS);
1139
1140         if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1141                 CA91CX42_DGCS_PERR)) {
1142
1143                 printk(KERN_ERR "ca91c042: DMA Error. DGCS=%08X\n", val);
1144                 val = ioread32(bridge->base + DCTL);
1145         }
1146
1147         /* Remove list from running list */
1148         mutex_lock(&(ctrlr->mtx));
1149         list_del(&(list->list));
1150         mutex_unlock(&(ctrlr->mtx));
1151
1152         return retval;
1153
1154 }
1155
1156 int ca91cx42_dma_list_empty(struct vme_dma_list *list)
1157 {
1158         struct list_head *pos, *temp;
1159         struct ca91cx42_dma_entry *entry;
1160
1161         /* detach and free each entry */
1162         list_for_each_safe(pos, temp, &(list->entries)) {
1163                 list_del(pos);
1164                 entry = list_entry(pos, struct ca91cx42_dma_entry, list);
1165                 kfree(entry);
1166         }
1167
1168         return 0;
1169 }
1170
1171 /*
1172  * All 4 location monitors reside at the same base - this is therefore a
1173  * system wide configuration.
1174  *
1175  * This does not enable the LM monitor - that should be done when the first
1176  * callback is attached and disabled when the last callback is removed.
1177  */
1178 int ca91cx42_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
1179         vme_address_t aspace, vme_cycle_t cycle)
1180 {
1181         u32 temp_base, lm_ctl = 0;
1182         int i;
1183         struct ca91cx42_driver *bridge;
1184         struct device *dev;
1185
1186         bridge = lm->parent->driver_priv;
1187         dev = lm->parent->parent;
1188
1189         /* Check the alignment of the location monitor */
1190         temp_base = (u32)lm_base;
1191         if (temp_base & 0xffff) {
1192                 dev_err(dev, "Location monitor must be aligned to 64KB "
1193                         "boundary");
1194                 return -EINVAL;
1195         }
1196
1197         mutex_lock(&(lm->mtx));
1198
1199         /* If we already have a callback attached, we can't move it! */
1200         for (i = 0; i < lm->monitors; i++) {
1201                 if (bridge->lm_callback[i] != NULL) {
1202                         mutex_unlock(&(lm->mtx));
1203                         dev_err(dev, "Location monitor callback attached, "
1204                                 "can't reset\n");
1205                         return -EBUSY;
1206                 }
1207         }
1208
1209         switch (aspace) {
1210         case VME_A16:
1211                 lm_ctl |= CA91CX42_LM_CTL_AS_A16;
1212                 break;
1213         case VME_A24:
1214                 lm_ctl |= CA91CX42_LM_CTL_AS_A24;
1215                 break;
1216         case VME_A32:
1217                 lm_ctl |= CA91CX42_LM_CTL_AS_A32;
1218                 break;
1219         default:
1220                 mutex_unlock(&(lm->mtx));
1221                 dev_err(dev, "Invalid address space\n");
1222                 return -EINVAL;
1223                 break;
1224         }
1225
1226         if (cycle & VME_SUPER)
1227                 lm_ctl |= CA91CX42_LM_CTL_SUPR;
1228         if (cycle & VME_USER)
1229                 lm_ctl |= CA91CX42_LM_CTL_NPRIV;
1230         if (cycle & VME_PROG)
1231                 lm_ctl |= CA91CX42_LM_CTL_PGM;
1232         if (cycle & VME_DATA)
1233                 lm_ctl |= CA91CX42_LM_CTL_DATA;
1234
1235         iowrite32(lm_base, bridge->base + LM_BS);
1236         iowrite32(lm_ctl, bridge->base + LM_CTL);
1237
1238         mutex_unlock(&(lm->mtx));
1239
1240         return 0;
1241 }
1242
1243 /* Get configuration of the callback monitor and return whether it is enabled
1244  * or disabled.
1245  */
1246 int ca91cx42_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base,
1247         vme_address_t *aspace, vme_cycle_t *cycle)
1248 {
1249         u32 lm_ctl, enabled = 0;
1250         struct ca91cx42_driver *bridge;
1251
1252         bridge = lm->parent->driver_priv;
1253
1254         mutex_lock(&(lm->mtx));
1255
1256         *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS);
1257         lm_ctl = ioread32(bridge->base + LM_CTL);
1258
1259         if (lm_ctl & CA91CX42_LM_CTL_EN)
1260                 enabled = 1;
1261
1262         if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16)
1263                 *aspace = VME_A16;
1264         if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24)
1265                 *aspace = VME_A24;
1266         if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32)
1267                 *aspace = VME_A32;
1268
1269         *cycle = 0;
1270         if (lm_ctl & CA91CX42_LM_CTL_SUPR)
1271                 *cycle |= VME_SUPER;
1272         if (lm_ctl & CA91CX42_LM_CTL_NPRIV)
1273                 *cycle |= VME_USER;
1274         if (lm_ctl & CA91CX42_LM_CTL_PGM)
1275                 *cycle |= VME_PROG;
1276         if (lm_ctl & CA91CX42_LM_CTL_DATA)
1277                 *cycle |= VME_DATA;
1278
1279         mutex_unlock(&(lm->mtx));
1280
1281         return enabled;
1282 }
1283
1284 /*
1285  * Attach a callback to a specific location monitor.
1286  *
1287  * Callback will be passed the monitor triggered.
1288  */
1289 int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor,
1290         void (*callback)(int))
1291 {
1292         u32 lm_ctl, tmp;
1293         struct ca91cx42_driver *bridge;
1294         struct device *dev;
1295
1296         bridge = lm->parent->driver_priv;
1297         dev = lm->parent->parent;
1298
1299         mutex_lock(&(lm->mtx));
1300
1301         /* Ensure that the location monitor is configured - need PGM or DATA */
1302         lm_ctl = ioread32(bridge->base + LM_CTL);
1303         if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) {
1304                 mutex_unlock(&(lm->mtx));
1305                 dev_err(dev, "Location monitor not properly configured\n");
1306                 return -EINVAL;
1307         }
1308
1309         /* Check that a callback isn't already attached */
1310         if (bridge->lm_callback[monitor] != NULL) {
1311                 mutex_unlock(&(lm->mtx));
1312                 dev_err(dev, "Existing callback attached\n");
1313                 return -EBUSY;
1314         }
1315
1316         /* Attach callback */
1317         bridge->lm_callback[monitor] = callback;
1318
1319         /* Enable Location Monitor interrupt */
1320         tmp = ioread32(bridge->base + LINT_EN);
1321         tmp |= CA91CX42_LINT_LM[monitor];
1322         iowrite32(tmp, bridge->base + LINT_EN);
1323
1324         /* Ensure that global Location Monitor Enable set */
1325         if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) {
1326                 lm_ctl |= CA91CX42_LM_CTL_EN;
1327                 iowrite32(lm_ctl, bridge->base + LM_CTL);
1328         }
1329
1330         mutex_unlock(&(lm->mtx));
1331
1332         return 0;
1333 }
1334
1335 /*
1336  * Detach a callback function forn a specific location monitor.
1337  */
1338 int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor)
1339 {
1340         u32 tmp;
1341         struct ca91cx42_driver *bridge;
1342
1343         bridge = lm->parent->driver_priv;
1344
1345         mutex_lock(&(lm->mtx));
1346
1347         /* Disable Location Monitor and ensure previous interrupts are clear */
1348         tmp = ioread32(bridge->base + LINT_EN);
1349         tmp &= ~CA91CX42_LINT_LM[monitor];
1350         iowrite32(tmp, bridge->base + LINT_EN);
1351
1352         iowrite32(CA91CX42_LINT_LM[monitor],
1353                  bridge->base + LINT_STAT);
1354
1355         /* Detach callback */
1356         bridge->lm_callback[monitor] = NULL;
1357
1358         /* If all location monitors disabled, disable global Location Monitor */
1359         if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
1360                         CA91CX42_LINT_LM3)) == 0) {
1361                 tmp = ioread32(bridge->base + LM_CTL);
1362                 tmp &= ~CA91CX42_LM_CTL_EN;
1363                 iowrite32(tmp, bridge->base + LM_CTL);
1364         }
1365
1366         mutex_unlock(&(lm->mtx));
1367
1368         return 0;
1369 }
1370
1371 int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge)
1372 {
1373         u32 slot = 0;
1374         struct ca91cx42_driver *bridge;
1375
1376         bridge = ca91cx42_bridge->driver_priv;
1377
1378         if (!geoid) {
1379                 slot = ioread32(bridge->base + VCSR_BS);
1380                 slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27);
1381         } else
1382                 slot = geoid;
1383
1384         return (int)slot;
1385
1386 }
1387
1388 static int __init ca91cx42_init(void)
1389 {
1390         return pci_register_driver(&ca91cx42_driver);
1391 }
1392
1393 /*
1394  * Configure CR/CSR space
1395  *
1396  * Access to the CR/CSR can be configured at power-up. The location of the
1397  * CR/CSR registers in the CR/CSR address space is determined by the boards
1398  * Auto-ID or Geographic address. This function ensures that the window is
1399  * enabled at an offset consistent with the boards geopgraphic address.
1400  */
1401 static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge,
1402         struct pci_dev *pdev)
1403 {
1404         unsigned int crcsr_addr;
1405         int tmp, slot;
1406         struct ca91cx42_driver *bridge;
1407
1408         bridge = ca91cx42_bridge->driver_priv;
1409
1410         slot = ca91cx42_slot_get(ca91cx42_bridge);
1411
1412         /* Write CSR Base Address if slot ID is supplied as a module param */
1413         if (geoid)
1414                 iowrite32(geoid << 27, bridge->base + VCSR_BS);
1415
1416         dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot);
1417         if (slot == 0) {
1418                 dev_err(&pdev->dev, "Slot number is unset, not configuring "
1419                         "CR/CSR space\n");
1420                 return -EINVAL;
1421         }
1422
1423         /* Allocate mem for CR/CSR image */
1424         bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
1425                 &(bridge->crcsr_bus));
1426         if (bridge->crcsr_kernel == NULL) {
1427                 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
1428                         "image\n");
1429                 return -ENOMEM;
1430         }
1431
1432         memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
1433
1434         crcsr_addr = slot * (512 * 1024);
1435         iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO);
1436
1437         tmp = ioread32(bridge->base + VCSR_CTL);
1438         tmp |= CA91CX42_VCSR_CTL_EN;
1439         iowrite32(tmp, bridge->base + VCSR_CTL);
1440
1441         return 0;
1442 }
1443
1444 static void ca91cx42_crcsr_exit(struct vme_bridge *ca91cx42_bridge,
1445         struct pci_dev *pdev)
1446 {
1447         u32 tmp;
1448         struct ca91cx42_driver *bridge;
1449
1450         bridge = ca91cx42_bridge->driver_priv;
1451
1452         /* Turn off CR/CSR space */
1453         tmp = ioread32(bridge->base + VCSR_CTL);
1454         tmp &= ~CA91CX42_VCSR_CTL_EN;
1455         iowrite32(tmp, bridge->base + VCSR_CTL);
1456
1457         /* Free image */
1458         iowrite32(0, bridge->base + VCSR_TO);
1459
1460         pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
1461                 bridge->crcsr_bus);
1462 }
1463
1464 static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1465 {
1466         int retval, i;
1467         u32 data;
1468         struct list_head *pos = NULL;
1469         struct vme_bridge *ca91cx42_bridge;
1470         struct ca91cx42_driver *ca91cx42_device;
1471         struct vme_master_resource *master_image;
1472         struct vme_slave_resource *slave_image;
1473         struct vme_dma_resource *dma_ctrlr;
1474         struct vme_lm_resource *lm;
1475
1476         /* We want to support more than one of each bridge so we need to
1477          * dynamically allocate the bridge structure
1478          */
1479         ca91cx42_bridge = kmalloc(sizeof(struct vme_bridge), GFP_KERNEL);
1480
1481         if (ca91cx42_bridge == NULL) {
1482                 dev_err(&pdev->dev, "Failed to allocate memory for device "
1483                         "structure\n");
1484                 retval = -ENOMEM;
1485                 goto err_struct;
1486         }
1487
1488         memset(ca91cx42_bridge, 0, sizeof(struct vme_bridge));
1489
1490         ca91cx42_device = kmalloc(sizeof(struct ca91cx42_driver), GFP_KERNEL);
1491
1492         if (ca91cx42_device == NULL) {
1493                 dev_err(&pdev->dev, "Failed to allocate memory for device "
1494                         "structure\n");
1495                 retval = -ENOMEM;
1496                 goto err_driver;
1497         }
1498
1499         memset(ca91cx42_device, 0, sizeof(struct ca91cx42_driver));
1500
1501         ca91cx42_bridge->driver_priv = ca91cx42_device;
1502
1503         /* Enable the device */
1504         retval = pci_enable_device(pdev);
1505         if (retval) {
1506                 dev_err(&pdev->dev, "Unable to enable device\n");
1507                 goto err_enable;
1508         }
1509
1510         /* Map Registers */
1511         retval = pci_request_regions(pdev, driver_name);
1512         if (retval) {
1513                 dev_err(&pdev->dev, "Unable to reserve resources\n");
1514                 goto err_resource;
1515         }
1516
1517         /* map registers in BAR 0 */
1518         ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
1519                 4096);
1520         if (!ca91cx42_device->base) {
1521                 dev_err(&pdev->dev, "Unable to remap CRG region\n");
1522                 retval = -EIO;
1523                 goto err_remap;
1524         }
1525
1526         /* Check to see if the mapping worked out */
1527         data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF;
1528         if (data != PCI_VENDOR_ID_TUNDRA) {
1529                 dev_err(&pdev->dev, "PCI_ID check failed\n");
1530                 retval = -EIO;
1531                 goto err_test;
1532         }
1533
1534         /* Initialize wait queues & mutual exclusion flags */
1535         init_waitqueue_head(&(ca91cx42_device->dma_queue));
1536         init_waitqueue_head(&(ca91cx42_device->iack_queue));
1537         mutex_init(&(ca91cx42_device->vme_int));
1538         mutex_init(&(ca91cx42_device->vme_rmw));
1539
1540         ca91cx42_bridge->parent = &(pdev->dev);
1541         strcpy(ca91cx42_bridge->name, driver_name);
1542
1543         /* Setup IRQ */
1544         retval = ca91cx42_irq_init(ca91cx42_bridge);
1545         if (retval != 0) {
1546                 dev_err(&pdev->dev, "Chip Initialization failed.\n");
1547                 goto err_irq;
1548         }
1549
1550         /* Add master windows to list */
1551         INIT_LIST_HEAD(&(ca91cx42_bridge->master_resources));
1552         for (i = 0; i < CA91C142_MAX_MASTER; i++) {
1553                 master_image = kmalloc(sizeof(struct vme_master_resource),
1554                         GFP_KERNEL);
1555                 if (master_image == NULL) {
1556                         dev_err(&pdev->dev, "Failed to allocate memory for "
1557                         "master resource structure\n");
1558                         retval = -ENOMEM;
1559                         goto err_master;
1560                 }
1561                 master_image->parent = ca91cx42_bridge;
1562                 spin_lock_init(&(master_image->lock));
1563                 master_image->locked = 0;
1564                 master_image->number = i;
1565                 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
1566                         VME_CRCSR | VME_USER1 | VME_USER2;
1567                 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1568                         VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1569                 master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64;
1570                 memset(&(master_image->bus_resource), 0,
1571                         sizeof(struct resource));
1572                 master_image->kern_base  = NULL;
1573                 list_add_tail(&(master_image->list),
1574                         &(ca91cx42_bridge->master_resources));
1575         }
1576
1577         /* Add slave windows to list */
1578         INIT_LIST_HEAD(&(ca91cx42_bridge->slave_resources));
1579         for (i = 0; i < CA91C142_MAX_SLAVE; i++) {
1580                 slave_image = kmalloc(sizeof(struct vme_slave_resource),
1581                         GFP_KERNEL);
1582                 if (slave_image == NULL) {
1583                         dev_err(&pdev->dev, "Failed to allocate memory for "
1584                         "slave resource structure\n");
1585                         retval = -ENOMEM;
1586                         goto err_slave;
1587                 }
1588                 slave_image->parent = ca91cx42_bridge;
1589                 mutex_init(&(slave_image->mtx));
1590                 slave_image->locked = 0;
1591                 slave_image->number = i;
1592                 slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 |
1593                         VME_USER2;
1594
1595                 /* Only windows 0 and 4 support A16 */
1596                 if (i == 0 || i == 4)
1597                         slave_image->address_attr |= VME_A16;
1598
1599                 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1600                         VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1601                 list_add_tail(&(slave_image->list),
1602                         &(ca91cx42_bridge->slave_resources));
1603         }
1604
1605         /* Add dma engines to list */
1606         INIT_LIST_HEAD(&(ca91cx42_bridge->dma_resources));
1607         for (i = 0; i < CA91C142_MAX_DMA; i++) {
1608                 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
1609                         GFP_KERNEL);
1610                 if (dma_ctrlr == NULL) {
1611                         dev_err(&pdev->dev, "Failed to allocate memory for "
1612                         "dma resource structure\n");
1613                         retval = -ENOMEM;
1614                         goto err_dma;
1615                 }
1616                 dma_ctrlr->parent = ca91cx42_bridge;
1617                 mutex_init(&(dma_ctrlr->mtx));
1618                 dma_ctrlr->locked = 0;
1619                 dma_ctrlr->number = i;
1620                 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
1621                         VME_DMA_MEM_TO_VME;
1622                 INIT_LIST_HEAD(&(dma_ctrlr->pending));
1623                 INIT_LIST_HEAD(&(dma_ctrlr->running));
1624                 list_add_tail(&(dma_ctrlr->list),
1625                         &(ca91cx42_bridge->dma_resources));
1626         }
1627
1628         /* Add location monitor to list */
1629         INIT_LIST_HEAD(&(ca91cx42_bridge->lm_resources));
1630         lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
1631         if (lm == NULL) {
1632                 dev_err(&pdev->dev, "Failed to allocate memory for "
1633                 "location monitor resource structure\n");
1634                 retval = -ENOMEM;
1635                 goto err_lm;
1636         }
1637         lm->parent = ca91cx42_bridge;
1638         mutex_init(&(lm->mtx));
1639         lm->locked = 0;
1640         lm->number = 1;
1641         lm->monitors = 4;
1642         list_add_tail(&(lm->list), &(ca91cx42_bridge->lm_resources));
1643
1644         ca91cx42_bridge->slave_get = ca91cx42_slave_get;
1645         ca91cx42_bridge->slave_set = ca91cx42_slave_set;
1646         ca91cx42_bridge->master_get = ca91cx42_master_get;
1647         ca91cx42_bridge->master_set = ca91cx42_master_set;
1648         ca91cx42_bridge->master_read = ca91cx42_master_read;
1649         ca91cx42_bridge->master_write = ca91cx42_master_write;
1650         ca91cx42_bridge->master_rmw = ca91cx42_master_rmw;
1651         ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add;
1652         ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec;
1653         ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty;
1654         ca91cx42_bridge->irq_set = ca91cx42_irq_set;
1655         ca91cx42_bridge->irq_generate = ca91cx42_irq_generate;
1656         ca91cx42_bridge->lm_set = ca91cx42_lm_set;
1657         ca91cx42_bridge->lm_get = ca91cx42_lm_get;
1658         ca91cx42_bridge->lm_attach = ca91cx42_lm_attach;
1659         ca91cx42_bridge->lm_detach = ca91cx42_lm_detach;
1660         ca91cx42_bridge->slot_get = ca91cx42_slot_get;
1661
1662         data = ioread32(ca91cx42_device->base + MISC_CTL);
1663         dev_info(&pdev->dev, "Board is%s the VME system controller\n",
1664                 (data & CA91CX42_MISC_CTL_SYSCON) ? "" : " not");
1665         dev_info(&pdev->dev, "Slot ID is %d\n",
1666                 ca91cx42_slot_get(ca91cx42_bridge));
1667
1668         if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev)) {
1669                 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
1670         }
1671
1672         /* Need to save ca91cx42_bridge pointer locally in link list for use in
1673          * ca91cx42_remove()
1674          */
1675         retval = vme_register_bridge(ca91cx42_bridge);
1676         if (retval != 0) {
1677                 dev_err(&pdev->dev, "Chip Registration failed.\n");
1678                 goto err_reg;
1679         }
1680
1681         pci_set_drvdata(pdev, ca91cx42_bridge);
1682
1683         return 0;
1684
1685         vme_unregister_bridge(ca91cx42_bridge);
1686 err_reg:
1687         ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1688 err_lm:
1689         /* resources are stored in link list */
1690         list_for_each(pos, &(ca91cx42_bridge->lm_resources)) {
1691                 lm = list_entry(pos, struct vme_lm_resource, list);
1692                 list_del(pos);
1693                 kfree(lm);
1694         }
1695 err_dma:
1696         /* resources are stored in link list */
1697         list_for_each(pos, &(ca91cx42_bridge->dma_resources)) {
1698                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1699                 list_del(pos);
1700                 kfree(dma_ctrlr);
1701         }
1702 err_slave:
1703         /* resources are stored in link list */
1704         list_for_each(pos, &(ca91cx42_bridge->slave_resources)) {
1705                 slave_image = list_entry(pos, struct vme_slave_resource, list);
1706                 list_del(pos);
1707                 kfree(slave_image);
1708         }
1709 err_master:
1710         /* resources are stored in link list */
1711         list_for_each(pos, &(ca91cx42_bridge->master_resources)) {
1712                 master_image = list_entry(pos, struct vme_master_resource,
1713                         list);
1714                 list_del(pos);
1715                 kfree(master_image);
1716         }
1717
1718         ca91cx42_irq_exit(ca91cx42_device, pdev);
1719 err_irq:
1720 err_test:
1721         iounmap(ca91cx42_device->base);
1722 err_remap:
1723         pci_release_regions(pdev);
1724 err_resource:
1725         pci_disable_device(pdev);
1726 err_enable:
1727         kfree(ca91cx42_device);
1728 err_driver:
1729         kfree(ca91cx42_bridge);
1730 err_struct:
1731         return retval;
1732
1733 }
1734
1735 void ca91cx42_remove(struct pci_dev *pdev)
1736 {
1737         struct list_head *pos = NULL;
1738         struct vme_master_resource *master_image;
1739         struct vme_slave_resource *slave_image;
1740         struct vme_dma_resource *dma_ctrlr;
1741         struct vme_lm_resource *lm;
1742         struct ca91cx42_driver *bridge;
1743         struct vme_bridge *ca91cx42_bridge = pci_get_drvdata(pdev);
1744
1745         bridge = ca91cx42_bridge->driver_priv;
1746
1747
1748         /* Turn off Ints */
1749         iowrite32(0, bridge->base + LINT_EN);
1750
1751         /* Turn off the windows */
1752         iowrite32(0x00800000, bridge->base + LSI0_CTL);
1753         iowrite32(0x00800000, bridge->base + LSI1_CTL);
1754         iowrite32(0x00800000, bridge->base + LSI2_CTL);
1755         iowrite32(0x00800000, bridge->base + LSI3_CTL);
1756         iowrite32(0x00800000, bridge->base + LSI4_CTL);
1757         iowrite32(0x00800000, bridge->base + LSI5_CTL);
1758         iowrite32(0x00800000, bridge->base + LSI6_CTL);
1759         iowrite32(0x00800000, bridge->base + LSI7_CTL);
1760         iowrite32(0x00F00000, bridge->base + VSI0_CTL);
1761         iowrite32(0x00F00000, bridge->base + VSI1_CTL);
1762         iowrite32(0x00F00000, bridge->base + VSI2_CTL);
1763         iowrite32(0x00F00000, bridge->base + VSI3_CTL);
1764         iowrite32(0x00F00000, bridge->base + VSI4_CTL);
1765         iowrite32(0x00F00000, bridge->base + VSI5_CTL);
1766         iowrite32(0x00F00000, bridge->base + VSI6_CTL);
1767         iowrite32(0x00F00000, bridge->base + VSI7_CTL);
1768
1769         vme_unregister_bridge(ca91cx42_bridge);
1770
1771         ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1772
1773         /* resources are stored in link list */
1774         list_for_each(pos, &(ca91cx42_bridge->lm_resources)) {
1775                 lm = list_entry(pos, struct vme_lm_resource, list);
1776                 list_del(pos);
1777                 kfree(lm);
1778         }
1779
1780         /* resources are stored in link list */
1781         list_for_each(pos, &(ca91cx42_bridge->dma_resources)) {
1782                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1783                 list_del(pos);
1784                 kfree(dma_ctrlr);
1785         }
1786
1787         /* resources are stored in link list */
1788         list_for_each(pos, &(ca91cx42_bridge->slave_resources)) {
1789                 slave_image = list_entry(pos, struct vme_slave_resource, list);
1790                 list_del(pos);
1791                 kfree(slave_image);
1792         }
1793
1794         /* resources are stored in link list */
1795         list_for_each(pos, &(ca91cx42_bridge->master_resources)) {
1796                 master_image = list_entry(pos, struct vme_master_resource,
1797                         list);
1798                 list_del(pos);
1799                 kfree(master_image);
1800         }
1801
1802         ca91cx42_irq_exit(bridge, pdev);
1803
1804         iounmap(bridge->base);
1805
1806         pci_release_regions(pdev);
1807
1808         pci_disable_device(pdev);
1809
1810         kfree(ca91cx42_bridge);
1811 }
1812
1813 static void __exit ca91cx42_exit(void)
1814 {
1815         pci_unregister_driver(&ca91cx42_driver);
1816 }
1817
1818 MODULE_PARM_DESC(geoid, "Override geographical addressing");
1819 module_param(geoid, int, 0);
1820
1821 MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge");
1822 MODULE_LICENSE("GPL");
1823
1824 module_init(ca91cx42_init);
1825 module_exit(ca91cx42_exit);