drivers/staging/vme/bridges/vme_ca91cx42.c

   1 /*
   2  * Support for the Tundra Universe I/II VME-PCI Bridge Chips
   3  *
   4  * Author: Martyn Welch <martyn.welch@ge.com>
   5  * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
   6  *
   7  * Based on work by Tom Armistead and Ajit Prem
   8  * Copyright 2004 Motorola Inc.
   9  *
  10  * Derived from ca91c042.c by Michael Wyrick
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/mm.h>
  20 #include <linux/types.h>
  21 #include <linux/errno.h>
  22 #include <linux/pci.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/poll.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/sched.h>
  28 #include <linux/slab.h>
  29 #include <linux/time.h>
  30 #include <linux/io.h>
  31 #include <linux/uaccess.h>
  32
  33 #include "../vme.h"
  34 #include "../vme_bridge.h"
  35 #include "vme_ca91cx42.h"
  36
  37 static int __init ca91cx42_init(void);
  38 static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *);
  39 static void ca91cx42_remove(struct pci_dev *);
  40 static void __exit ca91cx42_exit(void);
  41
  42 /* Module parameters */
  43 static int geoid;
  44
  45 static char driver_name[] = "vme_ca91cx42";
  46
  47 static DEFINE_PCI_DEVICE_TABLE(ca91cx42_ids) = {
  48         { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) },
  49         { },
  50 };
  51
  52 static struct pci_driver ca91cx42_driver = {
  53         .name = driver_name,
  54         .id_table = ca91cx42_ids,
  55         .probe = ca91cx42_probe,
  56         .remove = ca91cx42_remove,
  57 };
  58
  59 static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge)
  60 {
  61         wake_up(&bridge->dma_queue);
  62
  63         return CA91CX42_LINT_DMA;
  64 }
  65
  66 static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat)
  67 {
  68         int i;
  69         u32 serviced = 0;
  70
  71         for (i = 0; i < 4; i++) {
  72                 if (stat & CA91CX42_LINT_LM[i]) {
  73                         /* We only enable interrupts if the callback is set */
  74                         bridge->lm_callback[i](i);
  75                         serviced |= CA91CX42_LINT_LM[i];
  76                 }
  77         }
  78
  79         return serviced;
  80 }
  81
  82 /* XXX This needs to be split into 4 queues */
  83 static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask)
  84 {
  85         wake_up(&bridge->mbox_queue);
  86
  87         return CA91CX42_LINT_MBOX;
  88 }
  89
  90 static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge)
  91 {
  92         wake_up(&bridge->iack_queue);
  93
  94         return CA91CX42_LINT_SW_IACK;
  95 }
  96
  97 static u32 ca91cx42_VERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
  98 {
  99         int val;
 100         struct ca91cx42_driver *bridge;
 101
 102         bridge = ca91cx42_bridge->driver_priv;
 103
 104         val = ioread32(bridge->base + DGCS);
 105
 106         if (!(val & 0x00000800)) {
 107                 dev_err(ca91cx42_bridge->parent, "ca91cx42_VERR_irqhandler DMA "
 108                         "Read Error DGCS=%08X\n", val);
 109         }
 110
 111         return CA91CX42_LINT_VERR;
 112 }
 113
 114 static u32 ca91cx42_LERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
 115 {
 116         int val;
 117         struct ca91cx42_driver *bridge;
 118
 119         bridge = ca91cx42_bridge->driver_priv;
 120
 121         val = ioread32(bridge->base + DGCS);
 122
 123         if (!(val & 0x00000800))
 124                 dev_err(ca91cx42_bridge->parent, "ca91cx42_LERR_irqhandler DMA "
 125                         "Read Error DGCS=%08X\n", val);
 126
 127         return CA91CX42_LINT_LERR;
 128 }
 129
 130
 131 static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge,
 132         int stat)
 133 {
 134         int vec, i, serviced = 0;
 135         struct ca91cx42_driver *bridge;
 136
 137         bridge = ca91cx42_bridge->driver_priv;
 138
 139
 140         for (i = 7; i > 0; i--) {
 141                 if (stat & (1 << i)) {
 142                         vec = ioread32(bridge->base +
 143                                 CA91CX42_V_STATID[i]) & 0xff;
 144
 145                         vme_irq_handler(ca91cx42_bridge, i, vec);
 146
 147                         serviced |= (1 << i);
 148                 }
 149         }
 150
 151         return serviced;
 152 }
 153
 154 static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr)
 155 {
 156         u32 stat, enable, serviced = 0;
 157         struct vme_bridge *ca91cx42_bridge;
 158         struct ca91cx42_driver *bridge;
 159
 160         ca91cx42_bridge = ptr;
 161
 162         bridge = ca91cx42_bridge->driver_priv;
 163
 164         enable = ioread32(bridge->base + LINT_EN);
 165         stat = ioread32(bridge->base + LINT_STAT);
 166
 167         /* Only look at unmasked interrupts */
 168         stat &= enable;
 169
 170         if (unlikely(!stat))
 171                 return IRQ_NONE;
 172
 173         if (stat & CA91CX42_LINT_DMA)
 174                 serviced |= ca91cx42_DMA_irqhandler(bridge);
 175         if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
 176                         CA91CX42_LINT_LM3))
 177                 serviced |= ca91cx42_LM_irqhandler(bridge, stat);
 178         if (stat & CA91CX42_LINT_MBOX)
 179                 serviced |= ca91cx42_MB_irqhandler(bridge, stat);
 180         if (stat & CA91CX42_LINT_SW_IACK)
 181                 serviced |= ca91cx42_IACK_irqhandler(bridge);
 182         if (stat & CA91CX42_LINT_VERR)
 183                 serviced |= ca91cx42_VERR_irqhandler(ca91cx42_bridge);
 184         if (stat & CA91CX42_LINT_LERR)
 185                 serviced |= ca91cx42_LERR_irqhandler(ca91cx42_bridge);
 186         if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 |
 187                         CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 |
 188                         CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 |
 189                         CA91CX42_LINT_VIRQ7))
 190                 serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat);
 191
 192         /* Clear serviced interrupts */
 193         iowrite32(stat, bridge->base + LINT_STAT);
 194
 195         return IRQ_HANDLED;
 196 }
 197
 198 static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge)
 199 {
 200         int result, tmp;
 201         struct pci_dev *pdev;
 202         struct ca91cx42_driver *bridge;
 203
 204         bridge = ca91cx42_bridge->driver_priv;
 205
 206         /* Need pdev */
 207         pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
 208
 209         /* Initialise list for VME bus errors */
 210         INIT_LIST_HEAD(&ca91cx42_bridge->vme_errors);
 211
 212         mutex_init(&ca91cx42_bridge->irq_mtx);
 213
 214         /* Disable interrupts from PCI to VME */
 215         iowrite32(0, bridge->base + VINT_EN);
 216
 217         /* Disable PCI interrupts */
 218         iowrite32(0, bridge->base + LINT_EN);
 219         /* Clear Any Pending PCI Interrupts */
 220         iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
 221
 222         result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED,
 223                         driver_name, ca91cx42_bridge);
 224         if (result) {
 225                 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
 226                        pdev->irq);
 227                 return result;
 228         }
 229
 230         /* Ensure all interrupts are mapped to PCI Interrupt 0 */
 231         iowrite32(0, bridge->base + LINT_MAP0);
 232         iowrite32(0, bridge->base + LINT_MAP1);
 233         iowrite32(0, bridge->base + LINT_MAP2);
 234
 235         /* Enable DMA, mailbox & LM Interrupts */
 236         tmp = CA91CX42_LINT_MBOX3 | CA91CX42_LINT_MBOX2 | CA91CX42_LINT_MBOX1 |
 237                 CA91CX42_LINT_MBOX0 | CA91CX42_LINT_SW_IACK |
 238                 CA91CX42_LINT_VERR | CA91CX42_LINT_LERR | CA91CX42_LINT_DMA;
 239
 240         iowrite32(tmp, bridge->base + LINT_EN);
 241
 242         return 0;
 243 }
 244
 245 static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge,
 246         struct pci_dev *pdev)
 247 {
 248         /* Disable interrupts from PCI to VME */
 249         iowrite32(0, bridge->base + VINT_EN);
 250
 251         /* Disable PCI interrupts */
 252         iowrite32(0, bridge->base + LINT_EN);
 253         /* Clear Any Pending PCI Interrupts */
 254         iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
 255
 256         free_irq(pdev->irq, pdev);
 257 }
 258
 259 /*
 260  * Set up an VME interrupt
 261  */
 262 static void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level,
 263         int state, int sync)
 264
 265 {
 266         struct pci_dev *pdev;
 267         u32 tmp;
 268         struct ca91cx42_driver *bridge;
 269
 270         bridge = ca91cx42_bridge->driver_priv;
 271
 272         /* Enable IRQ level */
 273         tmp = ioread32(bridge->base + LINT_EN);
 274
 275         if (state == 0)
 276                 tmp &= ~CA91CX42_LINT_VIRQ[level];
 277         else
 278                 tmp |= CA91CX42_LINT_VIRQ[level];
 279
 280         iowrite32(tmp, bridge->base + LINT_EN);
 281
 282         if ((state == 0) && (sync != 0)) {
 283                 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev,
 284                         dev);
 285
 286                 synchronize_irq(pdev->irq);
 287         }
 288 }
 289
 290 static int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level,
 291         int statid)
 292 {
 293         u32 tmp;
 294         struct ca91cx42_driver *bridge;
 295
 296         bridge = ca91cx42_bridge->driver_priv;
 297
 298         /* Universe can only generate even vectors */
 299         if (statid & 1)
 300                 return -EINVAL;
 301
 302         mutex_lock(&bridge->vme_int);
 303
 304         tmp = ioread32(bridge->base + VINT_EN);
 305
 306         /* Set Status/ID */
 307         iowrite32(statid << 24, bridge->base + STATID);
 308
 309         /* Assert VMEbus IRQ */
 310         tmp = tmp | (1 << (level + 24));
 311         iowrite32(tmp, bridge->base + VINT_EN);
 312
 313         /* Wait for IACK */
 314         wait_event_interruptible(bridge->iack_queue, 0);
 315
 316         /* Return interrupt to low state */
 317         tmp = ioread32(bridge->base + VINT_EN);
 318         tmp = tmp & ~(1 << (level + 24));
 319         iowrite32(tmp, bridge->base + VINT_EN);
 320
 321         mutex_unlock(&bridge->vme_int);
 322
 323         return 0;
 324 }
 325
 326 static int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled,
 327         unsigned long long vme_base, unsigned long long size,
 328         dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
 329 {
 330         unsigned int i, addr = 0, granularity;
 331         unsigned int temp_ctl = 0;
 332         unsigned int vme_bound, pci_offset;
 333         struct vme_bridge *ca91cx42_bridge;
 334         struct ca91cx42_driver *bridge;
 335
 336         ca91cx42_bridge = image->parent;
 337
 338         bridge = ca91cx42_bridge->driver_priv;
 339
 340         i = image->number;
 341
 342         switch (aspace) {
 343         case VME_A16:
 344                 addr |= CA91CX42_VSI_CTL_VAS_A16;
 345                 break;
 346         case VME_A24:
 347                 addr |= CA91CX42_VSI_CTL_VAS_A24;
 348                 break;
 349         case VME_A32:
 350                 addr |= CA91CX42_VSI_CTL_VAS_A32;
 351                 break;
 352         case VME_USER1:
 353                 addr |= CA91CX42_VSI_CTL_VAS_USER1;
 354                 break;
 355         case VME_USER2:
 356                 addr |= CA91CX42_VSI_CTL_VAS_USER2;
 357                 break;
 358         case VME_A64:
 359         case VME_CRCSR:
 360         case VME_USER3:
 361         case VME_USER4:
 362         default:
 363                 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
 364                 return -EINVAL;
 365                 break;
 366         }
 367
 368         /*
 369          * Bound address is a valid address for the window, adjust
 370          * accordingly
 371          */
 372         vme_bound = vme_base + size;
 373         pci_offset = pci_base - vme_base;
 374
 375         if ((i == 0) || (i == 4))
 376                 granularity = 0x1000;
 377         else
 378                 granularity = 0x10000;
 379
 380         if (vme_base & (granularity - 1)) {
 381                 dev_err(ca91cx42_bridge->parent, "Invalid VME base "
 382                         "alignment\n");
 383                 return -EINVAL;
 384         }
 385         if (vme_bound & (granularity - 1)) {
 386                 dev_err(ca91cx42_bridge->parent, "Invalid VME bound "
 387                         "alignment\n");
 388                 return -EINVAL;
 389         }
 390         if (pci_offset & (granularity - 1)) {
 391                 dev_err(ca91cx42_bridge->parent, "Invalid PCI Offset "
 392                         "alignment\n");
 393                 return -EINVAL;
 394         }
 395
 396         /* Disable while we are mucking around */
 397         temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
 398         temp_ctl &= ~CA91CX42_VSI_CTL_EN;
 399         iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
 400
 401         /* Setup mapping */
 402         iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]);
 403         iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]);
 404         iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]);
 405
 406         /* Setup address space */
 407         temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M;
 408         temp_ctl |= addr;
 409
 410         /* Setup cycle types */
 411         temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M);
 412         if (cycle & VME_SUPER)
 413                 temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR;
 414         if (cycle & VME_USER)
 415                 temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV;
 416         if (cycle & VME_PROG)
 417                 temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM;
 418         if (cycle & VME_DATA)
 419                 temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA;
 420
 421         /* Write ctl reg without enable */
 422         iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
 423
 424         if (enabled)
 425                 temp_ctl |= CA91CX42_VSI_CTL_EN;
 426
 427         iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
 428
 429         return 0;
 430 }
 431
 432 static int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled,
 433         unsigned long long *vme_base, unsigned long long *size,
 434         dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
 435 {
 436         unsigned int i, granularity = 0, ctl = 0;
 437         unsigned long long vme_bound, pci_offset;
 438         struct ca91cx42_driver *bridge;
 439
 440         bridge = image->parent->driver_priv;
 441
 442         i = image->number;
 443
 444         if ((i == 0) || (i == 4))
 445                 granularity = 0x1000;
 446         else
 447                 granularity = 0x10000;
 448
 449         /* Read Registers */
 450         ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
 451
 452         *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]);
 453         vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]);
 454         pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]);
 455
 456         *pci_base = (dma_addr_t)vme_base + pci_offset;
 457         *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
 458
 459         *enabled = 0;
 460         *aspace = 0;
 461         *cycle = 0;
 462
 463         if (ctl & CA91CX42_VSI_CTL_EN)
 464                 *enabled = 1;
 465
 466         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16)
 467                 *aspace = VME_A16;
 468         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24)
 469                 *aspace = VME_A24;
 470         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32)
 471                 *aspace = VME_A32;
 472         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1)
 473                 *aspace = VME_USER1;
 474         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2)
 475                 *aspace = VME_USER2;
 476
 477         if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR)
 478                 *cycle |= VME_SUPER;
 479         if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV)
 480                 *cycle |= VME_USER;
 481         if (ctl & CA91CX42_VSI_CTL_PGM_PGM)
 482                 *cycle |= VME_PROG;
 483         if (ctl & CA91CX42_VSI_CTL_PGM_DATA)
 484                 *cycle |= VME_DATA;
 485
 486         return 0;
 487 }
 488
 489 /*
 490  * Allocate and map PCI Resource
 491  */
 492 static int ca91cx42_alloc_resource(struct vme_master_resource *image,
 493         unsigned long long size)
 494 {
 495         unsigned long long existing_size;
 496         int retval = 0;
 497         struct pci_dev *pdev;
 498         struct vme_bridge *ca91cx42_bridge;
 499
 500         ca91cx42_bridge = image->parent;
 501
 502         /* Find pci_dev container of dev */
 503         if (ca91cx42_bridge->parent == NULL) {
 504                 dev_err(ca91cx42_bridge->parent, "Dev entry NULL\n");
 505                 return -EINVAL;
 506         }
 507         pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
 508
 509         existing_size = (unsigned long long)(image->bus_resource.end -
 510                 image->bus_resource.start);
 511
 512         /* If the existing size is OK, return */
 513         if (existing_size == (size - 1))
 514                 return 0;
 515
 516         if (existing_size != 0) {
 517                 iounmap(image->kern_base);
 518                 image->kern_base = NULL;
 519                 kfree(image->bus_resource.name);
 520                 release_resource(&image->bus_resource);
 521                 memset(&image->bus_resource, 0, sizeof(struct resource));
 522         }
 523
 524         if (image->bus_resource.name == NULL) {
 525                 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
 526                 if (image->bus_resource.name == NULL) {
 527                         dev_err(ca91cx42_bridge->parent, "Unable to allocate "
 528                                 "memory for resource name\n");
 529                         retval = -ENOMEM;
 530                         goto err_name;
 531                 }
 532         }
 533
 534         sprintf((char *)image->bus_resource.name, "%s.%d",
 535                 ca91cx42_bridge->name, image->number);
 536
 537         image->bus_resource.start = 0;
 538         image->bus_resource.end = (unsigned long)size;
 539         image->bus_resource.flags = IORESOURCE_MEM;
 540
 541         retval = pci_bus_alloc_resource(pdev->bus,
 542                 &image->bus_resource, size, size, PCIBIOS_MIN_MEM,
 543                 0, NULL, NULL);
 544         if (retval) {
 545                 dev_err(ca91cx42_bridge->parent, "Failed to allocate mem "
 546                         "resource for window %d size 0x%lx start 0x%lx\n",
 547                         image->number, (unsigned long)size,
 548                         (unsigned long)image->bus_resource.start);
 549                 goto err_resource;
 550         }
 551
 552         image->kern_base = ioremap_nocache(
 553                 image->bus_resource.start, size);
 554         if (image->kern_base == NULL) {
 555                 dev_err(ca91cx42_bridge->parent, "Failed to remap resource\n");
 556                 retval = -ENOMEM;
 557                 goto err_remap;
 558         }
 559
 560         return 0;
 561
 562 err_remap:
 563         release_resource(&image->bus_resource);
 564 err_resource:
 565         kfree(image->bus_resource.name);
 566         memset(&image->bus_resource, 0, sizeof(struct resource));
 567 err_name:
 568         return retval;
 569 }
 570
 571 /*
 572  * Free and unmap PCI Resource
 573  */
 574 static void ca91cx42_free_resource(struct vme_master_resource *image)
 575 {
 576         iounmap(image->kern_base);
 577         image->kern_base = NULL;
 578         release_resource(&image->bus_resource);
 579         kfree(image->bus_resource.name);
 580         memset(&image->bus_resource, 0, sizeof(struct resource));
 581 }
 582
 583
 584 static int ca91cx42_master_set(struct vme_master_resource *image, int enabled,
 585         unsigned long long vme_base, unsigned long long size,
 586         vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
 587 {
 588         int retval = 0;
 589         unsigned int i, granularity = 0;
 590         unsigned int temp_ctl = 0;
 591         unsigned long long pci_bound, vme_offset, pci_base;
 592         struct vme_bridge *ca91cx42_bridge;
 593         struct ca91cx42_driver *bridge;
 594
 595         ca91cx42_bridge = image->parent;
 596
 597         bridge = ca91cx42_bridge->driver_priv;
 598
 599         i = image->number;
 600
 601         if ((i == 0) || (i == 4))
 602                 granularity = 0x1000;
 603         else
 604                 granularity = 0x10000;
 605
 606         /* Verify input data */
 607         if (vme_base & (granularity - 1)) {
 608                 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
 609                         "alignment\n");
 610                 retval = -EINVAL;
 611                 goto err_window;
 612         }
 613         if (size & (granularity - 1)) {
 614                 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
 615                         "alignment\n");
 616                 retval = -EINVAL;
 617                 goto err_window;
 618         }
 619
 620         spin_lock(&image->lock);
 621
 622         /*
 623          * Let's allocate the resource here rather than further up the stack as
 624          * it avoids pushing loads of bus dependent stuff up the stack
 625          */
 626         retval = ca91cx42_alloc_resource(image, size);
 627         if (retval) {
 628                 spin_unlock(&image->lock);
 629                 dev_err(ca91cx42_bridge->parent, "Unable to allocate memory "
 630                         "for resource name\n");
 631                 retval = -ENOMEM;
 632                 goto err_res;
 633         }
 634
 635         pci_base = (unsigned long long)image->bus_resource.start;
 636
 637         /*
 638          * Bound address is a valid address for the window, adjust
 639          * according to window granularity.
 640          */
 641         pci_bound = pci_base + size;
 642         vme_offset = vme_base - pci_base;
 643
 644         /* Disable while we are mucking around */
 645         temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
 646         temp_ctl &= ~CA91CX42_LSI_CTL_EN;
 647         iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
 648
 649         /* Setup cycle types */
 650         temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M;
 651         if (cycle & VME_BLT)
 652                 temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT;
 653         if (cycle & VME_MBLT)
 654                 temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT;
 655
 656         /* Setup data width */
 657         temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M;
 658         switch (dwidth) {
 659         case VME_D8:
 660                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D8;
 661                 break;
 662         case VME_D16:
 663                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D16;
 664                 break;
 665         case VME_D32:
 666                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D32;
 667                 break;
 668         case VME_D64:
 669                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D64;
 670                 break;
 671         default:
 672                 spin_unlock(&image->lock);
 673                 dev_err(ca91cx42_bridge->parent, "Invalid data width\n");
 674                 retval = -EINVAL;
 675                 goto err_dwidth;
 676                 break;
 677         }
 678
 679         /* Setup address space */
 680         temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M;
 681         switch (aspace) {
 682         case VME_A16:
 683                 temp_ctl |= CA91CX42_LSI_CTL_VAS_A16;
 684                 break;
 685         case VME_A24:
 686                 temp_ctl |= CA91CX42_LSI_CTL_VAS_A24;
 687                 break;
 688         case VME_A32:
 689                 temp_ctl |= CA91CX42_LSI_CTL_VAS_A32;
 690                 break;
 691         case VME_CRCSR:
 692                 temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR;
 693                 break;
 694         case VME_USER1:
 695                 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1;
 696                 break;
 697         case VME_USER2:
 698                 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2;
 699                 break;
 700         case VME_A64:
 701         case VME_USER3:
 702         case VME_USER4:
 703         default:
 704                 spin_unlock(&image->lock);
 705                 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
 706                 retval = -EINVAL;
 707                 goto err_aspace;
 708                 break;
 709         }
 710
 711         temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M);
 712         if (cycle & VME_SUPER)
 713                 temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR;
 714         if (cycle & VME_PROG)
 715                 temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM;
 716
 717         /* Setup mapping */
 718         iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]);
 719         iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]);
 720         iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]);
 721
 722         /* Write ctl reg without enable */
 723         iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
 724
 725         if (enabled)
 726                 temp_ctl |= CA91CX42_LSI_CTL_EN;
 727
 728         iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
 729
 730         spin_unlock(&image->lock);
 731         return 0;
 732
 733 err_aspace:
 734 err_dwidth:
 735         ca91cx42_free_resource(image);
 736 err_res:
 737 err_window:
 738         return retval;
 739 }
 740
 741 static int __ca91cx42_master_get(struct vme_master_resource *image,
 742         int *enabled, unsigned long long *vme_base, unsigned long long *size,
 743         vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
 744 {
 745         unsigned int i, ctl;
 746         unsigned long long pci_base, pci_bound, vme_offset;
 747         struct ca91cx42_driver *bridge;
 748
 749         bridge = image->parent->driver_priv;
 750
 751         i = image->number;
 752
 753         ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
 754
 755         pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]);
 756         vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]);
 757         pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]);
 758
 759         *vme_base = pci_base + vme_offset;
 760         *size = (unsigned long long)(pci_bound - pci_base);
 761
 762         *enabled = 0;
 763         *aspace = 0;
 764         *cycle = 0;
 765         *dwidth = 0;
 766
 767         if (ctl & CA91CX42_LSI_CTL_EN)
 768                 *enabled = 1;
 769
 770         /* Setup address space */
 771         switch (ctl & CA91CX42_LSI_CTL_VAS_M) {
 772         case CA91CX42_LSI_CTL_VAS_A16:
 773                 *aspace = VME_A16;
 774                 break;
 775         case CA91CX42_LSI_CTL_VAS_A24:
 776                 *aspace = VME_A24;
 777                 break;
 778         case CA91CX42_LSI_CTL_VAS_A32:
 779                 *aspace = VME_A32;
 780                 break;
 781         case CA91CX42_LSI_CTL_VAS_CRCSR:
 782                 *aspace = VME_CRCSR;
 783                 break;
 784         case CA91CX42_LSI_CTL_VAS_USER1:
 785                 *aspace = VME_USER1;
 786                 break;
 787         case CA91CX42_LSI_CTL_VAS_USER2:
 788                 *aspace = VME_USER2;
 789                 break;
 790         }
 791
 792         /* XXX Not sure howto check for MBLT */
 793         /* Setup cycle types */
 794         if (ctl & CA91CX42_LSI_CTL_VCT_BLT)
 795                 *cycle |= VME_BLT;
 796         else
 797                 *cycle |= VME_SCT;
 798
 799         if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR)
 800                 *cycle |= VME_SUPER;
 801         else
 802                 *cycle |= VME_USER;
 803
 804         if (ctl & CA91CX42_LSI_CTL_PGM_PGM)
 805                 *cycle = VME_PROG;
 806         else
 807                 *cycle = VME_DATA;
 808
 809         /* Setup data width */
 810         switch (ctl & CA91CX42_LSI_CTL_VDW_M) {
 811         case CA91CX42_LSI_CTL_VDW_D8:
 812                 *dwidth = VME_D8;
 813                 break;
 814         case CA91CX42_LSI_CTL_VDW_D16:
 815                 *dwidth = VME_D16;
 816                 break;
 817         case CA91CX42_LSI_CTL_VDW_D32:
 818                 *dwidth = VME_D32;
 819                 break;
 820         case CA91CX42_LSI_CTL_VDW_D64:
 821                 *dwidth = VME_D64;
 822                 break;
 823         }
 824
 825         return 0;
 826 }
 827
 828 static int ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
 829         unsigned long long *vme_base, unsigned long long *size,
 830         vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
 831 {
 832         int retval;
 833
 834         spin_lock(&image->lock);
 835
 836         retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace,
 837                 cycle, dwidth);
 838
 839         spin_unlock(&image->lock);
 840
 841         return retval;
 842 }
 843
 844 static ssize_t ca91cx42_master_read(struct vme_master_resource *image,
 845         void *buf, size_t count, loff_t offset)
 846 {
 847         ssize_t retval;
 848         void *addr = image->kern_base + offset;
 849         unsigned int done = 0;
 850         unsigned int count32;
 851
 852         if (count == 0)
 853                 return 0;
 854
 855         spin_lock(&image->lock);
 856
 857         /* The following code handles VME address alignment problem
 858          * in order to assure the maximal data width cycle.
 859          * We cannot use memcpy_xxx directly here because it
 860          * may cut data transfer in 8-bits cycles, thus making
 861          * D16 cycle impossible.
 862          * From the other hand, the bridge itself assures that
 863          * maximal configured data cycle is used and splits it
 864          * automatically for non-aligned addresses.
 865          */
 866         if ((int)addr & 0x1) {
 867                 *(u8 *)buf = ioread8(addr);
 868                 done += 1;
 869                 if (done == count)
 870                         goto out;
 871         }
 872         if ((int)addr & 0x2) {
 873                 if ((count - done) < 2) {
 874                         *(u8 *)(buf + done) = ioread8(addr + done);
 875                         done += 1;
 876                         goto out;
 877                 } else {
 878                         *(u16 *)(buf + done) = ioread16(addr + done);
 879                         done += 2;
 880                 }
 881         }
 882
 883         count32 = (count - done) & ~0x3;
 884         if (count32 > 0) {
 885                 memcpy_fromio(buf + done, addr + done, (unsigned int)count);
 886                 done += count32;
 887         }
 888
 889         if ((count - done) & 0x2) {
 890                 *(u16 *)(buf + done) = ioread16(addr + done);
 891                 done += 2;
 892         }
 893         if ((count - done) & 0x1) {
 894                 *(u8 *)(buf + done) = ioread8(addr + done);
 895                 done += 1;
 896         }
 897 out:
 898         retval = count;
 899         spin_unlock(&image->lock);
 900
 901         return retval;
 902 }
 903
 904 static ssize_t ca91cx42_master_write(struct vme_master_resource *image,
 905         void *buf, size_t count, loff_t offset)
 906 {
 907         ssize_t retval;
 908         void *addr = image->kern_base + offset;
 909         unsigned int done = 0;
 910         unsigned int count32;
 911
 912         if (count == 0)
 913                 return 0;
 914
 915         spin_lock(&image->lock);
 916
 917         /* Here we apply for the same strategy we do in master_read
 918          * function in order to assure D16 cycle when required.
 919          */
 920         if ((int)addr & 0x1) {
 921                 iowrite8(*(u8 *)buf, addr);
 922                 done += 1;
 923                 if (done == count)
 924                         goto out;
 925         }
 926         if ((int)addr & 0x2) {
 927                 if ((count - done) < 2) {
 928                         iowrite8(*(u8 *)(buf + done), addr + done);
 929                         done += 1;
 930                         goto out;
 931                 } else {
 932                         iowrite16(*(u16 *)(buf + done), addr + done);
 933                         done += 2;
 934                 }
 935         }
 936
 937         count32 = (count - done) & ~0x3;
 938         if (count32 > 0) {
 939                 memcpy_toio(addr + done, buf + done, count32);
 940                 done += count32;
 941         }
 942
 943         if ((count - done) & 0x2) {
 944                 iowrite16(*(u16 *)(buf + done), addr + done);
 945                 done += 2;
 946         }
 947         if ((count - done) & 0x1) {
 948                 iowrite8(*(u8 *)(buf + done), addr + done);
 949                 done += 1;
 950         }
 951 out:
 952         retval = count;
 953
 954         spin_unlock(&image->lock);
 955
 956         return retval;
 957 }
 958
 959 static unsigned int ca91cx42_master_rmw(struct vme_master_resource *image,
 960         unsigned int mask, unsigned int compare, unsigned int swap,
 961         loff_t offset)
 962 {
 963         u32 pci_addr, result;
 964         int i;
 965         struct ca91cx42_driver *bridge;
 966         struct device *dev;
 967
 968         bridge = image->parent->driver_priv;
 969         dev = image->parent->parent;
 970
 971         /* Find the PCI address that maps to the desired VME address */
 972         i = image->number;
 973
 974         /* Locking as we can only do one of these at a time */
 975         mutex_lock(&bridge->vme_rmw);
 976
 977         /* Lock image */
 978         spin_lock(&image->lock);
 979
 980         pci_addr = (u32)image->kern_base + offset;
 981
 982         /* Address must be 4-byte aligned */
 983         if (pci_addr & 0x3) {
 984                 dev_err(dev, "RMW Address not 4-byte aligned\n");
 985                 result = -EINVAL;
 986                 goto out;
 987         }
 988
 989         /* Ensure RMW Disabled whilst configuring */
 990         iowrite32(0, bridge->base + SCYC_CTL);
 991
 992         /* Configure registers */
 993         iowrite32(mask, bridge->base + SCYC_EN);
 994         iowrite32(compare, bridge->base + SCYC_CMP);
 995         iowrite32(swap, bridge->base + SCYC_SWP);
 996         iowrite32(pci_addr, bridge->base + SCYC_ADDR);
 997
 998         /* Enable RMW */
 999         iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL);
1000
1001         /* Kick process off with a read to the required address. */
1002         result = ioread32(image->kern_base + offset);
1003
1004         /* Disable RMW */
1005         iowrite32(0, bridge->base + SCYC_CTL);
1006
1007 out:
1008         spin_unlock(&image->lock);
1009
1010         mutex_unlock(&bridge->vme_rmw);
1011
1012         return result;
1013 }
1014
1015 static int ca91cx42_dma_list_add(struct vme_dma_list *list,
1016         struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
1017 {
1018         struct ca91cx42_dma_entry *entry, *prev;
1019         struct vme_dma_pci *pci_attr;
1020         struct vme_dma_vme *vme_attr;
1021         dma_addr_t desc_ptr;
1022         int retval = 0;
1023         struct device *dev;
1024
1025         dev = list->parent->parent->parent;
1026
1027         /* XXX descriptor must be aligned on 64-bit boundaries */
1028         entry = kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL);
1029         if (entry == NULL) {
1030                 dev_err(dev, "Failed to allocate memory for dma resource "
1031                         "structure\n");
1032                 retval = -ENOMEM;
1033                 goto err_mem;
1034         }
1035
1036         /* Test descriptor alignment */
1037         if ((unsigned long)&entry->descriptor & CA91CX42_DCPP_M) {
1038                 dev_err(dev, "Descriptor not aligned to 16 byte boundary as "
1039                         "required: %p\n", &entry->descriptor);
1040                 retval = -EINVAL;
1041                 goto err_align;
1042         }
1043
1044         memset(&entry->descriptor, 0, sizeof(struct ca91cx42_dma_descriptor));
1045
1046         if (dest->type == VME_DMA_VME) {
1047                 entry->descriptor.dctl |= CA91CX42_DCTL_L2V;
1048                 vme_attr = dest->private;
1049                 pci_attr = src->private;
1050         } else {
1051                 vme_attr = src->private;
1052                 pci_attr = dest->private;
1053         }
1054
1055         /* Check we can do fulfill required attributes */
1056         if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 |
1057                 VME_USER2)) != 0) {
1058
1059                 dev_err(dev, "Unsupported cycle type\n");
1060                 retval = -EINVAL;
1061                 goto err_aspace;
1062         }
1063
1064         if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER |
1065                 VME_PROG | VME_DATA)) != 0) {
1066
1067                 dev_err(dev, "Unsupported cycle type\n");
1068                 retval = -EINVAL;
1069                 goto err_cycle;
1070         }
1071
1072         /* Check to see if we can fulfill source and destination */
1073         if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) ||
1074                 ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) {
1075
1076                 dev_err(dev, "Cannot perform transfer with this "
1077                         "source-destination combination\n");
1078                 retval = -EINVAL;
1079                 goto err_direct;
1080         }
1081
1082         /* Setup cycle types */
1083         if (vme_attr->cycle & VME_BLT)
1084                 entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT;
1085
1086         /* Setup data width */
1087         switch (vme_attr->dwidth) {
1088         case VME_D8:
1089                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8;
1090                 break;
1091         case VME_D16:
1092                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16;
1093                 break;
1094         case VME_D32:
1095                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32;
1096                 break;
1097         case VME_D64:
1098                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64;
1099                 break;
1100         default:
1101                 dev_err(dev, "Invalid data width\n");
1102                 return -EINVAL;
1103         }
1104
1105         /* Setup address space */
1106         switch (vme_attr->aspace) {
1107         case VME_A16:
1108                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16;
1109                 break;
1110         case VME_A24:
1111                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24;
1112                 break;
1113         case VME_A32:
1114                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32;
1115                 break;
1116         case VME_USER1:
1117                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1;
1118                 break;
1119         case VME_USER2:
1120                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2;
1121                 break;
1122         default:
1123                 dev_err(dev, "Invalid address space\n");
1124                 return -EINVAL;
1125                 break;
1126         }
1127
1128         if (vme_attr->cycle & VME_SUPER)
1129                 entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR;
1130         if (vme_attr->cycle & VME_PROG)
1131                 entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM;
1132
1133         entry->descriptor.dtbc = count;
1134         entry->descriptor.dla = pci_attr->address;
1135         entry->descriptor.dva = vme_attr->address;
1136         entry->descriptor.dcpp = CA91CX42_DCPP_NULL;
1137
1138         /* Add to list */
1139         list_add_tail(&entry->list, &list->entries);
1140
1141         /* Fill out previous descriptors "Next Address" */
1142         if (entry->list.prev != &list->entries) {
1143                 prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry,
1144                         list);
1145                 /* We need the bus address for the pointer */
1146                 desc_ptr = virt_to_bus(&entry->descriptor);
1147                 prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M;
1148         }
1149
1150         return 0;
1151
1152 err_cycle:
1153 err_aspace:
1154 err_direct:
1155 err_align:
1156         kfree(entry);
1157 err_mem:
1158         return retval;
1159 }
1160
1161 static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge)
1162 {
1163         u32 tmp;
1164         struct ca91cx42_driver *bridge;
1165
1166         bridge = ca91cx42_bridge->driver_priv;
1167
1168         tmp = ioread32(bridge->base + DGCS);
1169
1170         if (tmp & CA91CX42_DGCS_ACT)
1171                 return 0;
1172         else
1173                 return 1;
1174 }
1175
1176 static int ca91cx42_dma_list_exec(struct vme_dma_list *list)
1177 {
1178         struct vme_dma_resource *ctrlr;
1179         struct ca91cx42_dma_entry *entry;
1180         int retval = 0;
1181         dma_addr_t bus_addr;
1182         u32 val;
1183         struct device *dev;
1184         struct ca91cx42_driver *bridge;
1185
1186         ctrlr = list->parent;
1187
1188         bridge = ctrlr->parent->driver_priv;
1189         dev = ctrlr->parent->parent;
1190
1191         mutex_lock(&ctrlr->mtx);
1192
1193         if (!(list_empty(&ctrlr->running))) {
1194                 /*
1195                  * XXX We have an active DMA transfer and currently haven't
1196                  *     sorted out the mechanism for "pending" DMA transfers.
1197                  *     Return busy.
1198                  */
1199                 /* Need to add to pending here */
1200                 mutex_unlock(&ctrlr->mtx);
1201                 return -EBUSY;
1202         } else {
1203                 list_add(&list->list, &ctrlr->running);
1204         }
1205
1206         /* Get first bus address and write into registers */
1207         entry = list_first_entry(&list->entries, struct ca91cx42_dma_entry,
1208                 list);
1209
1210         bus_addr = virt_to_bus(&entry->descriptor);
1211
1212         mutex_unlock(&ctrlr->mtx);
1213
1214         iowrite32(0, bridge->base + DTBC);
1215         iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP);
1216
1217         /* Start the operation */
1218         val = ioread32(bridge->base + DGCS);
1219
1220         /* XXX Could set VMEbus On and Off Counters here */
1221         val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M);
1222
1223         val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT |
1224                 CA91CX42_DGCS_DONE | CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1225                 CA91CX42_DGCS_PERR);
1226
1227         iowrite32(val, bridge->base + DGCS);
1228
1229         val |= CA91CX42_DGCS_GO;
1230
1231         iowrite32(val, bridge->base + DGCS);
1232
1233         wait_event_interruptible(bridge->dma_queue,
1234                 ca91cx42_dma_busy(ctrlr->parent));
1235
1236         /*
1237          * Read status register, this register is valid until we kick off a
1238          * new transfer.
1239          */
1240         val = ioread32(bridge->base + DGCS);
1241
1242         if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1243                 CA91CX42_DGCS_PERR)) {
1244
1245                 dev_err(dev, "ca91c042: DMA Error. DGCS=%08X\n", val);
1246                 val = ioread32(bridge->base + DCTL);
1247         }
1248
1249         /* Remove list from running list */
1250         mutex_lock(&ctrlr->mtx);
1251         list_del(&list->list);
1252         mutex_unlock(&ctrlr->mtx);
1253
1254         return retval;
1255
1256 }
1257
1258 static int ca91cx42_dma_list_empty(struct vme_dma_list *list)
1259 {
1260         struct list_head *pos, *temp;
1261         struct ca91cx42_dma_entry *entry;
1262
1263         /* detach and free each entry */
1264         list_for_each_safe(pos, temp, &list->entries) {
1265                 list_del(pos);
1266                 entry = list_entry(pos, struct ca91cx42_dma_entry, list);
1267                 kfree(entry);
1268         }
1269
1270         return 0;
1271 }
1272
1273 /*
1274  * All 4 location monitors reside at the same base - this is therefore a
1275  * system wide configuration.
1276  *
1277  * This does not enable the LM monitor - that should be done when the first
1278  * callback is attached and disabled when the last callback is removed.
1279  */
1280 static int ca91cx42_lm_set(struct vme_lm_resource *lm,
1281         unsigned long long lm_base, vme_address_t aspace, vme_cycle_t cycle)
1282 {
1283         u32 temp_base, lm_ctl = 0;
1284         int i;
1285         struct ca91cx42_driver *bridge;
1286         struct device *dev;
1287
1288         bridge = lm->parent->driver_priv;
1289         dev = lm->parent->parent;
1290
1291         /* Check the alignment of the location monitor */
1292         temp_base = (u32)lm_base;
1293         if (temp_base & 0xffff) {
1294                 dev_err(dev, "Location monitor must be aligned to 64KB "
1295                         "boundary");
1296                 return -EINVAL;
1297         }
1298
1299         mutex_lock(&lm->mtx);
1300
1301         /* If we already have a callback attached, we can't move it! */
1302         for (i = 0; i < lm->monitors; i++) {
1303                 if (bridge->lm_callback[i] != NULL) {
1304                         mutex_unlock(&lm->mtx);
1305                         dev_err(dev, "Location monitor callback attached, "
1306                                 "can't reset\n");
1307                         return -EBUSY;
1308                 }
1309         }
1310
1311         switch (aspace) {
1312         case VME_A16:
1313                 lm_ctl |= CA91CX42_LM_CTL_AS_A16;
1314                 break;
1315         case VME_A24:
1316                 lm_ctl |= CA91CX42_LM_CTL_AS_A24;
1317                 break;
1318         case VME_A32:
1319                 lm_ctl |= CA91CX42_LM_CTL_AS_A32;
1320                 break;
1321         default:
1322                 mutex_unlock(&lm->mtx);
1323                 dev_err(dev, "Invalid address space\n");
1324                 return -EINVAL;
1325                 break;
1326         }
1327
1328         if (cycle & VME_SUPER)
1329                 lm_ctl |= CA91CX42_LM_CTL_SUPR;
1330         if (cycle & VME_USER)
1331                 lm_ctl |= CA91CX42_LM_CTL_NPRIV;
1332         if (cycle & VME_PROG)
1333                 lm_ctl |= CA91CX42_LM_CTL_PGM;
1334         if (cycle & VME_DATA)
1335                 lm_ctl |= CA91CX42_LM_CTL_DATA;
1336
1337         iowrite32(lm_base, bridge->base + LM_BS);
1338         iowrite32(lm_ctl, bridge->base + LM_CTL);
1339
1340         mutex_unlock(&lm->mtx);
1341
1342         return 0;
1343 }
1344
1345 /* Get configuration of the callback monitor and return whether it is enabled
1346  * or disabled.
1347  */
1348 static int ca91cx42_lm_get(struct vme_lm_resource *lm,
1349         unsigned long long *lm_base, vme_address_t *aspace, vme_cycle_t *cycle)
1350 {
1351         u32 lm_ctl, enabled = 0;
1352         struct ca91cx42_driver *bridge;
1353
1354         bridge = lm->parent->driver_priv;
1355
1356         mutex_lock(&lm->mtx);
1357
1358         *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS);
1359         lm_ctl = ioread32(bridge->base + LM_CTL);
1360
1361         if (lm_ctl & CA91CX42_LM_CTL_EN)
1362                 enabled = 1;
1363
1364         if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16)
1365                 *aspace = VME_A16;
1366         if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24)
1367                 *aspace = VME_A24;
1368         if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32)
1369                 *aspace = VME_A32;
1370
1371         *cycle = 0;
1372         if (lm_ctl & CA91CX42_LM_CTL_SUPR)
1373                 *cycle |= VME_SUPER;
1374         if (lm_ctl & CA91CX42_LM_CTL_NPRIV)
1375                 *cycle |= VME_USER;
1376         if (lm_ctl & CA91CX42_LM_CTL_PGM)
1377                 *cycle |= VME_PROG;
1378         if (lm_ctl & CA91CX42_LM_CTL_DATA)
1379                 *cycle |= VME_DATA;
1380
1381         mutex_unlock(&lm->mtx);
1382
1383         return enabled;
1384 }
1385
1386 /*
1387  * Attach a callback to a specific location monitor.
1388  *
1389  * Callback will be passed the monitor triggered.
1390  */
1391 static int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor,
1392         void (*callback)(int))
1393 {
1394         u32 lm_ctl, tmp;
1395         struct ca91cx42_driver *bridge;
1396         struct device *dev;
1397
1398         bridge = lm->parent->driver_priv;
1399         dev = lm->parent->parent;
1400
1401         mutex_lock(&lm->mtx);
1402
1403         /* Ensure that the location monitor is configured - need PGM or DATA */
1404         lm_ctl = ioread32(bridge->base + LM_CTL);
1405         if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) {
1406                 mutex_unlock(&lm->mtx);
1407                 dev_err(dev, "Location monitor not properly configured\n");
1408                 return -EINVAL;
1409         }
1410
1411         /* Check that a callback isn't already attached */
1412         if (bridge->lm_callback[monitor] != NULL) {
1413                 mutex_unlock(&lm->mtx);
1414                 dev_err(dev, "Existing callback attached\n");
1415                 return -EBUSY;
1416         }
1417
1418         /* Attach callback */
1419         bridge->lm_callback[monitor] = callback;
1420
1421         /* Enable Location Monitor interrupt */
1422         tmp = ioread32(bridge->base + LINT_EN);
1423         tmp |= CA91CX42_LINT_LM[monitor];
1424         iowrite32(tmp, bridge->base + LINT_EN);
1425
1426         /* Ensure that global Location Monitor Enable set */
1427         if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) {
1428                 lm_ctl |= CA91CX42_LM_CTL_EN;
1429                 iowrite32(lm_ctl, bridge->base + LM_CTL);
1430         }
1431
1432         mutex_unlock(&lm->mtx);
1433
1434         return 0;
1435 }
1436
1437 /*
1438  * Detach a callback function forn a specific location monitor.
1439  */
1440 static int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor)
1441 {
1442         u32 tmp;
1443         struct ca91cx42_driver *bridge;
1444
1445         bridge = lm->parent->driver_priv;
1446
1447         mutex_lock(&lm->mtx);
1448
1449         /* Disable Location Monitor and ensure previous interrupts are clear */
1450         tmp = ioread32(bridge->base + LINT_EN);
1451         tmp &= ~CA91CX42_LINT_LM[monitor];
1452         iowrite32(tmp, bridge->base + LINT_EN);
1453
1454         iowrite32(CA91CX42_LINT_LM[monitor],
1455                  bridge->base + LINT_STAT);
1456
1457         /* Detach callback */
1458         bridge->lm_callback[monitor] = NULL;
1459
1460         /* If all location monitors disabled, disable global Location Monitor */
1461         if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
1462                         CA91CX42_LINT_LM3)) == 0) {
1463                 tmp = ioread32(bridge->base + LM_CTL);
1464                 tmp &= ~CA91CX42_LM_CTL_EN;
1465                 iowrite32(tmp, bridge->base + LM_CTL);
1466         }
1467
1468         mutex_unlock(&lm->mtx);
1469
1470         return 0;
1471 }
1472
1473 static int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge)
1474 {
1475         u32 slot = 0;
1476         struct ca91cx42_driver *bridge;
1477
1478         bridge = ca91cx42_bridge->driver_priv;
1479
1480         if (!geoid) {
1481                 slot = ioread32(bridge->base + VCSR_BS);
1482                 slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27);
1483         } else
1484                 slot = geoid;
1485
1486         return (int)slot;
1487
1488 }
1489
1490 static int __init ca91cx42_init(void)
1491 {
1492         return pci_register_driver(&ca91cx42_driver);
1493 }
1494
1495 /*
1496  * Configure CR/CSR space
1497  *
1498  * Access to the CR/CSR can be configured at power-up. The location of the
1499  * CR/CSR registers in the CR/CSR address space is determined by the boards
1500  * Auto-ID or Geographic address. This function ensures that the window is
1501  * enabled at an offset consistent with the boards geopgraphic address.
1502  */
1503 static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge,
1504         struct pci_dev *pdev)
1505 {
1506         unsigned int crcsr_addr;
1507         int tmp, slot;
1508         struct ca91cx42_driver *bridge;
1509
1510         bridge = ca91cx42_bridge->driver_priv;
1511
1512         slot = ca91cx42_slot_get(ca91cx42_bridge);
1513
1514         /* Write CSR Base Address if slot ID is supplied as a module param */
1515         if (geoid)
1516                 iowrite32(geoid << 27, bridge->base + VCSR_BS);
1517
1518         dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot);
1519         if (slot == 0) {
1520                 dev_err(&pdev->dev, "Slot number is unset, not configuring "
1521                         "CR/CSR space\n");
1522                 return -EINVAL;
1523         }
1524
1525         /* Allocate mem for CR/CSR image */
1526         bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
1527                 &bridge->crcsr_bus);
1528         if (bridge->crcsr_kernel == NULL) {
1529                 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
1530                         "image\n");
1531                 return -ENOMEM;
1532         }
1533
1534         memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
1535
1536         crcsr_addr = slot * (512 * 1024);
1537         iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO);
1538
1539         tmp = ioread32(bridge->base + VCSR_CTL);
1540         tmp |= CA91CX42_VCSR_CTL_EN;
1541         iowrite32(tmp, bridge->base + VCSR_CTL);
1542
1543         return 0;
1544 }
1545
1546 static void ca91cx42_crcsr_exit(struct vme_bridge *ca91cx42_bridge,
1547         struct pci_dev *pdev)
1548 {
1549         u32 tmp;
1550         struct ca91cx42_driver *bridge;
1551
1552         bridge = ca91cx42_bridge->driver_priv;
1553
1554         /* Turn off CR/CSR space */
1555         tmp = ioread32(bridge->base + VCSR_CTL);
1556         tmp &= ~CA91CX42_VCSR_CTL_EN;
1557         iowrite32(tmp, bridge->base + VCSR_CTL);
1558
1559         /* Free image */
1560         iowrite32(0, bridge->base + VCSR_TO);
1561
1562         pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
1563                 bridge->crcsr_bus);
1564 }
1565
1566 static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1567 {
1568         int retval, i;
1569         u32 data;
1570         struct list_head *pos = NULL;
1571         struct vme_bridge *ca91cx42_bridge;
1572         struct ca91cx42_driver *ca91cx42_device;
1573         struct vme_master_resource *master_image;
1574         struct vme_slave_resource *slave_image;
1575         struct vme_dma_resource *dma_ctrlr;
1576         struct vme_lm_resource *lm;
1577
1578         /* We want to support more than one of each bridge so we need to
1579          * dynamically allocate the bridge structure
1580          */
1581         ca91cx42_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL);
1582
1583         if (ca91cx42_bridge == NULL) {
1584                 dev_err(&pdev->dev, "Failed to allocate memory for device "
1585                         "structure\n");
1586                 retval = -ENOMEM;
1587                 goto err_struct;
1588         }
1589
1590         ca91cx42_device = kzalloc(sizeof(struct ca91cx42_driver), GFP_KERNEL);
1591
1592         if (ca91cx42_device == NULL) {
1593                 dev_err(&pdev->dev, "Failed to allocate memory for device "
1594                         "structure\n");
1595                 retval = -ENOMEM;
1596                 goto err_driver;
1597         }
1598
1599         ca91cx42_bridge->driver_priv = ca91cx42_device;
1600
1601         /* Enable the device */
1602         retval = pci_enable_device(pdev);
1603         if (retval) {
1604                 dev_err(&pdev->dev, "Unable to enable device\n");
1605                 goto err_enable;
1606         }
1607
1608         /* Map Registers */
1609         retval = pci_request_regions(pdev, driver_name);
1610         if (retval) {
1611                 dev_err(&pdev->dev, "Unable to reserve resources\n");
1612                 goto err_resource;
1613         }
1614
1615         /* map registers in BAR 0 */
1616         ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
1617                 4096);
1618         if (!ca91cx42_device->base) {
1619                 dev_err(&pdev->dev, "Unable to remap CRG region\n");
1620                 retval = -EIO;
1621                 goto err_remap;
1622         }
1623
1624         /* Check to see if the mapping worked out */
1625         data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF;
1626         if (data != PCI_VENDOR_ID_TUNDRA) {
1627                 dev_err(&pdev->dev, "PCI_ID check failed\n");
1628                 retval = -EIO;
1629                 goto err_test;
1630         }
1631
1632         /* Initialize wait queues & mutual exclusion flags */
1633         init_waitqueue_head(&ca91cx42_device->dma_queue);
1634         init_waitqueue_head(&ca91cx42_device->iack_queue);
1635         mutex_init(&ca91cx42_device->vme_int);
1636         mutex_init(&ca91cx42_device->vme_rmw);
1637
1638         ca91cx42_bridge->parent = &pdev->dev;
1639         strcpy(ca91cx42_bridge->name, driver_name);
1640
1641         /* Setup IRQ */
1642         retval = ca91cx42_irq_init(ca91cx42_bridge);
1643         if (retval != 0) {
1644                 dev_err(&pdev->dev, "Chip Initialization failed.\n");
1645                 goto err_irq;
1646         }
1647
1648         /* Add master windows to list */
1649         INIT_LIST_HEAD(&ca91cx42_bridge->master_resources);
1650         for (i = 0; i < CA91C142_MAX_MASTER; i++) {
1651                 master_image = kmalloc(sizeof(struct vme_master_resource),
1652                         GFP_KERNEL);
1653                 if (master_image == NULL) {
1654                         dev_err(&pdev->dev, "Failed to allocate memory for "
1655                         "master resource structure\n");
1656                         retval = -ENOMEM;
1657                         goto err_master;
1658                 }
1659                 master_image->parent = ca91cx42_bridge;
1660                 spin_lock_init(&master_image->lock);
1661                 master_image->locked = 0;
1662                 master_image->number = i;
1663                 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
1664                         VME_CRCSR | VME_USER1 | VME_USER2;
1665                 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1666                         VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1667                 master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64;
1668                 memset(&master_image->bus_resource, 0,
1669                         sizeof(struct resource));
1670                 master_image->kern_base  = NULL;
1671                 list_add_tail(&master_image->list,
1672                         &ca91cx42_bridge->master_resources);
1673         }
1674
1675         /* Add slave windows to list */
1676         INIT_LIST_HEAD(&ca91cx42_bridge->slave_resources);
1677         for (i = 0; i < CA91C142_MAX_SLAVE; i++) {
1678                 slave_image = kmalloc(sizeof(struct vme_slave_resource),
1679                         GFP_KERNEL);
1680                 if (slave_image == NULL) {
1681                         dev_err(&pdev->dev, "Failed to allocate memory for "
1682                         "slave resource structure\n");
1683                         retval = -ENOMEM;
1684                         goto err_slave;
1685                 }
1686                 slave_image->parent = ca91cx42_bridge;
1687                 mutex_init(&slave_image->mtx);
1688                 slave_image->locked = 0;
1689                 slave_image->number = i;
1690                 slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 |
1691                         VME_USER2;
1692
1693                 /* Only windows 0 and 4 support A16 */
1694                 if (i == 0 || i == 4)
1695                         slave_image->address_attr |= VME_A16;
1696
1697                 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1698                         VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1699                 list_add_tail(&slave_image->list,
1700                         &ca91cx42_bridge->slave_resources);
1701         }
1702
1703         /* Add dma engines to list */
1704         INIT_LIST_HEAD(&ca91cx42_bridge->dma_resources);
1705         for (i = 0; i < CA91C142_MAX_DMA; i++) {
1706                 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
1707                         GFP_KERNEL);
1708                 if (dma_ctrlr == NULL) {
1709                         dev_err(&pdev->dev, "Failed to allocate memory for "
1710                         "dma resource structure\n");
1711                         retval = -ENOMEM;
1712                         goto err_dma;
1713                 }
1714                 dma_ctrlr->parent = ca91cx42_bridge;
1715                 mutex_init(&dma_ctrlr->mtx);
1716                 dma_ctrlr->locked = 0;
1717                 dma_ctrlr->number = i;
1718                 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
1719                         VME_DMA_MEM_TO_VME;
1720                 INIT_LIST_HEAD(&dma_ctrlr->pending);
1721                 INIT_LIST_HEAD(&dma_ctrlr->running);
1722                 list_add_tail(&dma_ctrlr->list,
1723                         &ca91cx42_bridge->dma_resources);
1724         }
1725
1726         /* Add location monitor to list */
1727         INIT_LIST_HEAD(&ca91cx42_bridge->lm_resources);
1728         lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
1729         if (lm == NULL) {
1730                 dev_err(&pdev->dev, "Failed to allocate memory for "
1731                 "location monitor resource structure\n");
1732                 retval = -ENOMEM;
1733                 goto err_lm;
1734         }
1735         lm->parent = ca91cx42_bridge;
1736         mutex_init(&lm->mtx);
1737         lm->locked = 0;
1738         lm->number = 1;
1739         lm->monitors = 4;
1740         list_add_tail(&lm->list, &ca91cx42_bridge->lm_resources);
1741
1742         ca91cx42_bridge->slave_get = ca91cx42_slave_get;
1743         ca91cx42_bridge->slave_set = ca91cx42_slave_set;
1744         ca91cx42_bridge->master_get = ca91cx42_master_get;
1745         ca91cx42_bridge->master_set = ca91cx42_master_set;
1746         ca91cx42_bridge->master_read = ca91cx42_master_read;
1747         ca91cx42_bridge->master_write = ca91cx42_master_write;
1748         ca91cx42_bridge->master_rmw = ca91cx42_master_rmw;
1749         ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add;
1750         ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec;
1751         ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty;
1752         ca91cx42_bridge->irq_set = ca91cx42_irq_set;
1753         ca91cx42_bridge->irq_generate = ca91cx42_irq_generate;
1754         ca91cx42_bridge->lm_set = ca91cx42_lm_set;
1755         ca91cx42_bridge->lm_get = ca91cx42_lm_get;
1756         ca91cx42_bridge->lm_attach = ca91cx42_lm_attach;
1757         ca91cx42_bridge->lm_detach = ca91cx42_lm_detach;
1758         ca91cx42_bridge->slot_get = ca91cx42_slot_get;
1759
1760         data = ioread32(ca91cx42_device->base + MISC_CTL);
1761         dev_info(&pdev->dev, "Board is%s the VME system controller\n",
1762                 (data & CA91CX42_MISC_CTL_SYSCON) ? "" : " not");
1763         dev_info(&pdev->dev, "Slot ID is %d\n",
1764                 ca91cx42_slot_get(ca91cx42_bridge));
1765
1766         if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev))
1767                 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
1768
1769         /* Need to save ca91cx42_bridge pointer locally in link list for use in
1770          * ca91cx42_remove()
1771          */
1772         retval = vme_register_bridge(ca91cx42_bridge);
1773         if (retval != 0) {
1774                 dev_err(&pdev->dev, "Chip Registration failed.\n");
1775                 goto err_reg;
1776         }
1777
1778         pci_set_drvdata(pdev, ca91cx42_bridge);
1779
1780         return 0;
1781
1782 err_reg:
1783         ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1784 err_lm:
1785         /* resources are stored in link list */
1786         list_for_each(pos, &ca91cx42_bridge->lm_resources) {
1787                 lm = list_entry(pos, struct vme_lm_resource, list);
1788                 list_del(pos);
1789                 kfree(lm);
1790         }
1791 err_dma:
1792         /* resources are stored in link list */
1793         list_for_each(pos, &ca91cx42_bridge->dma_resources) {
1794                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1795                 list_del(pos);
1796                 kfree(dma_ctrlr);
1797         }
1798 err_slave:
1799         /* resources are stored in link list */
1800         list_for_each(pos, &ca91cx42_bridge->slave_resources) {
1801                 slave_image = list_entry(pos, struct vme_slave_resource, list);
1802                 list_del(pos);
1803                 kfree(slave_image);
1804         }
1805 err_master:
1806         /* resources are stored in link list */
1807         list_for_each(pos, &ca91cx42_bridge->master_resources) {
1808                 master_image = list_entry(pos, struct vme_master_resource,
1809                         list);
1810                 list_del(pos);
1811                 kfree(master_image);
1812         }
1813
1814         ca91cx42_irq_exit(ca91cx42_device, pdev);
1815 err_irq:
1816 err_test:
1817         iounmap(ca91cx42_device->base);
1818 err_remap:
1819         pci_release_regions(pdev);
1820 err_resource:
1821         pci_disable_device(pdev);
1822 err_enable:
1823         kfree(ca91cx42_device);
1824 err_driver:
1825         kfree(ca91cx42_bridge);
1826 err_struct:
1827         return retval;
1828
1829 }
1830
1831 static void ca91cx42_remove(struct pci_dev *pdev)
1832 {
1833         struct list_head *pos = NULL;
1834         struct vme_master_resource *master_image;
1835         struct vme_slave_resource *slave_image;
1836         struct vme_dma_resource *dma_ctrlr;
1837         struct vme_lm_resource *lm;
1838         struct ca91cx42_driver *bridge;
1839         struct vme_bridge *ca91cx42_bridge = pci_get_drvdata(pdev);
1840
1841         bridge = ca91cx42_bridge->driver_priv;
1842
1843
1844         /* Turn off Ints */
1845         iowrite32(0, bridge->base + LINT_EN);
1846
1847         /* Turn off the windows */
1848         iowrite32(0x00800000, bridge->base + LSI0_CTL);
1849         iowrite32(0x00800000, bridge->base + LSI1_CTL);
1850         iowrite32(0x00800000, bridge->base + LSI2_CTL);
1851         iowrite32(0x00800000, bridge->base + LSI3_CTL);
1852         iowrite32(0x00800000, bridge->base + LSI4_CTL);
1853         iowrite32(0x00800000, bridge->base + LSI5_CTL);
1854         iowrite32(0x00800000, bridge->base + LSI6_CTL);
1855         iowrite32(0x00800000, bridge->base + LSI7_CTL);
1856         iowrite32(0x00F00000, bridge->base + VSI0_CTL);
1857         iowrite32(0x00F00000, bridge->base + VSI1_CTL);
1858         iowrite32(0x00F00000, bridge->base + VSI2_CTL);
1859         iowrite32(0x00F00000, bridge->base + VSI3_CTL);
1860         iowrite32(0x00F00000, bridge->base + VSI4_CTL);
1861         iowrite32(0x00F00000, bridge->base + VSI5_CTL);
1862         iowrite32(0x00F00000, bridge->base + VSI6_CTL);
1863         iowrite32(0x00F00000, bridge->base + VSI7_CTL);
1864
1865         vme_unregister_bridge(ca91cx42_bridge);
1866
1867         ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1868
1869         /* resources are stored in link list */
1870         list_for_each(pos, &ca91cx42_bridge->lm_resources) {
1871                 lm = list_entry(pos, struct vme_lm_resource, list);
1872                 list_del(pos);
1873                 kfree(lm);
1874         }
1875
1876         /* resources are stored in link list */
1877         list_for_each(pos, &ca91cx42_bridge->dma_resources) {
1878                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1879                 list_del(pos);
1880                 kfree(dma_ctrlr);
1881         }
1882
1883         /* resources are stored in link list */
1884         list_for_each(pos, &ca91cx42_bridge->slave_resources) {
1885                 slave_image = list_entry(pos, struct vme_slave_resource, list);
1886                 list_del(pos);
1887                 kfree(slave_image);
1888         }
1889
1890         /* resources are stored in link list */
1891         list_for_each(pos, &ca91cx42_bridge->master_resources) {
1892                 master_image = list_entry(pos, struct vme_master_resource,
1893                         list);
1894                 list_del(pos);
1895                 kfree(master_image);
1896         }
1897
1898         ca91cx42_irq_exit(bridge, pdev);
1899
1900         iounmap(bridge->base);
1901
1902         pci_release_regions(pdev);
1903
1904         pci_disable_device(pdev);
1905
1906         kfree(ca91cx42_bridge);
1907 }
1908
1909 static void __exit ca91cx42_exit(void)
1910 {
1911         pci_unregister_driver(&ca91cx42_driver);
1912 }
1913
1914 MODULE_PARM_DESC(geoid, "Override geographical addressing");
1915 module_param(geoid, int, 0);
1916
1917 MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge");
1918 MODULE_LICENSE("GPL");
1919
1920 module_init(ca91cx42_init);
1921 module_exit(ca91cx42_exit);