drivers/staging/tidspbridge/hw/MMURegAcM.h

   1 /*
   2  * MMURegAcM.h
   3  *
   4  * DSP-BIOS Bridge driver support functions for TI OMAP processors.
   5  *
   6  * Copyright (C) 2007 Texas Instruments, Inc.
   7  *
   8  * This package is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  13  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  14  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  15  */
  16
  17 #ifndef _MMU_REG_ACM_H
  18 #define _MMU_REG_ACM_H
  19
  20 #include <linux/io.h>
  21 #include <EasiGlobal.h>
  22
  23 #include "MMUAccInt.h"
  24
  25 #if defined(USE_LEVEL_1_MACROS)
  26
  27 #define MMUMMU_SYSCONFIG_READ_REGISTER32(base_address)\
  28     (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_READ_REGISTER32),\
  29       __raw_readl((base_address)+MMU_MMU_SYSCONFIG_OFFSET))
  30
  31 #define MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32(base_address, value)\
  32 {\
  33     const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
  34     register u32 data = __raw_readl((base_address)+offset);\
  35     register u32 new_value = (value);\
  36     _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32);\
  37     data &= ~(MMU_MMU_SYSCONFIG_IDLE_MODE_MASK);\
  38     new_value <<= MMU_MMU_SYSCONFIG_IDLE_MODE_OFFSET;\
  39     new_value &= MMU_MMU_SYSCONFIG_IDLE_MODE_MASK;\
  40     new_value |= data;\
  41     __raw_writel(new_value, base_address+offset);\
  42 }
  43
  44 #define MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32(base_address, value)\
  45 {\
  46     const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
  47     register u32 data = __raw_readl((base_address)+offset);\
  48     register u32 new_value = (value);\
  49     _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32);\
  50     data &= ~(MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK);\
  51     new_value <<= MMU_MMU_SYSCONFIG_AUTO_IDLE_OFFSET;\
  52     new_value &= MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK;\
  53     new_value |= data;\
  54     __raw_writel(new_value, base_address+offset);\
  55 }
  56
  57 #define MMUMMU_IRQSTATUS_READ_REGISTER32(base_address)\
  58     (_DEBUG_LEVEL1_EASI(easil1_mmummu_irqstatus_read_register32),\
  59       __raw_readl((base_address)+MMU_MMU_IRQSTATUS_OFFSET))
  60
  61 #define MMUMMU_IRQSTATUS_WRITE_REGISTER32(base_address, value)\
  62 {\
  63     const u32 offset = MMU_MMU_IRQSTATUS_OFFSET;\
  64     register u32 new_value = (value);\
  65     _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQSTATUS_WRITE_REGISTER32);\
  66     __raw_writel(new_value, (base_address)+offset);\
  67 }
  68
  69 #define MMUMMU_IRQENABLE_READ_REGISTER32(base_address)\
  70     (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQENABLE_READ_REGISTER32),\
  71       __raw_readl((base_address)+MMU_MMU_IRQENABLE_OFFSET))
  72
  73 #define MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, value)\
  74 {\
  75     const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\
  76     register u32 new_value = (value);\
  77     _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQENABLE_WRITE_REGISTER32);\
  78     __raw_writel(new_value, (base_address)+offset);\
  79 }
  80
  81 #define MMUMMU_WALKING_STTWL_RUNNING_READ32(base_address)\
  82     (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_WALKING_STTWL_RUNNING_READ32),\
  83       (((__raw_readl(((base_address)+(MMU_MMU_WALKING_ST_OFFSET))))\
  84       & MMU_MMU_WALKING_ST_TWL_RUNNING_MASK) >>\
  85       MMU_MMU_WALKING_ST_TWL_RUNNING_OFFSET))
  86
  87 #define MMUMMU_CNTLTWL_ENABLE_READ32(base_address)\
  88     (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLTWL_ENABLE_READ32),\
  89       (((__raw_readl(((base_address)+(MMU_MMU_CNTL_OFFSET)))) &\
  90       MMU_MMU_CNTL_TWL_ENABLE_MASK) >>\
  91       MMU_MMU_CNTL_TWL_ENABLE_OFFSET))
  92
  93 #define MMUMMU_CNTLTWL_ENABLE_WRITE32(base_address, value)\
  94 {\
  95     const u32 offset = MMU_MMU_CNTL_OFFSET;\
  96     register u32 data = __raw_readl((base_address)+offset);\
  97     register u32 new_value = (value);\
  98     _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLTWL_ENABLE_WRITE32);\
  99     data &= ~(MMU_MMU_CNTL_TWL_ENABLE_MASK);\
 100     new_value <<= MMU_MMU_CNTL_TWL_ENABLE_OFFSET;\
 101     new_value &= MMU_MMU_CNTL_TWL_ENABLE_MASK;\
 102     new_value |= data;\
 103     __raw_writel(new_value, base_address+offset);\
 104 }
 105
 106 #define MMUMMU_CNTLMMU_ENABLE_WRITE32(base_address, value)\
 107 {\
 108     const u32 offset = MMU_MMU_CNTL_OFFSET;\
 109     register u32 data = __raw_readl((base_address)+offset);\
 110     register u32 new_value = (value);\
 111     _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLMMU_ENABLE_WRITE32);\
 112     data &= ~(MMU_MMU_CNTL_MMU_ENABLE_MASK);\
 113     new_value <<= MMU_MMU_CNTL_MMU_ENABLE_OFFSET;\
 114     new_value &= MMU_MMU_CNTL_MMU_ENABLE_MASK;\
 115     new_value |= data;\
 116     __raw_writel(new_value, base_address+offset);\
 117 }
 118
 119 #define MMUMMU_FAULT_AD_READ_REGISTER32(base_address)\
 120     (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_FAULT_AD_READ_REGISTER32),\
 121       __raw_readl((base_address)+MMU_MMU_FAULT_AD_OFFSET))
 122
 123 #define MMUMMU_TTB_WRITE_REGISTER32(base_address, value)\
 124 {\
 125     const u32 offset = MMU_MMU_TTB_OFFSET;\
 126     register u32 new_value = (value);\
 127     _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_TTB_WRITE_REGISTER32);\
 128     __raw_writel(new_value, (base_address)+offset);\
 129 }
 130
 131 #define MMUMMU_LOCK_READ_REGISTER32(base_address)\
 132     (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_READ_REGISTER32),\
 133       __raw_readl((base_address)+MMU_MMU_LOCK_OFFSET))
 134
 135 #define MMUMMU_LOCK_WRITE_REGISTER32(base_address, value)\
 136 {\
 137     const u32 offset = MMU_MMU_LOCK_OFFSET;\
 138     register u32 new_value = (value);\
 139     _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_WRITE_REGISTER32);\
 140     __raw_writel(new_value, (base_address)+offset);\
 141 }
 142
 143 #define MMUMMU_LOCK_BASE_VALUE_READ32(base_address)\
 144     (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_BASE_VALUE_READ32),\
 145       (((__raw_readl(((base_address)+(MMU_MMU_LOCK_OFFSET)))) &\
 146       MMU_MMU_LOCK_BASE_VALUE_MASK) >>\
 147       MMU_MMU_LOCK_BASE_VALUE_OFFSET))
 148
 149 #define MMUMMU_LOCK_BASE_VALUE_WRITE32(base_address, value)\
 150 {\
 151     const u32 offset = MMU_MMU_LOCK_OFFSET;\
 152     register u32 data = __raw_readl((base_address)+offset);\
 153     register u32 new_value = (value);\
 154     _DEBUG_LEVEL1_EASI(easil1_mmummu_lock_base_value_write32);\
 155     data &= ~(MMU_MMU_LOCK_BASE_VALUE_MASK);\
 156     new_value <<= MMU_MMU_LOCK_BASE_VALUE_OFFSET;\
 157     new_value &= MMU_MMU_LOCK_BASE_VALUE_MASK;\
 158     new_value |= data;\
 159     __raw_writel(new_value, base_address+offset);\
 160 }
 161
 162 #define MMUMMU_LOCK_CURRENT_VICTIM_READ32(base_address)\
 163     (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_READ32),\
 164       (((__raw_readl(((base_address)+(MMU_MMU_LOCK_OFFSET)))) &\
 165       MMU_MMU_LOCK_CURRENT_VICTIM_MASK) >>\
 166       MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET))
 167
 168 #define MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(base_address, value)\
 169 {\
 170     const u32 offset = MMU_MMU_LOCK_OFFSET;\
 171     register u32 data = __raw_readl((base_address)+offset);\
 172     register u32 new_value = (value);\
 173     _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_WRITE32);\
 174     data &= ~(MMU_MMU_LOCK_CURRENT_VICTIM_MASK);\
 175     new_value <<= MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET;\
 176     new_value &= MMU_MMU_LOCK_CURRENT_VICTIM_MASK;\
 177     new_value |= data;\
 178     __raw_writel(new_value, base_address+offset);\
 179 }
 180
 181 #define MMUMMU_LOCK_CURRENT_VICTIM_SET32(var, value)\
 182     (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_SET32),\
 183       (((var) & ~(MMU_MMU_LOCK_CURRENT_VICTIM_MASK)) |\
 184       (((value) << MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET) &\
 185       MMU_MMU_LOCK_CURRENT_VICTIM_MASK)))
 186
 187 #define MMUMMU_LD_TLB_READ_REGISTER32(base_address)\
 188     (_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LD_TLB_READ_REGISTER32),\
 189       __raw_readl((base_address)+MMU_MMU_LD_TLB_OFFSET))
 190
 191 #define MMUMMU_LD_TLB_WRITE_REGISTER32(base_address, value)\
 192 {\
 193     const u32 offset = MMU_MMU_LD_TLB_OFFSET;\
 194     register u32 new_value = (value);\
 195     _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LD_TLB_WRITE_REGISTER32);\
 196     __raw_writel(new_value, (base_address)+offset);\
 197 }
 198
 199 #define MMUMMU_CAM_WRITE_REGISTER32(base_address, value)\
 200 {\
 201     const u32 offset = MMU_MMU_CAM_OFFSET;\
 202     register u32 new_value = (value);\
 203     _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CAM_WRITE_REGISTER32);\
 204     __raw_writel(new_value, (base_address)+offset);\
 205 }
 206
 207 #define MMUMMU_RAM_WRITE_REGISTER32(base_address, value)\
 208 {\
 209     const u32 offset = MMU_MMU_RAM_OFFSET;\
 210     register u32 new_value = (value);\
 211     _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_RAM_WRITE_REGISTER32);\
 212     __raw_writel(new_value, (base_address)+offset);\
 213 }
 214
 215 #define MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32(base_address, value)\
 216 {\
 217     const u32 offset = MMU_MMU_FLUSH_ENTRY_OFFSET;\
 218     register u32 new_value = (value);\
 219     _DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32);\
 220     __raw_writel(new_value, (base_address)+offset);\
 221 }
 222
 223 #endif /* USE_LEVEL_1_MACROS */
 224
 225 #endif /* _MMU_REG_ACM_H */