drivers/staging/tidspbridge/core/tiomap3430.c

   1 /*
   2  * tiomap.c
   3  *
   4  * DSP-BIOS Bridge driver support functions for TI OMAP processors.
   5  *
   6  * Processor Manager Driver for TI OMAP3430 EVM.
   7  *
   8  * Copyright (C) 2005-2006 Texas Instruments, Inc.
   9  *
  10  * This package is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  15  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  16  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  17  */
  18
  19 #include <plat/dsp.h>
  20
  21 #include <linux/types.h>
  22 /*  ----------------------------------- Host OS */
  23 #include <dspbridge/host_os.h>
  24 #include <linux/mm.h>
  25 #include <linux/mmzone.h>
  26 #include <plat/control.h>
  27
  28 /*  ----------------------------------- DSP/BIOS Bridge */
  29 #include <dspbridge/dbdefs.h>
  30
  31 /*  ----------------------------------- Trace & Debug */
  32 #include <dspbridge/dbc.h>
  33
  34 /*  ----------------------------------- OS Adaptation Layer */
  35 #include <dspbridge/drv.h>
  36 #include <dspbridge/sync.h>
  37
  38 /*  ----------------------------------- Link Driver */
  39 #include <dspbridge/dspdefs.h>
  40 #include <dspbridge/dspchnl.h>
  41 #include <dspbridge/dspdeh.h>
  42 #include <dspbridge/dspio.h>
  43 #include <dspbridge/dspmsg.h>
  44 #include <dspbridge/pwr.h>
  45 #include <dspbridge/io_sm.h>
  46
  47 /*  ----------------------------------- Platform Manager */
  48 #include <dspbridge/dev.h>
  49 #include <dspbridge/dspapi.h>
  50 #include <dspbridge/wdt.h>
  51
  52 /*  ----------------------------------- Local */
  53 #include "_tiomap.h"
  54 #include "_tiomap_pwr.h"
  55 #include "tiomap_io.h"
  56
  57 /* Offset in shared mem to write to in order to synchronize start with DSP */
  58 #define SHMSYNCOFFSET 4         /* GPP byte offset */
  59
  60 #define BUFFERSIZE 1024
  61
  62 #define TIHELEN_ACKTIMEOUT  10000
  63
  64 #define MMU_SECTION_ADDR_MASK    0xFFF00000
  65 #define MMU_SSECTION_ADDR_MASK   0xFF000000
  66 #define MMU_LARGE_PAGE_MASK      0xFFFF0000
  67 #define MMU_SMALL_PAGE_MASK      0xFFFFF000
  68 #define OMAP3_IVA2_BOOTADDR_MASK 0xFFFFFC00
  69 #define PAGES_II_LVL_TABLE   512
  70
  71 /* Forward Declarations: */
  72 static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt);
  73 static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
  74                                   u8 *host_buff,
  75                                   u32 dsp_addr, u32 ul_num_bytes,
  76                                   u32 mem_type);
  77 static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
  78                                    u32 dsp_addr);
  79 static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
  80                                     int *board_state);
  81 static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt);
  82 static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
  83                                    u8 *host_buff,
  84                                    u32 dsp_addr, u32 ul_num_bytes,
  85                                    u32 mem_type);
  86 static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
  87                                     u32 brd_state);
  88 static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
  89                                    u32 dsp_dest_addr, u32 dsp_src_addr,
  90                                    u32 ul_num_bytes, u32 mem_type);
  91 static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
  92                                     u8 *host_buff, u32 dsp_addr,
  93                                     u32 ul_num_bytes, u32 mem_type);
  94 static int bridge_dev_create(struct bridge_dev_context
  95                                         **dev_cntxt,
  96                                         struct dev_object *hdev_obj,
  97                                         struct cfg_hostres *config_param);
  98 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
  99                                   u32 dw_cmd, void *pargs);
 100 static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt);
 101 bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr);
 102
 103 /*
 104  *  This Bridge driver's function interface table.
 105  */
 106 static struct bridge_drv_interface drv_interface_fxns = {
 107         /* Bridge API ver. for which this bridge driver is built. */
 108         BRD_API_MAJOR_VERSION,
 109         BRD_API_MINOR_VERSION,
 110         bridge_dev_create,
 111         bridge_dev_destroy,
 112         bridge_dev_ctrl,
 113         bridge_brd_monitor,
 114         bridge_brd_start,
 115         bridge_brd_stop,
 116         bridge_brd_status,
 117         bridge_brd_read,
 118         bridge_brd_write,
 119         bridge_brd_set_state,
 120         bridge_brd_mem_copy,
 121         bridge_brd_mem_write,
 122         /* The following CHNL functions are provided by chnl_io.lib: */
 123         bridge_chnl_create,
 124         bridge_chnl_destroy,
 125         bridge_chnl_open,
 126         bridge_chnl_close,
 127         bridge_chnl_add_io_req,
 128         bridge_chnl_get_ioc,
 129         bridge_chnl_cancel_io,
 130         bridge_chnl_flush_io,
 131         bridge_chnl_get_info,
 132         bridge_chnl_get_mgr_info,
 133         bridge_chnl_idle,
 134         bridge_chnl_register_notify,
 135         /* The following IO functions are provided by chnl_io.lib: */
 136         bridge_io_create,
 137         bridge_io_destroy,
 138         bridge_io_on_loaded,
 139         bridge_io_get_proc_load,
 140         /* The following msg_ctrl functions are provided by chnl_io.lib: */
 141         bridge_msg_create,
 142         bridge_msg_create_queue,
 143         bridge_msg_delete,
 144         bridge_msg_delete_queue,
 145         bridge_msg_get,
 146         bridge_msg_put,
 147         bridge_msg_register_notify,
 148         bridge_msg_set_queue_id,
 149 };
 150
 151 /*
 152  *  ======== bridge_drv_entry ========
 153  *  purpose:
 154  *      Bridge Driver entry point.
 155  */
 156 void bridge_drv_entry(struct bridge_drv_interface **drv_intf,
 157                    const char *driver_file_name)
 158 {
 159
 160         DBC_REQUIRE(driver_file_name != NULL);
 161
 162         io_sm_init();           /* Initialization of io_sm module */
 163
 164         if (strcmp(driver_file_name, "UMA") == 0)
 165                 *drv_intf = &drv_interface_fxns;
 166         else
 167                 dev_dbg(bridge, "%s Unknown Bridge file name", __func__);
 168
 169 }
 170
 171 /*
 172  *  ======== bridge_brd_monitor ========
 173  *  purpose:
 174  *      This bridge_brd_monitor puts DSP into a Loadable state.
 175  *      i.e Application can load and start the device.
 176  *
 177  *  Preconditions:
 178  *      Device in 'OFF' state.
 179  */
 180 static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt)
 181 {
 182         struct bridge_dev_context *dev_context = dev_ctxt;
 183         u32 temp;
 184         struct omap_dsp_platform_data *pdata =
 185                 omap_dspbridge_dev->dev.platform_data;
 186
 187         temp = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
 188                                         OMAP_POWERSTATEST_MASK;
 189         if (!(temp & 0x02)) {
 190                 /* IVA2 is not in ON state */
 191                 /* Read and set PM_PWSTCTRL_IVA2  to ON */
 192                 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
 193                         PWRDM_POWER_ON, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
 194                 /* Set the SW supervised state transition */
 195                 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP,
 196                                         OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 197
 198                 /* Wait until the state has moved to ON */
 199                 while ((*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
 200                                                 OMAP_INTRANSITION_MASK)
 201                         ;
 202                 /* Disable Automatic transition */
 203                 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_DISABLE_AUTO,
 204                                         OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 205         }
 206
 207         dsp_clk_enable(DSP_CLK_IVA2);
 208
 209         /* set the device state to IDLE */
 210         dev_context->dw_brd_state = BRD_IDLE;
 211
 212         return 0;
 213 }
 214
 215 /*
 216  *  ======== bridge_brd_read ========
 217  *  purpose:
 218  *      Reads buffers for DSP memory.
 219  */
 220 static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
 221                                   u8 *host_buff, u32 dsp_addr,
 222                                   u32 ul_num_bytes, u32 mem_type)
 223 {
 224         int status = 0;
 225         struct bridge_dev_context *dev_context = dev_ctxt;
 226         u32 offset;
 227         u32 dsp_base_addr = dev_ctxt->dw_dsp_base_addr;
 228
 229         if (dsp_addr < dev_context->dw_dsp_start_add) {
 230                 status = -EPERM;
 231                 return status;
 232         }
 233         /* change here to account for the 3 bands of the DSP internal memory */
 234         if ((dsp_addr - dev_context->dw_dsp_start_add) <
 235             dev_context->dw_internal_size) {
 236                 offset = dsp_addr - dev_context->dw_dsp_start_add;
 237         } else {
 238                 status = read_ext_dsp_data(dev_context, host_buff, dsp_addr,
 239                                            ul_num_bytes, mem_type);
 240                 return status;
 241         }
 242         /* copy the data from  DSP memory, */
 243         memcpy(host_buff, (void *)(dsp_base_addr + offset), ul_num_bytes);
 244         return status;
 245 }
 246
 247 /*
 248  *  ======== bridge_brd_set_state ========
 249  *  purpose:
 250  *      This routine updates the Board status.
 251  */
 252 static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
 253                                     u32 brd_state)
 254 {
 255         int status = 0;
 256         struct bridge_dev_context *dev_context = dev_ctxt;
 257
 258         dev_context->dw_brd_state = brd_state;
 259         return status;
 260 }
 261
 262 /*
 263  *  ======== bridge_brd_start ========
 264  *  purpose:
 265  *      Initializes DSP MMU and Starts DSP.
 266  *
 267  *  Preconditions:
 268  *  a) DSP domain is 'ACTIVE'.
 269  *  b) DSP_RST1 is asserted.
 270  *  b) DSP_RST2 is released.
 271  */
 272 static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
 273                                    u32 dsp_addr)
 274 {
 275         int status = 0;
 276         struct bridge_dev_context *dev_context = dev_ctxt;
 277         struct iommu *mmu = NULL;
 278         struct shm_segs *sm_sg;
 279         int l4_i = 0, tlb_i = 0;
 280         u32 sg0_da = 0, sg1_da = 0;
 281         struct bridge_ioctl_extproc *tlb = dev_context->atlb_entry;
 282         u32 dw_sync_addr = 0;
 283         u32 ul_shm_base;        /* Gpp Phys SM base addr(byte) */
 284         u32 ul_shm_base_virt;   /* Dsp Virt SM base addr */
 285         u32 ul_tlb_base_virt;   /* Base of MMU TLB entry */
 286         /* Offset of shm_base_virt from tlb_base_virt */
 287         u32 ul_shm_offset_virt;
 288         struct cfg_hostres *resources = NULL;
 289         u32 temp;
 290         u32 ul_dsp_clk_rate;
 291         u32 ul_dsp_clk_addr;
 292         u32 ul_bios_gp_timer;
 293         u32 clk_cmd;
 294         struct io_mgr *hio_mgr;
 295         u32 ul_load_monitor_timer;
 296         struct omap_dsp_platform_data *pdata =
 297                 omap_dspbridge_dev->dev.platform_data;
 298
 299         /* The device context contains all the mmu setup info from when the
 300          * last dsp base image was loaded. The first entry is always
 301          * SHMMEM base. */
 302         /* Get SHM_BEG - convert to byte address */
 303         (void)dev_get_symbol(dev_context->hdev_obj, SHMBASENAME,
 304                              &ul_shm_base_virt);
 305         ul_shm_base_virt *= DSPWORDSIZE;
 306         DBC_ASSERT(ul_shm_base_virt != 0);
 307         /* DSP Virtual address */
 308         ul_tlb_base_virt = dev_context->sh_s.seg0_da;
 309         DBC_ASSERT(ul_tlb_base_virt <= ul_shm_base_virt);
 310         ul_shm_offset_virt =
 311             ul_shm_base_virt - (ul_tlb_base_virt * DSPWORDSIZE);
 312         /* Kernel logical address */
 313         ul_shm_base = dev_context->sh_s.seg0_va + ul_shm_offset_virt;
 314
 315         DBC_ASSERT(ul_shm_base != 0);
 316         /* 2nd wd is used as sync field */
 317         dw_sync_addr = ul_shm_base + SHMSYNCOFFSET;
 318         /* Write a signature into the shm base + offset; this will
 319          * get cleared when the DSP program starts. */
 320         if ((ul_shm_base_virt == 0) || (ul_shm_base == 0)) {
 321                 pr_err("%s: Illegal SM base\n", __func__);
 322                 status = -EPERM;
 323         } else
 324                 __raw_writel(0xffffffff, dw_sync_addr);
 325
 326         if (!status) {
 327                 resources = dev_context->resources;
 328                 if (!resources)
 329                         status = -EPERM;
 330
 331                 /* Assert RST1 i.e only the RST only for DSP megacell */
 332                 if (!status) {
 333                         (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
 334                                         OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD,
 335                                         OMAP2_RM_RSTCTRL);
 336                         /* Mask address with 1K for compatibility */
 337                         __raw_writel(dsp_addr & OMAP3_IVA2_BOOTADDR_MASK,
 338                                         OMAP343X_CTRL_REGADDR(
 339                                         OMAP343X_CONTROL_IVA2_BOOTADDR));
 340                         /*
 341                          * Set bootmode to self loop if dsp_debug flag is true
 342                          */
 343                         __raw_writel((dsp_debug) ? OMAP3_IVA2_BOOTMOD_IDLE : 0,
 344                                         OMAP343X_CTRL_REGADDR(
 345                                         OMAP343X_CONTROL_IVA2_BOOTMOD));
 346                 }
 347         }
 348
 349         if (!status) {
 350                 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
 351                                         OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 352                 mmu = dev_context->dsp_mmu;
 353                 if (mmu)
 354                         dsp_mmu_exit(mmu);
 355                 mmu = dsp_mmu_init();
 356                 if (IS_ERR(mmu)) {
 357                         dev_err(bridge, "dsp_mmu_init failed!\n");
 358                         dev_context->dsp_mmu = NULL;
 359                         status = (int)mmu;
 360                 }
 361         }
 362         if (!status) {
 363                 dev_context->dsp_mmu = mmu;
 364                 sm_sg = &dev_context->sh_s;
 365                 sg0_da = iommu_kmap(mmu, sm_sg->seg0_da, sm_sg->seg0_pa,
 366                         sm_sg->seg0_size, IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_32);
 367                 if (IS_ERR_VALUE(sg0_da)) {
 368                         status = (int)sg0_da;
 369                         sg0_da = 0;
 370                 }
 371         }
 372         if (!status) {
 373                 sg1_da = iommu_kmap(mmu, sm_sg->seg1_da, sm_sg->seg1_pa,
 374                         sm_sg->seg1_size, IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_32);
 375                 if (IS_ERR_VALUE(sg1_da)) {
 376                         status = (int)sg1_da;
 377                         sg1_da = 0;
 378                 }
 379         }
 380         if (!status) {
 381                 u32 da;
 382                 for (tlb_i = 0; tlb_i < BRDIOCTL_NUMOFMMUTLB; tlb_i++) {
 383                         if (!tlb[tlb_i].ul_gpp_pa)
 384                                 continue;
 385
 386                         dev_dbg(bridge, "IOMMU %d GppPa: 0x%x DspVa 0x%x Size"
 387                                 " 0x%x\n", tlb_i, tlb[tlb_i].ul_gpp_pa,
 388                                 tlb[tlb_i].ul_dsp_va, tlb[tlb_i].ul_size);
 389
 390                         da = iommu_kmap(mmu, tlb[tlb_i].ul_dsp_va,
 391                                 tlb[tlb_i].ul_gpp_pa, PAGE_SIZE,
 392                                 IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_32);
 393                         if (IS_ERR_VALUE(da)) {
 394                                 status = (int)da;
 395                                 break;
 396                         }
 397                 }
 398         }
 399         if (!status) {
 400                 u32 da;
 401                 l4_i = 0;
 402                 while (l4_peripheral_table[l4_i].phys_addr) {
 403                         da = iommu_kmap(mmu, l4_peripheral_table[l4_i].
 404                                 dsp_virt_addr, l4_peripheral_table[l4_i].
 405                                 phys_addr, PAGE_SIZE,
 406                                 IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_32);
 407                         if (IS_ERR_VALUE(da)) {
 408                                 status = (int)da;
 409                                 break;
 410                         }
 411                         l4_i++;
 412                 }
 413         }
 414
 415         /* Lock the above TLB entries and get the BIOS and load monitor timer
 416          * information */
 417         if (!status) {
 418                 /* Enable the BIOS clock */
 419                 (void)dev_get_symbol(dev_context->hdev_obj,
 420                                      BRIDGEINIT_BIOSGPTIMER, &ul_bios_gp_timer);
 421                 (void)dev_get_symbol(dev_context->hdev_obj,
 422                                      BRIDGEINIT_LOADMON_GPTIMER,
 423                                      &ul_load_monitor_timer);
 424
 425                 if (ul_load_monitor_timer != 0xFFFF) {
 426                         clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
 427                             ul_load_monitor_timer;
 428                         dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
 429                 } else {
 430                         dev_dbg(bridge, "Not able to get the symbol for Load "
 431                                 "Monitor Timer\n");
 432                 }
 433
 434                 if (ul_bios_gp_timer != 0xFFFF) {
 435                         clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
 436                             ul_bios_gp_timer;
 437                         dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
 438                 } else {
 439                         dev_dbg(bridge,
 440                                 "Not able to get the symbol for BIOS Timer\n");
 441                 }
 442
 443                 /* Set the DSP clock rate */
 444                 (void)dev_get_symbol(dev_context->hdev_obj,
 445                                      "_BRIDGEINIT_DSP_FREQ", &ul_dsp_clk_addr);
 446                 /*Set Autoidle Mode for IVA2 PLL */
 447                 (*pdata->dsp_cm_write)(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
 448                                 OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL);
 449
 450                 if ((unsigned int *)ul_dsp_clk_addr != NULL) {
 451                         /* Get the clock rate */
 452                         ul_dsp_clk_rate = dsp_clk_get_iva2_rate();
 453                         dev_dbg(bridge, "%s: DSP clock rate (KHZ): 0x%x \n",
 454                                 __func__, ul_dsp_clk_rate);
 455                         (void)bridge_brd_write(dev_context,
 456                                                (u8 *) &ul_dsp_clk_rate,
 457                                                ul_dsp_clk_addr, sizeof(u32), 0);
 458                 }
 459                 /*
 460                  * Enable Mailbox events and also drain any pending
 461                  * stale messages.
 462                  */
 463                 dev_context->mbox = omap_mbox_get("dsp");
 464                 if (IS_ERR(dev_context->mbox)) {
 465                         dev_context->mbox = NULL;
 466                         pr_err("%s: Failed to get dsp mailbox handle\n",
 467                                                                 __func__);
 468                         status = -EPERM;
 469                 }
 470
 471         }
 472         if (!status) {
 473                 dev_context->mbox->rxq->callback = (int (*)(void *))io_mbox_msg;
 474
 475 /*PM_IVA2GRPSEL_PER = 0xC0;*/
 476                 temp = readl(resources->dw_per_pm_base + 0xA8);
 477                 temp = (temp & 0xFFFFFF30) | 0xC0;
 478                 writel(temp, resources->dw_per_pm_base + 0xA8);
 479
 480 /*PM_MPUGRPSEL_PER &= 0xFFFFFF3F; */
 481                 temp = readl(resources->dw_per_pm_base + 0xA4);
 482                 temp = (temp & 0xFFFFFF3F);
 483                 writel(temp, resources->dw_per_pm_base + 0xA4);
 484 /*CM_SLEEPDEP_PER |= 0x04; */
 485                 temp = readl(resources->dw_per_base + 0x44);
 486                 temp = (temp & 0xFFFFFFFB) | 0x04;
 487                 writel(temp, resources->dw_per_base + 0x44);
 488
 489 /*CM_CLKSTCTRL_IVA2 = 0x00000003 -To Allow automatic transitions */
 490                 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_ENABLE_AUTO,
 491                                         OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 492
 493                 /* Let DSP go */
 494                 dev_dbg(bridge, "%s Unreset\n", __func__);
 495                 /* release the RST1, DSP starts executing now .. */
 496                 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK, 0,
 497                                         OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 498
 499                 dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", dw_sync_addr);
 500                 dev_dbg(bridge, "DSP c_int00 Address =  0x%x\n", dsp_addr);
 501                 if (dsp_debug)
 502                         while (__raw_readw(dw_sync_addr))
 503                                 ;;
 504
 505                 /* Wait for DSP to clear word in shared memory */
 506                 /* Read the Location */
 507                 if (!wait_for_start(dev_context, dw_sync_addr))
 508                         status = -ETIMEDOUT;
 509
 510                 /* Start wdt */
 511                 dsp_wdt_sm_set((void *)ul_shm_base);
 512                 dsp_wdt_enable(true);
 513
 514                 status = dev_get_io_mgr(dev_context->hdev_obj, &hio_mgr);
 515                 if (hio_mgr) {
 516                         io_sh_msetting(hio_mgr, SHM_OPPINFO, NULL);
 517                         /* Write the synchronization bit to indicate the
 518                          * completion of OPP table update to DSP
 519                          */
 520                         __raw_writel(0XCAFECAFE, dw_sync_addr);
 521
 522                         /* update board state */
 523                         dev_context->dw_brd_state = BRD_RUNNING;
 524                         return 0;
 525                 } else {
 526                         dev_context->dw_brd_state = BRD_UNKNOWN;
 527                 }
 528         }
 529
 530         while (tlb_i--) {
 531                 if (!tlb[tlb_i].ul_gpp_pa)
 532                         continue;
 533                 iommu_kunmap(mmu, tlb[tlb_i].ul_gpp_va);
 534         }
 535         while (l4_i--)
 536                 iommu_kunmap(mmu, l4_peripheral_table[l4_i].dsp_virt_addr);
 537         if (sg0_da)
 538                 iommu_kunmap(mmu, sg0_da);
 539         if (sg1_da)
 540                 iommu_kunmap(mmu, sg1_da);
 541         return status;
 542 }
 543
 544 /*
 545  *  ======== bridge_brd_stop ========
 546  *  purpose:
 547  *      Puts DSP in self loop.
 548  *
 549  *  Preconditions :
 550  *  a) None
 551  */
 552 static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt)
 553 {
 554         int status = 0;
 555         struct bridge_dev_context *dev_context = dev_ctxt;
 556         u32 dsp_pwr_state;
 557         int i;
 558         struct bridge_ioctl_extproc *tlb = dev_context->atlb_entry;
 559         struct omap_dsp_platform_data *pdata =
 560                 omap_dspbridge_dev->dev.platform_data;
 561
 562         if (dev_context->dw_brd_state == BRD_STOPPED)
 563                 return status;
 564
 565         /* as per TRM, it is advised to first drive the IVA2 to 'Standby' mode,
 566          * before turning off the clocks.. This is to ensure that there are no
 567          * pending L3 or other transactons from IVA2 */
 568         dsp_pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
 569                                         OMAP_POWERSTATEST_MASK;
 570         if (dsp_pwr_state != PWRDM_POWER_OFF) {
 571                 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
 572                                         OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 573                 sm_interrupt_dsp(dev_context, MBX_PM_DSPIDLE);
 574                 mdelay(10);
 575
 576                 /* IVA2 is not in OFF state */
 577                 /* Set PM_PWSTCTRL_IVA2  to OFF */
 578                 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
 579                         PWRDM_POWER_OFF, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
 580                 /* Set the SW supervised state transition for Sleep */
 581                 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_SLEEP,
 582                                         OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 583         }
 584         udelay(10);
 585         /* Release the Ext Base virtual Address as the next DSP Program
 586          * may have a different load address */
 587         if (dev_context->dw_dsp_ext_base_addr)
 588                 dev_context->dw_dsp_ext_base_addr = 0;
 589
 590         dev_context->dw_brd_state = BRD_STOPPED;        /* update board state */
 591
 592         dsp_wdt_enable(false);
 593
 594         /* Reset DSP */
 595         (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
 596                 OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 597
 598         /* Disable the mailbox interrupts */
 599         if (dev_context->mbox) {
 600                 omap_mbox_disable_irq(dev_context->mbox, IRQ_RX);
 601                 omap_mbox_put(dev_context->mbox);
 602                 dev_context->mbox = NULL;
 603         }
 604         if (dev_context->dsp_mmu) {
 605                 pr_err("Proc stop mmu if statement\n");
 606                 for (i = 0; i < BRDIOCTL_NUMOFMMUTLB; i++) {
 607                         if (!tlb[i].ul_gpp_pa)
 608                                 continue;
 609                         iommu_kunmap(dev_context->dsp_mmu, tlb[i].ul_gpp_va);
 610                 }
 611                 i = 0;
 612                 while (l4_peripheral_table[i].phys_addr) {
 613                         iommu_kunmap(dev_context->dsp_mmu,
 614                                 l4_peripheral_table[i].dsp_virt_addr);
 615                         i++;
 616                 }
 617                 iommu_kunmap(dev_context->dsp_mmu, dev_context->sh_s.seg0_da);
 618                 iommu_kunmap(dev_context->dsp_mmu, dev_context->sh_s.seg1_da);
 619                 dsp_mmu_exit(dev_context->dsp_mmu);
 620                 dev_context->dsp_mmu = NULL;
 621         }
 622         /* Reset IVA IOMMU*/
 623         (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK,
 624                 OMAP3430_RST2_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 625
 626         dsp_clock_disable_all(dev_context->dsp_per_clks);
 627         dsp_clk_disable(DSP_CLK_IVA2);
 628
 629         return status;
 630 }
 631
 632 /*
 633  *  ======== bridge_brd_status ========
 634  *      Returns the board status.
 635  */
 636 static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
 637                                     int *board_state)
 638 {
 639         struct bridge_dev_context *dev_context = dev_ctxt;
 640         *board_state = dev_context->dw_brd_state;
 641         return 0;
 642 }
 643
 644 /*
 645  *  ======== bridge_brd_write ========
 646  *      Copies the buffers to DSP internal or external memory.
 647  */
 648 static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
 649                                    u8 *host_buff, u32 dsp_addr,
 650                                    u32 ul_num_bytes, u32 mem_type)
 651 {
 652         int status = 0;
 653         struct bridge_dev_context *dev_context = dev_ctxt;
 654
 655         if (dsp_addr < dev_context->dw_dsp_start_add) {
 656                 status = -EPERM;
 657                 return status;
 658         }
 659         if ((dsp_addr - dev_context->dw_dsp_start_add) <
 660             dev_context->dw_internal_size) {
 661                 status = write_dsp_data(dev_ctxt, host_buff, dsp_addr,
 662                                         ul_num_bytes, mem_type);
 663         } else {
 664                 status = write_ext_dsp_data(dev_context, host_buff, dsp_addr,
 665                                             ul_num_bytes, mem_type, false);
 666         }
 667
 668         return status;
 669 }
 670
 671 /*
 672  *  ======== bridge_dev_create ========
 673  *      Creates a driver object. Puts DSP in self loop.
 674  */
 675 static int bridge_dev_create(struct bridge_dev_context
 676                                         **dev_cntxt,
 677                                         struct dev_object *hdev_obj,
 678                                         struct cfg_hostres *config_param)
 679 {
 680         int status = 0;
 681         struct bridge_dev_context *dev_context = NULL;
 682         s32 entry_ndx;
 683         struct cfg_hostres *resources = config_param;
 684         struct drv_data *drv_datap = dev_get_drvdata(bridge);
 685
 686         /* Allocate and initialize a data structure to contain the bridge driver
 687          *  state, which becomes the context for later calls into this driver */
 688         dev_context = kzalloc(sizeof(struct bridge_dev_context), GFP_KERNEL);
 689         if (!dev_context) {
 690                 status = -ENOMEM;
 691                 goto func_end;
 692         }
 693
 694         dev_context->dw_dsp_start_add = (u32) OMAP_GEM_BASE;
 695         dev_context->dw_self_loop = (u32) NULL;
 696         dev_context->dsp_per_clks = 0;
 697         dev_context->dw_internal_size = OMAP_DSP_SIZE;
 698         /*  Clear dev context MMU table entries.
 699          *  These get set on bridge_io_on_loaded() call after program loaded. */
 700         for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB; entry_ndx++) {
 701                 dev_context->atlb_entry[entry_ndx].ul_gpp_pa =
 702                     dev_context->atlb_entry[entry_ndx].ul_dsp_va = 0;
 703         }
 704         dev_context->dw_dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *)
 705                                                                  (config_param->
 706                                                                   dw_mem_base
 707                                                                   [3]),
 708                                                                  config_param->
 709                                                                  dw_mem_length
 710                                                                  [3]);
 711         if (!dev_context->dw_dsp_base_addr)
 712                 status = -EPERM;
 713
 714         if (!status) {
 715                 dev_context->tc_word_swap_on = drv_datap->tc_wordswapon;
 716                 dev_context->hdev_obj = hdev_obj;
 717                 /* Store current board state. */
 718                 dev_context->dw_brd_state = BRD_UNKNOWN;
 719                 dev_context->resources = resources;
 720                 dsp_clk_enable(DSP_CLK_IVA2);
 721                 bridge_brd_stop(dev_context);
 722                 /* Return ptr to our device state to the DSP API for storage */
 723                 *dev_cntxt = dev_context;
 724         } else {
 725                 kfree(dev_context);
 726         }
 727 func_end:
 728         return status;
 729 }
 730
 731 /*
 732  *  ======== bridge_dev_ctrl ========
 733  *      Receives device specific commands.
 734  */
 735 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
 736                                   u32 dw_cmd, void *pargs)
 737 {
 738         int status = 0;
 739         struct bridge_ioctl_extproc *pa_ext_proc =
 740                                         (struct bridge_ioctl_extproc *)pargs;
 741         s32 ndx;
 742
 743         switch (dw_cmd) {
 744         case BRDIOCTL_CHNLREAD:
 745                 break;
 746         case BRDIOCTL_CHNLWRITE:
 747                 break;
 748         case BRDIOCTL_SETMMUCONFIG:
 749                 /* store away dsp-mmu setup values for later use */
 750                 for (ndx = 0; ndx < BRDIOCTL_NUMOFMMUTLB; ndx++, pa_ext_proc++)
 751                         dev_context->atlb_entry[ndx] = *pa_ext_proc;
 752                 break;
 753         case BRDIOCTL_DEEPSLEEP:
 754         case BRDIOCTL_EMERGENCYSLEEP:
 755                 /* Currently only DSP Idle is supported Need to update for
 756                  * later releases */
 757                 status = sleep_dsp(dev_context, PWR_DEEPSLEEP, pargs);
 758                 break;
 759         case BRDIOCTL_WAKEUP:
 760                 status = wake_dsp(dev_context, pargs);
 761                 break;
 762         case BRDIOCTL_CLK_CTRL:
 763                 status = 0;
 764                 /* Looking For Baseport Fix for Clocks */
 765                 status = dsp_peripheral_clk_ctrl(dev_context, pargs);
 766                 break;
 767         case BRDIOCTL_PWR_HIBERNATE:
 768                 status = handle_hibernation_from_dsp(dev_context);
 769                 break;
 770         case BRDIOCTL_PRESCALE_NOTIFY:
 771                 status = pre_scale_dsp(dev_context, pargs);
 772                 break;
 773         case BRDIOCTL_POSTSCALE_NOTIFY:
 774                 status = post_scale_dsp(dev_context, pargs);
 775                 break;
 776         case BRDIOCTL_CONSTRAINT_REQUEST:
 777                 status = handle_constraints_set(dev_context, pargs);
 778                 break;
 779         default:
 780                 status = -EPERM;
 781                 break;
 782         }
 783         return status;
 784 }
 785
 786 /*
 787  *  ======== bridge_dev_destroy ========
 788  *      Destroys the driver object.
 789  */
 790 static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt)
 791 {
 792         int status = 0;
 793         struct bridge_dev_context *dev_context = (struct bridge_dev_context *)
 794             dev_ctxt;
 795         struct cfg_hostres *host_res;
 796         u32 shm_size;
 797         struct drv_data *drv_datap = dev_get_drvdata(bridge);
 798
 799         /* It should never happen */
 800         if (!dev_ctxt)
 801                 return -EFAULT;
 802
 803         /* first put the device to stop state */
 804         bridge_brd_stop(dev_context);
 805
 806         if (dev_context->resources) {
 807                 host_res = dev_context->resources;
 808                 shm_size = drv_datap->shm_size;
 809                 if (shm_size >= 0x10000) {
 810                         if ((host_res->dw_mem_base[1]) &&
 811                             (host_res->dw_mem_phys[1])) {
 812                                 mem_free_phys_mem((void *)
 813                                                   host_res->dw_mem_base
 814                                                   [1],
 815                                                   host_res->dw_mem_phys
 816                                                   [1], shm_size);
 817                         }
 818                 } else {
 819                         dev_dbg(bridge, "%s: Error getting shm size "
 820                                 "from registry: %x. Not calling "
 821                                 "mem_free_phys_mem\n", __func__,
 822                                 status);
 823                 }
 824                 host_res->dw_mem_base[1] = 0;
 825                 host_res->dw_mem_phys[1] = 0;
 826
 827                 if (host_res->dw_mem_base[0])
 828                         iounmap((void *)host_res->dw_mem_base[0]);
 829                 if (host_res->dw_mem_base[2])
 830                         iounmap((void *)host_res->dw_mem_base[2]);
 831                 if (host_res->dw_mem_base[3])
 832                         iounmap((void *)host_res->dw_mem_base[3]);
 833                 if (host_res->dw_mem_base[4])
 834                         iounmap((void *)host_res->dw_mem_base[4]);
 835                 if (host_res->dw_per_base)
 836                         iounmap(host_res->dw_per_base);
 837                 if (host_res->dw_per_pm_base)
 838                         iounmap((void *)host_res->dw_per_pm_base);
 839                 if (host_res->dw_core_pm_base)
 840                         iounmap((void *)host_res->dw_core_pm_base);
 841                 if (host_res->dw_sys_ctrl_base)
 842                         iounmap(host_res->dw_sys_ctrl_base);
 843
 844                 host_res->dw_mem_base[0] = (u32) NULL;
 845                 host_res->dw_mem_base[2] = (u32) NULL;
 846                 host_res->dw_mem_base[3] = (u32) NULL;
 847                 host_res->dw_mem_base[4] = (u32) NULL;
 848                 host_res->dw_sys_ctrl_base = NULL;
 849
 850                 kfree(host_res);
 851         }
 852
 853         /* Free the driver's device context: */
 854         kfree(drv_datap->base_img);
 855         kfree(drv_datap);
 856         dev_set_drvdata(bridge, NULL);
 857         kfree((void *)dev_ctxt);
 858         return status;
 859 }
 860
 861 static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
 862                                    u32 dsp_dest_addr, u32 dsp_src_addr,
 863                                    u32 ul_num_bytes, u32 mem_type)
 864 {
 865         int status = 0;
 866         u32 src_addr = dsp_src_addr;
 867         u32 dest_addr = dsp_dest_addr;
 868         u32 copy_bytes = 0;
 869         u32 total_bytes = ul_num_bytes;
 870         u8 host_buf[BUFFERSIZE];
 871         struct bridge_dev_context *dev_context = dev_ctxt;
 872         while (total_bytes > 0 && !status) {
 873                 copy_bytes =
 874                     total_bytes > BUFFERSIZE ? BUFFERSIZE : total_bytes;
 875                 /* Read from External memory */
 876                 status = read_ext_dsp_data(dev_ctxt, host_buf, src_addr,
 877                                            copy_bytes, mem_type);
 878                 if (!status) {
 879                         if (dest_addr < (dev_context->dw_dsp_start_add +
 880                                          dev_context->dw_internal_size)) {
 881                                 /* Write to Internal memory */
 882                                 status = write_dsp_data(dev_ctxt, host_buf,
 883                                                         dest_addr, copy_bytes,
 884                                                         mem_type);
 885                         } else {
 886                                 /* Write to External memory */
 887                                 status =
 888                                     write_ext_dsp_data(dev_ctxt, host_buf,
 889                                                        dest_addr, copy_bytes,
 890                                                        mem_type, false);
 891                         }
 892                 }
 893                 total_bytes -= copy_bytes;
 894                 src_addr += copy_bytes;
 895                 dest_addr += copy_bytes;
 896         }
 897         return status;
 898 }
 899
 900 /* Mem Write does not halt the DSP to write unlike bridge_brd_write */
 901 static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
 902                                     u8 *host_buff, u32 dsp_addr,
 903                                     u32 ul_num_bytes, u32 mem_type)
 904 {
 905         int status = 0;
 906         struct bridge_dev_context *dev_context = dev_ctxt;
 907         u32 ul_remain_bytes = 0;
 908         u32 ul_bytes = 0;
 909         ul_remain_bytes = ul_num_bytes;
 910         while (ul_remain_bytes > 0 && !status) {
 911                 ul_bytes =
 912                     ul_remain_bytes > BUFFERSIZE ? BUFFERSIZE : ul_remain_bytes;
 913                 if (dsp_addr < (dev_context->dw_dsp_start_add +
 914                                  dev_context->dw_internal_size)) {
 915                         status =
 916                             write_dsp_data(dev_ctxt, host_buff, dsp_addr,
 917                                            ul_bytes, mem_type);
 918                 } else {
 919                         status = write_ext_dsp_data(dev_ctxt, host_buff,
 920                                                     dsp_addr, ul_bytes,
 921                                                     mem_type, true);
 922                 }
 923                 ul_remain_bytes -= ul_bytes;
 924                 dsp_addr += ul_bytes;
 925                 host_buff = host_buff + ul_bytes;
 926         }
 927         return status;
 928 }
 929
 930 /*
 931  *  ======== wait_for_start ========
 932  *      Wait for the singal from DSP that it has started, or time out.
 933  */
 934 bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr)
 935 {
 936         u16 timeout = TIHELEN_ACKTIMEOUT;
 937
 938         /*  Wait for response from board */
 939         while (__raw_readw(dw_sync_addr) && --timeout)
 940                 udelay(10);
 941
 942         /*  If timed out: return false */
 943         if (!timeout) {
 944                 pr_err("%s: Timed out waiting DSP to Start\n", __func__);
 945                 return false;
 946         }
 947         return true;
 948 }