2 * SBE 2T3E3 synchronous serial card driver for Linux
4 * Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
10 * This code is based on a driver written by SBE Inc.
13 #include <linux/netdevice.h>
14 #include <linux/types.h>
15 #include <linux/errno.h>
20 void dc_init(struct channel *sc)
25 /*dc_reset(sc);*/ /* do not want to reset here */
30 val = SBE_2T3E3_21143_VAL_READ_LINE_ENABLE |
31 SBE_2T3E3_21143_VAL_READ_MULTIPLE_ENABLE |
32 SBE_2T3E3_21143_VAL_TRANSMIT_AUTOMATIC_POLLING_200us |
33 SBE_2T3E3_21143_VAL_BUS_ARBITRATION_RR;
35 if (sc->h.command & 16)
36 val |= SBE_2T3E3_21143_VAL_WRITE_AND_INVALIDATE_ENABLE;
38 switch (sc->h.cache_size) {
40 val |= SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_32;
43 val |= SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_16;
46 val |= SBE_2T3E3_21143_VAL_CACHE_ALIGNMENT_8;
52 dc_write(sc->addr, SBE_2T3E3_21143_REG_BUS_MODE, val);
54 /* OPERATION_MODE (CSR6) */
55 val = SBE_2T3E3_21143_VAL_RECEIVE_ALL |
56 SBE_2T3E3_21143_VAL_MUST_BE_ONE |
57 SBE_2T3E3_21143_VAL_THRESHOLD_CONTROL_BITS_1 |
58 SBE_2T3E3_21143_VAL_LOOPBACK_OFF |
59 SBE_2T3E3_21143_VAL_PASS_ALL_MULTICAST |
60 SBE_2T3E3_21143_VAL_PROMISCUOUS_MODE |
61 SBE_2T3E3_21143_VAL_PASS_BAD_FRAMES;
62 dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, val);
63 if (sc->p.loopback == SBE_2T3E3_LOOPBACK_ETHERNET)
64 sc->p.loopback = SBE_2T3E3_LOOPBACK_NONE;
66 #if 0 /* No need to clear this register - and it may be in use */
68 * BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT (CSR9)
71 dc_write(sc->addr, SBE_2T3E3_21143_REG_BOOT_ROM_SERIAL_ROM_AND_MII_MANAGEMENT, val);
75 * GENERAL_PURPOSE_TIMER_AND_INTERRUPT_MITIGATION_CONTROL (CSR11)
77 val = SBE_2T3E3_21143_VAL_CYCLE_SIZE |
78 SBE_2T3E3_21143_VAL_TRANSMIT_TIMER |
79 SBE_2T3E3_21143_VAL_NUMBER_OF_TRANSMIT_PACKETS |
80 SBE_2T3E3_21143_VAL_RECEIVE_TIMER |
81 SBE_2T3E3_21143_VAL_NUMBER_OF_RECEIVE_PACKETS;
82 dc_write(sc->addr, SBE_2T3E3_21143_REG_GENERAL_PURPOSE_TIMER_AND_INTERRUPT_MITIGATION_CONTROL, val);
84 /* prepare descriptors and data for receive and transmit procecsses */
85 if (dc_init_descriptor_list(sc) != 0)
88 /* clear ethernet interrupts status */
89 dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, 0xFFFFFFFF);
91 /* SIA mode registers */
92 dc_set_output_port(sc);
95 void dc_start(struct channel *sc)
99 if (!(sc->r.flags & SBE_2T3E3_FLAG_NETWORK_UP))
104 /* get actual LOS and OOF status */
105 switch (sc->p.frame_type) {
106 case SBE_2T3E3_FRAME_TYPE_E3_G751:
107 case SBE_2T3E3_FRAME_TYPE_E3_G832:
108 val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_E3_RX_CONFIGURATION_STATUS_2);
109 dev_dbg(&sc->pdev->dev, "Start Framer Rx Status = %02X\n", val);
110 sc->s.OOF = val & SBE_2T3E3_FRAMER_VAL_E3_RX_OOF ? 1 : 0;
112 case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
113 case SBE_2T3E3_FRAME_TYPE_T3_M13:
114 val = exar7250_read(sc, SBE_2T3E3_FRAMER_REG_T3_RX_CONFIGURATION_STATUS);
115 dev_dbg(&sc->pdev->dev, "Start Framer Rx Status = %02X\n", val);
116 sc->s.OOF = val & SBE_2T3E3_FRAMER_VAL_T3_RX_OOF ? 1 : 0;
123 /* start receive and transmit processes */
124 dc_transmitter_onoff(sc, SBE_2T3E3_ON);
125 dc_receiver_onoff(sc, SBE_2T3E3_ON);
127 /* start interrupts */
131 #define MAX_INT_WAIT_CNT 12000
132 void dc_stop(struct channel *sc)
136 /* stop receive and transmit processes */
137 dc_receiver_onoff(sc, SBE_2T3E3_OFF);
138 dc_transmitter_onoff(sc, SBE_2T3E3_OFF);
140 /* turn off ethernet interrupts */
143 /* wait to ensure the interrupts have been completed */
144 for (wcnt = 0; wcnt < MAX_INT_WAIT_CNT; wcnt++) {
146 if (!sc->interrupt_active)
149 if (wcnt >= MAX_INT_WAIT_CNT)
150 dev_warn(&sc->pdev->dev, "SBE 2T3E3: Interrupt active too long\n");
152 /* clear all receive/transmit data */
153 dc_drop_descriptor_list(sc);
156 void dc_start_intr(struct channel *sc)
158 if (sc->p.loopback == SBE_2T3E3_LOOPBACK_NONE && sc->s.OOF)
161 if (sc->p.receiver_on || sc->p.transmitter_on) {
162 if (!sc->ether.interrupt_enable_mask)
163 dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, 0xFFFFFFFF);
165 sc->ether.interrupt_enable_mask =
166 SBE_2T3E3_21143_VAL_NORMAL_INTERRUPT_SUMMARY_ENABLE |
167 SBE_2T3E3_21143_VAL_ABNORMAL_INTERRUPT_SUMMARY_ENABLE |
168 SBE_2T3E3_21143_VAL_RECEIVE_STOPPED_ENABLE |
169 SBE_2T3E3_21143_VAL_RECEIVE_BUFFER_UNAVAILABLE_ENABLE |
170 SBE_2T3E3_21143_VAL_RECEIVE_INTERRUPT_ENABLE |
171 SBE_2T3E3_21143_VAL_TRANSMIT_UNDERFLOW_INTERRUPT_ENABLE |
172 SBE_2T3E3_21143_VAL_TRANSMIT_BUFFER_UNAVAILABLE_ENABLE |
173 SBE_2T3E3_21143_VAL_TRANSMIT_STOPPED_ENABLE |
174 SBE_2T3E3_21143_VAL_TRANSMIT_INTERRUPT_ENABLE;
176 dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE,
177 sc->ether.interrupt_enable_mask);
181 void dc_stop_intr(struct channel *sc)
183 sc->ether.interrupt_enable_mask = 0;
184 dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE, 0);
187 void dc_reset(struct channel *sc)
189 /* turn off ethernet interrupts */
190 dc_write(sc->addr, SBE_2T3E3_21143_REG_INTERRUPT_ENABLE, 0);
191 dc_write(sc->addr, SBE_2T3E3_21143_REG_STATUS, 0xFFFFFFFF);
194 dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_BUS_MODE,
195 SBE_2T3E3_21143_VAL_SOFTWARE_RESET);
196 udelay(4); /* 50 PCI cycles < 2us */
198 /* clear hardware configuration */
199 dc_write(sc->addr, SBE_2T3E3_21143_REG_BUS_MODE, 0);
201 /* clear software configuration */
202 dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, 0);
204 /* turn off SIA reset */
205 dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY,
206 SBE_2T3E3_21143_VAL_SIA_RESET);
207 dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_TRANSMIT_AND_RECEIVE, 0);
208 dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_AND_GENERAL_PURPOSE_PORT, 0);
212 void dc_receiver_onoff(struct channel *sc, u32 mode)
216 if (sc->p.receiver_on == mode)
221 if (dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
222 SBE_2T3E3_21143_VAL_RECEIVE_START) {
223 dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
224 SBE_2T3E3_21143_VAL_RECEIVE_START);
226 for (i = 0; i < 16; i++) {
227 state = dc_read(sc->addr, SBE_2T3E3_21143_REG_STATUS) &
228 SBE_2T3E3_21143_VAL_RECEIVE_PROCESS_STATE;
229 if (state == SBE_2T3E3_21143_VAL_RX_STOPPED)
233 if (state != SBE_2T3E3_21143_VAL_RX_STOPPED)
234 dev_warn(&sc->pdev->dev, "SBE 2T3E3: Rx failed to stop\n");
236 dev_info(&sc->pdev->dev, "SBE 2T3E3: Rx off\n");
240 dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
241 SBE_2T3E3_21143_VAL_RECEIVE_START);
243 dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_POLL_DEMAND, 0xFFFFFFFF);
249 sc->p.receiver_on = mode;
252 void dc_transmitter_onoff(struct channel *sc, u32 mode)
256 if (sc->p.transmitter_on == mode)
261 if (dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
262 SBE_2T3E3_21143_VAL_TRANSMISSION_START) {
263 dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
264 SBE_2T3E3_21143_VAL_TRANSMISSION_START);
266 for (i = 0; i < 16; i++) {
267 state = dc_read(sc->addr, SBE_2T3E3_21143_REG_STATUS) &
268 SBE_2T3E3_21143_VAL_TRANSMISSION_PROCESS_STATE;
269 if (state == SBE_2T3E3_21143_VAL_TX_STOPPED)
273 if (state != SBE_2T3E3_21143_VAL_TX_STOPPED)
274 dev_warn(&sc->pdev->dev, "SBE 2T3E3: Tx failed to stop\n");
278 dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
279 SBE_2T3E3_21143_VAL_TRANSMISSION_START);
281 dc_write(sc->addr, SBE_2T3E3_21143_REG_TRANSMIT_POLL_DEMAND, 0xFFFFFFFF);
287 sc->p.transmitter_on = mode;
292 void dc_set_loopback(struct channel *sc, u32 mode)
297 case SBE_2T3E3_21143_VAL_LOOPBACK_OFF:
298 case SBE_2T3E3_21143_VAL_LOOPBACK_INTERNAL:
306 dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY,
307 SBE_2T3E3_21143_VAL_SIA_RESET);
309 dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY,
310 SBE_2T3E3_21143_VAL_SIA_RESET);
313 /* select loopback mode */
314 val = dc_read(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE) &
315 ~SBE_2T3E3_21143_VAL_OPERATING_MODE;
317 dc_write(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE, val);
319 if (mode == SBE_2T3E3_21143_VAL_LOOPBACK_OFF)
320 dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
321 SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
323 dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
324 SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
327 u32 dc_init_descriptor_list(struct channel *sc)
332 if (sc->ether.rx_ring == NULL)
333 sc->ether.rx_ring = kzalloc(SBE_2T3E3_RX_DESC_RING_SIZE *
334 sizeof(t3e3_rx_desc_t), GFP_KERNEL);
335 if (sc->ether.rx_ring == NULL) {
336 dev_err(&sc->pdev->dev, "SBE 2T3E3: no buffer space for RX ring\n");
340 if (sc->ether.tx_ring == NULL)
341 sc->ether.tx_ring = kzalloc(SBE_2T3E3_TX_DESC_RING_SIZE *
342 sizeof(t3e3_tx_desc_t), GFP_KERNEL);
343 if (sc->ether.tx_ring == NULL) {
344 #ifdef T3E3_USE_CONTIGMALLOC
345 t3e3_contigmemory_size = SBE_2T3E3_RX_DESC_RING_SIZE *
346 sizeof(t3e3_rx_desc_t);
348 kfree(sc->ether.rx_ring);
349 sc->ether.rx_ring = NULL;
350 dev_err(&sc->pdev->dev, "SBE 2T3E3: no buffer space for RX ring\n");
358 for (i = 0; i < SBE_2T3E3_RX_DESC_RING_SIZE; i++) {
359 sc->ether.rx_ring[i].rdes0 = SBE_2T3E3_RX_DESC_21143_OWN;
360 sc->ether.rx_ring[i].rdes1 =
361 SBE_2T3E3_RX_DESC_SECOND_ADDRESS_CHAINED | SBE_2T3E3_MTU;
363 if (sc->ether.rx_data[i] == NULL) {
364 if (!(m = dev_alloc_skb(MCLBYTES))) {
365 for (j = 0; j < i; j++) {
366 dev_kfree_skb_any(sc->ether.rx_data[j]);
367 sc->ether.rx_data[j] = NULL;
369 #ifdef T3E3_USE_CONTIGMALLOC
370 t3e3_contigmemory_size = SBE_2T3E3_RX_DESC_RING_SIZE *
371 sizeof(t3e3_rx_desc_t);
373 kfree(sc->ether.rx_ring);
374 sc->ether.rx_ring = NULL;
375 #ifdef T3E3_USE_CONTIGMALLOC
376 t3e3_contigmemory_size = SBE_2T3E3_TX_DESC_RING_SIZE *
377 sizeof(t3e3_tx_desc_t);
379 kfree(sc->ether.tx_ring);
380 sc->ether.tx_ring = NULL;
381 dev_err(&sc->pdev->dev, "SBE 2T3E3: token_alloc err:"
382 " no buffer space for RX ring\n");
385 sc->ether.rx_data[i] = m;
387 sc->ether.rx_ring[i].rdes2 = virt_to_phys(sc->ether.rx_data[i]->data);
389 sc->ether.rx_ring[i].rdes3 = virt_to_phys(
390 &sc->ether.rx_ring[(i + 1) % SBE_2T3E3_RX_DESC_RING_SIZE]);
392 sc->ether.rx_ring[SBE_2T3E3_RX_DESC_RING_SIZE - 1].rdes1 |=
393 SBE_2T3E3_RX_DESC_END_OF_RING;
394 sc->ether.rx_ring_current_read = 0;
396 dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_LIST_BASE_ADDRESS,
397 virt_to_phys(&sc->ether.rx_ring[0]));
402 for (i = 0; i < SBE_2T3E3_TX_DESC_RING_SIZE; i++) {
403 sc->ether.tx_ring[i].tdes0 = 0;
404 sc->ether.tx_ring[i].tdes1 = SBE_2T3E3_TX_DESC_SECOND_ADDRESS_CHAINED |
405 SBE_2T3E3_TX_DESC_DISABLE_PADDING;
407 sc->ether.tx_ring[i].tdes2 = 0;
408 sc->ether.tx_data[i] = NULL;
410 sc->ether.tx_ring[i].tdes3 = virt_to_phys(
411 &sc->ether.tx_ring[(i + 1) % SBE_2T3E3_TX_DESC_RING_SIZE]);
413 sc->ether.tx_ring[SBE_2T3E3_TX_DESC_RING_SIZE - 1].tdes1 |=
414 SBE_2T3E3_TX_DESC_END_OF_RING;
416 dc_write(sc->addr, SBE_2T3E3_21143_REG_TRANSMIT_LIST_BASE_ADDRESS,
417 virt_to_phys(&sc->ether.tx_ring[0]));
418 sc->ether.tx_ring_current_read = 0;
419 sc->ether.tx_ring_current_write = 0;
420 sc->ether.tx_free_cnt = SBE_2T3E3_TX_DESC_RING_SIZE;
421 spin_lock_init(&sc->ether.tx_lock);
426 void dc_clear_descriptor_list(struct channel *sc)
430 /* clear CSR3 and CSR4 */
431 dc_write(sc->addr, SBE_2T3E3_21143_REG_RECEIVE_LIST_BASE_ADDRESS, 0);
432 dc_write(sc->addr, SBE_2T3E3_21143_REG_TRANSMIT_LIST_BASE_ADDRESS, 0);
434 /* free all data buffers on TX ring */
435 for (i = 0; i < SBE_2T3E3_TX_DESC_RING_SIZE; i++) {
436 if (sc->ether.tx_data[i] != NULL) {
437 dev_kfree_skb_any(sc->ether.tx_data[i]);
438 sc->ether.tx_data[i] = NULL;
443 void dc_drop_descriptor_list(struct channel *sc)
447 dc_clear_descriptor_list(sc);
449 /* free all data buffers on RX ring */
450 for (i = 0; i < SBE_2T3E3_RX_DESC_RING_SIZE; i++) {
451 if (sc->ether.rx_data[i] != NULL) {
452 dev_kfree_skb_any(sc->ether.rx_data[i]);
453 sc->ether.rx_data[i] = NULL;
457 if (sc->ether.rx_ring != NULL) {
458 #ifdef T3E3_USE_CONTIGMALLOC
459 t3e3_contigmemory_size = SBE_2T3E3_RX_DESC_RING_SIZE *
460 sizeof(t3e3_rx_desc_t);
462 kfree(sc->ether.rx_ring);
463 sc->ether.rx_ring = NULL;
466 if (sc->ether.tx_ring != NULL) {
467 #ifdef T3E3_USE_CONTIGMALLOC
468 t3e3_contigmemory_size = SBE_2T3E3_TX_DESC_RING_SIZE *
469 sizeof(t3e3_tx_desc_t);
471 kfree(sc->ether.tx_ring);
472 sc->ether.tx_ring = NULL;
477 void dc_set_output_port(struct channel *sc)
479 dc_clear_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
480 SBE_2T3E3_21143_VAL_PORT_SELECT);
482 dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_STATUS, 0x00000301);
483 dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_CONNECTIVITY, 0);
484 dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_TRANSMIT_AND_RECEIVE, 0);
485 dc_write(sc->addr, SBE_2T3E3_21143_REG_SIA_AND_GENERAL_PURPOSE_PORT, 0x08000011);
487 dc_set_bits(sc->addr, SBE_2T3E3_21143_REG_OPERATION_MODE,
488 SBE_2T3E3_21143_VAL_TRANSMIT_THRESHOLD_MODE_100Mbs |
489 SBE_2T3E3_21143_VAL_HEARTBEAT_DISABLE |
490 SBE_2T3E3_21143_VAL_PORT_SELECT |
491 SBE_2T3E3_21143_VAL_FULL_DUPLEX_MODE);
494 void dc_restart(struct channel *sc)
496 dev_warn(&sc->pdev->dev, "SBE 2T3E3: 21143 restart\n");
500 dc_init(sc); /* stop + reset + init */