drivers/staging/rts_pstor/xd.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   wwang (wei_wang@realsil.com.cn)
  20  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21  */
  22
  23 #include <linux/blkdev.h>
  24 #include <linux/kthread.h>
  25 #include <linux/sched.h>
  26
  27 #include "rtsx.h"
  28 #include "rtsx_transport.h"
  29 #include "rtsx_scsi.h"
  30 #include "rtsx_card.h"
  31 #include "xd.h"
  32
  33 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no);
  34 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, u16 logoff, u8 start_page, u8 end_page);
  35
  36 static inline void xd_set_err_code(struct rtsx_chip *chip, u8 err_code)
  37 {
  38         struct xd_info *xd_card = &(chip->xd_card);
  39
  40         xd_card->err_code = err_code;
  41 }
  42
  43 static inline int xd_check_err_code(struct rtsx_chip *chip, u8 err_code)
  44 {
  45         struct xd_info *xd_card = &(chip->xd_card);
  46
  47         return (xd_card->err_code == err_code);
  48 }
  49
  50 static int xd_set_init_para(struct rtsx_chip *chip)
  51 {
  52         struct xd_info *xd_card = &(chip->xd_card);
  53         int retval;
  54
  55         if (chip->asic_code)
  56                 xd_card->xd_clock = 47;
  57         else
  58                 xd_card->xd_clock = CLK_50;
  59
  60         retval = switch_clock(chip, xd_card->xd_clock);
  61         if (retval != STATUS_SUCCESS)
  62                 TRACE_RET(chip, STATUS_FAIL);
  63
  64         return STATUS_SUCCESS;
  65 }
  66
  67 static int xd_switch_clock(struct rtsx_chip *chip)
  68 {
  69         struct xd_info *xd_card = &(chip->xd_card);
  70         int retval;
  71
  72         retval = select_card(chip, XD_CARD);
  73         if (retval != STATUS_SUCCESS)
  74                 TRACE_RET(chip, STATUS_FAIL);
  75
  76         retval = switch_clock(chip, xd_card->xd_clock);
  77         if (retval != STATUS_SUCCESS)
  78                 TRACE_RET(chip, STATUS_FAIL);
  79
  80         return STATUS_SUCCESS;
  81 }
  82
  83 static int xd_read_id(struct rtsx_chip *chip, u8 id_cmd, u8 *id_buf, u8 buf_len)
  84 {
  85         int retval, i;
  86         u8 *ptr;
  87
  88         rtsx_init_cmd(chip);
  89
  90         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd);
  91         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_ID);
  92         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
  93
  94         for (i = 0; i < 4; i++)
  95                 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0);
  96
  97         retval = rtsx_send_cmd(chip, XD_CARD, 20);
  98         if (retval < 0)
  99                 TRACE_RET(chip, STATUS_FAIL);
 100
 101         ptr = rtsx_get_cmd_data(chip) + 1;
 102         if (id_buf && buf_len) {
 103                 if (buf_len > 4)
 104                         buf_len = 4;
 105                 memcpy(id_buf, ptr, buf_len);
 106         }
 107
 108         return STATUS_SUCCESS;
 109 }
 110
 111 static void xd_assign_phy_addr(struct rtsx_chip *chip, u32 addr, u8 mode)
 112 {
 113         struct xd_info *xd_card = &(chip->xd_card);
 114
 115         switch (mode) {
 116         case XD_RW_ADDR:
 117                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0);
 118                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr);
 119                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF, (u8)(addr >> 8));
 120                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3, 0xFF, (u8)(addr >> 16));
 121                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
 122                                 xd_card->addr_cycle | XD_CALC_ECC | XD_BA_NO_TRANSFORM);
 123                 break;
 124
 125         case XD_ERASE_ADDR:
 126                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, (u8)addr);
 127                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)(addr >> 8));
 128                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF, (u8)(addr >> 16));
 129                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
 130                                 (xd_card->addr_cycle - 1) | XD_CALC_ECC | XD_BA_NO_TRANSFORM);
 131                 break;
 132
 133         default:
 134                 break;
 135         }
 136 }
 137
 138 static int xd_read_redundant(struct rtsx_chip *chip, u32 page_addr, u8 *buf, int buf_len)
 139 {
 140         int retval, i;
 141
 142         rtsx_init_cmd(chip);
 143
 144         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
 145
 146         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_REDUNDANT);
 147         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
 148
 149         for (i = 0; i < 6; i++)
 150                 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_PAGE_STATUS + i), 0, 0);
 151         for (i = 0; i < 4; i++)
 152                 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_RESERVED0 + i), 0, 0);
 153         rtsx_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0);
 154
 155         retval = rtsx_send_cmd(chip, XD_CARD, 500);
 156         if (retval < 0)
 157                 TRACE_RET(chip, STATUS_FAIL);
 158
 159         if (buf && buf_len) {
 160                 u8 *ptr = rtsx_get_cmd_data(chip) + 1;
 161
 162                 if (buf_len > 11)
 163                         buf_len = 11;
 164                 memcpy(buf, ptr, buf_len);
 165         }
 166
 167         return STATUS_SUCCESS;
 168 }
 169
 170 static int xd_read_data_from_ppb(struct rtsx_chip *chip, int offset, u8 *buf, int buf_len)
 171 {
 172         int retval, i;
 173
 174         if (!buf || (buf_len < 0))
 175                 TRACE_RET(chip, STATUS_FAIL);
 176
 177         rtsx_init_cmd(chip);
 178
 179         for (i = 0; i < buf_len; i++)
 180                 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i, 0, 0);
 181
 182         retval = rtsx_send_cmd(chip, 0, 250);
 183         if (retval < 0) {
 184                 rtsx_clear_xd_error(chip);
 185                 TRACE_RET(chip, STATUS_FAIL);
 186         }
 187
 188         memcpy(buf, rtsx_get_cmd_data(chip), buf_len);
 189
 190         return STATUS_SUCCESS;
 191 }
 192
 193 static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf, int buf_len)
 194 {
 195         int retval;
 196         u8 reg;
 197
 198         if (!buf || (buf_len < 10))
 199                 TRACE_RET(chip, STATUS_FAIL);
 200
 201         rtsx_init_cmd(chip);
 202
 203         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
 204
 205         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
 206         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
 207         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
 208
 209         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_PAGES);
 210         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
 211
 212         retval = rtsx_send_cmd(chip, XD_CARD, 250);
 213         if (retval == -ETIMEDOUT) {
 214                 rtsx_clear_xd_error(chip);
 215                 TRACE_RET(chip, STATUS_FAIL);
 216         }
 217
 218         RTSX_READ_REG(chip, XD_PAGE_STATUS, &reg);
 219         if (reg != XD_GPG) {
 220                 rtsx_clear_xd_error(chip);
 221                 TRACE_RET(chip, STATUS_FAIL);
 222         }
 223
 224         RTSX_READ_REG(chip, XD_CTL, &reg);
 225         if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) {
 226                 retval = xd_read_data_from_ppb(chip, 0, buf, buf_len);
 227                 if (retval != STATUS_SUCCESS)
 228                         TRACE_RET(chip, STATUS_FAIL);
 229                 if (reg & XD_ECC1_ERROR) {
 230                         u8 ecc_bit, ecc_byte;
 231
 232                         RTSX_READ_REG(chip, XD_ECC_BIT1, &ecc_bit);
 233                         RTSX_READ_REG(chip, XD_ECC_BYTE1, &ecc_byte);
 234
 235                         RTSX_DEBUGP("ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n", ecc_bit, ecc_byte);
 236                         if (ecc_byte < buf_len) {
 237                                 RTSX_DEBUGP("Before correct: 0x%x\n", buf[ecc_byte]);
 238                                 buf[ecc_byte] ^= (1 << ecc_bit);
 239                                 RTSX_DEBUGP("After correct: 0x%x\n", buf[ecc_byte]);
 240                         }
 241                 }
 242         } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) {
 243                 rtsx_clear_xd_error(chip);
 244
 245                 retval = xd_read_data_from_ppb(chip, 256, buf, buf_len);
 246                 if (retval != STATUS_SUCCESS)
 247                         TRACE_RET(chip, STATUS_FAIL);
 248                 if (reg & XD_ECC2_ERROR) {
 249                         u8 ecc_bit, ecc_byte;
 250
 251                         RTSX_READ_REG(chip, XD_ECC_BIT2, &ecc_bit);
 252                         RTSX_READ_REG(chip, XD_ECC_BYTE2, &ecc_byte);
 253
 254                         RTSX_DEBUGP("ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n", ecc_bit, ecc_byte);
 255                         if (ecc_byte < buf_len) {
 256                                 RTSX_DEBUGP("Before correct: 0x%x\n", buf[ecc_byte]);
 257                                 buf[ecc_byte] ^= (1 << ecc_bit);
 258                                 RTSX_DEBUGP("After correct: 0x%x\n", buf[ecc_byte]);
 259                         }
 260                 }
 261         } else {
 262                 rtsx_clear_xd_error(chip);
 263                 TRACE_RET(chip, STATUS_FAIL);
 264         }
 265
 266         return STATUS_SUCCESS;
 267 }
 268
 269 static void xd_fill_pull_ctl_disable(struct rtsx_chip *chip)
 270 {
 271         if (CHECK_PID(chip, 0x5209)) {
 272                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
 273                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
 274                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xD5);
 275                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
 276                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
 277                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x15);
 278         } else if (CHECK_PID(chip, 0x5208)) {
 279                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
 280                         XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
 281                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
 282                         XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
 283                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
 284                         XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
 285                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
 286                         XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD);
 287                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
 288                         MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
 289                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
 290         } else if (CHECK_PID(chip, 0x5288)) {
 291                 if (CHECK_BARO_PKG(chip, QFN)) {
 292                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
 293                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
 294                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x4B);
 295                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x69);
 296                 }
 297         }
 298 }
 299
 300 static void xd_fill_pull_ctl_stage1_barossa(struct rtsx_chip *chip)
 301 {
 302         if (CHECK_BARO_PKG(chip, QFN)) {
 303                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
 304                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
 305                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x4B);
 306                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
 307         }
 308 }
 309
 310 static void xd_fill_pull_ctl_enable(struct rtsx_chip *chip)
 311 {
 312         if (CHECK_PID(chip, 0x5209)) {
 313                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xAA);
 314                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
 315                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xD5);
 316                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
 317                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
 318                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x15);
 319         } else if (CHECK_PID(chip, 0x5208)) {
 320                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
 321                         XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
 322                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
 323                         XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
 324                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
 325                         XD_WP_PD | XD_CE_PU | XD_CLE_PD | XD_CD_PU);
 326                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
 327                         XD_RDY_PU | XD_WE_PU | XD_RE_PU | XD_ALE_PD);
 328                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
 329                         MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
 330                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
 331         } else if (CHECK_PID(chip, 0x5288)) {
 332                 if (CHECK_BARO_PKG(chip, QFN)) {
 333                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
 334                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
 335                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x53);
 336                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0xA9);
 337                 }
 338         }
 339 }
 340
 341 static int xd_pull_ctl_disable(struct rtsx_chip *chip)
 342 {
 343         if (CHECK_PID(chip, 0x5209)) {
 344                 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
 345                 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
 346                 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0xD5);
 347                 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x55);
 348                 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, 0x55);
 349                 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, 0x15);
 350         } else if (CHECK_PID(chip, 0x5208)) {
 351                 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF,
 352                         XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
 353                 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF,
 354                         XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
 355                 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF,
 356                         XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
 357                 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF,
 358                         XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD);
 359                 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
 360                         MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
 361                 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
 362         } else if (CHECK_PID(chip, 0x5288)) {
 363                 if (CHECK_BARO_PKG(chip, QFN)) {
 364                         RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
 365                         RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
 366                         RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B);
 367                         RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69);
 368                 }
 369         }
 370
 371         return STATUS_SUCCESS;
 372 }
 373
 374 static void xd_clear_dma_buffer(struct rtsx_chip *chip)
 375 {
 376         if (CHECK_PID(chip, 0x5209)) {
 377                 int retval;
 378                 u8 *buf;
 379
 380                 RTSX_DEBUGP("xD ECC error, dummy write!\n");
 381
 382                 buf = (u8 *)rtsx_alloc_dma_buf(chip, 512, GFP_KERNEL);
 383                 if (!buf)
 384                         return;
 385
 386                 rtsx_init_cmd(chip);
 387
 388                 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
 389
 390                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
 391                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, SD_CLK_EN);
 392                 if (chip->asic_code) {
 393                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0xAA);
 394                 } else {
 395                         rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL,
 396                                         FPGA_SD_PULL_CTL_BIT, 0);
 397                 }
 398
 399                 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
 400                 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
 401                 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
 402                 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
 403                 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x03, SD_BUS_WIDTH_4);
 404
 405                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
 406
 407                 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 408                         SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
 409                 rtsx_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
 410
 411                 rtsx_send_cmd_no_wait(chip);
 412
 413                 retval = rtsx_transfer_data(chip, SD_CARD, buf, 512, 0, DMA_TO_DEVICE, 100);
 414                 if (retval < 0) {
 415                         u8 val;
 416
 417                         rtsx_read_register(chip, SD_STAT1, &val);
 418                         RTSX_DEBUGP("SD_STAT1: 0x%x\n", val);
 419
 420                         rtsx_read_register(chip, SD_STAT2, &val);
 421                         RTSX_DEBUGP("SD_STAT2: 0x%x\n", val);
 422
 423                         rtsx_read_register(chip, SD_BUS_STAT, &val);
 424                         RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", val);
 425
 426                         rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
 427                 }
 428
 429                 rtsx_free_dma_buf(chip, buf);
 430
 431                 if (chip->asic_code) {
 432                         rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, 0x55);
 433                 } else {
 434                         rtsx_write_register(chip, FPGA_PULL_CTL,
 435                                                 FPGA_SD_PULL_CTL_BIT, FPGA_SD_PULL_CTL_BIT);
 436                 }
 437                 rtsx_write_register(chip, CARD_SELECT, 0x07, XD_MOD_SEL);
 438                 rtsx_write_register(chip, CARD_CLK_EN, SD_CLK_EN, 0);
 439         }
 440 }
 441
 442 static int reset_xd(struct rtsx_chip *chip)
 443 {
 444         struct xd_info *xd_card = &(chip->xd_card);
 445         int retval, i, j;
 446         u8 *ptr, id_buf[4], redunt[11];
 447
 448         retval = select_card(chip, XD_CARD);
 449         if (retval != STATUS_SUCCESS)
 450                 TRACE_RET(chip, STATUS_FAIL);
 451
 452         rtsx_init_cmd(chip);
 453
 454         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF, XD_PGSTS_NOT_FF);
 455         if (chip->asic_code) {
 456                 if (!CHECK_PID(chip, 0x5288))
 457                         xd_fill_pull_ctl_disable(chip);
 458                 else
 459                         xd_fill_pull_ctl_stage1_barossa(chip);
 460         } else {
 461                 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
 462                         (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3) | 0x20);
 463         }
 464
 465         if (!chip->ft2_fast_mode)
 466                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_INIT, XD_NO_AUTO_PWR_OFF, 0);
 467
 468         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
 469
 470         retval = rtsx_send_cmd(chip, XD_CARD, 100);
 471         if (retval < 0)
 472                 TRACE_RET(chip, STATUS_FAIL);
 473
 474         if (!chip->ft2_fast_mode) {
 475                 retval = card_power_off(chip, XD_CARD);
 476                 if (retval != STATUS_SUCCESS)
 477                         TRACE_RET(chip, STATUS_FAIL);
 478
 479                 wait_timeout(250);
 480
 481                 if (CHECK_PID(chip, 0x5209))
 482                         RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0xAA);
 483
 484                 rtsx_init_cmd(chip);
 485
 486                 if (chip->asic_code) {
 487                         xd_fill_pull_ctl_enable(chip);
 488                 } else {
 489                         rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
 490                                 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2) | 0x20);
 491                 }
 492
 493                 retval = rtsx_send_cmd(chip, XD_CARD, 100);
 494                 if (retval < 0)
 495                         TRACE_RET(chip, STATUS_FAIL);
 496
 497                 retval = card_power_on(chip, XD_CARD);
 498                 if (retval != STATUS_SUCCESS)
 499                         TRACE_RET(chip, STATUS_FAIL);
 500
 501 #ifdef SUPPORT_OCP
 502                 wait_timeout(50);
 503                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
 504                         RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat);
 505                         TRACE_RET(chip, STATUS_FAIL);
 506                 }
 507 #endif
 508         }
 509
 510         rtsx_init_cmd(chip);
 511
 512         if (chip->ft2_fast_mode) {
 513                 if (chip->asic_code) {
 514                         xd_fill_pull_ctl_enable(chip);
 515                 } else {
 516                         rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
 517                                 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2) | 0x20);
 518                 }
 519         }
 520
 521         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, XD_OUTPUT_EN);
 522         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN);
 523
 524         retval = rtsx_send_cmd(chip, XD_CARD, 100);
 525         if (retval < 0)
 526                 TRACE_RET(chip, STATUS_FAIL);
 527
 528         if (!chip->ft2_fast_mode)
 529                 wait_timeout(200);
 530
 531         retval = xd_set_init_para(chip);
 532         if (retval != STATUS_SUCCESS)
 533                 TRACE_RET(chip, STATUS_FAIL);
 534
 535         /* Read ID to check if the timing setting is right */
 536         for (i = 0; i < 4; i++) {
 537                 rtsx_init_cmd(chip);
 538
 539                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF,
 540                                 XD_TIME_SETUP_STEP * 3 + XD_TIME_RW_STEP * (2 + i) + XD_TIME_RWN_STEP * i);
 541                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF,
 542                                 XD_TIME_SETUP_STEP * 3 + XD_TIME_RW_STEP * (4 + i) + XD_TIME_RWN_STEP * (3 + i));
 543
 544                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_RESET);
 545                 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
 546
 547                 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
 548                 rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
 549
 550                 retval = rtsx_send_cmd(chip, XD_CARD, 100);
 551                 if (retval < 0)
 552                         TRACE_RET(chip, STATUS_FAIL);
 553
 554                 ptr = rtsx_get_cmd_data(chip) + 1;
 555
 556                 RTSX_DEBUGP("XD_DAT: 0x%x, XD_CTL: 0x%x\n", ptr[0], ptr[1]);
 557
 558                 if (((ptr[0] & READY_FLAG) != READY_STATE) || !(ptr[1] & XD_RDY))
 559                         continue;
 560
 561                 retval = xd_read_id(chip, READ_ID, id_buf, 4);
 562                 if (retval != STATUS_SUCCESS)
 563                         TRACE_RET(chip, STATUS_FAIL);
 564
 565                 RTSX_DEBUGP("READ_ID: 0x%x 0x%x 0x%x 0x%x\n",
 566                                         id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
 567
 568                 xd_card->device_code = id_buf[1];
 569
 570                 /* Check if the xD card is supported */
 571                 switch (xd_card->device_code) {
 572                 case XD_4M_X8_512_1:
 573                 case XD_4M_X8_512_2:
 574                         xd_card->block_shift = 4;
 575                         xd_card->page_off = 0x0F;
 576                         xd_card->addr_cycle = 3;
 577                         xd_card->zone_cnt = 1;
 578                         xd_card->capacity = 8000;
 579                         XD_SET_4MB(xd_card);
 580                         break;
 581                 case XD_8M_X8_512:
 582                         xd_card->block_shift = 4;
 583                         xd_card->page_off = 0x0F;
 584                         xd_card->addr_cycle = 3;
 585                         xd_card->zone_cnt = 1;
 586                         xd_card->capacity = 16000;
 587                         break;
 588                 case XD_16M_X8_512:
 589                         XD_PAGE_512(xd_card);
 590                         xd_card->addr_cycle = 3;
 591                         xd_card->zone_cnt = 1;
 592                         xd_card->capacity = 32000;
 593                         break;
 594                 case XD_32M_X8_512:
 595                         XD_PAGE_512(xd_card);
 596                         xd_card->addr_cycle = 3;
 597                         xd_card->zone_cnt = 2;
 598                         xd_card->capacity = 64000;
 599                         break;
 600                 case XD_64M_X8_512:
 601                         XD_PAGE_512(xd_card);
 602                         xd_card->addr_cycle = 4;
 603                         xd_card->zone_cnt = 4;
 604                         xd_card->capacity = 128000;
 605                         break;
 606                 case XD_128M_X8_512:
 607                         XD_PAGE_512(xd_card);
 608                         xd_card->addr_cycle = 4;
 609                         xd_card->zone_cnt = 8;
 610                         xd_card->capacity = 256000;
 611                         break;
 612                 case XD_256M_X8_512:
 613                         XD_PAGE_512(xd_card);
 614                         xd_card->addr_cycle = 4;
 615                         xd_card->zone_cnt = 16;
 616                         xd_card->capacity = 512000;
 617                         break;
 618                 case XD_512M_X8:
 619                         XD_PAGE_512(xd_card);
 620                         xd_card->addr_cycle = 4;
 621                         xd_card->zone_cnt = 32;
 622                         xd_card->capacity = 1024000;
 623                         break;
 624                 case xD_1G_X8_512:
 625                         XD_PAGE_512(xd_card);
 626                         xd_card->addr_cycle = 4;
 627                         xd_card->zone_cnt = 64;
 628                         xd_card->capacity = 2048000;
 629                         break;
 630                 case xD_2G_X8_512:
 631                         XD_PAGE_512(xd_card);
 632                         xd_card->addr_cycle = 4;
 633                         xd_card->zone_cnt = 128;
 634                         xd_card->capacity = 4096000;
 635                         break;
 636                 default:
 637                         continue;
 638                 }
 639
 640                 /* Confirm timing setting */
 641                 for (j = 0; j < 10; j++) {
 642                         retval = xd_read_id(chip, READ_ID, id_buf, 4);
 643                         if (retval != STATUS_SUCCESS)
 644                                 TRACE_RET(chip, STATUS_FAIL);
 645
 646                         if (id_buf[1] != xd_card->device_code)
 647                                 break;
 648                 }
 649
 650                 if (j == 10)
 651                         break;
 652         }
 653
 654         if (i == 4) {
 655                 xd_card->block_shift = 0;
 656                 xd_card->page_off = 0;
 657                 xd_card->addr_cycle = 0;
 658                 xd_card->capacity = 0;
 659
 660                 TRACE_RET(chip, STATUS_FAIL);
 661         }
 662
 663         retval = xd_read_id(chip, READ_xD_ID, id_buf, 4);
 664         if (retval != STATUS_SUCCESS)
 665                 TRACE_RET(chip, STATUS_FAIL);
 666         RTSX_DEBUGP("READ_xD_ID: 0x%x 0x%x 0x%x 0x%x\n",
 667                         id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
 668         if (id_buf[2] != XD_ID_CODE)
 669                 TRACE_RET(chip, STATUS_FAIL);
 670
 671         /* Search CIS block */
 672         for (i = 0; i < 24; i++) {
 673                 u32 page_addr;
 674
 675                 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS)
 676                         TRACE_RET(chip, STATUS_FAIL);
 677
 678                 page_addr = (u32)i << xd_card->block_shift;
 679
 680                 for (j = 0; j < 3; j++) {
 681                         retval = xd_read_redundant(chip, page_addr, redunt, 11);
 682                         if (retval == STATUS_SUCCESS)
 683                                 break;
 684                 }
 685                 if (j == 3)
 686                         continue;
 687
 688                 if (redunt[BLOCK_STATUS] != XD_GBLK)
 689                         continue;
 690
 691                 j = 0;
 692                 if (redunt[PAGE_STATUS] != XD_GPG) {
 693                         for (j = 1; j <= 8; j++) {
 694                                 retval = xd_read_redundant(chip, page_addr + j, redunt, 11);
 695                                 if (retval == STATUS_SUCCESS) {
 696                                         if (redunt[PAGE_STATUS] == XD_GPG)
 697                                                 break;
 698                                 }
 699                         }
 700
 701                         if (j == 9)
 702                                 break;
 703                 }
 704
 705                 /* Check CIS data */
 706                 if ((redunt[BLOCK_STATUS] == XD_GBLK) && (redunt[PARITY] & XD_BA1_ALL0)) {
 707                         u8 buf[10];
 708
 709                         page_addr += j;
 710
 711                         retval = xd_read_cis(chip, page_addr, buf, 10);
 712                         if (retval != STATUS_SUCCESS)
 713                                 TRACE_RET(chip, STATUS_FAIL);
 714
 715                         if ((buf[0] == 0x01) && (buf[1] == 0x03) && (buf[2] == 0xD9)
 716                                         && (buf[3] == 0x01) && (buf[4] == 0xFF)
 717                                         && (buf[5] == 0x18) && (buf[6] == 0x02)
 718                                         && (buf[7] == 0xDF) && (buf[8] == 0x01)
 719                                         && (buf[9] == 0x20)) {
 720                                 xd_card->cis_block = (u16)i;
 721                         }
 722                 }
 723
 724                 break;
 725         }
 726
 727         RTSX_DEBUGP("CIS block: 0x%x\n", xd_card->cis_block);
 728         if (xd_card->cis_block == 0xFFFF)
 729                 TRACE_RET(chip, STATUS_FAIL);
 730
 731         chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity;
 732
 733         return STATUS_SUCCESS;
 734 }
 735
 736 static int xd_check_data_blank(u8 *redunt)
 737 {
 738         int i;
 739
 740         for (i = 0; i < 6; i++) {
 741                 if (redunt[PAGE_STATUS + i] != 0xFF)
 742                         return 0;
 743         }
 744
 745         if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1)) != (XD_ECC1_ALL1 | XD_ECC2_ALL1))
 746                 return 0;
 747
 748
 749         for (i = 0; i < 4; i++) {
 750                 if (redunt[RESERVED0 + i] != 0xFF)
 751                         return 0;
 752         }
 753
 754         return 1;
 755 }
 756
 757 static u16 xd_load_log_block_addr(u8 *redunt)
 758 {
 759         u16 addr = 0xFFFF;
 760
 761         if (redunt[PARITY] & XD_BA1_BA2_EQL)
 762                 addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L];
 763         else if (redunt[PARITY] & XD_BA1_VALID)
 764                 addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L];
 765         else if (redunt[PARITY] & XD_BA2_VALID)
 766                 addr = ((u16)redunt[BLOCK_ADDR2_H] << 8) | redunt[BLOCK_ADDR2_L];
 767
 768         return addr;
 769 }
 770
 771 static int xd_init_l2p_tbl(struct rtsx_chip *chip)
 772 {
 773         struct xd_info *xd_card = &(chip->xd_card);
 774         int size, i;
 775
 776         RTSX_DEBUGP("xd_init_l2p_tbl: zone_cnt = %d\n", xd_card->zone_cnt);
 777
 778         if (xd_card->zone_cnt < 1)
 779                 TRACE_RET(chip, STATUS_FAIL);
 780
 781         size = xd_card->zone_cnt * sizeof(struct zone_entry);
 782         RTSX_DEBUGP("Buffer size for l2p table is %d\n", size);
 783
 784         xd_card->zone = (struct zone_entry *)vmalloc(size);
 785         if (!xd_card->zone)
 786                 TRACE_RET(chip, STATUS_ERROR);
 787
 788         for (i = 0; i < xd_card->zone_cnt; i++) {
 789                 xd_card->zone[i].build_flag = 0;
 790                 xd_card->zone[i].l2p_table = NULL;
 791                 xd_card->zone[i].free_table = NULL;
 792                 xd_card->zone[i].get_index = 0;
 793                 xd_card->zone[i].set_index = 0;
 794                 xd_card->zone[i].unused_blk_cnt = 0;
 795         }
 796
 797         return STATUS_SUCCESS;
 798 }
 799
 800 static inline void free_zone(struct zone_entry *zone)
 801 {
 802         RTSX_DEBUGP("free_zone\n");
 803
 804         if (!zone)
 805                 return;
 806
 807         zone->build_flag = 0;
 808         zone->set_index = 0;
 809         zone->get_index = 0;
 810         zone->unused_blk_cnt = 0;
 811         if (zone->l2p_table) {
 812                 vfree(zone->l2p_table);
 813                 zone->l2p_table = NULL;
 814         }
 815         if (zone->free_table) {
 816                 vfree(zone->free_table);
 817                 zone->free_table = NULL;
 818         }
 819 }
 820
 821 static void xd_set_unused_block(struct rtsx_chip *chip, u32 phy_blk)
 822 {
 823         struct xd_info *xd_card = &(chip->xd_card);
 824         struct zone_entry *zone;
 825         int zone_no;
 826
 827         zone_no = (int)phy_blk >> 10;
 828         if (zone_no >= xd_card->zone_cnt) {
 829                 RTSX_DEBUGP("Set unused block to invalid zone (zone_no = %d, zone_cnt = %d)\n",
 830                         zone_no, xd_card->zone_cnt);
 831                 return;
 832         }
 833         zone = &(xd_card->zone[zone_no]);
 834
 835         if (zone->free_table == NULL) {
 836                 if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS)
 837                         return;
 838         }
 839
 840         if ((zone->set_index >= XD_FREE_TABLE_CNT)
 841                         || (zone->set_index < 0)) {
 842                 free_zone(zone);
 843                 RTSX_DEBUGP("Set unused block fail, invalid set_index\n");
 844                 return;
 845         }
 846
 847         RTSX_DEBUGP("Set unused block to index %d\n", zone->set_index);
 848
 849         zone->free_table[zone->set_index++] = (u16) (phy_blk & 0x3ff);
 850         if (zone->set_index >= XD_FREE_TABLE_CNT)
 851                 zone->set_index = 0;
 852         zone->unused_blk_cnt++;
 853 }
 854
 855 static u32 xd_get_unused_block(struct rtsx_chip *chip, int zone_no)
 856 {
 857         struct xd_info *xd_card = &(chip->xd_card);
 858         struct zone_entry *zone;
 859         u32 phy_blk;
 860
 861         if (zone_no >= xd_card->zone_cnt) {
 862                 RTSX_DEBUGP("Get unused block from invalid zone (zone_no = %d, zone_cnt = %d)\n",
 863                         zone_no, xd_card->zone_cnt);
 864                 return BLK_NOT_FOUND;
 865         }
 866         zone = &(xd_card->zone[zone_no]);
 867
 868         if ((zone->unused_blk_cnt == 0) || (zone->set_index == zone->get_index)) {
 869                 free_zone(zone);
 870                 RTSX_DEBUGP("Get unused block fail, no unused block available\n");
 871                 return BLK_NOT_FOUND;
 872         }
 873         if ((zone->get_index >= XD_FREE_TABLE_CNT) || (zone->get_index < 0)) {
 874                 free_zone(zone);
 875                 RTSX_DEBUGP("Get unused block fail, invalid get_index\n");
 876                 return BLK_NOT_FOUND;
 877         }
 878
 879         RTSX_DEBUGP("Get unused block from index %d\n", zone->get_index);
 880
 881         phy_blk = zone->free_table[zone->get_index];
 882         zone->free_table[zone->get_index++] = 0xFFFF;
 883         if (zone->get_index >= XD_FREE_TABLE_CNT)
 884                 zone->get_index = 0;
 885         zone->unused_blk_cnt--;
 886
 887         phy_blk += ((u32)(zone_no) << 10);
 888         return phy_blk;
 889 }
 890
 891 static void xd_set_l2p_tbl(struct rtsx_chip *chip, int zone_no, u16 log_off, u16 phy_off)
 892 {
 893         struct xd_info *xd_card = &(chip->xd_card);
 894         struct zone_entry *zone;
 895
 896         zone = &(xd_card->zone[zone_no]);
 897         zone->l2p_table[log_off] = phy_off;
 898 }
 899
 900 static u32 xd_get_l2p_tbl(struct rtsx_chip *chip, int zone_no, u16 log_off)
 901 {
 902         struct xd_info *xd_card = &(chip->xd_card);
 903         struct zone_entry *zone;
 904         int retval;
 905
 906         zone = &(xd_card->zone[zone_no]);
 907         if (zone->l2p_table[log_off] == 0xFFFF) {
 908                 u32 phy_blk = 0;
 909                 int i;
 910
 911 #ifdef XD_DELAY_WRITE
 912                 retval = xd_delay_write(chip);
 913                 if (retval != STATUS_SUCCESS) {
 914                         RTSX_DEBUGP("In xd_get_l2p_tbl, delay write fail!\n");
 915                         return BLK_NOT_FOUND;
 916                 }
 917 #endif
 918
 919                 if (zone->unused_blk_cnt <= 0) {
 920                         RTSX_DEBUGP("No unused block!\n");
 921                         return BLK_NOT_FOUND;
 922                 }
 923
 924                 for (i = 0; i < zone->unused_blk_cnt; i++) {
 925                         phy_blk = xd_get_unused_block(chip, zone_no);
 926                         if (phy_blk == BLK_NOT_FOUND) {
 927                                 RTSX_DEBUGP("No unused block available!\n");
 928                                 return BLK_NOT_FOUND;
 929                         }
 930
 931                         retval = xd_init_page(chip, phy_blk, log_off, 0, xd_card->page_off + 1);
 932                         if (retval == STATUS_SUCCESS)
 933                                 break;
 934                 }
 935                 if (i >= zone->unused_blk_cnt) {
 936                         RTSX_DEBUGP("No good unused block available!\n");
 937                         return BLK_NOT_FOUND;
 938                 }
 939
 940                 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(phy_blk & 0x3FF));
 941                 return phy_blk;
 942         }
 943
 944         return (u32)zone->l2p_table[log_off] + ((u32)(zone_no) << 10);
 945 }
 946
 947 int reset_xd_card(struct rtsx_chip *chip)
 948 {
 949         struct xd_info *xd_card = &(chip->xd_card);
 950         int retval;
 951
 952         memset(xd_card, 0, sizeof(struct xd_info));
 953
 954         xd_card->block_shift = 0;
 955         xd_card->page_off = 0;
 956         xd_card->addr_cycle = 0;
 957         xd_card->capacity = 0;
 958         xd_card->zone_cnt = 0;
 959         xd_card->cis_block = 0xFFFF;
 960         xd_card->delay_write.delay_write_flag = 0;
 961
 962         retval = enable_card_clock(chip, XD_CARD);
 963         if (retval != STATUS_SUCCESS)
 964                 TRACE_RET(chip, STATUS_FAIL);
 965
 966         retval = reset_xd(chip);
 967         if (retval != STATUS_SUCCESS)
 968                 TRACE_RET(chip, STATUS_FAIL);
 969
 970         retval = xd_init_l2p_tbl(chip);
 971         if (retval != STATUS_SUCCESS)
 972                 TRACE_RET(chip, STATUS_FAIL);
 973
 974         return STATUS_SUCCESS;
 975 }
 976
 977 static int xd_mark_bad_block(struct rtsx_chip *chip, u32 phy_blk)
 978 {
 979         struct xd_info *xd_card = &(chip->xd_card);
 980         int retval;
 981         u32 page_addr;
 982         u8 reg = 0;
 983
 984         RTSX_DEBUGP("mark block 0x%x as bad block\n", phy_blk);
 985
 986         if (phy_blk == BLK_NOT_FOUND)
 987                 TRACE_RET(chip, STATUS_FAIL);
 988
 989         rtsx_init_cmd(chip);
 990
 991         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
 992         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_LATER_BBLK);
 993         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF);
 994         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF);
 995         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF);
 996         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF);
 997         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF);
 998         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF);
 999         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF);
1000         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF);
1001
1002         page_addr = phy_blk << xd_card->block_shift;
1003
1004         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1005
1006         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, xd_card->page_off + 1);
1007
1008         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1009         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1010
1011         retval = rtsx_send_cmd(chip, XD_CARD, 500);
1012         if (retval < 0) {
1013                 rtsx_clear_xd_error(chip);
1014                 rtsx_read_register(chip, XD_DAT, &reg);
1015                 if (reg & PROGRAM_ERROR)
1016                         xd_set_err_code(chip, XD_PRG_ERROR);
1017                 else
1018                         xd_set_err_code(chip, XD_TO_ERROR);
1019                 TRACE_RET(chip, STATUS_FAIL);
1020         }
1021
1022         return STATUS_SUCCESS;
1023 }
1024
1025 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, u16 logoff, u8 start_page, u8 end_page)
1026 {
1027         struct xd_info *xd_card = &(chip->xd_card);
1028         int retval;
1029         u32 page_addr;
1030         u8 reg = 0;
1031
1032         RTSX_DEBUGP("Init block 0x%x\n", phy_blk);
1033
1034         if (start_page > end_page)
1035                 TRACE_RET(chip, STATUS_FAIL);
1036         if (phy_blk == BLK_NOT_FOUND)
1037                 TRACE_RET(chip, STATUS_FAIL);
1038
1039         rtsx_init_cmd(chip);
1040
1041         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF);
1042         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF);
1043         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, (u8)(logoff >> 8));
1044         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)logoff);
1045
1046         page_addr = (phy_blk << xd_card->block_shift) + start_page;
1047
1048         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1049
1050         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM, XD_BA_TRANSFORM);
1051
1052         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, (end_page - start_page));
1053
1054         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1055         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1056
1057         retval = rtsx_send_cmd(chip, XD_CARD, 500);
1058         if (retval < 0) {
1059                 rtsx_clear_xd_error(chip);
1060                 rtsx_read_register(chip, XD_DAT, &reg);
1061                 if (reg & PROGRAM_ERROR) {
1062                         xd_mark_bad_block(chip, phy_blk);
1063                         xd_set_err_code(chip, XD_PRG_ERROR);
1064                 } else {
1065                         xd_set_err_code(chip, XD_TO_ERROR);
1066                 }
1067                 TRACE_RET(chip, STATUS_FAIL);
1068         }
1069
1070         return STATUS_SUCCESS;
1071 }
1072
1073 static int xd_copy_page(struct rtsx_chip *chip, u32 old_blk, u32 new_blk, u8 start_page, u8 end_page)
1074 {
1075         struct xd_info *xd_card = &(chip->xd_card);
1076         u32 old_page, new_page;
1077         u8 i, reg = 0;
1078         int retval;
1079
1080         RTSX_DEBUGP("Copy page from block 0x%x to block 0x%x\n", old_blk, new_blk);
1081
1082         if (start_page > end_page)
1083                 TRACE_RET(chip, STATUS_FAIL);
1084
1085         if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND))
1086                 TRACE_RET(chip, STATUS_FAIL);
1087
1088         old_page = (old_blk << xd_card->block_shift) + start_page;
1089         new_page = (new_blk << xd_card->block_shift) + start_page;
1090
1091         XD_CLR_BAD_NEWBLK(xd_card);
1092
1093         RTSX_WRITE_REG(chip, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
1094
1095         for (i = start_page; i < end_page; i++) {
1096                 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1097                         rtsx_clear_xd_error(chip);
1098                         xd_set_err_code(chip, XD_NO_CARD);
1099                         TRACE_RET(chip, STATUS_FAIL);
1100                 }
1101
1102                 rtsx_init_cmd(chip);
1103
1104                 xd_assign_phy_addr(chip, old_page, XD_RW_ADDR);
1105
1106                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1107                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS, 0);
1108                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_PAGES);
1109                 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1110
1111                 retval = rtsx_send_cmd(chip, XD_CARD, 500);
1112                 if (retval < 0) {
1113                         rtsx_clear_xd_error(chip);
1114                         reg = 0;
1115                         rtsx_read_register(chip, XD_CTL, &reg);
1116                         if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) {
1117                                 wait_timeout(100);
1118
1119                                 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1120                                         xd_set_err_code(chip, XD_NO_CARD);
1121                                         TRACE_RET(chip, STATUS_FAIL);
1122                                 }
1123
1124                                 if (((reg & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) ==
1125                                                 (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1126                                         || ((reg & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) ==
1127                                                 (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1128                                         rtsx_write_register(chip, XD_PAGE_STATUS, 0xFF, XD_BPG);
1129                                         rtsx_write_register(chip, XD_BLOCK_STATUS, 0xFF, XD_GBLK);
1130                                         XD_SET_BAD_OLDBLK(xd_card);
1131                                         RTSX_DEBUGP("old block 0x%x ecc error\n", old_blk);
1132                                 }
1133                         } else {
1134                                 xd_set_err_code(chip, XD_TO_ERROR);
1135                                 TRACE_RET(chip, STATUS_FAIL);
1136                         }
1137                 }
1138
1139                 if (XD_CHK_BAD_OLDBLK(xd_card))
1140                         rtsx_clear_xd_error(chip);
1141
1142                 rtsx_init_cmd(chip);
1143
1144                 xd_assign_phy_addr(chip, new_page, XD_RW_ADDR);
1145                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1146                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1147                              XD_TRANSFER_START | XD_WRITE_PAGES);
1148                 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1149
1150                 retval = rtsx_send_cmd(chip, XD_CARD, 300);
1151                 if (retval < 0) {
1152                         rtsx_clear_xd_error(chip);
1153                         reg = 0;
1154                         rtsx_read_register(chip, XD_DAT, &reg);
1155                         if (reg & PROGRAM_ERROR) {
1156                                 xd_mark_bad_block(chip, new_blk);
1157                                 xd_set_err_code(chip, XD_PRG_ERROR);
1158                                 XD_SET_BAD_NEWBLK(xd_card);
1159                         } else {
1160                                 xd_set_err_code(chip, XD_TO_ERROR);
1161                         }
1162                         TRACE_RET(chip, STATUS_FAIL);
1163                 }
1164
1165                 old_page++;
1166                 new_page++;
1167         }
1168
1169         return STATUS_SUCCESS;
1170 }
1171
1172 static int xd_reset_cmd(struct rtsx_chip *chip)
1173 {
1174         int retval;
1175         u8 *ptr;
1176
1177         rtsx_init_cmd(chip);
1178
1179         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_RESET);
1180         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1181         rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1182         rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
1183
1184         retval = rtsx_send_cmd(chip, XD_CARD, 100);
1185         if (retval < 0)
1186                 TRACE_RET(chip, STATUS_FAIL);
1187
1188         ptr = rtsx_get_cmd_data(chip) + 1;
1189         if (((ptr[0] & READY_FLAG) == READY_STATE) && (ptr[1] & XD_RDY))
1190                 return STATUS_SUCCESS;
1191
1192         TRACE_RET(chip, STATUS_FAIL);
1193 }
1194
1195 static int xd_erase_block(struct rtsx_chip *chip, u32 phy_blk)
1196 {
1197         struct xd_info *xd_card = &(chip->xd_card);
1198         u32 page_addr;
1199         u8 reg = 0, *ptr;
1200         int i, retval;
1201
1202         if (phy_blk == BLK_NOT_FOUND)
1203                 TRACE_RET(chip, STATUS_FAIL);
1204
1205         page_addr = phy_blk << xd_card->block_shift;
1206
1207         for (i = 0; i < 3; i++) {
1208                 rtsx_init_cmd(chip);
1209
1210                 xd_assign_phy_addr(chip, page_addr, XD_ERASE_ADDR);
1211
1212                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_ERASE);
1213                 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1214                 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1215
1216                 retval = rtsx_send_cmd(chip, XD_CARD, 250);
1217                 if (retval < 0) {
1218                         rtsx_clear_xd_error(chip);
1219                         rtsx_read_register(chip, XD_DAT, &reg);
1220                         if (reg & PROGRAM_ERROR) {
1221                                 xd_mark_bad_block(chip, phy_blk);
1222                                 xd_set_err_code(chip, XD_PRG_ERROR);
1223                                 TRACE_RET(chip, STATUS_FAIL);
1224                         } else {
1225                                 xd_set_err_code(chip, XD_ERASE_FAIL);
1226                         }
1227                         retval = xd_reset_cmd(chip);
1228                         if (retval != STATUS_SUCCESS)
1229                                 TRACE_RET(chip, STATUS_FAIL);
1230                         continue;
1231                 }
1232
1233                 ptr = rtsx_get_cmd_data(chip) + 1;
1234                 if (*ptr & PROGRAM_ERROR) {
1235                         xd_mark_bad_block(chip, phy_blk);
1236                         xd_set_err_code(chip, XD_PRG_ERROR);
1237                         TRACE_RET(chip, STATUS_FAIL);
1238                 }
1239
1240                 return STATUS_SUCCESS;
1241         }
1242
1243         xd_mark_bad_block(chip, phy_blk);
1244         xd_set_err_code(chip, XD_ERASE_FAIL);
1245         TRACE_RET(chip, STATUS_FAIL);
1246 }
1247
1248
1249 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no)
1250 {
1251         struct xd_info *xd_card = &(chip->xd_card);
1252         struct zone_entry *zone;
1253         int retval;
1254         u32 start, end, i;
1255         u16 max_logoff, cur_fst_page_logoff, cur_lst_page_logoff, ent_lst_page_logoff;
1256         u8 redunt[11];
1257
1258         RTSX_DEBUGP("xd_build_l2p_tbl: %d\n", zone_no);
1259
1260         if (xd_card->zone == NULL) {
1261                 retval = xd_init_l2p_tbl(chip);
1262                 if (retval != STATUS_SUCCESS)
1263                         return retval;
1264         }
1265
1266         if (xd_card->zone[zone_no].build_flag) {
1267                 RTSX_DEBUGP("l2p table of zone %d has been built\n", zone_no);
1268                 return STATUS_SUCCESS;
1269         }
1270
1271         zone = &(xd_card->zone[zone_no]);
1272
1273         if (zone->l2p_table == NULL) {
1274                 zone->l2p_table = (u16 *)vmalloc(2000);
1275                 if (zone->l2p_table == NULL)
1276                         TRACE_GOTO(chip, Build_Fail);
1277         }
1278         memset((u8 *)(zone->l2p_table), 0xff, 2000);
1279
1280         if (zone->free_table == NULL) {
1281                 zone->free_table = (u16 *)vmalloc(XD_FREE_TABLE_CNT * 2);
1282                 if (zone->free_table == NULL)
1283                         TRACE_GOTO(chip, Build_Fail);
1284         }
1285         memset((u8 *)(zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2);
1286
1287         if (zone_no == 0) {
1288                 if (xd_card->cis_block == 0xFFFF)
1289                         start = 0;
1290                 else
1291                         start = xd_card->cis_block + 1;
1292                 if (XD_CHK_4MB(xd_card)) {
1293                         end = 0x200;
1294                         max_logoff = 499;
1295                 } else {
1296                         end = 0x400;
1297                         max_logoff = 999;
1298                 }
1299         } else {
1300                 start = (u32)(zone_no) << 10;
1301                 end = (u32)(zone_no + 1) << 10;
1302                 max_logoff = 999;
1303         }
1304
1305         RTSX_DEBUGP("start block 0x%x, end block 0x%x\n", start, end);
1306
1307         zone->set_index = zone->get_index = 0;
1308         zone->unused_blk_cnt = 0;
1309
1310         for (i = start; i < end; i++) {
1311                 u32 page_addr = i << xd_card->block_shift;
1312                 u32 phy_block;
1313
1314                 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1315                 if (retval != STATUS_SUCCESS)
1316                         continue;
1317
1318                 if (redunt[BLOCK_STATUS] != 0xFF) {
1319                         RTSX_DEBUGP("bad block\n");
1320                         continue;
1321                 }
1322
1323                 if (xd_check_data_blank(redunt)) {
1324                         RTSX_DEBUGP("blank block\n");
1325                         xd_set_unused_block(chip, i);
1326                         continue;
1327                 }
1328
1329                 cur_fst_page_logoff = xd_load_log_block_addr(redunt);
1330                 if ((cur_fst_page_logoff == 0xFFFF) || (cur_fst_page_logoff > max_logoff)) {
1331                         retval = xd_erase_block(chip, i);
1332                         if (retval == STATUS_SUCCESS)
1333                                 xd_set_unused_block(chip, i);
1334                         continue;
1335                 }
1336
1337                 if ((zone_no == 0) && (cur_fst_page_logoff == 0) && (redunt[PAGE_STATUS] != XD_GPG))
1338                         XD_SET_MBR_FAIL(xd_card);
1339
1340                 if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) {
1341                         zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF);
1342                         continue;
1343                 }
1344
1345                 phy_block = zone->l2p_table[cur_fst_page_logoff] + ((u32)((zone_no) << 10));
1346
1347                 page_addr = ((i + 1) << xd_card->block_shift) - 1;
1348
1349                 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1350                 if (retval != STATUS_SUCCESS)
1351                         continue;
1352
1353                 cur_lst_page_logoff = xd_load_log_block_addr(redunt);
1354                 if (cur_lst_page_logoff == cur_fst_page_logoff) {
1355                         int m;
1356
1357                         page_addr = ((phy_block + 1) << xd_card->block_shift) - 1;
1358
1359                         for (m = 0; m < 3; m++) {
1360                                 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1361                                 if (retval == STATUS_SUCCESS)
1362                                         break;
1363                         }
1364
1365                         if (m == 3) {
1366                                 zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF);
1367                                 retval = xd_erase_block(chip, phy_block);
1368                                 if (retval == STATUS_SUCCESS)
1369                                         xd_set_unused_block(chip, phy_block);
1370                                 continue;
1371                         }
1372
1373                         ent_lst_page_logoff = xd_load_log_block_addr(redunt);
1374                         if (ent_lst_page_logoff != cur_fst_page_logoff) {
1375                                 zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF);
1376                                 retval = xd_erase_block(chip, phy_block);
1377                                 if (retval == STATUS_SUCCESS)
1378                                         xd_set_unused_block(chip, phy_block);
1379                                 continue;
1380                         } else {
1381                                 retval = xd_erase_block(chip, i);
1382                                 if (retval == STATUS_SUCCESS)
1383                                         xd_set_unused_block(chip, i);
1384                         }
1385                 } else {
1386                         retval = xd_erase_block(chip, i);
1387                         if (retval == STATUS_SUCCESS)
1388                                 xd_set_unused_block(chip, i);
1389                 }
1390         }
1391
1392         if (XD_CHK_4MB(xd_card))
1393                 end = 500;
1394         else
1395                 end = 1000;
1396
1397         i = 0;
1398         for (start = 0; start < end; start++) {
1399                 if (zone->l2p_table[start] == 0xFFFF)
1400                         i++;
1401         }
1402
1403         RTSX_DEBUGP("Block count %d, invalid L2P entry %d\n", end, i);
1404         RTSX_DEBUGP("Total unused block: %d\n", zone->unused_blk_cnt);
1405
1406         if ((zone->unused_blk_cnt - i) < 1)
1407                 chip->card_wp |= XD_CARD;
1408
1409         zone->build_flag = 1;
1410
1411         return STATUS_SUCCESS;
1412
1413 Build_Fail:
1414         if (zone->l2p_table) {
1415                 vfree(zone->l2p_table);
1416                 zone->l2p_table = NULL;
1417         }
1418         if (zone->free_table) {
1419                 vfree(zone->free_table);
1420                 zone->free_table = NULL;
1421         }
1422
1423         return STATUS_FAIL;
1424 }
1425
1426 static int xd_send_cmd(struct rtsx_chip *chip, u8 cmd)
1427 {
1428         int retval;
1429
1430         rtsx_init_cmd(chip);
1431
1432         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd);
1433         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_SET_CMD);
1434         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1435
1436         retval = rtsx_send_cmd(chip, XD_CARD, 200);
1437         if (retval < 0)
1438                 TRACE_RET(chip, STATUS_FAIL);
1439
1440         return STATUS_SUCCESS;
1441 }
1442
1443 static int xd_read_multiple_pages(struct rtsx_chip *chip, u32 phy_blk, u32 log_blk,
1444                 u8 start_page, u8 end_page, u8 *buf, unsigned int *index, unsigned int *offset)
1445 {
1446         struct xd_info *xd_card = &(chip->xd_card);
1447         u32 page_addr, new_blk;
1448         u16 log_off;
1449         u8 reg_val, page_cnt;
1450         int zone_no, retval, i;
1451
1452         if (start_page > end_page)
1453                 TRACE_RET(chip, STATUS_FAIL);
1454
1455         page_cnt = end_page - start_page;
1456         zone_no = (int)(log_blk / 1000);
1457         log_off = (u16)(log_blk % 1000);
1458
1459         if ((phy_blk & 0x3FF) == 0x3FF) {
1460                 for (i = 0; i < 256; i++) {
1461                         page_addr = ((u32)i) << xd_card->block_shift;
1462
1463                         retval = xd_read_redundant(chip, page_addr, NULL, 0);
1464                         if (retval == STATUS_SUCCESS)
1465                                 break;
1466
1467                         if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1468                                 xd_set_err_code(chip, XD_NO_CARD);
1469                                 TRACE_RET(chip, STATUS_FAIL);
1470                         }
1471                 }
1472         }
1473
1474         page_addr = (phy_blk << xd_card->block_shift) + start_page;
1475
1476         rtsx_init_cmd(chip);
1477
1478         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1479         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE, XD_PPB_TO_SIE);
1480         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1481         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1482         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1483                         XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
1484
1485         trans_dma_enable(chip->srb->sc_data_direction, chip, page_cnt * 512, DMA_512);
1486
1487         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_PAGES);
1488         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1489                      XD_TRANSFER_END | XD_PPB_EMPTY, XD_TRANSFER_END | XD_PPB_EMPTY);
1490
1491         rtsx_send_cmd_no_wait(chip);
1492
1493         retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512, scsi_sg_count(chip->srb),
1494                         index, offset, DMA_FROM_DEVICE, chip->xd_timeout);
1495         if (retval < 0) {
1496                 rtsx_clear_xd_error(chip);
1497                 xd_clear_dma_buffer(chip);
1498
1499                 if (retval == -ETIMEDOUT) {
1500                         xd_set_err_code(chip, XD_TO_ERROR);
1501                         TRACE_RET(chip, STATUS_FAIL);
1502                 } else {
1503                         TRACE_GOTO(chip, Fail);
1504                 }
1505         }
1506
1507         return STATUS_SUCCESS;
1508
1509 Fail:
1510         RTSX_READ_REG(chip, XD_PAGE_STATUS, &reg_val);
1511
1512         if (reg_val !=  XD_GPG)
1513                 xd_set_err_code(chip, XD_PRG_ERROR);
1514
1515         RTSX_READ_REG(chip, XD_CTL, &reg_val);
1516
1517         if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1518                                 == (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1519                 || ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))
1520                         == (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1521                 wait_timeout(100);
1522
1523                 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1524                         xd_set_err_code(chip, XD_NO_CARD);
1525                         TRACE_RET(chip, STATUS_FAIL);
1526                 }
1527
1528                 xd_set_err_code(chip, XD_ECC_ERROR);
1529
1530                 new_blk = xd_get_unused_block(chip, zone_no);
1531                 if (new_blk == NO_NEW_BLK) {
1532                         XD_CLR_BAD_OLDBLK(xd_card);
1533                         TRACE_RET(chip, STATUS_FAIL);
1534                 }
1535
1536                 retval = xd_copy_page(chip, phy_blk, new_blk, 0, xd_card->page_off + 1);
1537                 if (retval != STATUS_SUCCESS) {
1538                         if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1539                                 retval = xd_erase_block(chip, new_blk);
1540                                 if (retval == STATUS_SUCCESS)
1541                                         xd_set_unused_block(chip, new_blk);
1542                         } else {
1543                                 XD_CLR_BAD_NEWBLK(xd_card);
1544                         }
1545                         XD_CLR_BAD_OLDBLK(xd_card);
1546                         TRACE_RET(chip, STATUS_FAIL);
1547                 }
1548                 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1549                 xd_erase_block(chip, phy_blk);
1550                 xd_mark_bad_block(chip, phy_blk);
1551                 XD_CLR_BAD_OLDBLK(xd_card);
1552         }
1553
1554         TRACE_RET(chip, STATUS_FAIL);
1555 }
1556
1557 static int xd_finish_write(struct rtsx_chip *chip,
1558                 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1559 {
1560         struct xd_info *xd_card = &(chip->xd_card);
1561         int retval, zone_no;
1562         u16 log_off;
1563
1564         RTSX_DEBUGP("xd_finish_write, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n",
1565                                 old_blk, new_blk, log_blk);
1566
1567         if (page_off > xd_card->page_off)
1568                 TRACE_RET(chip, STATUS_FAIL);
1569
1570         zone_no = (int)(log_blk / 1000);
1571         log_off = (u16)(log_blk % 1000);
1572
1573         if (old_blk == BLK_NOT_FOUND) {
1574                 retval = xd_init_page(chip, new_blk, log_off,
1575                                 page_off, xd_card->page_off + 1);
1576                 if (retval != STATUS_SUCCESS) {
1577                         retval = xd_erase_block(chip, new_blk);
1578                         if (retval == STATUS_SUCCESS)
1579                                 xd_set_unused_block(chip, new_blk);
1580                         TRACE_RET(chip, STATUS_FAIL);
1581                 }
1582         } else {
1583                 retval = xd_copy_page(chip, old_blk, new_blk,
1584                                 page_off, xd_card->page_off + 1);
1585                 if (retval != STATUS_SUCCESS) {
1586                         if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1587                                 retval = xd_erase_block(chip, new_blk);
1588                                 if (retval == STATUS_SUCCESS)
1589                                         xd_set_unused_block(chip, new_blk);
1590                         }
1591                         XD_CLR_BAD_NEWBLK(xd_card);
1592                         TRACE_RET(chip, STATUS_FAIL);
1593                 }
1594
1595                 retval = xd_erase_block(chip, old_blk);
1596                 if (retval == STATUS_SUCCESS) {
1597                         if (XD_CHK_BAD_OLDBLK(xd_card)) {
1598                                 xd_mark_bad_block(chip, old_blk);
1599                                 XD_CLR_BAD_OLDBLK(xd_card);
1600                         } else {
1601                                 xd_set_unused_block(chip, old_blk);
1602                         }
1603                 } else {
1604                         xd_set_err_code(chip, XD_NO_ERROR);
1605                         XD_CLR_BAD_OLDBLK(xd_card);
1606                 }
1607         }
1608
1609         xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1610
1611         return STATUS_SUCCESS;
1612 }
1613
1614 static int xd_prepare_write(struct rtsx_chip *chip,
1615                 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1616 {
1617         int retval;
1618
1619         RTSX_DEBUGP("%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x, page_off = %d\n",
1620                                 __func__, old_blk, new_blk, log_blk, (int)page_off);
1621
1622         if (page_off) {
1623                 retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off);
1624                 if (retval != STATUS_SUCCESS)
1625                         TRACE_RET(chip, STATUS_FAIL);
1626         }
1627
1628         return STATUS_SUCCESS;
1629 }
1630
1631
1632 static int xd_write_multiple_pages(struct rtsx_chip *chip, u32 old_blk, u32 new_blk, u32 log_blk,
1633                 u8 start_page, u8 end_page, u8 *buf, unsigned int *index, unsigned int *offset)
1634 {
1635         struct xd_info *xd_card = &(chip->xd_card);
1636         u32 page_addr;
1637         int zone_no, retval;
1638         u16 log_off;
1639         u8 page_cnt, reg_val;
1640
1641         RTSX_DEBUGP("%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n",
1642                                 __func__, old_blk, new_blk, log_blk);
1643
1644         if (start_page > end_page)
1645                 TRACE_RET(chip, STATUS_FAIL);
1646
1647         page_cnt = end_page - start_page;
1648         zone_no = (int)(log_blk / 1000);
1649         log_off = (u16)(log_blk % 1000);
1650
1651         page_addr = (new_blk << xd_card->block_shift) + start_page;
1652
1653         retval = xd_send_cmd(chip, READ1_1);
1654         if (retval != STATUS_SUCCESS)
1655                 TRACE_RET(chip, STATUS_FAIL);
1656
1657         rtsx_init_cmd(chip);
1658
1659         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, (u8)(log_off >> 8));
1660         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)log_off);
1661         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK);
1662         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1663
1664         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1665
1666         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM, XD_BA_TRANSFORM);
1667         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1668         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1669
1670         trans_dma_enable(chip->srb->sc_data_direction, chip, page_cnt * 512, DMA_512);
1671
1672         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_WRITE_PAGES);
1673         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1674
1675         rtsx_send_cmd_no_wait(chip);
1676
1677         retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512, scsi_sg_count(chip->srb),
1678                         index, offset, DMA_TO_DEVICE, chip->xd_timeout);
1679         if (retval < 0) {
1680                 rtsx_clear_xd_error(chip);
1681
1682                 if (retval == -ETIMEDOUT) {
1683                         xd_set_err_code(chip, XD_TO_ERROR);
1684                         TRACE_RET(chip, STATUS_FAIL);
1685                 } else {
1686                         TRACE_GOTO(chip, Fail);
1687                 }
1688         }
1689
1690         if (end_page == (xd_card->page_off + 1)) {
1691                 xd_card->delay_write.delay_write_flag = 0;
1692
1693                 if (old_blk != BLK_NOT_FOUND) {
1694                         retval = xd_erase_block(chip, old_blk);
1695                         if (retval == STATUS_SUCCESS) {
1696                                 if (XD_CHK_BAD_OLDBLK(xd_card)) {
1697                                         xd_mark_bad_block(chip, old_blk);
1698                                         XD_CLR_BAD_OLDBLK(xd_card);
1699                                 } else {
1700                                         xd_set_unused_block(chip, old_blk);
1701                                 }
1702                         } else {
1703                                 xd_set_err_code(chip, XD_NO_ERROR);
1704                                 XD_CLR_BAD_OLDBLK(xd_card);
1705                         }
1706                 }
1707                 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1708         }
1709
1710         return STATUS_SUCCESS;
1711
1712 Fail:
1713         RTSX_READ_REG(chip, XD_DAT, &reg_val);
1714         if (reg_val & PROGRAM_ERROR) {
1715                 xd_set_err_code(chip, XD_PRG_ERROR);
1716                 xd_mark_bad_block(chip, new_blk);
1717         }
1718
1719         TRACE_RET(chip, STATUS_FAIL);
1720 }
1721
1722 #ifdef XD_DELAY_WRITE
1723 int xd_delay_write(struct rtsx_chip *chip)
1724 {
1725         struct xd_info *xd_card = &(chip->xd_card);
1726         struct xd_delay_write_tag *delay_write = &(xd_card->delay_write);
1727         int retval;
1728
1729         if (delay_write->delay_write_flag) {
1730                 RTSX_DEBUGP("xd_delay_write\n");
1731                 retval = xd_switch_clock(chip);
1732                 if (retval != STATUS_SUCCESS)
1733                         TRACE_RET(chip, STATUS_FAIL);
1734
1735                 delay_write->delay_write_flag = 0;
1736                 retval = xd_finish_write(chip,
1737                                 delay_write->old_phyblock, delay_write->new_phyblock,
1738                                 delay_write->logblock, delay_write->pageoff);
1739                 if (retval != STATUS_SUCCESS)
1740                         TRACE_RET(chip, STATUS_FAIL);
1741         }
1742
1743         return STATUS_SUCCESS;
1744 }
1745 #endif
1746
1747 int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt)
1748 {
1749         struct xd_info *xd_card = &(chip->xd_card);
1750         unsigned int lun = SCSI_LUN(srb);
1751 #ifdef XD_DELAY_WRITE
1752         struct xd_delay_write_tag *delay_write = &(xd_card->delay_write);
1753 #endif
1754         int retval, zone_no;
1755         unsigned int index = 0, offset = 0;
1756         u32 log_blk, old_blk = 0, new_blk = 0;
1757         u16 log_off, total_sec_cnt = sector_cnt;
1758         u8 start_page, end_page = 0, page_cnt;
1759         u8 *ptr;
1760
1761         xd_set_err_code(chip, XD_NO_ERROR);
1762
1763         xd_card->cleanup_counter = 0;
1764
1765         RTSX_DEBUGP("xd_rw: scsi_sg_count = %d\n", scsi_sg_count(srb));
1766
1767         ptr = (u8 *)scsi_sglist(srb);
1768
1769         retval = xd_switch_clock(chip);
1770         if (retval != STATUS_SUCCESS)
1771                 TRACE_RET(chip, STATUS_FAIL);
1772
1773
1774         if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1775                 chip->card_fail |= XD_CARD;
1776                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1777                 TRACE_RET(chip, STATUS_FAIL);
1778         }
1779
1780         log_blk = start_sector >> xd_card->block_shift;
1781         start_page = (u8)start_sector & xd_card->page_off;
1782         zone_no = (int)(log_blk / 1000);
1783         log_off = (u16)(log_blk % 1000);
1784
1785         if (xd_card->zone[zone_no].build_flag == 0) {
1786                 retval = xd_build_l2p_tbl(chip, zone_no);
1787                 if (retval != STATUS_SUCCESS) {
1788                         chip->card_fail |= XD_CARD;
1789                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1790                         TRACE_RET(chip, STATUS_FAIL);
1791                 }
1792         }
1793
1794         if (srb->sc_data_direction == DMA_TO_DEVICE) {
1795 #ifdef XD_DELAY_WRITE
1796                 if (delay_write->delay_write_flag &&
1797                                 (delay_write->logblock == log_blk) &&
1798                                 (start_page > delay_write->pageoff)) {
1799                         delay_write->delay_write_flag = 0;
1800                         if (delay_write->old_phyblock != BLK_NOT_FOUND) {
1801                                 retval = xd_copy_page(chip,
1802                                         delay_write->old_phyblock,
1803                                         delay_write->new_phyblock,
1804                                         delay_write->pageoff, start_page);
1805                                 if (retval != STATUS_SUCCESS) {
1806                                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1807                                         TRACE_RET(chip, STATUS_FAIL);
1808                                 }
1809                         }
1810                         old_blk = delay_write->old_phyblock;
1811                         new_blk = delay_write->new_phyblock;
1812                 } else if (delay_write->delay_write_flag &&
1813                                 (delay_write->logblock == log_blk) &&
1814                                 (start_page == delay_write->pageoff)) {
1815                         delay_write->delay_write_flag = 0;
1816                         old_blk = delay_write->old_phyblock;
1817                         new_blk = delay_write->new_phyblock;
1818                 } else {
1819                         retval = xd_delay_write(chip);
1820                         if (retval != STATUS_SUCCESS) {
1821                                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1822                                 TRACE_RET(chip, STATUS_FAIL);
1823                         }
1824 #endif
1825                         old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1826                         new_blk  = xd_get_unused_block(chip, zone_no);
1827                         if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND)) {
1828                                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1829                                 TRACE_RET(chip, STATUS_FAIL);
1830                         }
1831
1832                         retval = xd_prepare_write(chip, old_blk, new_blk, log_blk, start_page);
1833                         if (retval != STATUS_SUCCESS) {
1834                                 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1835                                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1836                                         TRACE_RET(chip, STATUS_FAIL);
1837                                 }
1838                                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1839                                 TRACE_RET(chip, STATUS_FAIL);
1840                         }
1841 #ifdef XD_DELAY_WRITE
1842                 }
1843 #endif
1844         } else {
1845 #ifdef XD_DELAY_WRITE
1846                 retval = xd_delay_write(chip);
1847                 if (retval != STATUS_SUCCESS) {
1848                         if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1849                                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1850                                 TRACE_RET(chip, STATUS_FAIL);
1851                         }
1852                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1853                         TRACE_RET(chip, STATUS_FAIL);
1854                 }
1855 #endif
1856
1857                 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1858                 if (old_blk == BLK_NOT_FOUND) {
1859                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1860                         TRACE_RET(chip, STATUS_FAIL);
1861                 }
1862         }
1863
1864         RTSX_DEBUGP("old_blk = 0x%x\n", old_blk);
1865
1866         while (total_sec_cnt) {
1867                 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1868                         chip->card_fail |= XD_CARD;
1869                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1870                         TRACE_RET(chip, STATUS_FAIL);
1871                 }
1872
1873                 if ((start_page + total_sec_cnt) > (xd_card->page_off + 1))
1874                         end_page = xd_card->page_off + 1;
1875                 else
1876                         end_page = start_page + (u8)total_sec_cnt;
1877
1878                 page_cnt = end_page - start_page;
1879                 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
1880                         retval = xd_read_multiple_pages(chip, old_blk, log_blk,
1881                                         start_page, end_page, ptr, &index, &offset);
1882                         if (retval != STATUS_SUCCESS) {
1883                                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1884                                 TRACE_RET(chip, STATUS_FAIL);
1885                         }
1886                 } else {
1887                         retval = xd_write_multiple_pages(chip, old_blk, new_blk, log_blk,
1888                                         start_page, end_page, ptr, &index, &offset);
1889                         if (retval != STATUS_SUCCESS) {
1890                                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1891                                 TRACE_RET(chip, STATUS_FAIL);
1892                         }
1893                 }
1894
1895                 total_sec_cnt -= page_cnt;
1896                 if (scsi_sg_count(srb) == 0)
1897                         ptr += page_cnt * 512;
1898
1899                 if (total_sec_cnt == 0)
1900                         break;
1901
1902                 log_blk++;
1903                 zone_no = (int)(log_blk / 1000);
1904                 log_off = (u16)(log_blk % 1000);
1905
1906                 if (xd_card->zone[zone_no].build_flag == 0) {
1907                         retval = xd_build_l2p_tbl(chip, zone_no);
1908                         if (retval != STATUS_SUCCESS) {
1909                                 chip->card_fail |= XD_CARD;
1910                                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1911                                 TRACE_RET(chip, STATUS_FAIL);
1912                         }
1913                 }
1914
1915                 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1916                 if (old_blk == BLK_NOT_FOUND) {
1917                         if (srb->sc_data_direction == DMA_FROM_DEVICE)
1918                                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1919                         else
1920                                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1921
1922                         TRACE_RET(chip, STATUS_FAIL);
1923                 }
1924
1925                 if (srb->sc_data_direction == DMA_TO_DEVICE) {
1926                         new_blk = xd_get_unused_block(chip, zone_no);
1927                         if (new_blk == BLK_NOT_FOUND) {
1928                                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1929                                 TRACE_RET(chip, STATUS_FAIL);
1930                         }
1931                 }
1932
1933                 start_page = 0;
1934         }
1935
1936         if ((srb->sc_data_direction == DMA_TO_DEVICE) &&
1937                         (end_page != (xd_card->page_off + 1))) {
1938 #ifdef XD_DELAY_WRITE
1939                 delay_write->delay_write_flag = 1;
1940                 delay_write->old_phyblock = old_blk;
1941                 delay_write->new_phyblock = new_blk;
1942                 delay_write->logblock = log_blk;
1943                 delay_write->pageoff = end_page;
1944 #else
1945                 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1946                         chip->card_fail |= XD_CARD;
1947                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1948                         TRACE_RET(chip, STATUS_FAIL);
1949                 }
1950
1951                 retval = xd_finish_write(chip, old_blk, new_blk, log_blk, end_page);
1952                 if (retval != STATUS_SUCCESS) {
1953                         if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1954                                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1955                                 TRACE_RET(chip, STATUS_FAIL);
1956                         }
1957                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1958                         TRACE_RET(chip, STATUS_FAIL);
1959                 }
1960 #endif
1961         }
1962
1963         scsi_set_resid(srb, 0);
1964
1965         return STATUS_SUCCESS;
1966 }
1967
1968 void xd_free_l2p_tbl(struct rtsx_chip *chip)
1969 {
1970         struct xd_info *xd_card = &(chip->xd_card);
1971         int i = 0;
1972
1973         if (xd_card->zone != NULL) {
1974                 for (i = 0; i < xd_card->zone_cnt; i++) {
1975                         if (xd_card->zone[i].l2p_table != NULL) {
1976                                 vfree(xd_card->zone[i].l2p_table);
1977                                 xd_card->zone[i].l2p_table = NULL;
1978                         }
1979                         if (xd_card->zone[i].free_table != NULL) {
1980                                 vfree(xd_card->zone[i].free_table);
1981                                 xd_card->zone[i].free_table = NULL;
1982                         }
1983                 }
1984                 vfree(xd_card->zone);
1985                 xd_card->zone = NULL;
1986         }
1987 }
1988
1989 void xd_cleanup_work(struct rtsx_chip *chip)
1990 {
1991 #ifdef XD_DELAY_WRITE
1992         struct xd_info *xd_card = &(chip->xd_card);
1993
1994         if (xd_card->delay_write.delay_write_flag) {
1995                 RTSX_DEBUGP("xD: delay write\n");
1996                 xd_delay_write(chip);
1997                 xd_card->cleanup_counter = 0;
1998         }
1999 #endif
2000 }
2001
2002 int xd_power_off_card3v3(struct rtsx_chip *chip)
2003 {
2004         int retval;
2005
2006         retval = disable_card_clock(chip, XD_CARD);
2007         if (retval != STATUS_SUCCESS)
2008                 TRACE_RET(chip, STATUS_FAIL);
2009
2010         RTSX_WRITE_REG(chip, CARD_OE, XD_OUTPUT_EN, 0);
2011
2012         if (!chip->ft2_fast_mode) {
2013                 retval = card_power_off(chip, XD_CARD);
2014                 if (retval != STATUS_SUCCESS)
2015                         TRACE_RET(chip, STATUS_FAIL);
2016
2017                 wait_timeout(50);
2018         }
2019
2020         if (chip->asic_code) {
2021                 retval = xd_pull_ctl_disable(chip);
2022                 if (retval != STATUS_SUCCESS)
2023                         TRACE_RET(chip, STATUS_FAIL);
2024         } else {
2025                 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF, 0xDF);
2026         }
2027
2028         return STATUS_SUCCESS;
2029 }
2030
2031 int release_xd_card(struct rtsx_chip *chip)
2032 {
2033         struct xd_info *xd_card = &(chip->xd_card);
2034         int retval;
2035
2036         RTSX_DEBUGP("release_xd_card\n");
2037
2038         chip->card_ready &= ~XD_CARD;
2039         chip->card_fail &= ~XD_CARD;
2040         chip->card_wp &= ~XD_CARD;
2041
2042         xd_card->delay_write.delay_write_flag = 0;
2043
2044         xd_free_l2p_tbl(chip);
2045
2046         retval = xd_power_off_card3v3(chip);
2047         if (retval != STATUS_SUCCESS)
2048                 TRACE_RET(chip, STATUS_FAIL);
2049
2050         return STATUS_SUCCESS;
2051 }