1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
28 #include "rtsx_transport.h"
29 #include "rtsx_scsi.h"
30 #include "rtsx_card.h"
33 static inline void ms_set_err_code(struct rtsx_chip *chip, u8 err_code)
35 struct ms_info *ms_card = &(chip->ms_card);
37 ms_card->err_code = err_code;
40 static inline int ms_check_err_code(struct rtsx_chip *chip, u8 err_code)
42 struct ms_info *ms_card = &(chip->ms_card);
44 return (ms_card->err_code == err_code);
47 static int ms_parse_err_code(struct rtsx_chip *chip)
49 TRACE_RET(chip, STATUS_FAIL);
52 static int ms_transfer_tpc(struct rtsx_chip *chip, u8 trans_mode, u8 tpc, u8 cnt, u8 cfg)
54 struct ms_info *ms_card = &(chip->ms_card);
58 RTSX_DEBUGP("ms_transfer_tpc: tpc = 0x%x\n", tpc);
62 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
63 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
64 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
65 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
67 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode);
68 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
70 rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
72 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
74 rtsx_clear_ms_error(chip);
75 ms_set_err_code(chip, MS_TO_ERROR);
76 TRACE_RET(chip, ms_parse_err_code(chip));
79 ptr = rtsx_get_cmd_data(chip) + 1;
81 if (!(tpc & 0x08)) { /* Read Packet */
82 if (*ptr & MS_CRC16_ERR) {
83 ms_set_err_code(chip, MS_CRC16_ERROR);
84 TRACE_RET(chip, ms_parse_err_code(chip));
86 } else { /* Write Packet */
87 if (CHK_MSPRO(ms_card) && !(*ptr & 0x80)) {
88 if (*ptr & (MS_INT_ERR | MS_INT_CMDNK)) {
89 ms_set_err_code(chip, MS_CMD_NK);
90 TRACE_RET(chip, ms_parse_err_code(chip));
95 if (*ptr & MS_RDY_TIMEOUT) {
96 rtsx_clear_ms_error(chip);
97 ms_set_err_code(chip, MS_TO_ERROR);
98 TRACE_RET(chip, ms_parse_err_code(chip));
101 return STATUS_SUCCESS;
104 static int ms_transfer_data(struct rtsx_chip *chip, u8 trans_mode, u8 tpc, u16 sec_cnt,
105 u8 cfg, int mode_2k, int use_sg, void *buf, int buf_len)
108 u8 val, err_code = 0;
109 enum dma_data_direction dir;
111 if (!buf || !buf_len) {
112 TRACE_RET(chip, STATUS_FAIL);
115 if (trans_mode == MS_TM_AUTO_READ) {
116 dir = DMA_FROM_DEVICE;
117 err_code = MS_FLASH_READ_ERROR;
118 } else if (trans_mode == MS_TM_AUTO_WRITE) {
120 err_code = MS_FLASH_WRITE_ERROR;
122 TRACE_RET(chip, STATUS_FAIL);
127 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
128 rtsx_add_cmd(chip, WRITE_REG_CMD,
129 MS_SECTOR_CNT_H, 0xFF, (u8)(sec_cnt >> 8));
130 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt);
131 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
134 rtsx_add_cmd(chip, WRITE_REG_CMD,
135 MS_CFG, MS_2K_SECTOR_MODE, MS_2K_SECTOR_MODE);
137 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE, 0);
140 trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512);
142 rtsx_add_cmd(chip, WRITE_REG_CMD,
143 MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode);
144 rtsx_add_cmd(chip, CHECK_REG_CMD,
145 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
147 rtsx_send_cmd_no_wait(chip);
149 retval = rtsx_transfer_data(chip, MS_CARD, buf, buf_len,
150 use_sg, dir, chip->mspro_timeout);
152 ms_set_err_code(chip, err_code);
153 if (retval == -ETIMEDOUT) {
154 retval = STATUS_TIMEDOUT;
156 retval = STATUS_FAIL;
158 TRACE_RET(chip, retval);
161 RTSX_READ_REG(chip, MS_TRANS_CFG, &val);
162 if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
163 TRACE_RET(chip, STATUS_FAIL);
166 return STATUS_SUCCESS;
169 static int ms_write_bytes(struct rtsx_chip *chip,
170 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
172 struct ms_info *ms_card = &(chip->ms_card);
175 if (!data || (data_len < cnt)) {
176 TRACE_RET(chip, STATUS_ERROR);
181 for (i = 0; i < cnt; i++) {
182 rtsx_add_cmd(chip, WRITE_REG_CMD,
183 PPBUF_BASE2 + i, 0xFF, data[i]);
186 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, 0xFF);
189 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
190 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
191 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
192 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
194 rtsx_add_cmd(chip, WRITE_REG_CMD,
195 MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_WRITE_BYTES);
196 rtsx_add_cmd(chip, CHECK_REG_CMD,
197 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
199 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
203 rtsx_read_register(chip, MS_TRANS_CFG, &val);
204 RTSX_DEBUGP("MS_TRANS_CFG: 0x%02x\n", val);
206 rtsx_clear_ms_error(chip);
209 if (val & MS_CRC16_ERR) {
210 ms_set_err_code(chip, MS_CRC16_ERROR);
211 TRACE_RET(chip, ms_parse_err_code(chip));
214 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
215 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
216 ms_set_err_code(chip, MS_CMD_NK);
217 TRACE_RET(chip, ms_parse_err_code(chip));
222 if (val & MS_RDY_TIMEOUT) {
223 ms_set_err_code(chip, MS_TO_ERROR);
224 TRACE_RET(chip, ms_parse_err_code(chip));
227 ms_set_err_code(chip, MS_TO_ERROR);
228 TRACE_RET(chip, ms_parse_err_code(chip));
231 return STATUS_SUCCESS;
234 static int ms_read_bytes(struct rtsx_chip *chip, u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
236 struct ms_info *ms_card = &(chip->ms_card);
241 TRACE_RET(chip, STATUS_ERROR);
246 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
247 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
248 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
249 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
251 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_READ_BYTES);
252 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
254 for (i = 0; i < data_len - 1; i++) {
255 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0);
258 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0, 0);
260 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1, 0, 0);
263 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
267 rtsx_read_register(chip, MS_TRANS_CFG, &val);
268 rtsx_clear_ms_error(chip);
271 if (val & MS_CRC16_ERR) {
272 ms_set_err_code(chip, MS_CRC16_ERROR);
273 TRACE_RET(chip, ms_parse_err_code(chip));
276 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
277 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
278 ms_set_err_code(chip, MS_CMD_NK);
279 TRACE_RET(chip, ms_parse_err_code(chip));
284 if (val & MS_RDY_TIMEOUT) {
285 ms_set_err_code(chip, MS_TO_ERROR);
286 TRACE_RET(chip, ms_parse_err_code(chip));
289 ms_set_err_code(chip, MS_TO_ERROR);
290 TRACE_RET(chip, ms_parse_err_code(chip));
293 ptr = rtsx_get_cmd_data(chip) + 1;
295 for (i = 0; i < data_len; i++) {
299 if ((tpc == PRO_READ_SHORT_DATA) && (data_len == 8)) {
300 RTSX_DEBUGP("Read format progress:\n");
304 return STATUS_SUCCESS;
307 static int ms_set_rw_reg_addr(struct rtsx_chip *chip,
308 u8 read_start, u8 read_cnt, u8 write_start, u8 write_cnt)
313 data[0] = read_start;
315 data[2] = write_start;
318 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
319 retval = ms_write_bytes(chip, SET_RW_REG_ADRS, 4,
320 NO_WAIT_INT, data, 4);
321 if (retval == STATUS_SUCCESS)
322 return STATUS_SUCCESS;
323 rtsx_clear_ms_error(chip);
326 TRACE_RET(chip, STATUS_FAIL);
329 static int ms_send_cmd(struct rtsx_chip *chip, u8 cmd, u8 cfg)
336 return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1);
339 static int ms_set_init_para(struct rtsx_chip *chip)
341 struct ms_info *ms_card = &(chip->ms_card);
344 if (CHK_HG8BIT(ms_card)) {
345 if (chip->asic_code) {
346 ms_card->ms_clock = chip->asic_ms_hg_clk;
348 ms_card->ms_clock = chip->fpga_ms_hg_clk;
350 } else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) {
351 if (chip->asic_code) {
352 ms_card->ms_clock = chip->asic_ms_4bit_clk;
354 ms_card->ms_clock = chip->fpga_ms_4bit_clk;
357 if (chip->asic_code) {
358 ms_card->ms_clock = chip->asic_ms_1bit_clk;
360 ms_card->ms_clock = chip->fpga_ms_1bit_clk;
364 retval = switch_clock(chip, ms_card->ms_clock);
365 if (retval != STATUS_SUCCESS) {
366 TRACE_RET(chip, STATUS_FAIL);
369 retval = select_card(chip, MS_CARD);
370 if (retval != STATUS_SUCCESS) {
371 TRACE_RET(chip, STATUS_FAIL);
374 return STATUS_SUCCESS;
377 static int ms_switch_clock(struct rtsx_chip *chip)
379 struct ms_info *ms_card = &(chip->ms_card);
382 retval = select_card(chip, MS_CARD);
383 if (retval != STATUS_SUCCESS) {
384 TRACE_RET(chip, STATUS_FAIL);
387 retval = switch_clock(chip, ms_card->ms_clock);
388 if (retval != STATUS_SUCCESS) {
389 TRACE_RET(chip, STATUS_FAIL);
392 return STATUS_SUCCESS;
395 static int ms_pull_ctl_disable(struct rtsx_chip *chip)
397 if (CHECK_PID(chip, 0x5209)) {
398 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x55);
399 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, 0x55);
400 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, 0x15);
401 } else if (CHECK_PID(chip, 0x5208)) {
402 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF,
403 MS_D1_PD | MS_D2_PD | MS_CLK_PD | MS_D6_PD);
404 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF,
405 MS_D3_PD | MS_D0_PD | MS_BS_PD | XD_D4_PD);
406 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF,
407 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
408 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF,
409 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
410 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
411 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
412 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF,
413 MS_D5_PD | MS_D4_PD);
414 } else if (CHECK_PID(chip, 0x5288)) {
415 if (CHECK_BARO_PKG(chip, QFN)) {
416 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
417 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
418 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B);
419 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69);
423 return STATUS_SUCCESS;
426 static int ms_pull_ctl_enable(struct rtsx_chip *chip)
432 if (CHECK_PID(chip, 0x5209)) {
433 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
434 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
435 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x15);
436 } else if (CHECK_PID(chip, 0x5208)) {
437 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
438 MS_D1_PD | MS_D2_PD | MS_CLK_NP | MS_D6_PD);
439 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
440 MS_D3_PD | MS_D0_PD | MS_BS_NP | XD_D4_PD);
441 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
442 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
443 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
444 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
445 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
446 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
447 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
448 MS_D5_PD | MS_D4_PD);
449 } else if (CHECK_PID(chip, 0x5288)) {
450 if (CHECK_BARO_PKG(chip, QFN)) {
451 rtsx_add_cmd(chip, WRITE_REG_CMD,
452 CARD_PULL_CTL1, 0xFF, 0x55);
453 rtsx_add_cmd(chip, WRITE_REG_CMD,
454 CARD_PULL_CTL2, 0xFF, 0x45);
455 rtsx_add_cmd(chip, WRITE_REG_CMD,
456 CARD_PULL_CTL3, 0xFF, 0x4B);
457 rtsx_add_cmd(chip, WRITE_REG_CMD,
458 CARD_PULL_CTL4, 0xFF, 0x29);
462 retval = rtsx_send_cmd(chip, MS_CARD, 100);
464 TRACE_RET(chip, STATUS_FAIL);
467 return STATUS_SUCCESS;
470 static int ms_prepare_reset(struct rtsx_chip *chip)
472 struct ms_info *ms_card = &(chip->ms_card);
476 ms_card->ms_type = 0;
477 ms_card->check_ms_flow = 0;
478 ms_card->switch_8bit_fail = 0;
479 ms_card->delay_write.delay_write_flag = 0;
481 ms_card->pro_under_formatting = 0;
483 retval = ms_power_off_card3v3(chip);
484 if (retval != STATUS_SUCCESS) {
485 TRACE_RET(chip, STATUS_FAIL);
488 if (!chip->ft2_fast_mode)
491 retval = enable_card_clock(chip, MS_CARD);
492 if (retval != STATUS_SUCCESS) {
493 TRACE_RET(chip, STATUS_FAIL);
496 if (chip->asic_code) {
497 retval = ms_pull_ctl_enable(chip);
498 if (retval != STATUS_SUCCESS) {
499 TRACE_RET(chip, STATUS_FAIL);
502 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, FPGA_MS_PULL_CTL_BIT | 0x20, 0);
505 if (!chip->ft2_fast_mode) {
506 retval = card_power_on(chip, MS_CARD);
507 if (retval != STATUS_SUCCESS) {
508 TRACE_RET(chip, STATUS_FAIL);
513 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
514 oc_mask = MS_OC_NOW | MS_OC_EVER;
516 oc_mask = SD_OC_NOW | SD_OC_EVER;
518 if (chip->ocp_stat & oc_mask) {
519 RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n",
521 TRACE_RET(chip, STATUS_FAIL);
526 RTSX_WRITE_REG(chip, CARD_OE, MS_OUTPUT_EN, MS_OUTPUT_EN);
528 if (chip->asic_code) {
529 RTSX_WRITE_REG(chip, MS_CFG, 0xFF,
530 SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT |
531 NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
533 RTSX_WRITE_REG(chip, MS_CFG, 0xFF,
534 SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT |
535 NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
537 RTSX_WRITE_REG(chip, MS_TRANS_CFG, 0xFF, NO_WAIT_INT | NO_AUTO_READ_INT_REG);
538 RTSX_WRITE_REG(chip, CARD_STOP, MS_STOP | MS_CLR_ERR, MS_STOP | MS_CLR_ERR);
540 retval = ms_set_init_para(chip);
541 if (retval != STATUS_SUCCESS) {
542 TRACE_RET(chip, STATUS_FAIL);
545 return STATUS_SUCCESS;
548 static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus)
550 struct ms_info *ms_card = &(chip->ms_card);
554 retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1);
555 if (retval != STATUS_SUCCESS) {
556 TRACE_RET(chip, STATUS_FAIL);
559 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
560 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG, 6, NO_WAIT_INT);
561 if (retval == STATUS_SUCCESS) {
565 if (i == MS_MAX_RETRY_COUNT) {
566 TRACE_RET(chip, STATUS_FAIL);
569 RTSX_READ_REG(chip, PPBUF_BASE2 + 2, &val);
570 RTSX_DEBUGP("Type register: 0x%x\n", val);
573 ms_card->check_ms_flow = 1;
575 TRACE_RET(chip, STATUS_FAIL);
578 RTSX_READ_REG(chip, PPBUF_BASE2 + 4, &val);
579 RTSX_DEBUGP("Category register: 0x%x\n", val);
581 ms_card->check_ms_flow = 1;
582 TRACE_RET(chip, STATUS_FAIL);
585 RTSX_READ_REG(chip, PPBUF_BASE2 + 5, &val);
586 RTSX_DEBUGP("Class register: 0x%x\n", val);
588 RTSX_READ_REG(chip, PPBUF_BASE2, &val);
589 if (val & WRT_PRTCT) {
590 chip->card_wp |= MS_CARD;
592 chip->card_wp &= ~MS_CARD;
594 } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) {
595 chip->card_wp |= MS_CARD;
597 ms_card->check_ms_flow = 1;
598 TRACE_RET(chip, STATUS_FAIL);
601 ms_card->ms_type |= TYPE_MSPRO;
603 RTSX_READ_REG(chip, PPBUF_BASE2 + 3, &val);
604 RTSX_DEBUGP("IF Mode register: 0x%x\n", val);
606 ms_card->ms_type &= 0x0F;
607 } else if (val == 7) {
608 if (switch_8bit_bus) {
609 ms_card->ms_type |= MS_HG;
611 ms_card->ms_type &= 0x0F;
614 TRACE_RET(chip, STATUS_FAIL);
617 return STATUS_SUCCESS;
620 static int ms_confirm_cpu_startup(struct rtsx_chip *chip)
625 /* Confirm CPU StartUp */
628 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
629 ms_set_err_code(chip, MS_NO_CARD);
630 TRACE_RET(chip, STATUS_FAIL);
633 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
634 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
635 if (retval == STATUS_SUCCESS) {
639 if (i == MS_MAX_RETRY_COUNT) {
640 TRACE_RET(chip, STATUS_FAIL);
644 TRACE_RET(chip, STATUS_FAIL);
648 } while (!(val & INT_REG_CED));
650 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
651 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
652 if (retval == STATUS_SUCCESS)
655 if (i == MS_MAX_RETRY_COUNT) {
656 TRACE_RET(chip, STATUS_FAIL);
659 if (val & INT_REG_ERR) {
660 if (val & INT_REG_CMDNK) {
661 chip->card_wp |= (MS_CARD);
663 TRACE_RET(chip, STATUS_FAIL);
666 /* -- end confirm CPU startup */
668 return STATUS_SUCCESS;
671 static int ms_switch_parallel_bus(struct rtsx_chip *chip)
676 data[0] = PARALLEL_4BIT_IF;
678 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
679 retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, data, 2);
680 if (retval == STATUS_SUCCESS)
683 if (retval != STATUS_SUCCESS) {
684 TRACE_RET(chip, STATUS_FAIL);
687 return STATUS_SUCCESS;
690 static int ms_switch_8bit_bus(struct rtsx_chip *chip)
692 struct ms_info *ms_card = &(chip->ms_card);
696 data[0] = PARALLEL_8BIT_IF;
698 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
699 retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, data, 2);
700 if (retval == STATUS_SUCCESS) {
704 if (retval != STATUS_SUCCESS) {
705 TRACE_RET(chip, STATUS_FAIL);
708 RTSX_WRITE_REG(chip, MS_CFG, 0x98, MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING);
709 ms_card->ms_type |= MS_8BIT;
710 retval = ms_set_init_para(chip);
711 if (retval != STATUS_SUCCESS) {
712 TRACE_RET(chip, STATUS_FAIL);
715 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
716 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1, NO_WAIT_INT);
717 if (retval != STATUS_SUCCESS) {
718 TRACE_RET(chip, STATUS_FAIL);
722 return STATUS_SUCCESS;
725 static int ms_pro_reset_flow(struct rtsx_chip *chip, int switch_8bit_bus)
727 struct ms_info *ms_card = &(chip->ms_card);
730 for (i = 0; i < 3; i++) {
731 retval = ms_prepare_reset(chip);
732 if (retval != STATUS_SUCCESS) {
733 TRACE_RET(chip, STATUS_FAIL);
736 retval = ms_identify_media_type(chip, switch_8bit_bus);
737 if (retval != STATUS_SUCCESS) {
738 TRACE_RET(chip, STATUS_FAIL);
741 retval = ms_confirm_cpu_startup(chip);
742 if (retval != STATUS_SUCCESS) {
743 TRACE_RET(chip, STATUS_FAIL);
746 retval = ms_switch_parallel_bus(chip);
747 if (retval != STATUS_SUCCESS) {
748 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
749 ms_set_err_code(chip, MS_NO_CARD);
750 TRACE_RET(chip, STATUS_FAIL);
758 if (retval != STATUS_SUCCESS) {
759 TRACE_RET(chip, STATUS_FAIL);
762 /* Switch MS-PRO into Parallel mode */
763 RTSX_WRITE_REG(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4);
764 RTSX_WRITE_REG(chip, MS_CFG, PUSH_TIME_ODD, PUSH_TIME_ODD);
766 retval = ms_set_init_para(chip);
767 if (retval != STATUS_SUCCESS) {
768 TRACE_RET(chip, STATUS_FAIL);
771 /* If MSPro HG Card, We shall try to switch to 8-bit bus */
772 if (CHK_MSHG(ms_card) && chip->support_ms_8bit && switch_8bit_bus) {
773 retval = ms_switch_8bit_bus(chip);
774 if (retval != STATUS_SUCCESS) {
775 ms_card->switch_8bit_fail = 1;
776 TRACE_RET(chip, STATUS_FAIL);
780 return STATUS_SUCCESS;
784 static int msxc_change_power(struct rtsx_chip *chip, u8 mode)
789 ms_cleanup_work(chip);
791 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
792 if (retval != STATUS_SUCCESS) {
793 TRACE_RET(chip, STATUS_FAIL);
803 retval = ms_write_bytes(chip, PRO_WRITE_REG , 6, NO_WAIT_INT, buf, 6);
804 if (retval != STATUS_SUCCESS) {
805 TRACE_RET(chip, STATUS_FAIL);
808 retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT);
809 if (retval != STATUS_SUCCESS) {
810 TRACE_RET(chip, STATUS_FAIL);
813 RTSX_READ_REG(chip, MS_TRANS_CFG, buf);
814 if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR)) {
815 TRACE_RET(chip, STATUS_FAIL);
818 return STATUS_SUCCESS;
822 static int ms_read_attribute_info(struct rtsx_chip *chip)
824 struct ms_info *ms_card = &(chip->ms_card);
826 u8 val, *buf, class_code, device_type, sub_class, data[16];
827 u16 total_blk = 0, blk_size = 0;
829 u32 xc_total_blk = 0, xc_blk_size = 0;
831 u32 sys_info_addr = 0, sys_info_size;
832 #ifdef SUPPORT_PCGL_1P18
833 u32 model_name_addr = 0, model_name_size;
834 int found_sys_info = 0, found_model_name = 0;
837 retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7);
838 if (retval != STATUS_SUCCESS) {
839 TRACE_RET(chip, STATUS_FAIL);
842 if (CHK_MS8BIT(ms_card)) {
843 data[0] = PARALLEL_8BIT_IF;
845 data[0] = PARALLEL_4BIT_IF;
856 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
857 retval = ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT, data, 8);
858 if (retval == STATUS_SUCCESS) {
862 if (retval != STATUS_SUCCESS) {
863 TRACE_RET(chip, STATUS_FAIL);
866 buf = (u8 *)rtsx_alloc_dma_buf(chip, 64 * 512, GFP_KERNEL);
868 TRACE_RET(chip, STATUS_ERROR);
871 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
872 retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT);
873 if (retval != STATUS_SUCCESS) {
876 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
877 if (retval != STATUS_SUCCESS) {
878 rtsx_free_dma_buf(chip, buf);
879 TRACE_RET(chip, STATUS_FAIL);
881 if (!(val & MS_INT_BREQ)) {
882 rtsx_free_dma_buf(chip, buf);
883 TRACE_RET(chip, STATUS_FAIL);
885 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
886 0x40, WAIT_INT, 0, 0, buf, 64 * 512);
887 if (retval == STATUS_SUCCESS) {
890 rtsx_clear_ms_error(chip);
893 if (retval != STATUS_SUCCESS) {
894 rtsx_free_dma_buf(chip, buf);
895 TRACE_RET(chip, STATUS_FAIL);
900 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
901 if (retval != STATUS_SUCCESS) {
902 rtsx_free_dma_buf(chip, buf);
903 TRACE_RET(chip, STATUS_FAIL);
906 if ((val & MS_INT_CED) || !(val & MS_INT_BREQ))
909 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, PRO_READ_LONG_DATA, 0, WAIT_INT);
910 if (retval != STATUS_SUCCESS) {
911 rtsx_free_dma_buf(chip, buf);
912 TRACE_RET(chip, STATUS_FAIL);
918 if (retval != STATUS_SUCCESS) {
919 rtsx_free_dma_buf(chip, buf);
920 TRACE_RET(chip, STATUS_FAIL);
923 if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) {
924 /* Signature code is wrong */
925 rtsx_free_dma_buf(chip, buf);
926 TRACE_RET(chip, STATUS_FAIL);
929 if ((buf[4] < 1) || (buf[4] > 12)) {
930 rtsx_free_dma_buf(chip, buf);
931 TRACE_RET(chip, STATUS_FAIL);
934 for (i = 0; i < buf[4]; i++) {
935 int cur_addr_off = 16 + i * 12;
938 if ((buf[cur_addr_off + 8] == 0x10) || (buf[cur_addr_off + 8] == 0x13))
940 if (buf[cur_addr_off + 8] == 0x10)
943 sys_info_addr = ((u32)buf[cur_addr_off + 0] << 24) |
944 ((u32)buf[cur_addr_off + 1] << 16) |
945 ((u32)buf[cur_addr_off + 2] << 8) | buf[cur_addr_off + 3];
946 sys_info_size = ((u32)buf[cur_addr_off + 4] << 24) |
947 ((u32)buf[cur_addr_off + 5] << 16) |
948 ((u32)buf[cur_addr_off + 6] << 8) | buf[cur_addr_off + 7];
949 RTSX_DEBUGP("sys_info_addr = 0x%x, sys_info_size = 0x%x\n",
950 sys_info_addr, sys_info_size);
951 if (sys_info_size != 96) {
952 rtsx_free_dma_buf(chip, buf);
953 TRACE_RET(chip, STATUS_FAIL);
955 if (sys_info_addr < 0x1A0) {
956 rtsx_free_dma_buf(chip, buf);
957 TRACE_RET(chip, STATUS_FAIL);
959 if ((sys_info_size + sys_info_addr) > 0x8000) {
960 rtsx_free_dma_buf(chip, buf);
961 TRACE_RET(chip, STATUS_FAIL);
965 if (buf[cur_addr_off + 8] == 0x13) {
966 ms_card->ms_type |= MS_XC;
969 #ifdef SUPPORT_PCGL_1P18
975 #ifdef SUPPORT_PCGL_1P18
976 if (buf[cur_addr_off + 8] == 0x15) {
977 model_name_addr = ((u32)buf[cur_addr_off + 0] << 24) |
978 ((u32)buf[cur_addr_off + 1] << 16) |
979 ((u32)buf[cur_addr_off + 2] << 8) | buf[cur_addr_off + 3];
980 model_name_size = ((u32)buf[cur_addr_off + 4] << 24) |
981 ((u32)buf[cur_addr_off + 5] << 16) |
982 ((u32)buf[cur_addr_off + 6] << 8) | buf[cur_addr_off + 7];
983 RTSX_DEBUGP("model_name_addr = 0x%x, model_name_size = 0x%x\n",
984 model_name_addr, model_name_size);
985 if (model_name_size != 48) {
986 rtsx_free_dma_buf(chip, buf);
987 TRACE_RET(chip, STATUS_FAIL);
989 if (model_name_addr < 0x1A0) {
990 rtsx_free_dma_buf(chip, buf);
991 TRACE_RET(chip, STATUS_FAIL);
993 if ((model_name_size + model_name_addr) > 0x8000) {
994 rtsx_free_dma_buf(chip, buf);
995 TRACE_RET(chip, STATUS_FAIL);
998 found_model_name = 1;
1001 if (found_sys_info && found_model_name)
1007 rtsx_free_dma_buf(chip, buf);
1008 TRACE_RET(chip, STATUS_FAIL);
1011 class_code = buf[sys_info_addr + 0];
1012 device_type = buf[sys_info_addr + 56];
1013 sub_class = buf[sys_info_addr + 46];
1015 if (CHK_MSXC(ms_card)) {
1016 xc_total_blk = ((u32)buf[sys_info_addr + 6] << 24) |
1017 ((u32)buf[sys_info_addr + 7] << 16) |
1018 ((u32)buf[sys_info_addr + 8] << 8) |
1019 buf[sys_info_addr + 9];
1020 xc_blk_size = ((u32)buf[sys_info_addr + 32] << 24) |
1021 ((u32)buf[sys_info_addr + 33] << 16) |
1022 ((u32)buf[sys_info_addr + 34] << 8) |
1023 buf[sys_info_addr + 35];
1024 RTSX_DEBUGP("xc_total_blk = 0x%x, xc_blk_size = 0x%x\n", xc_total_blk, xc_blk_size);
1026 total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7];
1027 blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3];
1028 RTSX_DEBUGP("total_blk = 0x%x, blk_size = 0x%x\n", total_blk, blk_size);
1031 total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7];
1032 blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3];
1033 RTSX_DEBUGP("total_blk = 0x%x, blk_size = 0x%x\n", total_blk, blk_size);
1036 RTSX_DEBUGP("class_code = 0x%x, device_type = 0x%x, sub_class = 0x%x\n",
1037 class_code, device_type, sub_class);
1039 memcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96);
1040 #ifdef SUPPORT_PCGL_1P18
1041 memcpy(ms_card->raw_model_name, buf + model_name_addr, 48);
1044 rtsx_free_dma_buf(chip, buf);
1047 if (CHK_MSXC(ms_card)) {
1048 if (class_code != 0x03) {
1049 TRACE_RET(chip, STATUS_FAIL);
1052 if (class_code != 0x02) {
1053 TRACE_RET(chip, STATUS_FAIL);
1057 if (class_code != 0x02) {
1058 TRACE_RET(chip, STATUS_FAIL);
1062 if (device_type != 0x00) {
1063 if ((device_type == 0x01) || (device_type == 0x02) ||
1064 (device_type == 0x03)) {
1065 chip->card_wp |= MS_CARD;
1067 TRACE_RET(chip, STATUS_FAIL);
1071 if (sub_class & 0xC0) {
1072 TRACE_RET(chip, STATUS_FAIL);
1075 RTSX_DEBUGP("class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\n",
1076 class_code, device_type, sub_class);
1079 if (CHK_MSXC(ms_card)) {
1080 chip->capacity[chip->card2lun[MS_CARD]] =
1081 ms_card->capacity = xc_total_blk * xc_blk_size;
1083 chip->capacity[chip->card2lun[MS_CARD]] =
1084 ms_card->capacity = total_blk * blk_size;
1087 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity = total_blk * blk_size;
1090 return STATUS_SUCCESS;
1093 #ifdef SUPPORT_MAGIC_GATE
1094 static int mg_set_tpc_para_sub(struct rtsx_chip *chip, int type, u8 mg_entry_num);
1097 static int reset_ms_pro(struct rtsx_chip *chip)
1099 struct ms_info *ms_card = &(chip->ms_card);
1101 #ifdef XC_POWERCLASS
1102 u8 change_power_class;
1104 if (chip->ms_power_class_en & 0x02)
1105 change_power_class = 2;
1106 else if (chip->ms_power_class_en & 0x01)
1107 change_power_class = 1;
1109 change_power_class = 0;
1112 #ifdef XC_POWERCLASS
1115 retval = ms_pro_reset_flow(chip, 1);
1116 if (retval != STATUS_SUCCESS) {
1117 if (ms_card->switch_8bit_fail) {
1118 retval = ms_pro_reset_flow(chip, 0);
1119 if (retval != STATUS_SUCCESS) {
1120 TRACE_RET(chip, STATUS_FAIL);
1123 TRACE_RET(chip, STATUS_FAIL);
1127 retval = ms_read_attribute_info(chip);
1128 if (retval != STATUS_SUCCESS) {
1129 TRACE_RET(chip, STATUS_FAIL);
1132 #ifdef XC_POWERCLASS
1133 if (CHK_HG8BIT(ms_card)) {
1134 change_power_class = 0;
1137 if (change_power_class && CHK_MSXC(ms_card)) {
1138 u8 power_class_en = chip->ms_power_class_en;
1140 RTSX_DEBUGP("power_class_en = 0x%x\n", power_class_en);
1141 RTSX_DEBUGP("change_power_class = %d\n", change_power_class);
1143 if (change_power_class) {
1144 power_class_en &= (1 << (change_power_class - 1));
1149 if (power_class_en) {
1150 u8 power_class_mode = (ms_card->raw_sys_info[46] & 0x18) >> 3;
1151 RTSX_DEBUGP("power_class_mode = 0x%x", power_class_mode);
1152 if (change_power_class > power_class_mode)
1153 change_power_class = power_class_mode;
1154 if (change_power_class) {
1155 retval = msxc_change_power(chip, change_power_class);
1156 if (retval != STATUS_SUCCESS) {
1157 change_power_class--;
1165 #ifdef SUPPORT_MAGIC_GATE
1166 retval = mg_set_tpc_para_sub(chip, 0, 0);
1167 if (retval != STATUS_SUCCESS) {
1168 TRACE_RET(chip, STATUS_FAIL);
1172 if (CHK_HG8BIT(ms_card)) {
1173 chip->card_bus_width[chip->card2lun[MS_CARD]] = 8;
1175 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
1178 return STATUS_SUCCESS;
1181 static int ms_read_status_reg(struct rtsx_chip *chip)
1186 retval = ms_set_rw_reg_addr(chip, StatusReg0, 2, 0, 0);
1187 if (retval != STATUS_SUCCESS) {
1188 TRACE_RET(chip, STATUS_FAIL);
1191 retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2);
1192 if (retval != STATUS_SUCCESS) {
1193 TRACE_RET(chip, STATUS_FAIL);
1196 if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) {
1197 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1198 TRACE_RET(chip, STATUS_FAIL);
1201 return STATUS_SUCCESS;
1205 static int ms_read_extra_data(struct rtsx_chip *chip,
1206 u16 block_addr, u8 page_num, u8 *buf, int buf_len)
1208 struct ms_info *ms_card = &(chip->ms_card);
1212 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6);
1213 if (retval != STATUS_SUCCESS) {
1214 TRACE_RET(chip, STATUS_FAIL);
1217 if (CHK_MS4BIT(ms_card)) {
1218 /* Parallel interface */
1221 /* Serial interface */
1225 data[2] = (u8)(block_addr >> 8);
1226 data[3] = (u8)block_addr;
1230 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1231 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
1232 if (retval == STATUS_SUCCESS)
1235 if (i == MS_MAX_RETRY_COUNT) {
1236 TRACE_RET(chip, STATUS_FAIL);
1239 ms_set_err_code(chip, MS_NO_ERROR);
1241 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1242 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1243 if (retval == STATUS_SUCCESS)
1246 if (i == MS_MAX_RETRY_COUNT) {
1247 TRACE_RET(chip, STATUS_FAIL);
1250 ms_set_err_code(chip, MS_NO_ERROR);
1251 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1252 if (retval != STATUS_SUCCESS) {
1253 TRACE_RET(chip, STATUS_FAIL);
1255 if (val & INT_REG_CMDNK) {
1256 ms_set_err_code(chip, MS_CMD_NK);
1257 TRACE_RET(chip, STATUS_FAIL);
1259 if (val & INT_REG_CED) {
1260 if (val & INT_REG_ERR) {
1261 retval = ms_read_status_reg(chip);
1262 if (retval != STATUS_SUCCESS) {
1263 TRACE_RET(chip, STATUS_FAIL);
1265 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6);
1266 if (retval != STATUS_SUCCESS) {
1267 TRACE_RET(chip, STATUS_FAIL);
1272 retval = ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT, data, MS_EXTRA_SIZE);
1273 if (retval != STATUS_SUCCESS) {
1274 TRACE_RET(chip, STATUS_FAIL);
1277 if (buf && buf_len) {
1278 if (buf_len > MS_EXTRA_SIZE)
1279 buf_len = MS_EXTRA_SIZE;
1280 memcpy(buf, data, buf_len);
1283 return STATUS_SUCCESS;
1286 static int ms_write_extra_data(struct rtsx_chip *chip,
1287 u16 block_addr, u8 page_num, u8 *buf, int buf_len)
1289 struct ms_info *ms_card = &(chip->ms_card);
1293 if (!buf || (buf_len < MS_EXTRA_SIZE)) {
1294 TRACE_RET(chip, STATUS_FAIL);
1297 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6 + MS_EXTRA_SIZE);
1298 if (retval != STATUS_SUCCESS) {
1299 TRACE_RET(chip, STATUS_FAIL);
1302 if (CHK_MS4BIT(ms_card)) {
1308 data[2] = (u8)(block_addr >> 8);
1309 data[3] = (u8)block_addr;
1313 for (i = 6; i < MS_EXTRA_SIZE + 6; i++) {
1314 data[i] = buf[i - 6];
1317 retval = ms_write_bytes(chip, WRITE_REG , (6+MS_EXTRA_SIZE), NO_WAIT_INT, data, 16);
1318 if (retval != STATUS_SUCCESS) {
1319 TRACE_RET(chip, STATUS_FAIL);
1322 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1323 if (retval != STATUS_SUCCESS) {
1324 TRACE_RET(chip, STATUS_FAIL);
1327 ms_set_err_code(chip, MS_NO_ERROR);
1328 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1329 if (retval != STATUS_SUCCESS) {
1330 TRACE_RET(chip, STATUS_FAIL);
1332 if (val & INT_REG_CMDNK) {
1333 ms_set_err_code(chip, MS_CMD_NK);
1334 TRACE_RET(chip, STATUS_FAIL);
1336 if (val & INT_REG_CED) {
1337 if (val & INT_REG_ERR) {
1338 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1339 TRACE_RET(chip, STATUS_FAIL);
1343 return STATUS_SUCCESS;
1347 static int ms_read_page(struct rtsx_chip *chip, u16 block_addr, u8 page_num)
1349 struct ms_info *ms_card = &(chip->ms_card);
1353 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6);
1354 if (retval != STATUS_SUCCESS) {
1355 TRACE_RET(chip, STATUS_FAIL);
1358 if (CHK_MS4BIT(ms_card)) {
1364 data[2] = (u8)(block_addr >> 8);
1365 data[3] = (u8)block_addr;
1369 retval = ms_write_bytes(chip, WRITE_REG , 6, NO_WAIT_INT, data, 6);
1370 if (retval != STATUS_SUCCESS) {
1371 TRACE_RET(chip, STATUS_FAIL);
1374 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1375 if (retval != STATUS_SUCCESS) {
1376 TRACE_RET(chip, STATUS_FAIL);
1379 ms_set_err_code(chip, MS_NO_ERROR);
1380 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1381 if (retval != STATUS_SUCCESS) {
1382 TRACE_RET(chip, STATUS_FAIL);
1384 if (val & INT_REG_CMDNK) {
1385 ms_set_err_code(chip, MS_CMD_NK);
1386 TRACE_RET(chip, STATUS_FAIL);
1389 if (val & INT_REG_CED) {
1390 if (val & INT_REG_ERR) {
1391 if (!(val & INT_REG_BREQ)) {
1392 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1393 TRACE_RET(chip, STATUS_FAIL);
1395 retval = ms_read_status_reg(chip);
1396 if (retval != STATUS_SUCCESS) {
1397 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1400 if (!(val & INT_REG_BREQ)) {
1401 ms_set_err_code(chip, MS_BREQ_ERROR);
1402 TRACE_RET(chip, STATUS_FAIL);
1407 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA, 0, NO_WAIT_INT);
1408 if (retval != STATUS_SUCCESS) {
1409 TRACE_RET(chip, STATUS_FAIL);
1412 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) {
1413 TRACE_RET(chip, STATUS_FAIL);
1416 return STATUS_SUCCESS;
1420 static int ms_set_bad_block(struct rtsx_chip *chip, u16 phy_blk)
1422 struct ms_info *ms_card = &(chip->ms_card);
1424 u8 val, data[8], extra[MS_EXTRA_SIZE];
1426 retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE);
1427 if (retval != STATUS_SUCCESS) {
1428 TRACE_RET(chip, STATUS_FAIL);
1431 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 7);
1432 if (retval != STATUS_SUCCESS) {
1433 TRACE_RET(chip, STATUS_FAIL);
1436 ms_set_err_code(chip, MS_NO_ERROR);
1438 if (CHK_MS4BIT(ms_card)) {
1444 data[2] = (u8)(phy_blk >> 8);
1445 data[3] = (u8)phy_blk;
1448 data[6] = extra[0] & 0x7F;
1451 retval = ms_write_bytes(chip, WRITE_REG , 7, NO_WAIT_INT, data, 7);
1452 if (retval != STATUS_SUCCESS) {
1453 TRACE_RET(chip, STATUS_FAIL);
1456 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1457 if (retval != STATUS_SUCCESS) {
1458 TRACE_RET(chip, STATUS_FAIL);
1461 ms_set_err_code(chip, MS_NO_ERROR);
1462 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1463 if (retval != STATUS_SUCCESS) {
1464 TRACE_RET(chip, STATUS_FAIL);
1467 if (val & INT_REG_CMDNK) {
1468 ms_set_err_code(chip, MS_CMD_NK);
1469 TRACE_RET(chip, STATUS_FAIL);
1472 if (val & INT_REG_CED) {
1473 if (val & INT_REG_ERR) {
1474 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1475 TRACE_RET(chip, STATUS_FAIL);
1479 return STATUS_SUCCESS;
1483 static int ms_erase_block(struct rtsx_chip *chip, u16 phy_blk)
1485 struct ms_info *ms_card = &(chip->ms_card);
1489 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6);
1490 if (retval != STATUS_SUCCESS) {
1491 TRACE_RET(chip, STATUS_FAIL);
1494 ms_set_err_code(chip, MS_NO_ERROR);
1496 if (CHK_MS4BIT(ms_card)) {
1502 data[2] = (u8)(phy_blk >> 8);
1503 data[3] = (u8)phy_blk;
1507 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
1508 if (retval != STATUS_SUCCESS) {
1509 TRACE_RET(chip, STATUS_FAIL);
1513 retval = ms_send_cmd(chip, BLOCK_ERASE, WAIT_INT);
1514 if (retval != STATUS_SUCCESS) {
1515 TRACE_RET(chip, STATUS_FAIL);
1518 ms_set_err_code(chip, MS_NO_ERROR);
1519 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1520 if (retval != STATUS_SUCCESS) {
1521 TRACE_RET(chip, STATUS_FAIL);
1524 if (val & INT_REG_CMDNK) {
1530 ms_set_err_code(chip, MS_CMD_NK);
1531 ms_set_bad_block(chip, phy_blk);
1532 TRACE_RET(chip, STATUS_FAIL);
1535 if (val & INT_REG_CED) {
1536 if (val & INT_REG_ERR) {
1537 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1538 TRACE_RET(chip, STATUS_FAIL);
1542 return STATUS_SUCCESS;
1546 static void ms_set_page_status(u16 log_blk, u8 type, u8 *extra, int extra_len)
1548 if (!extra || (extra_len < MS_EXTRA_SIZE)) {
1552 memset(extra, 0xFF, MS_EXTRA_SIZE);
1554 if (type == setPS_NG) {
1555 /* set page status as 1:NG,and block status keep 1:OK */
1558 /* set page status as 0:Data Error,and block status keep 1:OK */
1562 extra[2] = (u8)(log_blk >> 8);
1563 extra[3] = (u8)log_blk;
1566 static int ms_init_page(struct rtsx_chip *chip, u16 phy_blk, u16 log_blk, u8 start_page, u8 end_page)
1569 u8 extra[MS_EXTRA_SIZE], i;
1571 memset(extra, 0xff, MS_EXTRA_SIZE);
1573 extra[0] = 0xf8; /* Block, page OK, data erased */
1575 extra[2] = (u8)(log_blk >> 8);
1576 extra[3] = (u8)log_blk;
1578 for (i = start_page; i < end_page; i++) {
1579 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1580 ms_set_err_code(chip, MS_NO_CARD);
1581 TRACE_RET(chip, STATUS_FAIL);
1584 retval = ms_write_extra_data(chip, phy_blk, i, extra, MS_EXTRA_SIZE);
1585 if (retval != STATUS_SUCCESS) {
1586 TRACE_RET(chip, STATUS_FAIL);
1590 return STATUS_SUCCESS;
1593 static int ms_copy_page(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
1594 u16 log_blk, u8 start_page, u8 end_page)
1596 struct ms_info *ms_card = &(chip->ms_card);
1597 int retval, rty_cnt, uncorrect_flag = 0;
1598 u8 extra[MS_EXTRA_SIZE], val, i, j, data[16];
1600 RTSX_DEBUGP("Copy page from 0x%x to 0x%x, logical block is 0x%x\n",
1601 old_blk, new_blk, log_blk);
1602 RTSX_DEBUGP("start_page = %d, end_page = %d\n", start_page, end_page);
1604 retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE);
1605 if (retval != STATUS_SUCCESS) {
1606 TRACE_RET(chip, STATUS_FAIL);
1609 retval = ms_read_status_reg(chip);
1610 if (retval != STATUS_SUCCESS) {
1611 TRACE_RET(chip, STATUS_FAIL);
1614 RTSX_READ_REG(chip, PPBUF_BASE2, &val);
1616 if (val & BUF_FULL) {
1617 retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT);
1618 if (retval != STATUS_SUCCESS) {
1619 TRACE_RET(chip, STATUS_FAIL);
1622 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1623 if (retval != STATUS_SUCCESS) {
1624 TRACE_RET(chip, STATUS_FAIL);
1627 if (!(val & INT_REG_CED)) {
1628 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1629 TRACE_RET(chip, STATUS_FAIL);
1633 for (i = start_page; i < end_page; i++) {
1634 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1635 ms_set_err_code(chip, MS_NO_CARD);
1636 TRACE_RET(chip, STATUS_FAIL);
1639 ms_read_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE);
1641 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6);
1642 if (retval != STATUS_SUCCESS) {
1643 TRACE_RET(chip, STATUS_FAIL);
1646 ms_set_err_code(chip, MS_NO_ERROR);
1648 if (CHK_MS4BIT(ms_card)) {
1654 data[2] = (u8)(old_blk >> 8);
1655 data[3] = (u8)old_blk;
1659 retval = ms_write_bytes(chip, WRITE_REG , 6, NO_WAIT_INT, data, 6);
1660 if (retval != STATUS_SUCCESS) {
1661 TRACE_RET(chip, STATUS_FAIL);
1664 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1665 if (retval != STATUS_SUCCESS) {
1666 TRACE_RET(chip, STATUS_FAIL);
1669 ms_set_err_code(chip, MS_NO_ERROR);
1670 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1671 if (retval != STATUS_SUCCESS) {
1672 TRACE_RET(chip, STATUS_FAIL);
1675 if (val & INT_REG_CMDNK) {
1676 ms_set_err_code(chip, MS_CMD_NK);
1677 TRACE_RET(chip, STATUS_FAIL);
1680 if (val & INT_REG_CED) {
1681 if (val & INT_REG_ERR) {
1682 retval = ms_read_status_reg(chip);
1683 if (retval != STATUS_SUCCESS) {
1685 RTSX_DEBUGP("Uncorrectable error\n");
1690 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA, 0, NO_WAIT_INT);
1691 if (retval != STATUS_SUCCESS) {
1692 TRACE_RET(chip, STATUS_FAIL);
1695 if (uncorrect_flag) {
1696 ms_set_page_status(log_blk, setPS_NG, extra, MS_EXTRA_SIZE);
1700 ms_write_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE);
1701 RTSX_DEBUGP("page %d : extra[0] = 0x%x\n", i, extra[0]);
1702 MS_SET_BAD_BLOCK_FLG(ms_card);
1704 ms_set_page_status(log_blk, setPS_Error, extra, MS_EXTRA_SIZE);
1705 ms_write_extra_data(chip, new_blk, i, extra, MS_EXTRA_SIZE);
1709 for (rty_cnt = 0; rty_cnt < MS_MAX_RETRY_COUNT; rty_cnt++) {
1710 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_WRITE,
1711 WRITE_PAGE_DATA, 0, NO_WAIT_INT);
1712 if (retval == STATUS_SUCCESS) {
1716 if (rty_cnt == MS_MAX_RETRY_COUNT) {
1717 TRACE_RET(chip, STATUS_FAIL);
1721 if (!(val & INT_REG_BREQ)) {
1722 ms_set_err_code(chip, MS_BREQ_ERROR);
1723 TRACE_RET(chip, STATUS_FAIL);
1727 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1728 MS_EXTRA_SIZE, SystemParm, (6+MS_EXTRA_SIZE));
1730 ms_set_err_code(chip, MS_NO_ERROR);
1732 if (CHK_MS4BIT(ms_card)) {
1738 data[2] = (u8)(new_blk >> 8);
1739 data[3] = (u8)new_blk;
1743 if ((extra[0] & 0x60) != 0x60) {
1749 data[6 + 2] = (u8)(log_blk >> 8);
1750 data[6 + 3] = (u8)log_blk;
1752 for (j = 4; j <= MS_EXTRA_SIZE; j++) {
1756 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE), NO_WAIT_INT, data, 16);
1757 if (retval != STATUS_SUCCESS) {
1758 TRACE_RET(chip, STATUS_FAIL);
1761 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1762 if (retval != STATUS_SUCCESS) {
1763 TRACE_RET(chip, STATUS_FAIL);
1766 ms_set_err_code(chip, MS_NO_ERROR);
1767 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1768 if (retval != STATUS_SUCCESS) {
1769 TRACE_RET(chip, STATUS_FAIL);
1772 if (val & INT_REG_CMDNK) {
1773 ms_set_err_code(chip, MS_CMD_NK);
1774 TRACE_RET(chip, STATUS_FAIL);
1777 if (val & INT_REG_CED) {
1778 if (val & INT_REG_ERR) {
1779 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1780 TRACE_RET(chip, STATUS_FAIL);
1785 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 7);
1786 if (retval != STATUS_SUCCESS) {
1787 TRACE_RET(chip, STATUS_FAIL);
1790 ms_set_err_code(chip, MS_NO_ERROR);
1792 if (CHK_MS4BIT(ms_card)) {
1798 data[2] = (u8)(old_blk >> 8);
1799 data[3] = (u8)old_blk;
1805 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 8);
1806 if (retval != STATUS_SUCCESS) {
1807 TRACE_RET(chip, STATUS_FAIL);
1810 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1811 if (retval != STATUS_SUCCESS) {
1812 TRACE_RET(chip, STATUS_FAIL);
1815 ms_set_err_code(chip, MS_NO_ERROR);
1816 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1817 if (retval != STATUS_SUCCESS) {
1818 TRACE_RET(chip, STATUS_FAIL);
1821 if (val & INT_REG_CMDNK) {
1822 ms_set_err_code(chip, MS_CMD_NK);
1823 TRACE_RET(chip, STATUS_FAIL);
1826 if (val & INT_REG_CED) {
1827 if (val & INT_REG_ERR) {
1828 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1829 TRACE_RET(chip, STATUS_FAIL);
1835 return STATUS_SUCCESS;
1839 static int reset_ms(struct rtsx_chip *chip)
1841 struct ms_info *ms_card = &(chip->ms_card);
1843 u16 i, reg_addr, block_size;
1844 u8 val, extra[MS_EXTRA_SIZE], j, *ptr;
1845 #ifndef SUPPORT_MAGIC_GATE
1849 retval = ms_prepare_reset(chip);
1850 if (retval != STATUS_SUCCESS) {
1851 TRACE_RET(chip, STATUS_FAIL);
1854 ms_card->ms_type |= TYPE_MS;
1856 retval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT);
1857 if (retval != STATUS_SUCCESS) {
1858 TRACE_RET(chip, STATUS_FAIL);
1861 retval = ms_read_status_reg(chip);
1862 if (retval != STATUS_SUCCESS) {
1863 TRACE_RET(chip, STATUS_FAIL);
1866 RTSX_READ_REG(chip, PPBUF_BASE2, &val);
1867 if (val & WRT_PRTCT) {
1868 chip->card_wp |= MS_CARD;
1870 chip->card_wp &= ~MS_CARD;
1876 /* Search Boot Block */
1877 while (i < (MAX_DEFECTIVE_BLOCK + 2)) {
1878 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1879 ms_set_err_code(chip, MS_NO_CARD);
1880 TRACE_RET(chip, STATUS_FAIL);
1883 retval = ms_read_extra_data(chip, i, 0, extra, MS_EXTRA_SIZE);
1884 if (retval != STATUS_SUCCESS) {
1889 if (extra[0] & BLOCK_OK) {
1890 if (!(extra[1] & NOT_BOOT_BLOCK)) {
1891 ms_card->boot_block = i;
1898 if (i == (MAX_DEFECTIVE_BLOCK + 2)) {
1899 RTSX_DEBUGP("No boot block found!");
1900 TRACE_RET(chip, STATUS_FAIL);
1903 for (j = 0; j < 3; j++) {
1904 retval = ms_read_page(chip, ms_card->boot_block, j);
1905 if (retval != STATUS_SUCCESS) {
1906 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) {
1907 i = ms_card->boot_block + 1;
1908 ms_set_err_code(chip, MS_NO_ERROR);
1914 retval = ms_read_page(chip, ms_card->boot_block, 0);
1915 if (retval != STATUS_SUCCESS) {
1916 TRACE_RET(chip, STATUS_FAIL);
1919 /* Read MS system information as sys_info */
1920 rtsx_init_cmd(chip);
1922 for (i = 0; i < 96; i++) {
1923 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 0x1A0 + i, 0, 0);
1926 retval = rtsx_send_cmd(chip, MS_CARD, 100);
1928 TRACE_RET(chip, STATUS_FAIL);
1931 ptr = rtsx_get_cmd_data(chip);
1932 memcpy(ms_card->raw_sys_info, ptr, 96);
1934 /* Read useful block contents */
1935 rtsx_init_cmd(chip);
1937 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0);
1938 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0);
1940 for (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3; reg_addr++) {
1941 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
1944 for (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++) {
1945 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
1948 rtsx_add_cmd(chip, READ_REG_CMD, MS_Device_Type, 0, 0);
1949 rtsx_add_cmd(chip, READ_REG_CMD, MS_4bit_Support, 0, 0);
1951 retval = rtsx_send_cmd(chip, MS_CARD, 100);
1953 TRACE_RET(chip, STATUS_FAIL);
1956 ptr = rtsx_get_cmd_data(chip);
1958 RTSX_DEBUGP("Boot block data:\n");
1962 * HEADER_ID0, HEADER_ID1
1964 if (ptr[0] != 0x00 || ptr[1] != 0x01) {
1965 i = ms_card->boot_block + 1;
1970 * PAGE_SIZE_0, PAGE_SIZE_1
1972 if (ptr[12] != 0x02 || ptr[13] != 0x00) {
1973 i = ms_card->boot_block + 1;
1977 if ((ptr[14] == 1) || (ptr[14] == 3)) {
1978 chip->card_wp |= MS_CARD;
1981 /* BLOCK_SIZE_0, BLOCK_SIZE_1 */
1982 block_size = ((u16)ptr[6] << 8) | ptr[7];
1983 if (block_size == 0x0010) {
1984 /* Block size 16KB */
1985 ms_card->block_shift = 5;
1986 ms_card->page_off = 0x1F;
1987 } else if (block_size == 0x0008) {
1988 /* Block size 8KB */
1989 ms_card->block_shift = 4;
1990 ms_card->page_off = 0x0F;
1993 /* BLOCK_COUNT_0, BLOCK_COUNT_1 */
1994 ms_card->total_block = ((u16)ptr[8] << 8) | ptr[9];
1996 #ifdef SUPPORT_MAGIC_GATE
1999 if (ms_card->block_shift == 4) { /* 4MB or 8MB */
2000 if (j < 2) { /* Effective block for 4MB: 0x1F0 */
2001 ms_card->capacity = 0x1EE0;
2002 } else { /* Effective block for 8MB: 0x3E0 */
2003 ms_card->capacity = 0x3DE0;
2005 } else { /* 16MB, 32MB, 64MB or 128MB */
2006 if (j < 5) { /* Effective block for 16MB: 0x3E0 */
2007 ms_card->capacity = 0x7BC0;
2008 } else if (j < 0xA) { /* Effective block for 32MB: 0x7C0 */
2009 ms_card->capacity = 0xF7C0;
2010 } else if (j < 0x11) { /* Effective block for 64MB: 0xF80 */
2011 ms_card->capacity = 0x1EF80;
2012 } else { /* Effective block for 128MB: 0x1F00 */
2013 ms_card->capacity = 0x3DF00;
2017 /* EBLOCK_COUNT_0, EBLOCK_COUNT_1 */
2018 eblock_cnt = ((u16)ptr[10] << 8) | ptr[11];
2020 ms_card->capacity = ((u32)eblock_cnt - 2) << ms_card->block_shift;
2023 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;
2025 /* Switch I/F Mode */
2027 retval = ms_set_rw_reg_addr(chip, 0, 0, SystemParm, 1);
2028 if (retval != STATUS_SUCCESS) {
2029 TRACE_RET(chip, STATUS_FAIL);
2032 RTSX_WRITE_REG(chip, PPBUF_BASE2, 0xFF, 0x88);
2033 RTSX_WRITE_REG(chip, PPBUF_BASE2 + 1, 0xFF, 0);
2035 retval = ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG , 1, NO_WAIT_INT);
2036 if (retval != STATUS_SUCCESS) {
2037 TRACE_RET(chip, STATUS_FAIL);
2040 RTSX_WRITE_REG(chip, MS_CFG, 0x58 | MS_NO_CHECK_INT,
2041 MS_BUS_WIDTH_4 | PUSH_TIME_ODD | MS_NO_CHECK_INT);
2043 ms_card->ms_type |= MS_4BIT;
2046 if (CHK_MS4BIT(ms_card)) {
2047 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
2049 chip->card_bus_width[chip->card2lun[MS_CARD]] = 1;
2052 return STATUS_SUCCESS;
2055 static int ms_init_l2p_tbl(struct rtsx_chip *chip)
2057 struct ms_info *ms_card = &(chip->ms_card);
2058 int size, i, seg_no, retval;
2059 u16 defect_block, reg_addr;
2062 ms_card->segment_cnt = ms_card->total_block >> 9;
2063 RTSX_DEBUGP("ms_card->segment_cnt = %d\n", ms_card->segment_cnt);
2065 size = ms_card->segment_cnt * sizeof(struct zone_entry);
2066 ms_card->segment = (struct zone_entry *)vmalloc(size);
2067 if (ms_card->segment == NULL) {
2068 TRACE_RET(chip, STATUS_FAIL);
2070 memset(ms_card->segment, 0, size);
2072 retval = ms_read_page(chip, ms_card->boot_block, 1);
2073 if (retval != STATUS_SUCCESS) {
2074 TRACE_GOTO(chip, INIT_FAIL);
2077 reg_addr = PPBUF_BASE2;
2078 for (i = 0; i < (((ms_card->total_block >> 9) * 10) + 1); i++) {
2079 retval = rtsx_read_register(chip, reg_addr++, &val1);
2080 if (retval != STATUS_SUCCESS) {
2081 TRACE_GOTO(chip, INIT_FAIL);
2083 retval = rtsx_read_register(chip, reg_addr++, &val2);
2084 if (retval != STATUS_SUCCESS) {
2085 TRACE_GOTO(chip, INIT_FAIL);
2088 defect_block = ((u16)val1 << 8) | val2;
2089 if (defect_block == 0xFFFF) {
2092 seg_no = defect_block / 512;
2093 ms_card->segment[seg_no].defect_list[ms_card->segment[seg_no].disable_count++] = defect_block;
2096 for (i = 0; i < ms_card->segment_cnt; i++) {
2097 ms_card->segment[i].build_flag = 0;
2098 ms_card->segment[i].l2p_table = NULL;
2099 ms_card->segment[i].free_table = NULL;
2100 ms_card->segment[i].get_index = 0;
2101 ms_card->segment[i].set_index = 0;
2102 ms_card->segment[i].unused_blk_cnt = 0;
2104 RTSX_DEBUGP("defective block count of segment %d is %d\n",
2105 i, ms_card->segment[i].disable_count);
2108 return STATUS_SUCCESS;
2111 if (ms_card->segment) {
2112 vfree(ms_card->segment);
2113 ms_card->segment = NULL;
2119 static u16 ms_get_l2p_tbl(struct rtsx_chip *chip, int seg_no, u16 log_off)
2121 struct ms_info *ms_card = &(chip->ms_card);
2122 struct zone_entry *segment;
2124 if (ms_card->segment == NULL)
2127 segment = &(ms_card->segment[seg_no]);
2129 if (segment->l2p_table)
2130 return segment->l2p_table[log_off];
2135 static void ms_set_l2p_tbl(struct rtsx_chip *chip, int seg_no, u16 log_off, u16 phy_blk)
2137 struct ms_info *ms_card = &(chip->ms_card);
2138 struct zone_entry *segment;
2140 if (ms_card->segment == NULL)
2143 segment = &(ms_card->segment[seg_no]);
2144 if (segment->l2p_table) {
2145 segment->l2p_table[log_off] = phy_blk;
2149 static void ms_set_unused_block(struct rtsx_chip *chip, u16 phy_blk)
2151 struct ms_info *ms_card = &(chip->ms_card);
2152 struct zone_entry *segment;
2155 seg_no = (int)phy_blk >> 9;
2156 segment = &(ms_card->segment[seg_no]);
2158 segment->free_table[segment->set_index++] = phy_blk;
2159 if (segment->set_index >= MS_FREE_TABLE_CNT) {
2160 segment->set_index = 0;
2162 segment->unused_blk_cnt++;
2165 static u16 ms_get_unused_block(struct rtsx_chip *chip, int seg_no)
2167 struct ms_info *ms_card = &(chip->ms_card);
2168 struct zone_entry *segment;
2171 segment = &(ms_card->segment[seg_no]);
2173 if (segment->unused_blk_cnt <= 0)
2176 phy_blk = segment->free_table[segment->get_index];
2177 segment->free_table[segment->get_index++] = 0xFFFF;
2178 if (segment->get_index >= MS_FREE_TABLE_CNT) {
2179 segment->get_index = 0;
2181 segment->unused_blk_cnt--;
2186 static const unsigned short ms_start_idx[] = {0, 494, 990, 1486, 1982, 2478, 2974, 3470,
2187 3966, 4462, 4958, 5454, 5950, 6446, 6942, 7438, 7934};
2189 static int ms_arbitrate_l2p(struct rtsx_chip *chip, u16 phy_blk, u16 log_off, u8 us1, u8 us2)
2191 struct ms_info *ms_card = &(chip->ms_card);
2192 struct zone_entry *segment;
2196 seg_no = (int)phy_blk >> 9;
2197 segment = &(ms_card->segment[seg_no]);
2198 tmp_blk = segment->l2p_table[log_off];
2202 if (!(chip->card_wp & MS_CARD)) {
2203 ms_erase_block(chip, tmp_blk);
2205 ms_set_unused_block(chip, tmp_blk);
2206 segment->l2p_table[log_off] = phy_blk;
2208 if (!(chip->card_wp & MS_CARD)) {
2209 ms_erase_block(chip, phy_blk);
2211 ms_set_unused_block(chip, phy_blk);
2214 if (phy_blk < tmp_blk) {
2215 if (!(chip->card_wp & MS_CARD)) {
2216 ms_erase_block(chip, phy_blk);
2218 ms_set_unused_block(chip, phy_blk);
2220 if (!(chip->card_wp & MS_CARD)) {
2221 ms_erase_block(chip, tmp_blk);
2223 ms_set_unused_block(chip, tmp_blk);
2224 segment->l2p_table[log_off] = phy_blk;
2228 return STATUS_SUCCESS;
2231 static int ms_build_l2p_tbl(struct rtsx_chip *chip, int seg_no)
2233 struct ms_info *ms_card = &(chip->ms_card);
2234 struct zone_entry *segment;
2235 int retval, table_size, disable_cnt, defect_flag, i;
2236 u16 start, end, phy_blk, log_blk, tmp_blk;
2237 u8 extra[MS_EXTRA_SIZE], us1, us2;
2239 RTSX_DEBUGP("ms_build_l2p_tbl: %d\n", seg_no);
2241 if (ms_card->segment == NULL) {
2242 retval = ms_init_l2p_tbl(chip);
2243 if (retval != STATUS_SUCCESS) {
2244 TRACE_RET(chip, retval);
2248 if (ms_card->segment[seg_no].build_flag) {
2249 RTSX_DEBUGP("l2p table of segment %d has been built\n", seg_no);
2250 return STATUS_SUCCESS;
2259 segment = &(ms_card->segment[seg_no]);
2261 if (segment->l2p_table == NULL) {
2262 segment->l2p_table = (u16 *)vmalloc(table_size * 2);
2263 if (segment->l2p_table == NULL) {
2264 TRACE_GOTO(chip, BUILD_FAIL);
2267 memset((u8 *)(segment->l2p_table), 0xff, table_size * 2);
2269 if (segment->free_table == NULL) {
2270 segment->free_table = (u16 *)vmalloc(MS_FREE_TABLE_CNT * 2);
2271 if (segment->free_table == NULL) {
2272 TRACE_GOTO(chip, BUILD_FAIL);
2275 memset((u8 *)(segment->free_table), 0xff, MS_FREE_TABLE_CNT * 2);
2277 start = (u16)seg_no << 9;
2278 end = (u16)(seg_no + 1) << 9;
2280 disable_cnt = segment->disable_count;
2282 segment->get_index = segment->set_index = 0;
2283 segment->unused_blk_cnt = 0;
2285 for (phy_blk = start; phy_blk < end; phy_blk++) {
2288 for (i = 0; i < segment->disable_count; i++) {
2289 if (phy_blk == segment->defect_list[i]) {
2300 retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE);
2301 if (retval != STATUS_SUCCESS) {
2302 RTSX_DEBUGP("read extra data fail\n");
2303 ms_set_bad_block(chip, phy_blk);
2307 if (seg_no == ms_card->segment_cnt - 1) {
2308 if (!(extra[1] & NOT_TRANSLATION_TABLE)) {
2309 if (!(chip->card_wp & MS_CARD)) {
2310 retval = ms_erase_block(chip, phy_blk);
2311 if (retval != STATUS_SUCCESS)
2319 if (!(extra[0] & BLOCK_OK))
2321 if (!(extra[1] & NOT_BOOT_BLOCK))
2323 if ((extra[0] & PAGE_OK) != PAGE_OK)
2326 log_blk = ((u16)extra[2] << 8) | extra[3];
2328 if (log_blk == 0xFFFF) {
2329 if (!(chip->card_wp & MS_CARD)) {
2330 retval = ms_erase_block(chip, phy_blk);
2331 if (retval != STATUS_SUCCESS)
2334 ms_set_unused_block(chip, phy_blk);
2338 if ((log_blk < ms_start_idx[seg_no]) ||
2339 (log_blk >= ms_start_idx[seg_no+1])) {
2340 if (!(chip->card_wp & MS_CARD)) {
2341 retval = ms_erase_block(chip, phy_blk);
2342 if (retval != STATUS_SUCCESS)
2345 ms_set_unused_block(chip, phy_blk);
2349 if (segment->l2p_table[log_blk - ms_start_idx[seg_no]] == 0xFFFF) {
2350 segment->l2p_table[log_blk - ms_start_idx[seg_no]] = phy_blk;
2354 us1 = extra[0] & 0x10;
2355 tmp_blk = segment->l2p_table[log_blk - ms_start_idx[seg_no]];
2356 retval = ms_read_extra_data(chip, tmp_blk, 0, extra, MS_EXTRA_SIZE);
2357 if (retval != STATUS_SUCCESS)
2359 us2 = extra[0] & 0x10;
2361 (void)ms_arbitrate_l2p(chip, phy_blk, log_blk-ms_start_idx[seg_no], us1, us2);
2365 segment->build_flag = 1;
2367 RTSX_DEBUGP("unused block count: %d\n", segment->unused_blk_cnt);
2369 /* Logical Address Confirmation Process */
2370 if (seg_no == ms_card->segment_cnt - 1) {
2371 if (segment->unused_blk_cnt < 2) {
2372 chip->card_wp |= MS_CARD;
2375 if (segment->unused_blk_cnt < 1) {
2376 chip->card_wp |= MS_CARD;
2380 if (chip->card_wp & MS_CARD)
2381 return STATUS_SUCCESS;
2383 for (log_blk = ms_start_idx[seg_no]; log_blk < ms_start_idx[seg_no + 1]; log_blk++) {
2384 if (segment->l2p_table[log_blk-ms_start_idx[seg_no]] == 0xFFFF) {
2385 phy_blk = ms_get_unused_block(chip, seg_no);
2386 if (phy_blk == 0xFFFF) {
2387 chip->card_wp |= MS_CARD;
2388 return STATUS_SUCCESS;
2390 retval = ms_init_page(chip, phy_blk, log_blk, 0, 1);
2391 if (retval != STATUS_SUCCESS) {
2392 TRACE_GOTO(chip, BUILD_FAIL);
2394 segment->l2p_table[log_blk-ms_start_idx[seg_no]] = phy_blk;
2395 if (seg_no == ms_card->segment_cnt - 1) {
2396 if (segment->unused_blk_cnt < 2) {
2397 chip->card_wp |= MS_CARD;
2398 return STATUS_SUCCESS;
2401 if (segment->unused_blk_cnt < 1) {
2402 chip->card_wp |= MS_CARD;
2403 return STATUS_SUCCESS;
2409 /* Make boot block be the first normal block */
2411 for (log_blk = 0; log_blk < 494; log_blk++) {
2412 tmp_blk = segment->l2p_table[log_blk];
2413 if (tmp_blk < ms_card->boot_block) {
2414 RTSX_DEBUGP("Boot block is not the first normal block.\n");
2416 if (chip->card_wp & MS_CARD)
2419 phy_blk = ms_get_unused_block(chip, 0);
2420 retval = ms_copy_page(chip, tmp_blk, phy_blk,
2421 log_blk, 0, ms_card->page_off + 1);
2422 if (retval != STATUS_SUCCESS) {
2423 TRACE_RET(chip, STATUS_FAIL);
2426 segment->l2p_table[log_blk] = phy_blk;
2428 retval = ms_set_bad_block(chip, tmp_blk);
2429 if (retval != STATUS_SUCCESS) {
2430 TRACE_RET(chip, STATUS_FAIL);
2436 return STATUS_SUCCESS;
2439 segment->build_flag = 0;
2440 if (segment->l2p_table) {
2441 vfree(segment->l2p_table);
2442 segment->l2p_table = NULL;
2444 if (segment->free_table) {
2445 vfree(segment->free_table);
2446 segment->free_table = NULL;
2453 int reset_ms_card(struct rtsx_chip *chip)
2455 struct ms_info *ms_card = &(chip->ms_card);
2458 memset(ms_card, 0, sizeof(struct ms_info));
2460 retval = enable_card_clock(chip, MS_CARD);
2461 if (retval != STATUS_SUCCESS) {
2462 TRACE_RET(chip, STATUS_FAIL);
2465 retval = select_card(chip, MS_CARD);
2466 if (retval != STATUS_SUCCESS) {
2467 TRACE_RET(chip, STATUS_FAIL);
2470 ms_card->ms_type = 0;
2472 retval = reset_ms_pro(chip);
2473 if (retval != STATUS_SUCCESS) {
2474 if (ms_card->check_ms_flow) {
2475 retval = reset_ms(chip);
2476 if (retval != STATUS_SUCCESS) {
2477 TRACE_RET(chip, STATUS_FAIL);
2480 TRACE_RET(chip, STATUS_FAIL);
2484 retval = ms_set_init_para(chip);
2485 if (retval != STATUS_SUCCESS) {
2486 TRACE_RET(chip, STATUS_FAIL);
2489 if (!CHK_MSPRO(ms_card)) {
2490 /* Build table for the last segment,
2491 * to check if L2P talbe block exist,erasing it
2493 retval = ms_build_l2p_tbl(chip, ms_card->total_block / 512 - 1);
2494 if (retval != STATUS_SUCCESS) {
2495 TRACE_RET(chip, STATUS_FAIL);
2499 RTSX_DEBUGP("ms_card->ms_type = 0x%x\n", ms_card->ms_type);
2501 return STATUS_SUCCESS;
2504 static int mspro_set_rw_cmd(struct rtsx_chip *chip, u32 start_sec, u16 sec_cnt, u8 cmd)
2510 data[1] = (u8)(sec_cnt >> 8);
2511 data[2] = (u8)sec_cnt;
2512 data[3] = (u8)(start_sec >> 24);
2513 data[4] = (u8)(start_sec >> 16);
2514 data[5] = (u8)(start_sec >> 8);
2515 data[6] = (u8)start_sec;
2518 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2519 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT, data, 8);
2520 if (retval == STATUS_SUCCESS)
2523 if (i == MS_MAX_RETRY_COUNT) {
2524 TRACE_RET(chip, STATUS_FAIL);
2527 return STATUS_SUCCESS;
2531 void mspro_stop_seq_mode(struct rtsx_chip *chip)
2533 struct ms_info *ms_card = &(chip->ms_card);
2536 RTSX_DEBUGP("--%s--\n", __func__);
2538 if (ms_card->seq_mode) {
2539 retval = ms_switch_clock(chip);
2540 if (retval != STATUS_SUCCESS)
2543 ms_card->seq_mode = 0;
2544 ms_card->total_sec_cnt = 0;
2545 ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2547 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
2551 static inline int ms_auto_tune_clock(struct rtsx_chip *chip)
2553 struct ms_info *ms_card = &(chip->ms_card);
2556 RTSX_DEBUGP("--%s--\n", __func__);
2558 if (chip->asic_code) {
2559 if (ms_card->ms_clock > 30) {
2560 ms_card->ms_clock -= 20;
2563 if (ms_card->ms_clock == CLK_80) {
2564 ms_card->ms_clock = CLK_60;
2565 } else if (ms_card->ms_clock == CLK_60) {
2566 ms_card->ms_clock = CLK_40;
2570 retval = ms_switch_clock(chip);
2571 if (retval != STATUS_SUCCESS) {
2572 TRACE_RET(chip, STATUS_FAIL);
2575 return STATUS_SUCCESS;
2578 static int mspro_rw_multi_sector(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt)
2580 struct ms_info *ms_card = &(chip->ms_card);
2581 int retval, mode_2k = 0;
2583 u8 val, trans_mode, rw_tpc, rw_cmd;
2585 ms_set_err_code(chip, MS_NO_ERROR);
2587 ms_card->cleanup_counter = 0;
2589 if (CHK_MSHG(ms_card)) {
2590 if ((start_sector % 4) || (sector_cnt % 4)) {
2591 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2592 rw_tpc = PRO_READ_LONG_DATA;
2593 rw_cmd = PRO_READ_DATA;
2595 rw_tpc = PRO_WRITE_LONG_DATA;
2596 rw_cmd = PRO_WRITE_DATA;
2599 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2600 rw_tpc = PRO_READ_QUAD_DATA;
2601 rw_cmd = PRO_READ_2K_DATA;
2603 rw_tpc = PRO_WRITE_QUAD_DATA;
2604 rw_cmd = PRO_WRITE_2K_DATA;
2609 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2610 rw_tpc = PRO_READ_LONG_DATA;
2611 rw_cmd = PRO_READ_DATA;
2613 rw_tpc = PRO_WRITE_LONG_DATA;
2614 rw_cmd = PRO_WRITE_DATA;
2618 retval = ms_switch_clock(chip);
2619 if (retval != STATUS_SUCCESS) {
2620 TRACE_RET(chip, STATUS_FAIL);
2623 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2624 trans_mode = MS_TM_AUTO_READ;
2626 trans_mode = MS_TM_AUTO_WRITE;
2629 RTSX_READ_REG(chip, MS_TRANS_CFG, &val);
2631 if (ms_card->seq_mode) {
2632 if ((ms_card->pre_dir != srb->sc_data_direction)
2633 || ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) != start_sector)
2634 || (mode_2k && (ms_card->seq_mode & MODE_512_SEQ))
2635 || (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ))
2636 || !(val & MS_INT_BREQ)
2637 || ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) {
2638 ms_card->seq_mode = 0;
2639 ms_card->total_sec_cnt = 0;
2640 if (val & MS_INT_BREQ) {
2641 retval = ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2642 if (retval != STATUS_SUCCESS) {
2643 TRACE_RET(chip, STATUS_FAIL);
2646 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
2651 if (!ms_card->seq_mode) {
2652 ms_card->total_sec_cnt = 0;
2653 if (sector_cnt >= SEQ_START_CRITERIA) {
2654 if ((ms_card->capacity - start_sector) > 0xFE00) {
2657 count = (u16)(ms_card->capacity - start_sector);
2659 if (count > sector_cnt) {
2661 ms_card->seq_mode |= MODE_2K_SEQ;
2663 ms_card->seq_mode |= MODE_512_SEQ;
2669 retval = mspro_set_rw_cmd(chip, start_sector, count, rw_cmd);
2670 if (retval != STATUS_SUCCESS) {
2671 ms_card->seq_mode = 0;
2672 TRACE_RET(chip, STATUS_FAIL);
2676 retval = ms_transfer_data(chip, trans_mode, rw_tpc, sector_cnt, WAIT_INT, mode_2k,
2677 scsi_sg_count(srb), scsi_sglist(srb), scsi_bufflen(srb));
2678 if (retval != STATUS_SUCCESS) {
2679 ms_card->seq_mode = 0;
2680 rtsx_read_register(chip, MS_TRANS_CFG, &val);
2681 rtsx_clear_ms_error(chip);
2683 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
2684 chip->rw_need_retry = 0;
2685 RTSX_DEBUGP("No card exist, exit mspro_rw_multi_sector\n");
2686 TRACE_RET(chip, STATUS_FAIL);
2689 if (val & MS_INT_BREQ) {
2690 ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2692 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
2693 RTSX_DEBUGP("MSPro CRC error, tune clock!\n");
2694 chip->rw_need_retry = 1;
2695 ms_auto_tune_clock(chip);
2698 TRACE_RET(chip, retval);
2701 if (ms_card->seq_mode) {
2702 ms_card->pre_sec_addr = start_sector;
2703 ms_card->pre_sec_cnt = sector_cnt;
2704 ms_card->pre_dir = srb->sc_data_direction;
2705 ms_card->total_sec_cnt += sector_cnt;
2708 return STATUS_SUCCESS;
2711 static int mspro_read_format_progress(struct rtsx_chip *chip, const int short_data_len)
2713 struct ms_info *ms_card = &(chip->ms_card);
2715 u32 total_progress, cur_progress;
2719 RTSX_DEBUGP("mspro_read_format_progress, short_data_len = %d\n", short_data_len);
2721 retval = ms_switch_clock(chip);
2722 if (retval != STATUS_SUCCESS) {
2723 ms_card->format_status = FORMAT_FAIL;
2724 TRACE_RET(chip, STATUS_FAIL);
2727 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
2728 if (retval != STATUS_SUCCESS) {
2729 ms_card->format_status = FORMAT_FAIL;
2730 TRACE_RET(chip, STATUS_FAIL);
2733 if (!(tmp & MS_INT_BREQ)) {
2734 if ((tmp & (MS_INT_CED | MS_INT_BREQ | MS_INT_CMDNK | MS_INT_ERR)) == MS_INT_CED) {
2735 ms_card->format_status = FORMAT_SUCCESS;
2736 return STATUS_SUCCESS;
2738 ms_card->format_status = FORMAT_FAIL;
2739 TRACE_RET(chip, STATUS_FAIL);
2742 if (short_data_len >= 256) {
2745 cnt = (u8)short_data_len;
2748 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, MS_NO_CHECK_INT);
2749 if (retval != STATUS_SUCCESS) {
2750 ms_card->format_status = FORMAT_FAIL;
2751 TRACE_RET(chip, STATUS_FAIL);
2754 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, cnt, WAIT_INT, data, 8);
2755 if (retval != STATUS_SUCCESS) {
2756 ms_card->format_status = FORMAT_FAIL;
2757 TRACE_RET(chip, STATUS_FAIL);
2760 total_progress = (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3];
2761 cur_progress = (data[4] << 24) | (data[5] << 16) | (data[6] << 8) | data[7];
2763 RTSX_DEBUGP("total_progress = %d, cur_progress = %d\n",
2764 total_progress, cur_progress);
2766 if (total_progress == 0) {
2767 ms_card->progress = 0;
2769 u64 ulltmp = (u64)cur_progress * (u64)65535;
2770 do_div(ulltmp, total_progress);
2771 ms_card->progress = (u16)ulltmp;
2773 RTSX_DEBUGP("progress = %d\n", ms_card->progress);
2775 for (i = 0; i < 5000; i++) {
2776 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
2777 if (retval != STATUS_SUCCESS) {
2778 ms_card->format_status = FORMAT_FAIL;
2779 TRACE_RET(chip, STATUS_FAIL);
2781 if (tmp & (MS_INT_CED | MS_INT_CMDNK | MS_INT_BREQ | MS_INT_ERR)) {
2788 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 0);
2789 if (retval != STATUS_SUCCESS) {
2790 ms_card->format_status = FORMAT_FAIL;
2791 TRACE_RET(chip, STATUS_FAIL);
2795 ms_card->format_status = FORMAT_FAIL;
2796 TRACE_RET(chip, STATUS_FAIL);
2799 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) {
2800 ms_card->format_status = FORMAT_FAIL;
2801 TRACE_RET(chip, STATUS_FAIL);
2804 if (tmp & MS_INT_CED) {
2805 ms_card->format_status = FORMAT_SUCCESS;
2806 ms_card->pro_under_formatting = 0;
2807 } else if (tmp & MS_INT_BREQ) {
2808 ms_card->format_status = FORMAT_IN_PROGRESS;
2810 ms_card->format_status = FORMAT_FAIL;
2811 ms_card->pro_under_formatting = 0;
2812 TRACE_RET(chip, STATUS_FAIL);
2815 return STATUS_SUCCESS;
2818 void mspro_polling_format_status(struct rtsx_chip *chip)
2820 struct ms_info *ms_card = &(chip->ms_card);
2823 if (ms_card->pro_under_formatting && (rtsx_get_stat(chip) != RTSX_STAT_SS)) {
2824 rtsx_set_stat(chip, RTSX_STAT_RUN);
2826 for (i = 0; i < 65535; i++) {
2827 mspro_read_format_progress(chip, MS_SHORT_DATA_LEN);
2828 if (ms_card->format_status != FORMAT_IN_PROGRESS)
2836 int mspro_format(struct scsi_cmnd *srb, struct rtsx_chip *chip, int short_data_len, int quick_format)
2838 struct ms_info *ms_card = &(chip->ms_card);
2843 RTSX_DEBUGP("--%s--\n", __func__);
2845 retval = ms_switch_clock(chip);
2846 if (retval != STATUS_SUCCESS) {
2847 TRACE_RET(chip, STATUS_FAIL);
2850 retval = ms_set_rw_reg_addr(chip, 0x00, 0x00, Pro_TPCParm, 0x01);
2851 if (retval != STATUS_SUCCESS) {
2852 TRACE_RET(chip, STATUS_FAIL);
2856 switch (short_data_len) {
2872 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2873 retval = ms_write_bytes(chip, PRO_WRITE_REG, 1, NO_WAIT_INT, buf, 2);
2874 if (retval == STATUS_SUCCESS)
2877 if (i == MS_MAX_RETRY_COUNT) {
2878 TRACE_RET(chip, STATUS_FAIL);
2886 retval = mspro_set_rw_cmd(chip, 0, para, PRO_FORMAT);
2887 if (retval != STATUS_SUCCESS) {
2888 TRACE_RET(chip, STATUS_FAIL);
2891 RTSX_READ_REG(chip, MS_TRANS_CFG, &tmp);
2893 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) {
2894 TRACE_RET(chip, STATUS_FAIL);
2897 if ((tmp & (MS_INT_BREQ | MS_INT_CED)) == MS_INT_BREQ) {
2898 ms_card->pro_under_formatting = 1;
2899 ms_card->progress = 0;
2900 ms_card->format_status = FORMAT_IN_PROGRESS;
2901 return STATUS_SUCCESS;
2904 if (tmp & MS_INT_CED) {
2905 ms_card->pro_under_formatting = 0;
2906 ms_card->progress = 0;
2907 ms_card->format_status = FORMAT_SUCCESS;
2908 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_NO_SENSE);
2909 return STATUS_SUCCESS;
2912 TRACE_RET(chip, STATUS_FAIL);
2916 static int ms_read_multiple_pages(struct rtsx_chip *chip, u16 phy_blk, u16 log_blk,
2917 u8 start_page, u8 end_page, u8 *buf, unsigned int *index, unsigned int *offset)
2919 struct ms_info *ms_card = &(chip->ms_card);
2921 u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6];
2924 retval = ms_read_extra_data(chip, phy_blk, start_page, extra, MS_EXTRA_SIZE);
2925 if (retval == STATUS_SUCCESS) {
2926 if ((extra[1] & 0x30) != 0x30) {
2927 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
2928 TRACE_RET(chip, STATUS_FAIL);
2932 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6);
2933 if (retval != STATUS_SUCCESS) {
2934 TRACE_RET(chip, STATUS_FAIL);
2937 if (CHK_MS4BIT(ms_card)) {
2943 data[2] = (u8)(phy_blk >> 8);
2944 data[3] = (u8)phy_blk;
2946 data[5] = start_page;
2948 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2949 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
2950 if (retval == STATUS_SUCCESS)
2953 if (i == MS_MAX_RETRY_COUNT) {
2954 TRACE_RET(chip, STATUS_FAIL);
2957 ms_set_err_code(chip, MS_NO_ERROR);
2959 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
2960 if (retval != STATUS_SUCCESS) {
2961 TRACE_RET(chip, STATUS_FAIL);
2966 for (page_addr = start_page; page_addr < end_page; page_addr++) {
2967 ms_set_err_code(chip, MS_NO_ERROR);
2969 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
2970 ms_set_err_code(chip, MS_NO_CARD);
2971 TRACE_RET(chip, STATUS_FAIL);
2974 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
2975 if (retval != STATUS_SUCCESS) {
2976 TRACE_RET(chip, STATUS_FAIL);
2978 if (val & INT_REG_CMDNK) {
2979 ms_set_err_code(chip, MS_CMD_NK);
2980 TRACE_RET(chip, STATUS_FAIL);
2982 if (val & INT_REG_ERR) {
2983 if (val & INT_REG_BREQ) {
2984 retval = ms_read_status_reg(chip);
2985 if (retval != STATUS_SUCCESS) {
2986 if (!(chip->card_wp & MS_CARD)) {
2988 ms_set_page_status(log_blk, setPS_NG, extra, MS_EXTRA_SIZE);
2989 ms_write_extra_data(chip, phy_blk,
2990 page_addr, extra, MS_EXTRA_SIZE);
2992 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
2993 TRACE_RET(chip, STATUS_FAIL);
2996 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
2997 TRACE_RET(chip, STATUS_FAIL);
3000 if (!(val & INT_REG_BREQ)) {
3001 ms_set_err_code(chip, MS_BREQ_ERROR);
3002 TRACE_RET(chip, STATUS_FAIL);
3006 if (page_addr == (end_page - 1)) {
3007 if (!(val & INT_REG_CED)) {
3008 retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT);
3009 if (retval != STATUS_SUCCESS) {
3010 TRACE_RET(chip, STATUS_FAIL);
3014 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3015 if (retval != STATUS_SUCCESS) {
3016 TRACE_RET(chip, STATUS_FAIL);
3018 if (!(val & INT_REG_CED)) {
3019 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3020 TRACE_RET(chip, STATUS_FAIL);
3023 trans_cfg = NO_WAIT_INT;
3025 trans_cfg = WAIT_INT;
3028 rtsx_init_cmd(chip);
3030 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, READ_PAGE_DATA);
3031 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, trans_cfg);
3032 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
3034 trans_dma_enable(DMA_FROM_DEVICE, chip, 512, DMA_512);
3036 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3037 MS_TRANSFER_START | MS_TM_NORMAL_READ);
3038 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
3040 rtsx_send_cmd_no_wait(chip);
3042 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 512, scsi_sg_count(chip->srb),
3043 index, offset, DMA_FROM_DEVICE, chip->ms_timeout);
3045 if (retval == -ETIMEDOUT) {
3046 ms_set_err_code(chip, MS_TO_ERROR);
3047 rtsx_clear_ms_error(chip);
3048 TRACE_RET(chip, STATUS_TIMEDOUT);
3051 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
3052 if (retval != STATUS_SUCCESS) {
3053 ms_set_err_code(chip, MS_TO_ERROR);
3054 rtsx_clear_ms_error(chip);
3055 TRACE_RET(chip, STATUS_TIMEDOUT);
3057 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
3058 ms_set_err_code(chip, MS_CRC16_ERROR);
3059 rtsx_clear_ms_error(chip);
3060 TRACE_RET(chip, STATUS_FAIL);
3064 if (scsi_sg_count(chip->srb) == 0)
3068 return STATUS_SUCCESS;
3071 static int ms_write_multiple_pages(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
3072 u16 log_blk, u8 start_page, u8 end_page, u8 *buf,
3073 unsigned int *index, unsigned int *offset)
3075 struct ms_info *ms_card = &(chip->ms_card);
3077 u8 page_addr, val, data[16];
3081 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 7);
3082 if (retval != STATUS_SUCCESS) {
3083 TRACE_RET(chip, STATUS_FAIL);
3086 if (CHK_MS4BIT(ms_card)) {
3092 data[2] = (u8)(old_blk >> 8);
3093 data[3] = (u8)old_blk;
3099 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 8);
3100 if (retval != STATUS_SUCCESS) {
3101 TRACE_RET(chip, STATUS_FAIL);
3104 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
3105 if (retval != STATUS_SUCCESS) {
3106 TRACE_RET(chip, STATUS_FAIL);
3109 ms_set_err_code(chip, MS_NO_ERROR);
3110 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1, NO_WAIT_INT);
3111 if (retval != STATUS_SUCCESS) {
3112 TRACE_RET(chip, STATUS_FAIL);
3116 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, (6 + MS_EXTRA_SIZE));
3117 if (retval != STATUS_SUCCESS) {
3118 TRACE_RET(chip, STATUS_FAIL);
3121 ms_set_err_code(chip, MS_NO_ERROR);
3123 if (CHK_MS4BIT(ms_card)) {
3129 data[2] = (u8)(new_blk >> 8);
3130 data[3] = (u8)new_blk;
3131 if ((end_page - start_page) == 1) {
3136 data[5] = start_page;
3139 data[8] = (u8)(log_blk >> 8);
3140 data[9] = (u8)log_blk;
3142 for (i = 0x0A; i < 0x10; i++) {
3146 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3147 retval = ms_write_bytes(chip, WRITE_REG, 6 + MS_EXTRA_SIZE, NO_WAIT_INT, data, 16);
3148 if (retval == STATUS_SUCCESS)
3151 if (i == MS_MAX_RETRY_COUNT) {
3152 TRACE_RET(chip, STATUS_FAIL);
3155 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3156 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
3157 if (retval == STATUS_SUCCESS)
3160 if (i == MS_MAX_RETRY_COUNT) {
3161 TRACE_RET(chip, STATUS_FAIL);
3164 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3165 if (retval != STATUS_SUCCESS) {
3166 TRACE_RET(chip, STATUS_FAIL);
3170 for (page_addr = start_page; page_addr < end_page; page_addr++) {
3171 ms_set_err_code(chip, MS_NO_ERROR);
3173 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3174 ms_set_err_code(chip, MS_NO_CARD);
3175 TRACE_RET(chip, STATUS_FAIL);
3178 if (val & INT_REG_CMDNK) {
3179 ms_set_err_code(chip, MS_CMD_NK);
3180 TRACE_RET(chip, STATUS_FAIL);
3182 if (val & INT_REG_ERR) {
3183 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3184 TRACE_RET(chip, STATUS_FAIL);
3186 if (!(val & INT_REG_BREQ)) {
3187 ms_set_err_code(chip, MS_BREQ_ERROR);
3188 TRACE_RET(chip, STATUS_FAIL);
3193 rtsx_init_cmd(chip);
3195 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, WRITE_PAGE_DATA);
3196 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, WAIT_INT);
3197 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
3199 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
3201 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3202 MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
3203 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
3205 rtsx_send_cmd_no_wait(chip);
3207 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 512, scsi_sg_count(chip->srb),
3208 index, offset, DMA_TO_DEVICE, chip->ms_timeout);
3210 ms_set_err_code(chip, MS_TO_ERROR);
3211 rtsx_clear_ms_error(chip);
3213 if (retval == -ETIMEDOUT) {
3214 TRACE_RET(chip, STATUS_TIMEDOUT);
3216 TRACE_RET(chip, STATUS_FAIL);
3220 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3221 if (retval != STATUS_SUCCESS) {
3222 TRACE_RET(chip, STATUS_FAIL);
3225 if ((end_page - start_page) == 1) {
3226 if (!(val & INT_REG_CED)) {
3227 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3228 TRACE_RET(chip, STATUS_FAIL);
3231 if (page_addr == (end_page - 1)) {
3232 if (!(val & INT_REG_CED)) {
3233 retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT);
3234 if (retval != STATUS_SUCCESS) {
3235 TRACE_RET(chip, STATUS_FAIL);
3239 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3240 if (retval != STATUS_SUCCESS) {
3241 TRACE_RET(chip, STATUS_FAIL);
3245 if ((page_addr == (end_page - 1)) || (page_addr == ms_card->page_off)) {
3246 if (!(val & INT_REG_CED)) {
3247 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3248 TRACE_RET(chip, STATUS_FAIL);
3253 if (scsi_sg_count(chip->srb) == 0)
3257 return STATUS_SUCCESS;
3261 static int ms_finish_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
3262 u16 log_blk, u8 page_off)
3264 struct ms_info *ms_card = &(chip->ms_card);
3267 retval = ms_copy_page(chip, old_blk, new_blk, log_blk,
3268 page_off, ms_card->page_off + 1);
3269 if (retval != STATUS_SUCCESS) {
3270 TRACE_RET(chip, STATUS_FAIL);
3273 seg_no = old_blk >> 9;
3275 if (MS_TST_BAD_BLOCK_FLG(ms_card)) {
3276 MS_CLR_BAD_BLOCK_FLG(ms_card);
3277 ms_set_bad_block(chip, old_blk);
3279 retval = ms_erase_block(chip, old_blk);
3280 if (retval == STATUS_SUCCESS) {
3281 ms_set_unused_block(chip, old_blk);
3285 ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk);
3287 return STATUS_SUCCESS;
3290 static int ms_prepare_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
3291 u16 log_blk, u8 start_page)
3296 retval = ms_copy_page(chip, old_blk, new_blk, log_blk, 0, start_page);
3297 if (retval != STATUS_SUCCESS) {
3298 TRACE_RET(chip, STATUS_FAIL);
3302 return STATUS_SUCCESS;
3305 #ifdef MS_DELAY_WRITE
3306 int ms_delay_write(struct rtsx_chip *chip)
3308 struct ms_info *ms_card = &(chip->ms_card);
3309 struct ms_delay_write_tag *delay_write = &(ms_card->delay_write);
3312 if (delay_write->delay_write_flag) {
3313 retval = ms_set_init_para(chip);
3314 if (retval != STATUS_SUCCESS) {
3315 TRACE_RET(chip, STATUS_FAIL);
3318 delay_write->delay_write_flag = 0;
3319 retval = ms_finish_write(chip,
3320 delay_write->old_phyblock, delay_write->new_phyblock,
3321 delay_write->logblock, delay_write->pageoff);
3322 if (retval != STATUS_SUCCESS) {
3323 TRACE_RET(chip, STATUS_FAIL);
3327 return STATUS_SUCCESS;
3331 static inline void ms_rw_fail(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3333 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3334 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3336 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
3340 static int ms_rw_multi_sector(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt)
3342 struct ms_info *ms_card = &(chip->ms_card);
3343 unsigned int lun = SCSI_LUN(srb);
3345 unsigned int index = 0, offset = 0;
3346 u16 old_blk = 0, new_blk = 0, log_blk, total_sec_cnt = sector_cnt;
3347 u8 start_page, end_page = 0, page_cnt;
3349 #ifdef MS_DELAY_WRITE
3350 struct ms_delay_write_tag *delay_write = &(ms_card->delay_write);
3353 ms_set_err_code(chip, MS_NO_ERROR);
3355 ms_card->cleanup_counter = 0;
3357 ptr = (u8 *)scsi_sglist(srb);
3359 retval = ms_switch_clock(chip);
3360 if (retval != STATUS_SUCCESS) {
3361 ms_rw_fail(srb, chip);
3362 TRACE_RET(chip, STATUS_FAIL);
3365 log_blk = (u16)(start_sector >> ms_card->block_shift);
3366 start_page = (u8)(start_sector & ms_card->page_off);
3368 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; seg_no++) {
3369 if (log_blk < ms_start_idx[seg_no+1])
3373 if (ms_card->segment[seg_no].build_flag == 0) {
3374 retval = ms_build_l2p_tbl(chip, seg_no);
3375 if (retval != STATUS_SUCCESS) {
3376 chip->card_fail |= MS_CARD;
3377 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3378 TRACE_RET(chip, STATUS_FAIL);
3382 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3383 #ifdef MS_DELAY_WRITE
3384 if (delay_write->delay_write_flag &&
3385 (delay_write->logblock == log_blk) &&
3386 (start_page > delay_write->pageoff)) {
3387 delay_write->delay_write_flag = 0;
3388 retval = ms_copy_page(chip,
3389 delay_write->old_phyblock,
3390 delay_write->new_phyblock, log_blk,
3391 delay_write->pageoff, start_page);
3392 if (retval != STATUS_SUCCESS) {
3393 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
3394 TRACE_RET(chip, STATUS_FAIL);
3396 old_blk = delay_write->old_phyblock;
3397 new_blk = delay_write->new_phyblock;
3398 } else if (delay_write->delay_write_flag &&
3399 (delay_write->logblock == log_blk) &&
3400 (start_page == delay_write->pageoff)) {
3401 delay_write->delay_write_flag = 0;
3402 old_blk = delay_write->old_phyblock;
3403 new_blk = delay_write->new_phyblock;
3405 retval = ms_delay_write(chip);
3406 if (retval != STATUS_SUCCESS) {
3407 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
3408 TRACE_RET(chip, STATUS_FAIL);
3411 old_blk = ms_get_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no]);
3412 new_blk = ms_get_unused_block(chip, seg_no);
3413 if ((old_blk == 0xFFFF) || (new_blk == 0xFFFF)) {
3414 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
3415 TRACE_RET(chip, STATUS_FAIL);
3418 retval = ms_prepare_write(chip, old_blk, new_blk, log_blk, start_page);
3419 if (retval != STATUS_SUCCESS) {
3420 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3421 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3422 TRACE_RET(chip, STATUS_FAIL);
3424 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
3425 TRACE_RET(chip, STATUS_FAIL);
3427 #ifdef MS_DELAY_WRITE
3431 #ifdef MS_DELAY_WRITE
3432 retval = ms_delay_write(chip);
3433 if (retval != STATUS_SUCCESS) {
3434 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3435 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3436 TRACE_RET(chip, STATUS_FAIL);
3438 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3439 TRACE_RET(chip, STATUS_FAIL);
3442 old_blk = ms_get_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no]);
3443 if (old_blk == 0xFFFF) {
3444 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3445 TRACE_RET(chip, STATUS_FAIL);
3449 RTSX_DEBUGP("seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", seg_no, old_blk, new_blk);
3451 while (total_sec_cnt) {
3452 if ((start_page + total_sec_cnt) > (ms_card->page_off + 1)) {
3453 end_page = ms_card->page_off + 1;
3455 end_page = start_page + (u8)total_sec_cnt;
3457 page_cnt = end_page - start_page;
3459 RTSX_DEBUGP("start_page = %d, end_page = %d, page_cnt = %d\n",
3460 start_page, end_page, page_cnt);
3462 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3463 retval = ms_read_multiple_pages(chip,
3464 old_blk, log_blk, start_page, end_page,
3465 ptr, &index, &offset);
3467 retval = ms_write_multiple_pages(chip, old_blk,
3468 new_blk, log_blk, start_page, end_page,
3469 ptr, &index, &offset);
3472 if (retval != STATUS_SUCCESS) {
3473 toggle_gpio(chip, 1);
3474 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3475 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3476 TRACE_RET(chip, STATUS_FAIL);
3478 ms_rw_fail(srb, chip);
3479 TRACE_RET(chip, STATUS_FAIL);
3482 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3483 if (end_page == (ms_card->page_off + 1)) {
3484 retval = ms_erase_block(chip, old_blk);
3485 if (retval == STATUS_SUCCESS) {
3486 ms_set_unused_block(chip, old_blk);
3488 ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk);
3492 total_sec_cnt -= page_cnt;
3493 if (scsi_sg_count(srb) == 0)
3494 ptr += page_cnt * 512;
3496 if (total_sec_cnt == 0)
3501 for (seg_no = 0; seg_no < sizeof(ms_start_idx)/2; seg_no++) {
3502 if (log_blk < ms_start_idx[seg_no+1])
3506 if (ms_card->segment[seg_no].build_flag == 0) {
3507 retval = ms_build_l2p_tbl(chip, seg_no);
3508 if (retval != STATUS_SUCCESS) {
3509 chip->card_fail |= MS_CARD;
3510 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3511 TRACE_RET(chip, STATUS_FAIL);
3515 old_blk = ms_get_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no]);
3516 if (old_blk == 0xFFFF) {
3517 ms_rw_fail(srb, chip);
3518 TRACE_RET(chip, STATUS_FAIL);
3521 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3522 new_blk = ms_get_unused_block(chip, seg_no);
3523 if (new_blk == 0xFFFF) {
3524 ms_rw_fail(srb, chip);
3525 TRACE_RET(chip, STATUS_FAIL);
3529 RTSX_DEBUGP("seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", seg_no, old_blk, new_blk);
3534 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3535 if (end_page < (ms_card->page_off + 1)) {
3536 #ifdef MS_DELAY_WRITE
3537 delay_write->delay_write_flag = 1;
3538 delay_write->old_phyblock = old_blk;
3539 delay_write->new_phyblock = new_blk;
3540 delay_write->logblock = log_blk;
3541 delay_write->pageoff = end_page;
3543 retval = ms_finish_write(chip, old_blk, new_blk, log_blk, end_page);
3544 if (retval != STATUS_SUCCESS) {
3545 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3546 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3547 TRACE_RET(chip, STATUS_FAIL);
3550 ms_rw_fail(srb, chip);
3551 TRACE_RET(chip, STATUS_FAIL);
3557 scsi_set_resid(srb, 0);
3559 return STATUS_SUCCESS;
3562 int ms_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt)
3564 struct ms_info *ms_card = &(chip->ms_card);
3567 if (CHK_MSPRO(ms_card)) {
3568 retval = mspro_rw_multi_sector(srb, chip, start_sector, sector_cnt);
3570 retval = ms_rw_multi_sector(srb, chip, start_sector, sector_cnt);
3577 void ms_free_l2p_tbl(struct rtsx_chip *chip)
3579 struct ms_info *ms_card = &(chip->ms_card);
3582 if (ms_card->segment != NULL) {
3583 for (i = 0; i < ms_card->segment_cnt; i++) {
3584 if (ms_card->segment[i].l2p_table != NULL) {
3585 vfree(ms_card->segment[i].l2p_table);
3586 ms_card->segment[i].l2p_table = NULL;
3588 if (ms_card->segment[i].free_table != NULL) {
3589 vfree(ms_card->segment[i].free_table);
3590 ms_card->segment[i].free_table = NULL;
3593 vfree(ms_card->segment);
3594 ms_card->segment = NULL;
3598 #ifdef SUPPORT_MAGIC_GATE
3600 #ifdef READ_BYTES_WAIT_INT
3601 static int ms_poll_int(struct rtsx_chip *chip)
3606 rtsx_init_cmd(chip);
3608 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANS_CFG, MS_INT_CED, MS_INT_CED);
3610 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
3611 if (retval != STATUS_SUCCESS) {
3612 TRACE_RET(chip, STATUS_FAIL);
3615 val = *rtsx_get_cmd_data(chip);
3616 if (val & MS_INT_ERR) {
3617 TRACE_RET(chip, STATUS_FAIL);
3620 return STATUS_SUCCESS;
3624 #ifdef MS_SAMPLE_INT_ERR
3625 static int check_ms_err(struct rtsx_chip *chip)
3630 retval = rtsx_read_register(chip, MS_TRANSFER, &val);
3631 if (retval != STATUS_SUCCESS)
3633 if (val & MS_TRANSFER_ERR)
3636 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
3637 if (retval != STATUS_SUCCESS)
3640 if (val & (MS_INT_ERR | MS_INT_CMDNK))
3646 static int check_ms_err(struct rtsx_chip *chip)
3651 retval = rtsx_read_register(chip, MS_TRANSFER, &val);
3652 if (retval != STATUS_SUCCESS)
3654 if (val & MS_TRANSFER_ERR)
3661 static int mg_send_ex_cmd(struct rtsx_chip *chip, u8 cmd, u8 entry_num)
3672 data[6] = entry_num;
3675 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3676 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT, data, 8);
3677 if (retval == STATUS_SUCCESS)
3680 if (i == MS_MAX_RETRY_COUNT) {
3681 TRACE_RET(chip, STATUS_FAIL);
3684 if (check_ms_err(chip)) {
3685 rtsx_clear_ms_error(chip);
3686 TRACE_RET(chip, STATUS_FAIL);
3689 return STATUS_SUCCESS;
3692 static int mg_set_tpc_para_sub(struct rtsx_chip *chip, int type, u8 mg_entry_num)
3697 RTSX_DEBUGP("--%s--\n", __func__);
3700 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_TPCParm, 1);
3702 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
3704 if (retval != STATUS_SUCCESS) {
3705 TRACE_RET(chip, STATUS_FAIL);
3714 buf[5] = mg_entry_num;
3716 retval = ms_write_bytes(chip, PRO_WRITE_REG, (type == 0) ? 1 : 6, NO_WAIT_INT, buf, 6);
3717 if (retval != STATUS_SUCCESS) {
3718 TRACE_RET(chip, STATUS_FAIL);
3721 return STATUS_SUCCESS;
3724 int mg_set_leaf_id(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3728 unsigned int lun = SCSI_LUN(srb);
3729 u8 buf1[32], buf2[12];
3731 RTSX_DEBUGP("--%s--\n", __func__);
3733 if (scsi_bufflen(srb) < 12) {
3734 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3735 TRACE_RET(chip, STATUS_FAIL);
3738 ms_cleanup_work(chip);
3740 retval = ms_switch_clock(chip);
3741 if (retval != STATUS_SUCCESS) {
3742 TRACE_RET(chip, STATUS_FAIL);
3745 retval = mg_send_ex_cmd(chip, MG_SET_LID, 0);
3746 if (retval != STATUS_SUCCESS) {
3747 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
3748 TRACE_RET(chip, STATUS_FAIL);
3751 memset(buf1, 0, 32);
3752 rtsx_stor_get_xfer_buf(buf2, min(12, (int)scsi_bufflen(srb)), srb);
3753 for (i = 0; i < 8; i++) {
3754 buf1[8+i] = buf2[4+i];
3756 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT, buf1, 32);
3757 if (retval != STATUS_SUCCESS) {
3758 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
3759 TRACE_RET(chip, STATUS_FAIL);
3761 if (check_ms_err(chip)) {
3762 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
3763 rtsx_clear_ms_error(chip);
3764 TRACE_RET(chip, STATUS_FAIL);
3767 return STATUS_SUCCESS;
3770 int mg_get_local_EKB(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3772 int retval = STATUS_FAIL;
3774 unsigned int lun = SCSI_LUN(srb);
3777 RTSX_DEBUGP("--%s--\n", __func__);
3779 ms_cleanup_work(chip);
3781 retval = ms_switch_clock(chip);
3782 if (retval != STATUS_SUCCESS) {
3783 TRACE_RET(chip, STATUS_FAIL);
3786 buf = (u8 *)rtsx_alloc_dma_buf(chip, 1540, GFP_KERNEL);
3788 TRACE_RET(chip, STATUS_ERROR);
3796 retval = mg_send_ex_cmd(chip, MG_GET_LEKB, 0);
3797 if (retval != STATUS_SUCCESS) {
3798 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3799 TRACE_GOTO(chip, GetEKBFinish);
3802 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
3803 3, WAIT_INT, 0, 0, buf + 4, 1536);
3804 if (retval != STATUS_SUCCESS) {
3805 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3806 rtsx_clear_ms_error(chip);
3807 TRACE_GOTO(chip, GetEKBFinish);
3809 if (check_ms_err(chip)) {
3810 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3811 rtsx_clear_ms_error(chip);
3812 TRACE_RET(chip, STATUS_FAIL);
3815 bufflen = min(1052, (int)scsi_bufflen(srb));
3816 rtsx_stor_set_xfer_buf(buf, bufflen, srb);
3820 rtsx_free_dma_buf(chip, buf);
3825 int mg_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3827 struct ms_info *ms_card = &(chip->ms_card);
3831 unsigned int lun = SCSI_LUN(srb);
3834 RTSX_DEBUGP("--%s--\n", __func__);
3836 ms_cleanup_work(chip);
3838 retval = ms_switch_clock(chip);
3839 if (retval != STATUS_SUCCESS) {
3840 TRACE_RET(chip, STATUS_FAIL);
3843 retval = mg_send_ex_cmd(chip, MG_GET_ID, 0);
3844 if (retval != STATUS_SUCCESS) {
3845 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3846 TRACE_RET(chip, STATUS_FAIL);
3849 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT, buf, 32);
3850 if (retval != STATUS_SUCCESS) {
3851 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3852 TRACE_RET(chip, STATUS_FAIL);
3854 if (check_ms_err(chip)) {
3855 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3856 rtsx_clear_ms_error(chip);
3857 TRACE_RET(chip, STATUS_FAIL);
3860 memcpy(ms_card->magic_gate_id, buf, 16);
3862 #ifdef READ_BYTES_WAIT_INT
3863 retval = ms_poll_int(chip);
3864 if (retval != STATUS_SUCCESS) {
3865 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3866 TRACE_RET(chip, STATUS_FAIL);
3870 retval = mg_send_ex_cmd(chip, MG_SET_RD, 0);
3871 if (retval != STATUS_SUCCESS) {
3872 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3873 TRACE_RET(chip, STATUS_FAIL);
3876 bufflen = min(12, (int)scsi_bufflen(srb));
3877 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
3879 for (i = 0; i < 8; i++) {
3882 for (i = 0; i < 24; i++) {
3885 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA,
3886 32, WAIT_INT, buf, 32);
3887 if (retval != STATUS_SUCCESS) {
3888 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3889 TRACE_RET(chip, STATUS_FAIL);
3891 if (check_ms_err(chip)) {
3892 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3893 rtsx_clear_ms_error(chip);
3894 TRACE_RET(chip, STATUS_FAIL);
3897 ms_card->mg_auth = 0;
3899 return STATUS_SUCCESS;
3902 int mg_get_rsp_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3904 struct ms_info *ms_card = &(chip->ms_card);
3907 unsigned int lun = SCSI_LUN(srb);
3908 u8 buf1[32], buf2[36];
3910 RTSX_DEBUGP("--%s--\n", __func__);
3912 ms_cleanup_work(chip);
3914 retval = ms_switch_clock(chip);
3915 if (retval != STATUS_SUCCESS) {
3916 TRACE_RET(chip, STATUS_FAIL);
3919 retval = mg_send_ex_cmd(chip, MG_MAKE_RMS, 0);
3920 if (retval != STATUS_SUCCESS) {
3921 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3922 TRACE_RET(chip, STATUS_FAIL);
3925 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT, buf1, 32);
3926 if (retval != STATUS_SUCCESS) {
3927 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3928 TRACE_RET(chip, STATUS_FAIL);
3930 if (check_ms_err(chip)) {
3931 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3932 rtsx_clear_ms_error(chip);
3933 TRACE_RET(chip, STATUS_FAIL);
3941 memcpy(buf2 + 4, ms_card->magic_gate_id, 16);
3942 memcpy(buf2 + 20, buf1, 16);
3944 bufflen = min(36, (int)scsi_bufflen(srb));
3945 rtsx_stor_set_xfer_buf(buf2, bufflen, srb);
3947 #ifdef READ_BYTES_WAIT_INT
3948 retval = ms_poll_int(chip);
3949 if (retval != STATUS_SUCCESS) {
3950 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3951 TRACE_RET(chip, STATUS_FAIL);
3955 return STATUS_SUCCESS;
3958 int mg_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3960 struct ms_info *ms_card = &(chip->ms_card);
3964 unsigned int lun = SCSI_LUN(srb);
3967 RTSX_DEBUGP("--%s--\n", __func__);
3969 ms_cleanup_work(chip);
3971 retval = ms_switch_clock(chip);
3972 if (retval != STATUS_SUCCESS) {
3973 TRACE_RET(chip, STATUS_FAIL);
3976 retval = mg_send_ex_cmd(chip, MG_MAKE_KSE, 0);
3977 if (retval != STATUS_SUCCESS) {
3978 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3979 TRACE_RET(chip, STATUS_FAIL);
3982 bufflen = min(12, (int)scsi_bufflen(srb));
3983 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
3985 for (i = 0; i < 8; i++) {
3988 for (i = 0; i < 24; i++) {
3991 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT, buf, 32);
3992 if (retval != STATUS_SUCCESS) {
3993 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3994 TRACE_RET(chip, STATUS_FAIL);
3996 if (check_ms_err(chip)) {
3997 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3998 rtsx_clear_ms_error(chip);
3999 TRACE_RET(chip, STATUS_FAIL);
4002 ms_card->mg_auth = 1;
4004 return STATUS_SUCCESS;
4007 int mg_get_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4009 struct ms_info *ms_card = &(chip->ms_card);
4012 unsigned int lun = SCSI_LUN(srb);
4015 RTSX_DEBUGP("--%s--\n", __func__);
4017 ms_cleanup_work(chip);
4019 retval = ms_switch_clock(chip);
4020 if (retval != STATUS_SUCCESS) {
4021 TRACE_RET(chip, STATUS_FAIL);
4024 buf = (u8 *)rtsx_alloc_dma_buf(chip, 1028, GFP_KERNEL);
4026 TRACE_RET(chip, STATUS_ERROR);
4034 retval = mg_send_ex_cmd(chip, MG_GET_IBD, ms_card->mg_entry_num);
4035 if (retval != STATUS_SUCCESS) {
4036 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4037 TRACE_GOTO(chip, GetICVFinish);
4040 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
4041 2, WAIT_INT, 0, 0, buf + 4, 1024);
4042 if (retval != STATUS_SUCCESS) {
4043 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4044 rtsx_clear_ms_error(chip);
4045 TRACE_GOTO(chip, GetICVFinish);
4047 if (check_ms_err(chip)) {
4048 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4049 rtsx_clear_ms_error(chip);
4050 TRACE_RET(chip, STATUS_FAIL);
4053 bufflen = min(1028, (int)scsi_bufflen(srb));
4054 rtsx_stor_set_xfer_buf(buf, bufflen, srb);
4058 rtsx_free_dma_buf(chip, buf);
4063 int mg_set_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4065 struct ms_info *ms_card = &(chip->ms_card);
4068 #ifdef MG_SET_ICV_SLOW
4071 unsigned int lun = SCSI_LUN(srb);
4074 RTSX_DEBUGP("--%s--\n", __func__);
4076 ms_cleanup_work(chip);
4078 retval = ms_switch_clock(chip);
4079 if (retval != STATUS_SUCCESS) {
4080 TRACE_RET(chip, STATUS_FAIL);
4083 buf = (u8 *)rtsx_alloc_dma_buf(chip, 1028, GFP_KERNEL);
4085 TRACE_RET(chip, STATUS_ERROR);
4088 bufflen = min(1028, (int)scsi_bufflen(srb));
4089 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
4091 retval = mg_send_ex_cmd(chip, MG_SET_IBD, ms_card->mg_entry_num);
4092 if (retval != STATUS_SUCCESS) {
4093 if (ms_card->mg_auth == 0) {
4094 if ((buf[5] & 0xC0) != 0) {
4095 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4097 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
4100 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
4102 TRACE_GOTO(chip, SetICVFinish);
4105 #ifdef MG_SET_ICV_SLOW
4106 for (i = 0; i < 2; i++) {
4109 rtsx_init_cmd(chip);
4111 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, PRO_WRITE_LONG_DATA);
4112 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, WAIT_INT);
4113 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
4115 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
4117 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
4118 MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
4119 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
4121 rtsx_send_cmd_no_wait(chip);
4123 retval = rtsx_transfer_data(chip, MS_CARD, buf + 4 + i*512, 512, 0, DMA_TO_DEVICE, 3000);
4124 if ((retval < 0) || check_ms_err(chip)) {
4125 rtsx_clear_ms_error(chip);
4126 if (ms_card->mg_auth == 0) {
4127 if ((buf[5] & 0xC0) != 0) {
4128 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4130 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
4133 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
4135 retval = STATUS_FAIL;
4136 TRACE_GOTO(chip, SetICVFinish);
4140 retval = ms_transfer_data(chip, MS_TM_AUTO_WRITE, PRO_WRITE_LONG_DATA,
4141 2, WAIT_INT, 0, 0, buf + 4, 1024);
4142 if ((retval != STATUS_SUCCESS) || check_ms_err(chip) {
4143 rtsx_clear_ms_error(chip);
4144 if (ms_card->mg_auth == 0) {
4145 if ((buf[5] & 0xC0) != 0) {
4146 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4148 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
4151 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
4153 TRACE_GOTO(chip, SetICVFinish);
4159 rtsx_free_dma_buf(chip, buf);
4164 #endif /* SUPPORT_MAGIC_GATE */
4166 void ms_cleanup_work(struct rtsx_chip *chip)
4168 struct ms_info *ms_card = &(chip->ms_card);
4170 if (CHK_MSPRO(ms_card)) {
4171 if (ms_card->seq_mode) {
4172 RTSX_DEBUGP("MS Pro: stop transmission\n");
4173 mspro_stop_seq_mode(chip);
4174 ms_card->cleanup_counter = 0;
4176 if (CHK_MSHG(ms_card)) {
4177 rtsx_write_register(chip, MS_CFG,
4178 MS_2K_SECTOR_MODE, 0x00);
4181 #ifdef MS_DELAY_WRITE
4182 else if ((!CHK_MSPRO(ms_card)) && ms_card->delay_write.delay_write_flag) {
4183 RTSX_DEBUGP("MS: delay write\n");
4184 ms_delay_write(chip);
4185 ms_card->cleanup_counter = 0;
4190 int ms_power_off_card3v3(struct rtsx_chip *chip)
4194 retval = disable_card_clock(chip, MS_CARD);
4195 if (retval != STATUS_SUCCESS) {
4196 TRACE_RET(chip, STATUS_FAIL);
4198 if (chip->asic_code) {
4199 retval = ms_pull_ctl_disable(chip);
4200 if (retval != STATUS_SUCCESS) {
4201 TRACE_RET(chip, STATUS_FAIL);
4204 RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
4205 FPGA_MS_PULL_CTL_BIT | 0x20, FPGA_MS_PULL_CTL_BIT);
4207 RTSX_WRITE_REG(chip, CARD_OE, MS_OUTPUT_EN, 0);
4208 if (!chip->ft2_fast_mode) {
4209 retval = card_power_off(chip, MS_CARD);
4210 if (retval != STATUS_SUCCESS) {
4211 TRACE_RET(chip, STATUS_FAIL);
4215 return STATUS_SUCCESS;
4218 int release_ms_card(struct rtsx_chip *chip)
4220 struct ms_info *ms_card = &(chip->ms_card);
4223 RTSX_DEBUGP("release_ms_card\n");
4225 #ifdef MS_DELAY_WRITE
4226 ms_card->delay_write.delay_write_flag = 0;
4228 ms_card->pro_under_formatting = 0;
4230 chip->card_ready &= ~MS_CARD;
4231 chip->card_fail &= ~MS_CARD;
4232 chip->card_wp &= ~MS_CARD;
4234 ms_free_l2p_tbl(chip);
4236 memset(ms_card->raw_sys_info, 0, 96);
4237 #ifdef SUPPORT_PCGL_1P18
4238 memset(ms_card->raw_model_name, 0, 48);
4241 retval = ms_power_off_card3v3(chip);
4242 if (retval != STATUS_SUCCESS) {
4243 TRACE_RET(chip, STATUS_FAIL);
4246 return STATUS_SUCCESS;