drivers/staging/rts5139/sd.c

   1 /* Driver for Realtek RTS51xx USB card reader
   2  *
   3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   wwang (wei_wang@realsil.com.cn)
  20  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21  * Maintainer:
  22  *   Edwin Rong (edwin_rong@realsil.com.cn)
  23  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  24  */
  25
  26 #include <linux/blkdev.h>
  27 #include <linux/kthread.h>
  28 #include <linux/sched.h>
  29
  30 #include "debug.h"
  31 #include "trace.h"
  32 #include "rts51x.h"
  33 #include "rts51x_transport.h"
  34 #include "rts51x_scsi.h"
  35 #include "rts51x_card.h"
  36 #include "sd.h"
  37
  38 static inline void sd_set_reset_fail(struct rts51x_chip *chip, u8 err_code)
  39 {
  40         struct sd_info *sd_card = &(chip->sd_card);
  41
  42         sd_card->sd_reset_fail |= err_code;
  43 }
  44
  45 static inline void sd_clear_reset_fail(struct rts51x_chip *chip)
  46 {
  47         struct sd_info *sd_card = &(chip->sd_card);
  48
  49         sd_card->sd_reset_fail = 0;
  50 }
  51
  52 static inline int sd_check_reset_fail(struct rts51x_chip *chip, u8 err_code)
  53 {
  54         struct sd_info *sd_card = &(chip->sd_card);
  55
  56         return sd_card->sd_reset_fail & err_code;
  57 }
  58
  59 static inline void sd_set_err_code(struct rts51x_chip *chip, u8 err_code)
  60 {
  61         struct sd_info *sd_card = &(chip->sd_card);
  62
  63         sd_card->err_code |= err_code;
  64 }
  65
  66 static inline void sd_clr_err_code(struct rts51x_chip *chip)
  67 {
  68         struct sd_info *sd_card = &(chip->sd_card);
  69
  70         sd_card->err_code = 0;
  71 }
  72
  73 static inline int sd_check_err_code(struct rts51x_chip *chip, u8 err_code)
  74 {
  75         struct sd_info *sd_card = &(chip->sd_card);
  76
  77         return sd_card->err_code & err_code;
  78 }
  79
  80 static int sd_parse_err_code(struct rts51x_chip *chip)
  81 {
  82         TRACE_RET(chip, STATUS_FAIL);
  83 }
  84
  85 int sd_check_data0_status(struct rts51x_chip *chip)
  86 {
  87         int retval;
  88         u8 stat;
  89
  90         retval = rts51x_ep0_read_register(chip, SD_BUS_STAT, &stat);
  91         if (retval != STATUS_SUCCESS)
  92                 TRACE_RET(chip, retval);
  93         if (!(stat & SD_DAT0_STATUS)) {
  94                 sd_set_err_code(chip, SD_BUSY);
  95                 TRACE_RET(chip, STATUS_FAIL);
  96         }
  97
  98         return STATUS_SUCCESS;
  99 }
 100
 101 static int sd_send_cmd_get_rsp(struct rts51x_chip *chip, u8 cmd_idx,
 102                                u32 arg, u8 rsp_type, u8 *rsp, int rsp_len)
 103 {
 104         struct sd_info *sd_card = &(chip->sd_card);
 105         int retval;
 106         int timeout = 50;
 107         u16 reg_addr;
 108         u8 buf[17], stat;
 109         int len = 2;
 110         int rty_cnt = 0;
 111
 112         sd_clr_err_code(chip);
 113
 114         RTS51X_DEBUGP("SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg);
 115
 116         if (rsp_type == SD_RSP_TYPE_R1b)
 117                 timeout = 3000;
 118
 119 RTY_SEND_CMD:
 120
 121         rts51x_init_cmd(chip);
 122
 123         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
 124         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8) (arg >> 24));
 125         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8) (arg >> 16));
 126         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8) (arg >> 8));
 127         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8) arg);
 128
 129         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
 130         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
 131                        PINGPONG_BUFFER);
 132         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 133                        SD_TM_CMD_RSP | SD_TRANSFER_START);
 134         rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER,
 135                        SD_TRANSFER_END | SD_STAT_IDLE,
 136                        SD_TRANSFER_END | SD_STAT_IDLE);
 137
 138         rts51x_add_cmd(chip, READ_REG_CMD, SD_STAT1, 0, 0);
 139
 140         if (CHECK_USB(chip, USB_20)) {
 141                 if (rsp_type == SD_RSP_TYPE_R2) {
 142                         /* Read data from ping-pong buffer */
 143                         for (reg_addr = PPBUF_BASE2;
 144                              reg_addr < PPBUF_BASE2 + 16; reg_addr++) {
 145                                 rts51x_add_cmd(chip, READ_REG_CMD, reg_addr, 0,
 146                                                0);
 147                         }
 148                         len = 18;
 149                 } else if (rsp_type != SD_RSP_TYPE_R0) {
 150                         /* Read data from SD_CMDx registers */
 151                         for (reg_addr = SD_CMD0; reg_addr <= SD_CMD4;
 152                              reg_addr++) {
 153                                 rts51x_add_cmd(chip, READ_REG_CMD, reg_addr, 0,
 154                                                0);
 155                         }
 156                         len = 7;
 157                 } else {
 158                         len = 2;
 159                 }
 160         } else {
 161                 len = 2;
 162         }
 163
 164         retval = rts51x_send_cmd(chip, MODE_CR, 100);
 165         if (retval != STATUS_SUCCESS)
 166                 TRACE_RET(chip, retval);
 167
 168         retval = rts51x_get_rsp(chip, len, timeout);
 169
 170         if (CHECK_SD_TRANS_FAIL(chip, retval)) {
 171                 u8 val;
 172
 173                 rts51x_ep0_read_register(chip, SD_STAT1, &val);
 174                 RTS51X_DEBUGP("SD_STAT1: 0x%x\n", val);
 175
 176                 rts51x_ep0_read_register(chip, SD_STAT2, &val);
 177                 RTS51X_DEBUGP("SD_STAT2: 0x%x\n", val);
 178
 179                 if (val & SD_RSP_80CLK_TIMEOUT)
 180                         sd_set_err_code(chip, SD_RSP_TIMEOUT);
 181
 182                 rts51x_ep0_read_register(chip, SD_BUS_STAT, &val);
 183                 RTS51X_DEBUGP("SD_BUS_STAT: 0x%x\n", val);
 184
 185                 if (retval == STATUS_TIMEDOUT) {
 186                         if (rsp_type & SD_WAIT_BUSY_END) {
 187                                 retval = sd_check_data0_status(chip);
 188                                 if (retval != STATUS_SUCCESS)
 189                                         TRACE_RET(chip, retval);
 190                         } else {
 191                                 sd_set_err_code(chip, SD_TO_ERR);
 192                         }
 193                 }
 194                 rts51x_clear_sd_error(chip);
 195
 196                 TRACE_RET(chip, STATUS_FAIL);
 197         }
 198
 199         if (rsp_type == SD_RSP_TYPE_R0)
 200                 return STATUS_SUCCESS;
 201
 202         if (CHECK_USB(chip, USB_20)) {
 203                 rts51x_read_rsp_buf(chip, 2, buf, len - 2);
 204         } else {
 205                 if (rsp_type == SD_RSP_TYPE_R2) {
 206                         reg_addr = PPBUF_BASE2;
 207                         len = 16;
 208                 } else {
 209                         reg_addr = SD_CMD0;
 210                         len = 5;
 211                 }
 212                 retval = rts51x_seq_read_register(chip, reg_addr,
 213                                                      (unsigned short)len, buf);
 214                 if (retval != STATUS_SUCCESS)
 215                         TRACE_RET(chip, retval);
 216         }
 217         stat = chip->rsp_buf[1];
 218
 219         /* Check (Start,Transmission) bit of Response */
 220         if ((buf[0] & 0xC0) != 0) {
 221                 sd_set_err_code(chip, SD_STS_ERR);
 222                 TRACE_RET(chip, STATUS_FAIL);
 223         }
 224         /* Check CRC7 */
 225         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
 226                 if (stat & SD_CRC7_ERR) {
 227                         if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
 228                                 sd_set_err_code(chip, SD_CRC_ERR);
 229                                 TRACE_RET(chip, STATUS_FAIL);
 230                         }
 231                         if (rty_cnt < SD_MAX_RETRY_COUNT) {
 232                                 wait_timeout(20);
 233                                 rty_cnt++;
 234                                 goto RTY_SEND_CMD;
 235                         } else {
 236                                 sd_set_err_code(chip, SD_CRC_ERR);
 237                                 TRACE_RET(chip, STATUS_FAIL);
 238                         }
 239                 }
 240         }
 241         /* Check Status */
 242         if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) {
 243                 if ((cmd_idx != SEND_RELATIVE_ADDR)
 244                     && (cmd_idx != SEND_IF_COND)) {
 245                         if (cmd_idx != STOP_TRANSMISSION) {
 246                                 if (buf[1] & 0x80)
 247                                         TRACE_RET(chip, STATUS_FAIL);
 248                         }
 249 #ifdef SUPPORT_SD_LOCK
 250                         /* exclude bit25 CARD_IS_LOCKED */
 251                         if (buf[1] & 0x7D) {
 252 #else
 253                         if (buf[1] & 0x7F) {
 254 #endif
 255                                 RTS51X_DEBUGP("buf[1]: 0x%02x\n", buf[1]);
 256                                 TRACE_RET(chip, STATUS_FAIL);
 257                         }
 258                         if (buf[2] & 0xFF) {
 259                                 RTS51X_DEBUGP("buf[2]: 0x%02x\n", buf[2]);
 260                                 TRACE_RET(chip, STATUS_FAIL);
 261                         }
 262                         if (buf[3] & 0x80) {
 263                                 RTS51X_DEBUGP("buf[3]: 0x%02x\n", buf[3]);
 264                                 TRACE_RET(chip, STATUS_FAIL);
 265                         }
 266                         if (buf[3] & 0x01) {
 267                                 /* Get "READY_FOR_DATA" bit */
 268                                 sd_card->sd_data_buf_ready = 1;
 269                         } else {
 270                                 sd_card->sd_data_buf_ready = 0;
 271                         }
 272                 }
 273         }
 274
 275         if (rsp && rsp_len)
 276                 memcpy(rsp, buf, rsp_len);
 277
 278         return STATUS_SUCCESS;
 279 }
 280
 281 static inline void sd_print_debug_reg(struct rts51x_chip *chip)
 282 {
 283 #ifdef CONFIG_RTS5139_DEBUG
 284         u8 val = 0;
 285
 286         rts51x_ep0_read_register(chip, SD_STAT1, &val);
 287         RTS51X_DEBUGP("SD_STAT1: 0x%x\n", val);
 288         rts51x_ep0_read_register(chip, SD_STAT2, &val);
 289         RTS51X_DEBUGP("SD_STAT2: 0x%x\n", val);
 290         rts51x_ep0_read_register(chip, SD_BUS_STAT, &val);
 291         RTS51X_DEBUGP("SD_BUS_STAT: 0x%x\n", val);
 292 #endif
 293 }
 294
 295 int sd_read_data(struct rts51x_chip *chip, u8 trans_mode, u8 *cmd, int cmd_len,
 296                  u16 byte_cnt, u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len,
 297                  int timeout)
 298 {
 299         struct sd_info *sd_card = &(chip->sd_card);
 300         int retval;
 301         int i;
 302
 303         sd_clr_err_code(chip);
 304
 305         if (!buf)
 306                 buf_len = 0;
 307
 308         if (buf_len > 512)
 309                 /* This function can't read data more than one page */
 310                 TRACE_RET(chip, STATUS_FAIL);
 311
 312         rts51x_init_cmd(chip);
 313
 314         if (cmd_len) {
 315                 RTS51X_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40);
 316                 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
 317                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0 + i, 0xFF,
 318                                        cmd[i]);
 319                 }
 320         }
 321         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8) byte_cnt);
 322         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF,
 323                        (u8) (byte_cnt >> 8));
 324         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, (u8) blk_cnt);
 325         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF,
 326                        (u8) (blk_cnt >> 8));
 327
 328         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x03, bus_width);
 329
 330         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
 331                        SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END
 332                        | SD_CHECK_CRC7 | SD_RSP_LEN_6);
 333         if (trans_mode != SD_TM_AUTO_TUNING) {
 334                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
 335                                PINGPONG_BUFFER);
 336         }
 337         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 338                        trans_mode | SD_TRANSFER_START);
 339         rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END,
 340                        SD_TRANSFER_END);
 341
 342         retval = rts51x_send_cmd(chip, MODE_CR, 100);
 343         if (retval != STATUS_SUCCESS)
 344                 TRACE_RET(chip, retval);
 345
 346         retval = rts51x_get_rsp(chip, 1, timeout);
 347
 348         if (CHECK_SD_TRANS_FAIL(chip, retval)) {
 349                 sd_print_debug_reg(chip);
 350                 if (retval == STATUS_TIMEDOUT) {
 351                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
 352                                             SD_RSP_TYPE_R1, NULL, 0);
 353                 }
 354
 355                 TRACE_RET(chip, STATUS_FAIL);
 356         }
 357
 358         if (buf && buf_len) {
 359                 retval = rts51x_read_ppbuf(chip, buf, buf_len);
 360                 if (retval != STATUS_SUCCESS)
 361                         TRACE_RET(chip, retval);
 362         }
 363
 364         return STATUS_SUCCESS;
 365 }
 366
 367 static int sd_write_data(struct rts51x_chip *chip, u8 trans_mode,
 368                          u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt,
 369                          u8 bus_width, u8 *buf, int buf_len, int timeout)
 370 {
 371         struct sd_info *sd_card = &(chip->sd_card);
 372         int retval;
 373         int i;
 374
 375         sd_clr_err_code(chip);
 376
 377         if (!buf)
 378                 buf_len = 0;
 379
 380         /* This function can't write data more than one page */
 381         if (buf_len > 512)
 382                 TRACE_RET(chip, STATUS_FAIL);
 383
 384         if (buf && buf_len) {
 385                 retval = rts51x_write_ppbuf(chip, buf, buf_len);
 386                 if (retval != STATUS_SUCCESS)
 387                         TRACE_RET(chip, retval);
 388         }
 389
 390         rts51x_init_cmd(chip);
 391
 392         if (cmd_len) {
 393                 RTS51X_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40);
 394                 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
 395                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0 + i, 0xFF,
 396                                        cmd[i]);
 397                 }
 398         }
 399         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8) byte_cnt);
 400         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF,
 401                        (u8) (byte_cnt >> 8));
 402         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, (u8) blk_cnt);
 403         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF,
 404                        (u8) (blk_cnt >> 8));
 405
 406         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x03, bus_width);
 407
 408         if (cmd_len) {
 409                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
 410                                SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 411                                SD_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
 412
 413         } else {
 414                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
 415                                SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 416                                SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 |
 417                                SD_RSP_LEN_6);
 418         }
 419
 420         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 421                        trans_mode | SD_TRANSFER_START);
 422         rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END,
 423                        SD_TRANSFER_END);
 424
 425         retval = rts51x_send_cmd(chip, MODE_CR, 100);
 426         if (retval != STATUS_SUCCESS)
 427                 TRACE_RET(chip, retval);
 428
 429         retval = rts51x_get_rsp(chip, 1, timeout);
 430
 431         if (CHECK_SD_TRANS_FAIL(chip, retval)) {
 432                 sd_print_debug_reg(chip);
 433
 434                 if (retval == STATUS_TIMEDOUT)
 435                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
 436                                             SD_RSP_TYPE_R1, NULL, 0);
 437
 438                 TRACE_RET(chip, STATUS_FAIL);
 439         }
 440
 441         return STATUS_SUCCESS;
 442 }
 443
 444 static int sd_check_csd(struct rts51x_chip *chip, char check_wp)
 445 {
 446         struct sd_info *sd_card = &(chip->sd_card);
 447         int retval;
 448         int i;
 449         u8 csd_ver, trans_speed;
 450         u8 rsp[16];
 451
 452         for (i = 0; i < 6; i++) {
 453                 if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST) {
 454                         sd_set_reset_fail(chip, SD_RESET_FAIL);
 455                         TRACE_RET(chip, STATUS_FAIL);
 456                 }
 457
 458                 retval =
 459                     sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr,
 460                                         SD_RSP_TYPE_R2, rsp, 16);
 461                 if (retval == STATUS_SUCCESS)
 462                         break;
 463         }
 464
 465         if (i == 6)
 466                 TRACE_RET(chip, STATUS_FAIL);
 467         memcpy(sd_card->raw_csd, rsp + 1, 15);
 468         /* Get CRC7 */
 469         RTS51X_READ_REG(chip, SD_CMD5, sd_card->raw_csd + 15);
 470
 471         RTS51X_DEBUGP("CSD Response:\n");
 472         RTS51X_DUMP(rsp, 16);
 473
 474         /* Get CSD Version */
 475         csd_ver = (rsp[1] & 0xc0) >> 6;
 476         RTS51X_DEBUGP("csd_ver = %d\n", csd_ver);
 477
 478         trans_speed = rsp[4];
 479         if ((trans_speed & 0x07) == 0x02) {     /* 10Mbits/s */
 480                 if ((trans_speed & 0xf8) >= 0x30) {     /* >25Mbits/s */
 481                         if (chip->asic_code)
 482                                 sd_card->sd_clock = 46;
 483                         else
 484                                 sd_card->sd_clock = CLK_50;
 485                 } else if ((trans_speed & 0xf8) == 0x28) { /* 20Mbits/s */
 486                         if (chip->asic_code)
 487                                 sd_card->sd_clock = 39;
 488                         else
 489                                 sd_card->sd_clock = CLK_40;
 490                 } else if ((trans_speed & 0xf8) == 0x20) { /* 15Mbits/s */
 491                         if (chip->asic_code)
 492                                 sd_card->sd_clock = 29;
 493                         else
 494                                 sd_card->sd_clock = CLK_30;
 495                 } else if ((trans_speed & 0xf8) >= 0x10) { /* 12Mbits/s */
 496                         if (chip->asic_code)
 497                                 sd_card->sd_clock = 23;
 498                         else
 499                                 sd_card->sd_clock = CLK_20;
 500                 } else if ((trans_speed & 0x08) >= 0x08) { /* 10Mbits/s */
 501                         if (chip->asic_code)
 502                                 sd_card->sd_clock = 19;
 503                         else
 504                                 sd_card->sd_clock = CLK_20;
 505                 } /*else { */
 506                         /*If this ,then slow card will use 30M clock */
 507                         /* TRACE_RET(chip, STATUS_FAIL); */
 508                 /* } */
 509         }
 510         /*else {
 511            TRACE_RET(chip, STATUS_FAIL);
 512            } */
 513         if (CHK_MMC_SECTOR_MODE(sd_card)) {
 514                 sd_card->capacity = 0;
 515         } else {
 516                 /* For High-Capacity Card, CSD_STRUCTURE always be "0x1" */
 517                 if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) {
 518                         /* Calculate total sector according to C_SIZE,
 519                          * C_SIZE_MULT & READ_BL_LEN */
 520                         u8 blk_size, c_size_mult;
 521                         u16 c_size;
 522                         /* Get READ_BL_LEN */
 523                         blk_size = rsp[6] & 0x0F;
 524                         /* Get C_SIZE */
 525                         c_size = ((u16) (rsp[7] & 0x03) << 10)
 526                             + ((u16) rsp[8] << 2)
 527                             + ((u16) (rsp[9] & 0xC0) >> 6);
 528                         /* Get C_SIZE_MUL */
 529                         c_size_mult = (u8) ((rsp[10] & 0x03) << 1);
 530                         c_size_mult += (rsp[11] & 0x80) >> 7;
 531                         /* Calculate total Capacity  */
 532                         sd_card->capacity =
 533                             (((u32) (c_size + 1)) *
 534                              (1 << (c_size_mult + 2))) << (blk_size - 9);
 535                 } else {
 536                         /* High Capacity Card and Use CSD2.0 Version */
 537                         u32 total_sector = 0;
 538                         total_sector = (((u32) rsp[8] & 0x3f) << 16) |
 539                             ((u32) rsp[9] << 8) | (u32) rsp[10];
 540                         /* Total Capacity= (C_SIZE+1) *
 541                          * 512K Byte = (C_SIZE+1)K Sector,1K = 1024 Bytes */
 542                         sd_card->capacity = (total_sector + 1) << 10;
 543                 }
 544         }
 545
 546         /* We need check Write-Protected Status by Field PERM WP or TEMP WP */
 547         if (check_wp) {
 548                 if (rsp[15] & 0x30)
 549                         chip->card_wp |= SD_CARD;
 550                 RTS51X_DEBUGP("CSD WP Status: 0x%x\n", rsp[15]);
 551         }
 552
 553         return STATUS_SUCCESS;
 554 }
 555
 556 static int sd_set_sample_push_timing(struct rts51x_chip *chip)
 557 {
 558         struct sd_info *sd_card = &(chip->sd_card);
 559         int retval;
 560
 561         rts51x_init_cmd(chip);
 562
 563         if (CHK_SD_SDR104(sd_card) || CHK_SD_SDR50(sd_card)) {
 564                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1,
 565                                0x0C | SD_ASYNC_FIFO_RST,
 566                                SD_30_MODE | SD_ASYNC_FIFO_RST);
 567                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
 568                                CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 569         } else if (CHK_SD_DDR50(sd_card) || CHK_MMC_DDR52(sd_card)) {
 570                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1,
 571                                0x0C | SD_ASYNC_FIFO_RST,
 572                                SD_DDR_MODE | SD_ASYNC_FIFO_RST);
 573                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
 574                                CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 575                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
 576                                DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
 577                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
 578                                DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
 579                                DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
 580         } else {
 581                 u8 val = 0;
 582
 583                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x0C, SD_20_MODE);
 584                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
 585                                CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
 586
 587                 if ((chip->option.sd_ctl & SD_PUSH_POINT_CTL_MASK) ==
 588                     SD_PUSH_POINT_AUTO) {
 589                         val = SD20_TX_NEG_EDGE;
 590                 } else if ((chip->option.sd_ctl & SD_PUSH_POINT_CTL_MASK) ==
 591                            SD_PUSH_POINT_DELAY) {
 592                         val = SD20_TX_14_AHEAD;
 593                 } else {
 594                         val = SD20_TX_NEG_EDGE;
 595                 }
 596                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
 597                                SD20_TX_SEL_MASK, val);
 598
 599                 if ((chip->option.sd_ctl & SD_SAMPLE_POINT_CTL_MASK) ==
 600                     SD_SAMPLE_POINT_AUTO) {
 601                         if (chip->asic_code) {
 602                                 if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card))
 603                                         val = SD20_RX_14_DELAY;
 604                                 else
 605                                         val = SD20_RX_POS_EDGE;
 606                         } else {
 607                                 val = SD20_RX_14_DELAY;
 608                         }
 609                 } else if ((chip->option.sd_ctl & SD_SAMPLE_POINT_CTL_MASK) ==
 610                            SD_SAMPLE_POINT_DELAY) {
 611                         val = SD20_RX_14_DELAY;
 612                 } else {
 613                         val = SD20_RX_POS_EDGE;
 614                 }
 615                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
 616                                SD20_RX_SEL_MASK, val);
 617         }
 618
 619         if (CHK_MMC_DDR52(sd_card) && CHK_MMC_8BIT(sd_card)) {
 620                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DMA1_CTL,
 621                                EXTEND_DMA1_ASYNC_SIGNAL, 0);
 622         }
 623
 624         retval = rts51x_send_cmd(chip, MODE_C, 100);
 625         if (retval != STATUS_SUCCESS)
 626                 TRACE_RET(chip, retval);
 627
 628         return STATUS_SUCCESS;
 629 }
 630
 631 static void sd_choose_proper_clock(struct rts51x_chip *chip)
 632 {
 633         struct sd_info *sd_card = &(chip->sd_card);
 634
 635         if (CHK_SD_SDR104(sd_card)) {
 636                 if (chip->asic_code)
 637                         sd_card->sd_clock = chip->option.asic_sd_sdr104_clk;
 638                 else
 639                         sd_card->sd_clock = chip->option.fpga_sd_sdr104_clk;
 640         } else if (CHK_SD_DDR50(sd_card)) {
 641                 if (chip->asic_code)
 642                         sd_card->sd_clock = chip->option.asic_sd_ddr50_clk;
 643                 else
 644                         sd_card->sd_clock = chip->option.fpga_sd_ddr50_clk;
 645         } else if (CHK_SD_SDR50(sd_card)) {
 646                 if (chip->asic_code)
 647                         sd_card->sd_clock = chip->option.asic_sd_sdr50_clk;
 648                 else
 649                         sd_card->sd_clock = chip->option.fpga_sd_sdr50_clk;
 650         } else if (CHK_SD_HS(sd_card)) {
 651                 if (chip->asic_code)
 652                         sd_card->sd_clock = chip->option.asic_sd_hs_clk;
 653                 else
 654                         sd_card->sd_clock = chip->option.fpga_sd_hs_clk;
 655         } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
 656                 if (chip->asic_code)
 657                         sd_card->sd_clock = chip->option.asic_mmc_52m_clk;
 658                 else
 659                         sd_card->sd_clock = chip->option.fpga_mmc_52m_clk;
 660         } else if (CHK_MMC_26M(sd_card)) {
 661                 if (chip->asic_code) {
 662                         sd_card->sd_clock = 46;
 663                         RTS51X_DEBUGP("Set MMC clock to 22.5MHz\n");
 664                 } else {
 665                         sd_card->sd_clock = CLK_50;
 666                 }
 667         }
 668 }
 669
 670 static int sd_set_init_para(struct rts51x_chip *chip)
 671 {
 672         struct sd_info *sd_card = &(chip->sd_card);
 673         int retval;
 674
 675         retval = sd_set_sample_push_timing(chip);
 676         if (retval != STATUS_SUCCESS)
 677                 TRACE_RET(chip, retval);
 678
 679         sd_choose_proper_clock(chip);
 680
 681         retval = switch_clock(chip, sd_card->sd_clock);
 682         if (retval != STATUS_SUCCESS)
 683                 TRACE_RET(chip, retval);
 684
 685         return STATUS_SUCCESS;
 686 }
 687
 688 int sd_select_card(struct rts51x_chip *chip, int select)
 689 {
 690         struct sd_info *sd_card = &(chip->sd_card);
 691         int retval;
 692         u8 cmd_idx, cmd_type;
 693         u32 addr;
 694
 695         if (select) {
 696                 cmd_idx = SELECT_CARD;
 697                 cmd_type = SD_RSP_TYPE_R1;
 698                 addr = sd_card->sd_addr;
 699         } else {
 700                 cmd_idx = DESELECT_CARD;
 701                 cmd_type = SD_RSP_TYPE_R0;
 702                 addr = 0;
 703         }
 704
 705         retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0);
 706         if (retval != STATUS_SUCCESS)
 707                 TRACE_RET(chip, retval);
 708
 709         return STATUS_SUCCESS;
 710 }
 711
 712 #ifdef SUPPORT_SD_LOCK
 713 int sd_update_lock_status(struct rts51x_chip *chip)
 714 {
 715         struct sd_info *sd_card = &(chip->sd_card);
 716         int retval;
 717         u8 rsp[5];
 718
 719         retval =
 720             sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
 721                                 SD_RSP_TYPE_R1, rsp, 5);
 722         if (retval != STATUS_SUCCESS)
 723                 TRACE_RET(chip, STATUS_FAIL);
 724
 725         if (rsp[1] & 0x02)
 726                 sd_card->sd_lock_status |= SD_LOCKED;
 727         else
 728                 sd_card->sd_lock_status &= ~SD_LOCKED;
 729
 730         RTS51X_DEBUGP("sd_card->sd_lock_status = 0x%x\n",
 731                        sd_card->sd_lock_status);
 732
 733         if (rsp[1] & 0x01) {
 734                 /* LOCK_UNLOCK_FAILED */
 735                 TRACE_RET(chip, STATUS_FAIL);
 736         }
 737
 738         return STATUS_SUCCESS;
 739 }
 740 #endif
 741
 742 int sd_wait_currentstate_dataready(struct rts51x_chip *chip, u8 statechk,
 743                                    u8 rdychk, u16 pollingcnt)
 744 {
 745         struct sd_info *sd_card = &(chip->sd_card);
 746         int retval;
 747         u8 rsp[5];
 748         u16 i;
 749
 750         for (i = 0; i < pollingcnt; i++) {
 751
 752                 retval =
 753                     sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
 754                                         SD_RSP_TYPE_R1, rsp, 5);
 755                 if (retval == STATUS_SUCCESS) {
 756                         if (((rsp[3] & 0x1E) == statechk)
 757                             && ((rsp[3] & 0x01) == rdychk)) {
 758                                 return STATUS_SUCCESS;
 759                         }
 760                 } else {
 761                         rts51x_clear_sd_error(chip);
 762                         TRACE_RET(chip, STATUS_FAIL);
 763                 }
 764         }
 765
 766         return STATUS_TIMEDOUT;
 767 }
 768
 769 static int sd_voltage_switch(struct rts51x_chip *chip)
 770 {
 771         int retval;
 772         u8 stat;
 773
 774         RTS51X_WRITE_REG(chip, SD_BUS_STAT,
 775                          SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP,
 776                          SD_CLK_TOGGLE_EN);
 777
 778         retval =
 779             sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1, NULL,
 780                                 0);
 781         if (retval != STATUS_SUCCESS)
 782                 TRACE_RET(chip, retval);
 783
 784         RTS51X_READ_REG(chip, SD_BUS_STAT, &stat);
 785         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 786                     SD_DAT1_STATUS | SD_DAT0_STATUS))
 787                 TRACE_RET(chip, STATUS_FAIL);
 788
 789         rts51x_init_cmd(chip);
 790         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BUS_STAT, 0xFF,
 791                        SD_CLK_FORCE_STOP);
 792         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_PAD_CTL, SD_IO_USING_1V8,
 793                        SD_IO_USING_1V8);
 794         if (chip->asic_code)
 795                 rts51x_add_cmd(chip, WRITE_REG_CMD, LDO_POWER_CFG,
 796                                TUNE_SD18_MASK, TUNE_SD18_1V8);
 797         retval = rts51x_send_cmd(chip, MODE_C, 100);
 798         if (retval != STATUS_SUCCESS)
 799                 TRACE_RET(chip, retval);
 800
 801         wait_timeout(chip->option.D3318_off_delay);
 802
 803         RTS51X_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
 804         wait_timeout(10);
 805
 806         RTS51X_READ_REG(chip, SD_BUS_STAT, &stat);
 807         if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 808                      SD_DAT1_STATUS | SD_DAT0_STATUS)) !=
 809             (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 810              SD_DAT1_STATUS | SD_DAT0_STATUS)) {
 811                 rts51x_init_cmd(chip);
 812                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BUS_STAT, 0xFF,
 813                                SD_CLK_FORCE_STOP);
 814                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, 0xFF, 0);
 815                 rts51x_send_cmd(chip, MODE_C, 100);
 816                 TRACE_RET(chip, STATUS_FAIL);
 817         }
 818         RTS51X_WRITE_REG(chip, SD_BUS_STAT,
 819                          SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 820
 821         return STATUS_SUCCESS;
 822 }
 823
 824 static int sd_change_phase(struct rts51x_chip *chip, u8 sample_point,
 825                            u8 tune_dir)
 826 {
 827         u16 SD_VP_CTL, SD_DCMPS_CTL;
 828         u8 val;
 829         int retval;
 830
 831         RTS51X_DEBUGP("sd_change_phase (sample_point = %d, tune_dir = %d)\n",
 832                        sample_point, tune_dir);
 833
 834         if (tune_dir == TUNE_RX) {
 835                 SD_VP_CTL = SD_VPCLK1_CTL;
 836                 SD_DCMPS_CTL = SD_DCMPS1_CTL;
 837         } else {
 838                 SD_VP_CTL = SD_VPCLK0_CTL;
 839                 SD_DCMPS_CTL = SD_DCMPS0_CTL;
 840         }
 841
 842         if (chip->asic_code) {
 843                 RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, CLK_CHANGE);
 844                 RTS51X_WRITE_REG(chip, SD_VP_CTL, 0x1F, sample_point);
 845                 RTS51X_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
 846                 RTS51X_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET,
 847                                  PHASE_NOT_RESET);
 848                 RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
 849         } else {
 850 #ifdef CONFIG_RTS5139_DEBUG
 851                 RTS51X_READ_REG(chip, SD_VP_CTL, &val);
 852                 RTS51X_DEBUGP("SD_VP_CTL: 0x%x\n", val);
 853                 RTS51X_READ_REG(chip, SD_DCMPS_CTL, &val);
 854                 RTS51X_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val);
 855 #endif
 856
 857                 RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, CLK_CHANGE);
 858                 udelay(100);
 859                 RTS51X_WRITE_REG(chip, SD_VP_CTL, 0xFF,
 860                                  PHASE_NOT_RESET | sample_point);
 861                 udelay(200);
 862
 863                 rts51x_init_cmd(chip);
 864                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE,
 865                                DCMPS_CHANGE);
 866                 rts51x_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL,
 867                                DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE);
 868                 retval = rts51x_send_cmd(chip, MODE_CR, 100);
 869                 if (retval != STATUS_SUCCESS)
 870                         TRACE_GOTO(chip, Fail);
 871
 872                 retval = rts51x_get_rsp(chip, 1, 500);
 873                 if (retval != STATUS_SUCCESS)
 874                         TRACE_GOTO(chip, Fail);
 875
 876                 val = chip->rsp_buf[0];
 877                 if (val & DCMPS_ERROR)
 878                         TRACE_GOTO(chip, Fail);
 879                 if ((val & DCMPS_CURRENT_PHASE) != sample_point)
 880                         TRACE_GOTO(chip, Fail);
 881                 RTS51X_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
 882                 RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
 883                 udelay(100);
 884         }
 885
 886         RTS51X_WRITE_REG(chip, SD_CFG1, SD_ASYNC_FIFO_RST, 0);
 887
 888         return STATUS_SUCCESS;
 889
 890 Fail:
 891 #ifdef CONFIG_RTS5139_DEBUG
 892         rts51x_ep0_read_register(chip, SD_VP_CTL, &val);
 893         RTS51X_DEBUGP("SD_VP_CTL: 0x%x\n", val);
 894         rts51x_ep0_read_register(chip, SD_DCMPS_CTL, &val);
 895         RTS51X_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val);
 896 #endif
 897
 898         RTS51X_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
 899         RTS51X_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, 0);
 900         wait_timeout(10);
 901
 902         return STATUS_FAIL;
 903 }
 904
 905 static int sd_check_spec(struct rts51x_chip *chip, u8 bus_width)
 906 {
 907         struct sd_info *sd_card = &(chip->sd_card);
 908         int retval;
 909         u8 cmd[5], buf[8];
 910
 911         retval =
 912             sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1,
 913                                 NULL, 0);
 914         if (retval != STATUS_SUCCESS)
 915                 TRACE_RET(chip, STATUS_FAIL);
 916
 917         cmd[0] = 0x40 | SEND_SCR;
 918         cmd[1] = 0;
 919         cmd[2] = 0;
 920         cmd[3] = 0;
 921         cmd[4] = 0;
 922
 923         retval =
 924             sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width, buf,
 925                          8, 250);
 926         if (retval != STATUS_SUCCESS) {
 927                 rts51x_clear_sd_error(chip);
 928                 TRACE_RET(chip, retval);
 929         }
 930
 931         memcpy(sd_card->raw_scr, buf, 8);
 932
 933         if ((buf[0] & 0x0F) == 0)
 934                 TRACE_RET(chip, STATUS_FAIL);
 935
 936         return STATUS_SUCCESS;
 937 }
 938
 939 static int sd_query_switch_result(struct rts51x_chip *chip, u8 func_group,
 940                                   u8 func_to_switch, u8 *buf, int buf_len)
 941 {
 942         u8 support_mask = 0, query_switch = 0, switch_busy = 0;
 943         int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0;
 944
 945         if (func_group == SD_FUNC_GROUP_1) {
 946                 support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET;
 947                 query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET;
 948                 check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET;
 949
 950                 switch (func_to_switch) {
 951                 case HS_SUPPORT:
 952                         support_mask = HS_SUPPORT_MASK;
 953                         query_switch = HS_QUERY_SWITCH_OK;
 954                         switch_busy = HS_SWITCH_BUSY;
 955                         break;
 956
 957                 case SDR50_SUPPORT:
 958                         support_mask = SDR50_SUPPORT_MASK;
 959                         query_switch = SDR50_QUERY_SWITCH_OK;
 960                         switch_busy = SDR50_SWITCH_BUSY;
 961                         break;
 962
 963                 case SDR104_SUPPORT:
 964                         support_mask = SDR104_SUPPORT_MASK;
 965                         query_switch = SDR104_QUERY_SWITCH_OK;
 966                         switch_busy = SDR104_SWITCH_BUSY;
 967                         break;
 968
 969                 case DDR50_SUPPORT:
 970                         support_mask = DDR50_SUPPORT_MASK;
 971                         query_switch = DDR50_QUERY_SWITCH_OK;
 972                         switch_busy = DDR50_SWITCH_BUSY;
 973                         break;
 974
 975                 default:
 976                         TRACE_RET(chip, STATUS_FAIL);
 977                 }
 978         } else if (func_group == SD_FUNC_GROUP_3) {
 979                 support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET;
 980                 query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET;
 981                 check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET;
 982
 983                 switch (func_to_switch) {
 984                 case DRIVING_TYPE_A:
 985                         support_mask = DRIVING_TYPE_A_MASK;
 986                         query_switch = TYPE_A_QUERY_SWITCH_OK;
 987                         switch_busy = TYPE_A_SWITCH_BUSY;
 988                         break;
 989
 990                 case DRIVING_TYPE_C:
 991                         support_mask = DRIVING_TYPE_C_MASK;
 992                         query_switch = TYPE_C_QUERY_SWITCH_OK;
 993                         switch_busy = TYPE_C_SWITCH_BUSY;
 994                         break;
 995
 996                 case DRIVING_TYPE_D:
 997                         support_mask = DRIVING_TYPE_D_MASK;
 998                         query_switch = TYPE_D_QUERY_SWITCH_OK;
 999                         switch_busy = TYPE_D_SWITCH_BUSY;
1000                         break;
1001
1002                 default:
1003                         TRACE_RET(chip, STATUS_FAIL);
1004                 }
1005         } else if (func_group == SD_FUNC_GROUP_4) {
1006                 support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET;
1007                 query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET;
1008                 check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET;
1009
1010                 switch (func_to_switch) {
1011                 case CURRENT_LIMIT_400:
1012                         support_mask = CURRENT_LIMIT_400_MASK;
1013                         query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK;
1014                         switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY;
1015                         break;
1016
1017                 case CURRENT_LIMIT_600:
1018                         support_mask = CURRENT_LIMIT_600_MASK;
1019                         query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK;
1020                         switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY;
1021                         break;
1022
1023                 case CURRENT_LIMIT_800:
1024                         support_mask = CURRENT_LIMIT_800_MASK;
1025                         query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK;
1026                         switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY;
1027                         break;
1028
1029                 default:
1030                         TRACE_RET(chip, STATUS_FAIL);
1031                 }
1032         } else {
1033                 TRACE_RET(chip, STATUS_FAIL);
1034         }
1035
1036         if (func_group == SD_FUNC_GROUP_4)
1037                 buf[query_switch_offset] =
1038                     (buf[query_switch_offset] & 0xf0) >> 4;
1039         if (!(buf[support_offset] & support_mask) ||
1040             ((buf[query_switch_offset] & 0x0F) != query_switch))
1041                 TRACE_RET(chip, STATUS_FAIL);
1042
1043         if ((buf[DATA_STRUCTURE_VER_OFFSET] == 0x01) &&
1044             ((buf[check_busy_offset] & switch_busy) == switch_busy))
1045                 TRACE_RET(chip, STATUS_FAIL);
1046
1047         return STATUS_SUCCESS;
1048 }
1049
1050 static int sd_check_switch_mode(struct rts51x_chip *chip, u8 mode,
1051                                 u8 func_group, u8 func_to_switch, u8 bus_width)
1052 {
1053         struct sd_info *sd_card = &(chip->sd_card);
1054         int retval;
1055         u8 cmd[5], buf[64];
1056
1057         RTS51X_DEBUGP("sd_check_switch_mode (mode = %d, func_group = %d,"
1058                 "func_to_switch = %d)\n", mode, func_group, func_to_switch);
1059
1060         cmd[0] = 0x40 | SWITCH;
1061         cmd[1] = mode;
1062
1063         if (func_group == SD_FUNC_GROUP_1) {
1064                 cmd[2] = 0xFF;
1065                 cmd[3] = 0xFF;
1066                 cmd[4] = 0xF0 + func_to_switch;
1067         } else if (func_group == SD_FUNC_GROUP_3) {
1068                 cmd[2] = 0xFF;
1069                 cmd[3] = 0xF0 + func_to_switch;
1070                 cmd[4] = 0xFF;
1071         } else if (func_group == SD_FUNC_GROUP_4) {
1072                 cmd[2] = 0xFF;
1073                 cmd[3] = 0x0F + (func_to_switch << 4);
1074                 cmd[4] = 0xFF;
1075         } else {
1076                 cmd[1] = SD_CHECK_MODE;
1077                 cmd[2] = 0xFF;
1078                 cmd[3] = 0xFF;
1079                 cmd[4] = 0xFF;
1080         }
1081
1082         retval =
1083             sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width, buf,
1084                          64, 250);
1085         if (retval != STATUS_SUCCESS) {
1086                 rts51x_clear_sd_error(chip);
1087                 TRACE_RET(chip, retval);
1088         }
1089
1090         if (func_group == NO_ARGUMENT) {
1091                 sd_card->func_group1_mask = buf[0x0D];
1092                 sd_card->func_group2_mask = buf[0x0B];
1093                 sd_card->func_group3_mask = buf[0x09];
1094                 sd_card->func_group4_mask = buf[0x07];
1095
1096                 RTS51X_DEBUGP("func_group1_mask = 0x%02x\n", buf[0x0D]);
1097                 RTS51X_DEBUGP("func_group2_mask = 0x%02x\n", buf[0x0B]);
1098                 RTS51X_DEBUGP("func_group3_mask = 0x%02x\n", buf[0x09]);
1099                 RTS51X_DEBUGP("func_group4_mask = 0x%02x\n", buf[0x07]);
1100         } else {
1101                 if ((buf[0] == 0) && (buf[1] == 0))
1102                         TRACE_RET(chip, STATUS_FAIL);
1103                 retval =
1104                     sd_query_switch_result(chip, func_group, func_to_switch,
1105                                            buf, 64);
1106                 if (retval != STATUS_SUCCESS)
1107                         TRACE_RET(chip, retval);
1108         }
1109
1110         return STATUS_SUCCESS;
1111 }
1112
1113 static int sd_check_switch(struct rts51x_chip *chip,
1114                            u8 func_group, u8 func_to_switch, u8 bus_width)
1115 {
1116         int retval;
1117         int i;
1118         int switch_good = 0;
1119
1120         for (i = 0; i < 3; i++) {
1121                 if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST) {
1122                         sd_set_reset_fail(chip, SD_RESET_FAIL);
1123                         TRACE_RET(chip, STATUS_FAIL);
1124                 }
1125
1126                 retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group,
1127                                               func_to_switch, bus_width);
1128                 if (retval == STATUS_SUCCESS) {
1129                         u8 stat;
1130
1131                         retval = sd_check_switch_mode(chip, SD_SWITCH_MODE,
1132                                         func_group, func_to_switch, bus_width);
1133                         if (retval == STATUS_SUCCESS) {
1134                                 switch_good = 1;
1135                                 break;
1136                         }
1137
1138                         RTS51X_READ_REG(chip, SD_STAT1, &stat);
1139
1140                         if (stat & SD_CRC16_ERR) {
1141                                 RTS51X_DEBUGP("SD CRC16 error when switching"
1142                                                         "mode\n");
1143                                 TRACE_RET(chip, STATUS_FAIL);
1144                         }
1145                 }
1146
1147                 wait_timeout(20);
1148         }
1149
1150         if (!switch_good)
1151                 TRACE_RET(chip, STATUS_FAIL);
1152
1153         return STATUS_SUCCESS;
1154 }
1155
1156 static int sd_switch_function(struct rts51x_chip *chip, u8 bus_width)
1157 {
1158         struct sd_info *sd_card = &(chip->sd_card);
1159         int retval;
1160         int i;
1161         u8 func_to_switch = 0;
1162
1163         /* Get supported functions */
1164         retval = sd_check_switch_mode(chip, SD_CHECK_MODE,
1165                                       NO_ARGUMENT, NO_ARGUMENT, bus_width);
1166         if (retval != STATUS_SUCCESS)
1167                 TRACE_RET(chip, retval);
1168
1169         sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail);
1170
1171         for (i = 0; i < 4; i++) {
1172                 switch ((u8) (chip->option.sd_speed_prior >> (i * 8))) {
1173                 case DDR50_SUPPORT:
1174                         if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK)
1175                             && (CHECK_UHS50(chip)))
1176                                 func_to_switch = DDR50_SUPPORT;
1177                         break;
1178
1179                 case SDR50_SUPPORT:
1180                         if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK)
1181                             && (CHECK_UHS50(chip)))
1182                                 func_to_switch = SDR50_SUPPORT;
1183                         break;
1184
1185                 case HS_SUPPORT:
1186                         if (sd_card->func_group1_mask & HS_SUPPORT_MASK)
1187                                 func_to_switch = HS_SUPPORT;
1188                         break;
1189
1190                 default:
1191                         continue;
1192                 }
1193
1194                 if (func_to_switch)
1195                         break;
1196         }
1197         RTS51X_DEBUGP("SD_FUNC_GROUP_1: func_to_switch = 0x%02x",
1198                        func_to_switch);
1199
1200 #ifdef SUPPORT_SD_LOCK
1201         if ((sd_card->sd_lock_status & SD_SDR_RST)
1202             && (DDR50_SUPPORT == func_to_switch)
1203             && (sd_card->func_group1_mask & SDR50_SUPPORT_MASK)) {
1204                 func_to_switch = SDR50_SUPPORT;
1205                 RTS51X_DEBUGP("Using SDR50 instead of DDR50 for SD Lock\n");
1206         }
1207 #endif
1208
1209         if (func_to_switch) {
1210                 retval =
1211                     sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch,
1212                                     bus_width);
1213                 if (retval != STATUS_SUCCESS) {
1214                         if (func_to_switch == SDR104_SUPPORT)
1215                                 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK;
1216                         else if (func_to_switch == DDR50_SUPPORT)
1217                                 sd_card->sd_switch_fail = DDR50_SUPPORT_MASK;
1218                         else if (func_to_switch == SDR50_SUPPORT)
1219                                 sd_card->sd_switch_fail = SDR50_SUPPORT_MASK;
1220                         else if (func_to_switch == HS_SUPPORT)
1221                                 sd_card->sd_switch_fail = HS_SUPPORT_MASK;
1222
1223                         TRACE_RET(chip, retval);
1224                 }
1225
1226                 if (func_to_switch == SDR104_SUPPORT)
1227                         SET_SD_SDR104(sd_card);
1228                 else if (func_to_switch == DDR50_SUPPORT)
1229                         SET_SD_DDR50(sd_card);
1230                 else if (func_to_switch == SDR50_SUPPORT)
1231                         SET_SD_SDR50(sd_card);
1232                 else
1233                         SET_SD_HS(sd_card);
1234         }
1235
1236         if (CHK_SD_DDR50(sd_card))
1237                 RTS51X_WRITE_REG(chip, SD_CFG1, 0x0C, SD_DDR_MODE);
1238
1239         func_to_switch = 0;
1240         if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK)
1241                 func_to_switch = CURRENT_LIMIT_400;
1242
1243         if (func_to_switch) {
1244                 RTS51X_DEBUGP("Try to switch current_limit_400\n");
1245                 retval =
1246                     sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch,
1247                                     bus_width);
1248                 RTS51X_DEBUGP("Switch current_limit_400 status: (%d)\n",
1249                                retval);
1250         }
1251
1252         return STATUS_SUCCESS;
1253 }
1254
1255 static int sd_wait_data_idle(struct rts51x_chip *chip)
1256 {
1257         int retval = STATUS_TIMEDOUT;
1258         int i;
1259         u8 val = 0;
1260
1261         for (i = 0; i < 100; i++) {
1262                 retval = rts51x_ep0_read_register(chip, SD_DATA_STATE, &val);
1263                 if (retval != STATUS_SUCCESS)
1264                         TRACE_RET(chip, STATUS_FAIL);
1265                 if (val & SD_DATA_IDLE) {
1266                         retval = STATUS_SUCCESS;
1267                         break;
1268                 }
1269                 udelay(100);
1270         }
1271         RTS51X_DEBUGP("SD_DATA_STATE: 0x%02x\n", val);
1272
1273         return retval;
1274 }
1275
1276 static int sd_sdr_tuning_rx_cmd(struct rts51x_chip *chip, u8 sample_point)
1277 {
1278         int retval;
1279         u8 cmd[5];
1280
1281         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1282         if (retval != STATUS_SUCCESS)
1283                 TRACE_RET(chip, retval);
1284
1285         cmd[0] = 0x40 | SEND_TUNING_PATTERN;
1286         cmd[1] = 0;
1287         cmd[2] = 0;
1288         cmd[3] = 0;
1289         cmd[4] = 0;
1290
1291         retval = sd_read_data(chip, SD_TM_AUTO_TUNING,
1292                               cmd, 5, 0x40, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1293         if (retval != STATUS_SUCCESS) {
1294                 /* Wait till SD DATA IDLE */
1295                 (void)sd_wait_data_idle(chip);
1296
1297                 rts51x_clear_sd_error(chip);
1298                 TRACE_RET(chip, STATUS_FAIL);
1299         }
1300
1301         return STATUS_SUCCESS;
1302 }
1303
1304 static int sd_ddr_tuning_rx_cmd(struct rts51x_chip *chip, u8 sample_point)
1305 {
1306         struct sd_info *sd_card = &(chip->sd_card);
1307         int retval;
1308         u8 cmd[5];
1309
1310         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1311         if (retval != STATUS_SUCCESS)
1312                 TRACE_RET(chip, retval);
1313
1314         RTS51X_DEBUGP("sd ddr tuning rx\n");
1315
1316         retval =
1317             sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1,
1318                                 NULL, 0);
1319         if (retval != STATUS_SUCCESS)
1320                 TRACE_RET(chip, retval);
1321
1322         cmd[0] = 0x40 | SD_STATUS;
1323         cmd[1] = 0;
1324         cmd[2] = 0;
1325         cmd[3] = 0;
1326         cmd[4] = 0;
1327
1328         retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1329                               cmd, 5, 64, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1330         if (retval != STATUS_SUCCESS) {
1331                 /* Wait till SD DATA IDLE */
1332                 (void)sd_wait_data_idle(chip);
1333
1334                 rts51x_clear_sd_error(chip);
1335                 TRACE_RET(chip, STATUS_FAIL);
1336         }
1337
1338         return STATUS_SUCCESS;
1339 }
1340
1341 static int mmc_ddr_tunning_rx_cmd(struct rts51x_chip *chip, u8 sample_point)
1342 {
1343         struct sd_info *sd_card = &(chip->sd_card);
1344         int retval;
1345         u8 cmd[5], bus_width;
1346
1347         if (CHK_MMC_8BIT(sd_card))
1348                 bus_width = SD_BUS_WIDTH_8;
1349         else if (CHK_MMC_4BIT(sd_card))
1350                 bus_width = SD_BUS_WIDTH_4;
1351         else
1352                 bus_width = SD_BUS_WIDTH_1;
1353
1354         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1355         if (retval != STATUS_SUCCESS)
1356                 TRACE_RET(chip, retval);
1357
1358         RTS51X_DEBUGP("mmc ddr tuning rx\n");
1359
1360         cmd[0] = 0x40 | SEND_EXT_CSD;
1361         cmd[1] = 0;
1362         cmd[2] = 0;
1363         cmd[3] = 0;
1364         cmd[4] = 0;
1365
1366         retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1367                               cmd, 5, 0x200, 1, bus_width, NULL, 0, 100);
1368         if (retval != STATUS_SUCCESS) {
1369                 /* Wait till SD DATA IDLE */
1370                 (void)sd_wait_data_idle(chip);
1371
1372                 rts51x_clear_sd_error(chip);
1373                 TRACE_RET(chip, STATUS_FAIL);
1374         }
1375
1376         return STATUS_SUCCESS;
1377 }
1378
1379 static int sd_sdr_tuning_tx_cmd(struct rts51x_chip *chip, u8 sample_point)
1380 {
1381         struct sd_info *sd_card = &(chip->sd_card);
1382         int retval;
1383
1384         retval = sd_change_phase(chip, sample_point, TUNE_TX);
1385         if (retval != STATUS_SUCCESS)
1386                 TRACE_RET(chip, retval);
1387
1388         RTS51X_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1389                          SD_RSP_80CLK_TIMEOUT_EN);
1390
1391         retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1392                                      SD_RSP_TYPE_R1, NULL, 0);
1393         if (retval != STATUS_SUCCESS) {
1394                 if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1395                         /* Tunning TX fail */
1396                         rts51x_ep0_write_register(chip, SD_CFG3,
1397                                                   SD_RSP_80CLK_TIMEOUT_EN, 0);
1398                         TRACE_RET(chip, STATUS_FAIL);
1399                 }
1400         }
1401
1402         RTS51X_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1403
1404         return STATUS_SUCCESS;
1405 }
1406
1407 static int sd_ddr_tuning_tx_cmd(struct rts51x_chip *chip, u8 sample_point)
1408 {
1409         struct sd_info *sd_card = &(chip->sd_card);
1410         int retval;
1411         u8 cmd[5], bus_width;
1412
1413         retval = sd_change_phase(chip, sample_point, TUNE_TX);
1414         if (retval != STATUS_SUCCESS)
1415                 TRACE_RET(chip, retval);
1416
1417         if (CHK_SD(sd_card)) {
1418                 bus_width = SD_BUS_WIDTH_4;
1419         } else {
1420                 if (CHK_MMC_8BIT(sd_card))
1421                         bus_width = SD_BUS_WIDTH_8;
1422                 else if (CHK_MMC_4BIT(sd_card))
1423                         bus_width = SD_BUS_WIDTH_4;
1424                 else
1425                         bus_width = SD_BUS_WIDTH_1;
1426         }
1427         retval = sd_wait_currentstate_dataready(chip, 0x08, 1, 20);
1428         if (retval != STATUS_SUCCESS)
1429                 TRACE_RET(chip, STATUS_FAIL);
1430
1431         RTS51X_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1432                          SD_RSP_80CLK_TIMEOUT_EN);
1433
1434         cmd[0] = 0x40 | PROGRAM_CSD;
1435         cmd[1] = 0;
1436         cmd[2] = 0;
1437         cmd[3] = 0;
1438         cmd[4] = 0;
1439
1440         retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2,
1441                         cmd, 5, 16, 1, bus_width, sd_card->raw_csd, 16, 100);
1442         if (retval != STATUS_SUCCESS) {
1443                 rts51x_clear_sd_error(chip);
1444                 /* Tunning TX fail */
1445                 rts51x_ep0_write_register(chip, SD_CFG3,
1446                                           SD_RSP_80CLK_TIMEOUT_EN, 0);
1447                 TRACE_RET(chip, STATUS_FAIL);
1448         }
1449
1450         RTS51X_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1451
1452         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1,
1453                             NULL, 0);
1454
1455         return STATUS_SUCCESS;
1456 }
1457
1458 static u8 sd_search_final_phase(struct rts51x_chip *chip, u32 phase_map,
1459                                 u8 tune_dir)
1460 {
1461         struct sd_info *sd_card = &(chip->sd_card);
1462         struct timing_phase_path path[MAX_PHASE + 1];
1463         int i, j, cont_path_cnt;
1464         int new_block, max_len;
1465         u8 final_phase = 0xFF;
1466         int final_path_idx;
1467
1468         if (phase_map == 0xffff) {
1469                 if (CHK_SD_DDR50(sd_card)) {
1470                         if (tune_dir == TUNE_TX)
1471                                 final_phase = chip->option.ddr50_tx_phase;
1472                         else
1473                                 final_phase = chip->option.ddr50_rx_phase;
1474                         RTS51X_DEBUGP("DDR50 tuning dir:%d all pass,"
1475                                         "so select default phase:0x%x.\n",
1476                                         tune_dir, final_phase);
1477                 } else {
1478                         if (tune_dir == TUNE_TX)
1479                                 final_phase = chip->option.sdr50_tx_phase;
1480                         else
1481                                 final_phase = chip->option.sdr50_rx_phase;
1482                         RTS51X_DEBUGP("SDR50 tuning dir:%d all pass,"
1483                                         "so select default phase:0x%x.\n",
1484                                         tune_dir, final_phase);
1485                 }
1486                 goto Search_Finish;
1487         }
1488
1489         cont_path_cnt = 0;
1490         new_block = 1;
1491         j = 0;
1492         for (i = 0; i < MAX_PHASE + 1; i++) {
1493                 if (phase_map & (1 << i)) {
1494                         if (new_block) {
1495                                 new_block = 0;
1496                                 j = cont_path_cnt++;
1497                                 path[j].start = i;
1498                                 path[j].end = i;
1499                         } else {
1500                                 path[j].end = i;
1501                         }
1502                 } else {
1503                         new_block = 1;
1504                         if (cont_path_cnt) {
1505                                 int idx = cont_path_cnt - 1;
1506                                 path[idx].len =
1507                                     path[idx].end - path[idx].start + 1;
1508                                 path[idx].mid =
1509                                     path[idx].start + path[idx].len / 2;
1510                         }
1511                 }
1512         }
1513
1514         if (cont_path_cnt == 0) {
1515                 RTS51X_DEBUGP("No continuous phase path\n");
1516                 goto Search_Finish;
1517         } else {
1518                 int idx = cont_path_cnt - 1;
1519                 path[idx].len = path[idx].end - path[idx].start + 1;
1520                 path[idx].mid = path[idx].start + path[idx].len / 2;
1521         }
1522
1523         if ((path[0].start == 0) &&
1524                         (path[cont_path_cnt - 1].end == MAX_PHASE)) {
1525                 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
1526                 path[0].len += path[cont_path_cnt - 1].len;
1527                 path[0].mid = path[0].start + path[0].len / 2;
1528                 if (path[0].mid < 0)
1529                         path[0].mid += MAX_PHASE + 1;
1530                 cont_path_cnt--;
1531         }
1532         max_len = 0;
1533         final_phase = 0;
1534         final_path_idx = 0;
1535         for (i = 0; i < cont_path_cnt; i++) {
1536                 if (path[i].len > max_len) {
1537                         max_len = path[i].len;
1538                         final_phase = (u8) path[i].mid;
1539                         final_path_idx = i;
1540                 }
1541
1542                 RTS51X_DEBUGP("path[%d].start = %d\n", i, path[i].start);
1543                 RTS51X_DEBUGP("path[%d].end = %d\n", i, path[i].end);
1544                 RTS51X_DEBUGP("path[%d].len = %d\n", i, path[i].len);
1545                 RTS51X_DEBUGP("path[%d].mid = %d\n", i, path[i].mid);
1546                 RTS51X_DEBUGP("\n");
1547         }
1548
1549         if ((tune_dir == TUNE_TX) && (CHK_SD_SDR50(sd_card))
1550             && chip->option.sdr50_phase_sel) {
1551                 if (max_len > 6) {
1552                         int temp_mid = (max_len - 6) / 2;
1553                         int temp_final_phase =
1554                             path[final_path_idx].end - (max_len -
1555                                                         (3 + temp_mid));
1556
1557                         if (temp_final_phase < 0)
1558                                 final_phase = temp_final_phase + MAX_PHASE + 1;
1559                         else
1560                                 final_phase = (u8) temp_final_phase;
1561                 }
1562         }
1563
1564 Search_Finish:
1565         RTS51X_DEBUGP("Final choosen phase: %d\n", final_phase);
1566         return final_phase;
1567 }
1568
1569 static int sd_tuning_rx(struct rts51x_chip *chip)
1570 {
1571         struct sd_info *sd_card = &(chip->sd_card);
1572         int retval;
1573         int i, j;
1574         u32 raw_phase_map[3], phase_map;
1575         u8 final_phase;
1576         int (*tuning_cmd) (struct rts51x_chip *chip, u8 sample_point);
1577
1578         if (CHK_SD(sd_card)) {
1579                 if (CHK_SD_DDR50(sd_card))
1580                         tuning_cmd = sd_ddr_tuning_rx_cmd;
1581                 else
1582                         tuning_cmd = sd_sdr_tuning_rx_cmd;
1583         } else {
1584                 if (CHK_MMC_DDR52(sd_card))
1585                         tuning_cmd = mmc_ddr_tunning_rx_cmd;
1586                 else
1587                         TRACE_RET(chip, STATUS_FAIL);
1588         }
1589
1590         for (i = 0; i < 3; i++) {
1591                 raw_phase_map[i] = 0;
1592                 for (j = MAX_PHASE; j >= 0; j--) {
1593                         if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST) {
1594                                 sd_set_reset_fail(chip, SD_RESET_FAIL);
1595                                 TRACE_RET(chip, STATUS_FAIL);
1596                         }
1597
1598                         retval = tuning_cmd(chip, (u8) j);
1599                         if (retval == STATUS_SUCCESS)
1600                                 raw_phase_map[i] |= 1 << j;
1601                         else
1602                                 RTS51X_DEBUGP("Tuning phase %d fail\n", j);
1603                 }
1604         }
1605
1606         phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1607         for (i = 0; i < 3; i++)
1608                 RTS51X_DEBUGP("RX raw_phase_map[%d] = 0x%04x\n", i,
1609                                raw_phase_map[i]);
1610         RTS51X_DEBUGP("RX phase_map = 0x%04x\n", phase_map);
1611
1612         final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX);
1613         if (final_phase == 0xFF)
1614                 TRACE_RET(chip, STATUS_FAIL);
1615
1616         retval = tuning_cmd(chip, final_phase);
1617         if (retval != STATUS_SUCCESS)
1618                 TRACE_RET(chip, retval);
1619
1620         return STATUS_SUCCESS;
1621 }
1622
1623 static int sd_ddr_pre_tuning_tx(struct rts51x_chip *chip)
1624 {
1625         struct sd_info *sd_card = &(chip->sd_card);
1626         int retval;
1627         u8 i;
1628         u8 pre_tune_tx_phase;
1629         u32 pre_tune_phase_map;
1630
1631         RTS51X_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1632                          SD_RSP_80CLK_TIMEOUT_EN);
1633
1634         pre_tune_tx_phase = 0xFF;
1635         pre_tune_phase_map = 0x0000;
1636         for (i = 0; i < MAX_PHASE + 1; i++) {
1637                 if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST) {
1638                         sd_set_reset_fail(chip, SD_RESET_FAIL);
1639                         TRACE_RET(chip, STATUS_FAIL);
1640                 }
1641
1642                 retval = sd_change_phase(chip, (u8) i, TUNE_TX);
1643                 if (retval != STATUS_SUCCESS)
1644                         TRACE_RET(chip, retval);
1645
1646                 retval =
1647                     sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1648                                         SD_RSP_TYPE_R1, NULL, 0);
1649                 if ((retval == STATUS_SUCCESS)
1650                     || !sd_check_err_code(chip, SD_RSP_TIMEOUT))
1651                         pre_tune_phase_map |= (u32) 1 << i;
1652         }
1653
1654         RTS51X_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1655
1656         pre_tune_tx_phase =
1657             sd_search_final_phase(chip, pre_tune_phase_map, TUNE_TX);
1658         if (pre_tune_tx_phase == 0xFF)
1659                 TRACE_RET(chip, STATUS_FAIL);
1660
1661         sd_change_phase(chip, pre_tune_tx_phase, TUNE_TX);
1662         RTS51X_DEBUGP("DDR TX pre tune phase: %d\n", (int)pre_tune_tx_phase);
1663
1664         return STATUS_SUCCESS;
1665 }
1666
1667 static int sd_tuning_tx(struct rts51x_chip *chip)
1668 {
1669         struct sd_info *sd_card = &(chip->sd_card);
1670         int retval;
1671         int i, j;
1672         u32 raw_phase_map[3], phase_map;
1673         u8 final_phase;
1674         int (*tuning_cmd) (struct rts51x_chip *chip, u8 sample_point);
1675
1676         if (CHK_SD(sd_card)) {
1677                 if (CHK_SD_DDR50(sd_card))
1678                         tuning_cmd = sd_ddr_tuning_tx_cmd;
1679                 else
1680                         tuning_cmd = sd_sdr_tuning_tx_cmd;
1681         } else {
1682                 if (CHK_MMC_DDR52(sd_card))
1683                         tuning_cmd = sd_ddr_tuning_tx_cmd;
1684                 else
1685                         TRACE_RET(chip, STATUS_FAIL);
1686         }
1687
1688         for (i = 0; i < 3; i++) {
1689                 raw_phase_map[i] = 0;
1690                 for (j = MAX_PHASE; j >= 0; j--) {
1691                         if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST) {
1692                                 sd_set_reset_fail(chip, SD_RESET_FAIL);
1693                                 TRACE_RET(chip, STATUS_FAIL);
1694                         }
1695
1696                         retval = tuning_cmd(chip, (u8) j);
1697                         if (retval == STATUS_SUCCESS)
1698                                 raw_phase_map[i] |= 1 << j;
1699                         else
1700                                 RTS51X_DEBUGP("Tuning phase %d fail\n", j);
1701                 }
1702         }
1703
1704         phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1705         for (i = 0; i < 3; i++)
1706                 RTS51X_DEBUGP("TX raw_phase_map[%d] = 0x%04x\n", i,
1707                                raw_phase_map[i]);
1708         RTS51X_DEBUGP("TX phase_map = 0x%04x\n", phase_map);
1709
1710         final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1711         if (final_phase == 0xFF)
1712                 TRACE_RET(chip, STATUS_FAIL);
1713
1714         retval = tuning_cmd(chip, final_phase);
1715         if (retval != STATUS_SUCCESS)
1716                 TRACE_RET(chip, retval);
1717
1718         return STATUS_SUCCESS;
1719 }
1720
1721 static int sd_sdr_tuning(struct rts51x_chip *chip)
1722 {
1723         int retval;
1724
1725         retval = sd_tuning_tx(chip);
1726         if (retval != STATUS_SUCCESS)
1727                 TRACE_RET(chip, retval);
1728
1729         retval = sd_tuning_rx(chip);
1730         if (retval != STATUS_SUCCESS)
1731                 TRACE_RET(chip, retval);
1732
1733         return STATUS_SUCCESS;
1734 }
1735
1736 static int sd_ddr_tuning(struct rts51x_chip *chip)
1737 {
1738         int retval;
1739
1740         if (!(chip->option.sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1741                 retval = sd_ddr_pre_tuning_tx(chip);
1742                 if (retval != STATUS_SUCCESS)
1743                         TRACE_RET(chip, retval);
1744         } else {
1745                 retval =
1746                     sd_change_phase(chip, (u8) chip->option.sd_ddr_tx_phase,
1747                                     TUNE_TX);
1748                 if (retval != STATUS_SUCCESS)
1749                         TRACE_RET(chip, retval);
1750         }
1751
1752         retval = sd_tuning_rx(chip);
1753         if (retval != STATUS_SUCCESS)
1754                 TRACE_RET(chip, retval);
1755
1756         if (!(chip->option.sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1757                 retval = sd_tuning_tx(chip);
1758                 if (retval != STATUS_SUCCESS)
1759                         TRACE_RET(chip, retval);
1760         }
1761
1762         return STATUS_SUCCESS;
1763 }
1764
1765 static int mmc_ddr_tuning(struct rts51x_chip *chip)
1766 {
1767         int retval;
1768
1769         if (!(chip->option.sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1770                 retval = sd_ddr_pre_tuning_tx(chip);
1771                 if (retval != STATUS_SUCCESS)
1772                         TRACE_RET(chip, retval);
1773         } else {
1774                 retval =
1775                     sd_change_phase(chip, (u8) chip->option.mmc_ddr_tx_phase,
1776                                     TUNE_TX);
1777                 if (retval != STATUS_SUCCESS)
1778                         TRACE_RET(chip, retval);
1779         }
1780
1781         retval = sd_tuning_rx(chip);
1782         if (retval != STATUS_SUCCESS)
1783                 TRACE_RET(chip, retval);
1784
1785         if (!(chip->option.sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1786                 retval = sd_tuning_tx(chip);
1787                 if (retval != STATUS_SUCCESS)
1788                         TRACE_RET(chip, retval);
1789         }
1790
1791         return STATUS_SUCCESS;
1792 }
1793
1794 int sd_switch_clock(struct rts51x_chip *chip)
1795 {
1796         struct sd_info *sd_card = &(chip->sd_card);
1797         int retval;
1798         int re_tuning = 0;
1799
1800         retval = rts51x_select_card(chip, SD_CARD);
1801         if (retval != STATUS_SUCCESS)
1802                 TRACE_RET(chip, retval);
1803
1804         if (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card)) {
1805                 if (sd_card->sd_clock != chip->cur_clk)
1806                         re_tuning = 1;
1807         }
1808
1809         retval = switch_clock(chip, sd_card->sd_clock);
1810         if (retval != STATUS_SUCCESS)
1811                 TRACE_RET(chip, retval);
1812
1813         if (re_tuning) {
1814                 if (CHK_SD(sd_card)) {
1815                         if (CHK_SD_DDR50(sd_card))
1816                                 retval = sd_ddr_tuning(chip);
1817                         else
1818                                 retval = sd_sdr_tuning(chip);
1819                 } else {
1820                         if (CHK_MMC_DDR52(sd_card))
1821                                 retval = mmc_ddr_tuning(chip);
1822                 }
1823
1824                 if (retval != STATUS_SUCCESS)
1825                         TRACE_RET(chip, retval);
1826         }
1827
1828         return STATUS_SUCCESS;
1829 }
1830
1831 static int sd_prepare_reset(struct rts51x_chip *chip)
1832 {
1833         struct sd_info *sd_card = &(chip->sd_card);
1834         int retval;
1835
1836         if (chip->asic_code)
1837                 sd_card->sd_clock = 29;
1838         else
1839                 sd_card->sd_clock = CLK_30;
1840
1841         /* Set SD Clocks */
1842         retval = sd_set_init_para(chip);
1843         if (retval != STATUS_SUCCESS)
1844                 TRACE_RET(chip, retval);
1845
1846         rts51x_init_cmd(chip);
1847
1848         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0xFF,
1849                        SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1);
1850         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 0xFF,
1851                        SD20_RX_POS_EDGE);
1852         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 0xFF, 0);
1853
1854         retval = rts51x_send_cmd(chip, MODE_C, 100);
1855         if (retval != STATUS_SUCCESS)
1856                 TRACE_RET(chip, retval);
1857
1858         retval = rts51x_select_card(chip, SD_CARD);
1859         if (retval != STATUS_SUCCESS)
1860                 TRACE_RET(chip, retval);
1861
1862         return STATUS_SUCCESS;
1863 }
1864
1865 static void sd_pull_ctl_disable(struct rts51x_chip *chip)
1866 {
1867         if (CHECK_PKG(chip, LQFP48)) {
1868                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
1869                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
1870                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
1871                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
1872                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
1873                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
1874         } else {
1875                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);
1876                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
1877                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
1878                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
1879                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x56);
1880                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
1881         }
1882 }
1883
1884 static void sd_pull_ctl_enable(struct rts51x_chip *chip)
1885 {
1886         if (CHECK_PKG(chip, LQFP48)) {
1887                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xAA);
1888                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0xAA);
1889                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xA9);
1890                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
1891                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
1892                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
1893         } else {
1894                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xA5);
1895                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x9A);
1896                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xA5);
1897                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x9A);
1898                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x65);
1899                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x5A);
1900         }
1901 }
1902
1903 static int sd_init_power(struct rts51x_chip *chip)
1904 {
1905         int retval;
1906
1907         rts51x_init_cmd(chip);
1908
1909         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, LDO3318_PWR_MASK,
1910                        LDO_ON);
1911         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_PAD_CTL, SD_IO_USING_1V8,
1912                        SD_IO_USING_3V3);
1913         if (chip->asic_code)
1914                 rts51x_add_cmd(chip, WRITE_REG_CMD, LDO_POWER_CFG,
1915                                TUNE_SD18_MASK, TUNE_SD18_3V3);
1916         if (chip->asic_code)
1917                 sd_pull_ctl_disable(chip);
1918         else
1919                 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL,
1920                                FPGA_SD_PULL_CTL_BIT | 0x20,
1921                                FPGA_SD_PULL_CTL_BIT);
1922         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
1923         if (!chip->option.FT2_fast_mode)
1924                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
1925                                POWER_OFF);
1926
1927         retval = rts51x_send_cmd(chip, MODE_C, 100);
1928         if (retval != STATUS_SUCCESS)
1929                 TRACE_RET(chip, retval);
1930         if (!chip->option.FT2_fast_mode) {
1931 #ifdef SD_XD_IO_FOLLOW_PWR
1932                 if (CHECK_PKG(chip, LQFP48)
1933                     || chip->option.rts5129_D3318_off_enable)
1934                         rts51x_write_register(chip, CARD_PWR_CTL,
1935                                         LDO_OFF, LDO_OFF);
1936 #endif
1937                 wait_timeout(250);
1938
1939 #ifdef SD_XD_IO_FOLLOW_PWR
1940                 if (CHECK_PKG(chip, LQFP48)
1941                     || chip->option.rts5129_D3318_off_enable) {
1942                         rts51x_init_cmd(chip);
1943                         if (chip->asic_code)
1944                                 sd_pull_ctl_enable(chip);
1945                         else
1946                                 rts51x_add_cmd(chip, WRITE_REG_CMD,
1947                                                FPGA_PULL_CTL,
1948                                                FPGA_SD_PULL_CTL_BIT | 0x20, 0);
1949                         retval = rts51x_send_cmd(chip, MODE_C, 100);
1950                         if (retval != STATUS_SUCCESS)
1951                                 TRACE_RET(chip, retval);
1952                 } else {
1953                         if (chip->asic_code)
1954                                 rts51x_write_register(chip, CARD_PULL_CTL6,
1955                                                       0x03, 0x00);
1956                 }
1957 #endif
1958
1959                 /* Power on card */
1960                 retval = card_power_on(chip, SD_CARD);
1961                 if (retval != STATUS_SUCCESS)
1962                         TRACE_RET(chip, retval);
1963
1964                 wait_timeout(260);
1965
1966 #ifdef SUPPORT_OCP
1967                 rts51x_get_card_status(chip, &(chip->card_status));
1968                 chip->ocp_stat = (chip->card_status >> 4) & 0x03;
1969
1970                 if (chip->ocp_stat & (MS_OCP_NOW | MS_OCP_EVER)) {
1971                         RTS51X_DEBUGP("Over current, OCPSTAT is 0x%x\n",
1972                                        chip->ocp_stat);
1973                         TRACE_RET(chip, STATUS_FAIL);
1974                 }
1975 #endif
1976         }
1977
1978         rts51x_init_cmd(chip);
1979         if (chip->asic_code) {
1980                 sd_pull_ctl_enable(chip);
1981         } else {
1982                 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL,
1983                                FPGA_SD_PULL_CTL_BIT | 0x20, 0);
1984         }
1985         retval = rts51x_send_cmd(chip, MODE_C, 100);
1986         if (retval != STATUS_SUCCESS)
1987                 TRACE_RET(chip, retval);
1988 #ifdef SD_XD_IO_FOLLOW_PWR
1989         rts51x_write_register(chip, CARD_INT_PEND, XD_INT | MS_INT | SD_INT,
1990                               XD_INT | MS_INT | SD_INT);
1991 #endif
1992
1993         RTS51X_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
1994
1995         return STATUS_SUCCESS;
1996 }
1997
1998 static int sd_dummy_clock(struct rts51x_chip *chip)
1999 {
2000         RTS51X_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
2001         wait_timeout(5);
2002         RTS51X_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0x00);
2003
2004         return STATUS_SUCCESS;
2005 }
2006
2007 int reset_sd(struct rts51x_chip *chip)
2008 {
2009         struct sd_info *sd_card = &(chip->sd_card);
2010         int retval, i = 0, j = 0, k = 0, hi_cap_flow = 0;
2011         int sd_dont_switch = 0;
2012         int support_1v8 = 0;
2013         u8 rsp[16];
2014         u8 switch_bus_width;
2015         u32 voltage = 0;
2016         u8 cmd[5], buf[64];
2017         u16 sd_card_type;
2018
2019         SET_SD(sd_card);
2020         CLR_RETRY_SD20_MODE(sd_card);
2021 Switch_Fail:
2022         i = 0;
2023         j = 0;
2024         k = 0;
2025         hi_cap_flow = 0;
2026         support_1v8 = 0;
2027 #ifdef SUPPORT_SD_LOCK
2028         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2029                 goto SD_UNLOCK_ENTRY;
2030 #endif
2031
2032         retval = sd_prepare_reset(chip);
2033         if (retval != STATUS_SUCCESS)
2034                 TRACE_RET(chip, retval);
2035
2036         sd_dummy_clock(chip);
2037
2038         /* Start Initialization Process of SD Card */
2039 RTY_SD_RST:
2040         retval =
2041             sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL,
2042                                 0);
2043         if (retval != STATUS_SUCCESS)
2044                 TRACE_RET(chip, retval);
2045
2046         wait_timeout(20);
2047
2048         retval =
2049             sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA, SD_RSP_TYPE_R7,
2050                                 rsp, 5);
2051         if (retval == STATUS_SUCCESS) {
2052                 if ((rsp[4] == 0xAA) && ((rsp[3] & 0x0f) == 0x01)) {
2053                         hi_cap_flow = 1;
2054                         if (CHK_RETRY_SD20_MODE(sd_card)) {
2055                                 voltage =
2056                                     SUPPORT_VOLTAGE |
2057                                     SUPPORT_HIGH_AND_EXTENDED_CAPACITY;
2058                         } else {
2059                                 voltage =
2060                                     SUPPORT_VOLTAGE |
2061                                     SUPPORT_HIGH_AND_EXTENDED_CAPACITY |
2062                                     SUPPORT_MAX_POWER_PERMANCE | SUPPORT_1V8;
2063                         }
2064                 }
2065         }
2066
2067         if (!hi_cap_flow) {
2068                 voltage = SUPPORT_VOLTAGE;
2069
2070                 retval =
2071                     sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0,
2072                                         NULL, 0);
2073                 if (retval != STATUS_SUCCESS)
2074                         TRACE_RET(chip, retval);
2075                 wait_timeout(20);
2076         }
2077
2078         /* ACMD41 */
2079         do {
2080                 {
2081                         u8 temp = 0;
2082                         rts51x_read_register(chip, CARD_INT_PEND, &temp);
2083                         RTS51X_DEBUGP("CARD_INT_PEND:%x\n", temp);
2084                         if (temp & SD_INT) {
2085                                 chip->reset_need_retry = 1;
2086                                 rts51x_write_register(chip, CARD_INT_PEND,
2087                                                       XD_INT | SD_INT | MS_INT,
2088                                                       XD_INT | SD_INT | MS_INT);
2089                                 sd_set_reset_fail(chip, SD_RESET_FAIL);
2090                                 TRACE_RET(chip, STATUS_FAIL);
2091                         }
2092                 }
2093
2094 RTY_CMD55:
2095                 retval =
2096                     sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1, NULL,
2097                                         0);
2098                 if (retval != STATUS_SUCCESS) {
2099                         if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST) {
2100                                 sd_set_reset_fail(chip, SD_RESET_FAIL);
2101                                 TRACE_RET(chip, STATUS_FAIL);
2102                         }
2103
2104                         j++;
2105                         if (chip->option.speed_mmc) {
2106                                 if (j < 2)
2107                                         goto RTY_CMD55;
2108                                 else
2109                                         TRACE_RET(chip, STATUS_FAIL);
2110                         } else {
2111                                 if (j < 3)
2112                                         goto RTY_SD_RST;
2113                                 else
2114                                         TRACE_RET(chip, STATUS_FAIL);
2115                         }
2116                 }
2117
2118                 retval =
2119                     sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage,
2120                                         SD_RSP_TYPE_R3, rsp, 5);
2121                 if (retval != STATUS_SUCCESS) {
2122                         k++;
2123                         if (k < 3)
2124                                 goto RTY_SD_RST;
2125                         else
2126                                 TRACE_RET(chip, STATUS_FAIL);
2127                 }
2128
2129                 i++;
2130                 wait_timeout(20);
2131         } while (!(rsp[1] & 0x80) && (i < 255)); /* Not complete power on */
2132
2133         if (i == 255) {
2134                 /* Time out */
2135                 TRACE_RET(chip, STATUS_FAIL);
2136         }
2137
2138         if (hi_cap_flow) {
2139                 if (rsp[1] & 0x40)
2140                         SET_SD_HCXC(sd_card);
2141                 else
2142                         CLR_SD_HCXC(sd_card);
2143                 if (!CHK_RETRY_SD20_MODE(sd_card)) {
2144                         if ((CHK_SD_HCXC(sd_card)) && (CHECK_UHS50(chip))) {
2145                                 support_1v8 = (rsp[1] & 0x01) ? 1 : 0;
2146                                 RTS51X_DEBUGP("support_1v8 = %d\n",
2147                                                support_1v8);
2148                         }
2149                 }
2150         } else {
2151                 CLR_SD_HCXC(sd_card);
2152                 support_1v8 = 0;
2153         }
2154
2155         /* CMD11: Switch Voltage */
2156         if (support_1v8 && CHECK_UHS50(chip)
2157             && !(((u8) chip->option.sd_speed_prior & SDR104_SUPPORT) ==
2158                  HS_SUPPORT)) {
2159                 retval = sd_voltage_switch(chip);
2160                 if (retval != STATUS_SUCCESS) {
2161                         SET_RETRY_SD20_MODE(sd_card);
2162                         sd_init_power(chip);
2163                         RTS51X_DEBUGP("1.8v switch fail\n");
2164                         goto Switch_Fail;
2165                 }
2166         }
2167
2168         /* CMD 2 */
2169         retval =
2170             sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, NULL, 0);
2171         if (retval != STATUS_SUCCESS)
2172                 TRACE_RET(chip, retval);
2173
2174         /* CMD 3 */
2175         retval =
2176             sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0, SD_RSP_TYPE_R6,
2177                                 rsp, 5);
2178         if (retval != STATUS_SUCCESS)
2179                 TRACE_RET(chip, retval);
2180
2181         sd_card->sd_addr = (u32) rsp[1] << 24;
2182         sd_card->sd_addr += (u32) rsp[2] << 16;
2183
2184         /* Get CSD register for Calculating Timing,Capacity,
2185          * Check CSD to determaine as if this is the SD ROM card */
2186         retval = sd_check_csd(chip, 1);
2187         if (retval != STATUS_SUCCESS)
2188                 TRACE_RET(chip, retval);
2189         /* Select SD card */
2190         retval = sd_select_card(chip, 1);
2191         if (retval != STATUS_SUCCESS)
2192                 TRACE_RET(chip, retval);
2193 #ifdef SUPPORT_SD_LOCK
2194 SD_UNLOCK_ENTRY:
2195         /* Get SD lock status */
2196         retval = sd_update_lock_status(chip);
2197         if (retval != STATUS_SUCCESS)
2198                 TRACE_RET(chip, STATUS_FAIL);
2199
2200         if (sd_card->sd_lock_status & SD_LOCKED) {
2201                 sd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST);
2202                 return STATUS_SUCCESS;
2203         } else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) {
2204                 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
2205         }
2206 #endif
2207
2208         /* ACMD42 */
2209         retval =
2210             sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1,
2211                                 NULL, 0);
2212         if (retval != STATUS_SUCCESS)
2213                 TRACE_RET(chip, retval);
2214
2215         retval =
2216             sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0, SD_RSP_TYPE_R1,
2217                                 NULL, 0);
2218         if (retval != STATUS_SUCCESS)
2219                 TRACE_RET(chip, retval);
2220
2221         if (support_1v8) {
2222                 /* ACMD6 */
2223                 retval =
2224                     sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2225                                         SD_RSP_TYPE_R1, NULL, 0);
2226                 if (retval != STATUS_SUCCESS)
2227                         TRACE_RET(chip, retval);
2228                 /* Enable 4 bit data bus */
2229                 retval =
2230                     sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, SD_RSP_TYPE_R1,
2231                                         NULL, 0);
2232                 if (retval != STATUS_SUCCESS)
2233                         TRACE_RET(chip, retval);
2234                 switch_bus_width = SD_BUS_WIDTH_4;
2235         } else {
2236                 switch_bus_width = SD_BUS_WIDTH_1;
2237         }
2238
2239         /* Set block length 512 bytes for all block commands */
2240         retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN,
2241                         0x200, SD_RSP_TYPE_R1, NULL, 0);
2242         if (retval != STATUS_SUCCESS)
2243                 TRACE_RET(chip, retval);
2244
2245         RTS51X_WRITE_REG(chip, SD_CFG1, SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
2246
2247         if (!(sd_card->raw_csd[4] & 0x40)) {
2248                 sd_dont_switch = 1;
2249                 RTS51X_DEBUGP("Not support class ten\n");
2250         }
2251
2252         if (!sd_dont_switch) {
2253                 /* Check the card whether flow SD1.1 spec or higher */
2254                 retval = sd_check_spec(chip, switch_bus_width);
2255                 if (retval == STATUS_SUCCESS) {
2256                         retval = sd_switch_function(chip, switch_bus_width);
2257                         if (retval != STATUS_SUCCESS) {
2258                                 if ((sd_card->sd_switch_fail ==
2259                                      SDR104_SUPPORT_MASK)
2260                                     || (sd_card->sd_switch_fail ==
2261                                         DDR50_SUPPORT_MASK)
2262                                     || (sd_card->sd_switch_fail ==
2263                                             SDR50_SUPPORT_MASK)) {
2264                                         sd_init_power(chip);
2265                                         SET_RETRY_SD20_MODE(sd_card);
2266                                 } else if (sd_card->sd_switch_fail ==
2267                                                 HS_SUPPORT_MASK) {
2268                                         sd_dont_switch = 1;
2269                                 }
2270                                 goto Switch_Fail;
2271                         }
2272                 } else {
2273                         if (support_1v8) {
2274                                 SET_RETRY_SD20_MODE(sd_card);
2275                                 sd_init_power(chip);
2276                                 sd_dont_switch = 1;
2277
2278                                 goto Switch_Fail;
2279                         }
2280                 }
2281         }
2282
2283         if (!support_1v8) {
2284                 /* ACMD6 */
2285                 retval =
2286                     sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2287                                         SD_RSP_TYPE_R1, NULL, 0);
2288                 if (retval != STATUS_SUCCESS)
2289                         TRACE_RET(chip, retval);
2290                 /* Enable 4 bit data bus */
2291                 retval =
2292                     sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, SD_RSP_TYPE_R1,
2293                                         NULL, 0);
2294                 if (retval != STATUS_SUCCESS)
2295                         TRACE_RET(chip, retval);
2296         }
2297 #ifdef SUPPORT_SD_LOCK
2298         /* clear 1 bit mode status */
2299         sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2300 #endif
2301
2302         if (CHK_SD30_SPEED(sd_card)) {
2303                 rts51x_write_register(chip, SD30_DRIVE_SEL, SD30_DRIVE_MASK,
2304                                       0x03);
2305
2306                 retval = sd_set_init_para(chip);
2307                 if (retval != STATUS_SUCCESS)
2308                         TRACE_RET(chip, retval);
2309
2310                 if (CHK_SD_DDR50(sd_card))
2311                         retval = sd_ddr_tuning(chip);
2312                 else
2313                         retval = sd_sdr_tuning(chip);
2314
2315                 if (retval != STATUS_SUCCESS) {
2316                         SET_RETRY_SD20_MODE(sd_card);
2317                         RTS51X_DEBUGP("tuning phase fail,goto SD20 mode\n");
2318                         sd_init_power(chip);
2319                         CLR_SD30_SPEED(sd_card);
2320                         goto Switch_Fail;
2321                 }
2322                 if (STATUS_SUCCESS ==
2323                     sd_wait_currentstate_dataready(chip, 0x08, 1, 20)) {
2324                         cmd[0] = 0x40 | READ_SINGLE_BLOCK;
2325                         cmd[1] = 0x00;
2326                         cmd[2] = 0x00;
2327                         cmd[3] = 0x00;
2328                         cmd[4] = 0x00;
2329                         retval =
2330                             sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 512,
2331                                          1, SD_BUS_WIDTH_4, NULL, 0, 600);
2332                         if (retval != STATUS_SUCCESS) {
2333                                 SET_RETRY_SD20_MODE(sd_card);
2334                                 RTS51X_DEBUGP("read lba0 fail,"
2335                                                         "goto SD20 mode\n");
2336                                 sd_init_power(chip);
2337                                 CLR_SD30_SPEED(sd_card);
2338                                 goto Switch_Fail;
2339                         }
2340                 }
2341         }
2342         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1,
2343                             NULL, 0);
2344
2345         retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2346                         SD_RSP_TYPE_R1, NULL, 0);
2347         if (retval == STATUS_SUCCESS) {
2348                 int ret;
2349                 cmd[0] = 0x40 | SEND_STATUS;
2350                 cmd[1] = 0x00;
2351                 cmd[2] = 0x00;
2352                 cmd[3] = 0x00;
2353                 cmd[4] = 0x00;
2354                 ret =
2355                     sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1,
2356                                  SD_BUS_WIDTH_4, buf, 64, 600);
2357                 if (ret == STATUS_SUCCESS) {
2358                         sd_card_type = ((u16) buf[2] << 8) | (u16) buf[3];
2359                         RTS51X_DEBUGP("sd_card_type:0x%4x\n", sd_card_type);
2360                         if ((sd_card_type == 0x0001)
2361                             || (sd_card_type == 0x0002))
2362                                 chip->card_wp |= SD_CARD;
2363                 } else {
2364                         rts51x_clear_sd_error(chip);
2365                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2366                                             SD_RSP_TYPE_R1, NULL, 0);
2367                 }
2368         } else {
2369                 rts51x_clear_sd_error(chip);
2370                 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2371                                     SD_RSP_TYPE_R1, NULL, 0);
2372         }
2373
2374         /* Check SD Machanical Write-Protect Switch */
2375         retval = rts51x_get_card_status(chip, &(chip->card_status));
2376         if (retval != STATUS_SUCCESS)
2377                 TRACE_RET(chip, retval);
2378         if (chip->card_status & SD_WP)
2379                 chip->card_wp |= SD_CARD;
2380
2381         chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2382
2383 #ifdef SUPPORT_SD_LOCK
2384         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
2385                 rts51x_init_cmd(chip);
2386
2387                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0x02);
2388                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 0x00);
2389
2390                 retval = rts51x_send_cmd(chip, MODE_C, 100);
2391                 if (retval != STATUS_SUCCESS)
2392                         TRACE_RET(chip, retval);
2393         }
2394 #endif
2395
2396         return STATUS_SUCCESS;
2397 }
2398
2399 static int mmc_test_switch_bus(struct rts51x_chip *chip, u8 width)
2400 {
2401         struct sd_info *sd_card = &(chip->sd_card);
2402         int retval;
2403         u8 buf[8] = { 0 }, bus_width;
2404         u16 byte_cnt;
2405         int len;
2406
2407         retval =
2408             sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL, 0);
2409         if (retval != STATUS_SUCCESS)
2410                 TRACE_RET(chip, retval);
2411
2412         if (width == MMC_8BIT_BUS) {
2413                 buf[0] = 0x55;
2414                 buf[1] = 0xAA;
2415                 len = 8;
2416                 byte_cnt = 8;
2417                 bus_width = SD_BUS_WIDTH_8;
2418         } else {
2419                 buf[0] = 0x5A;
2420                 len = 4;
2421                 byte_cnt = 4;
2422                 bus_width = SD_BUS_WIDTH_4;
2423         }
2424
2425         retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3,
2426                                NULL, 0, byte_cnt, 1, bus_width, buf, len, 100);
2427         if (retval != STATUS_SUCCESS) {
2428                 u8 val1 = 0, val2 = 0;
2429                 rts51x_ep0_read_register(chip, SD_STAT1, &val1);
2430                 rts51x_ep0_read_register(chip, SD_STAT2, &val2);
2431                 rts51x_clear_sd_error(chip);
2432                 if ((val1 & 0xE0) || val2)
2433                         TRACE_RET(chip, STATUS_FAIL);
2434         }
2435         RTS51X_DEBUGP("SD/MMC CMD %d\n", BUSTEST_R);
2436
2437         rts51x_init_cmd(chip);
2438
2439         /* CMD14 */
2440         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | BUSTEST_R);
2441
2442         if (width == MMC_8BIT_BUS)
2443                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x08);
2444         else
2445                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x04);
2446
2447         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
2448         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
2449
2450         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
2451                        SD_CALCULATE_CRC7 | SD_NO_CHECK_CRC16 |
2452                        SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
2453         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
2454                        PINGPONG_BUFFER);
2455         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
2456                        SD_TM_NORMAL_READ | SD_TRANSFER_START);
2457         rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END,
2458                        SD_TRANSFER_END);
2459
2460         rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0);
2461         if (width == MMC_8BIT_BUS) {
2462                 len = 3;
2463                 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0);
2464         } else {
2465                 len = 2;
2466         }
2467
2468         retval = rts51x_send_cmd(chip, MODE_CR, 100);
2469         if (retval != STATUS_SUCCESS)
2470                 TRACE_RET(chip, retval);
2471
2472         retval = rts51x_get_rsp(chip, len, 100);
2473         if (CHECK_SD_TRANS_FAIL(chip, retval)) {
2474                 rts51x_clear_sd_error(chip);
2475                 TRACE_RET(chip, STATUS_FAIL);
2476         }
2477
2478         rts51x_read_rsp_buf(chip, 1, buf, 2);
2479
2480         if (width == MMC_8BIT_BUS) {
2481                 RTS51X_DEBUGP("BUSTEST_R [8bits]: 0x%02x 0x%02x\n",
2482                                         buf[0], buf[1]);
2483                 if ((buf[0] == 0xAA) && (buf[1] == 0x55)) {
2484                         u8 rsp[5];
2485                         u32 arg;
2486
2487                         if (CHK_MMC_DDR52(sd_card))
2488                                 arg = 0x03B70600;
2489                         else
2490                                 arg = 0x03B70200;
2491                         /* Switch MMC to  8-bit mode */
2492                         retval =
2493                             sd_send_cmd_get_rsp(chip, SWITCH, arg,
2494                                                 SD_RSP_TYPE_R1b, rsp, 5);
2495                         if ((retval == STATUS_SUCCESS)
2496                             && !(rsp[4] & MMC_SWITCH_ERR))
2497                                 return STATUS_SUCCESS;
2498                 }
2499         } else {
2500                 RTS51X_DEBUGP("BUSTEST_R [4bits]: 0x%02x\n", buf[0]);
2501                 if (buf[0] == 0xA5) {
2502                         u8 rsp[5];
2503                         u32 arg;
2504
2505                         if (CHK_MMC_DDR52(sd_card))
2506                                 arg = 0x03B70500;
2507                         else
2508                                 arg = 0x03B70100;
2509                         /* Switch MMC to  4-bit mode */
2510                         retval =
2511                             sd_send_cmd_get_rsp(chip, SWITCH, arg,
2512                                                 SD_RSP_TYPE_R1b, rsp, 5);
2513                         if ((retval == STATUS_SUCCESS)
2514                             && !(rsp[4] & MMC_SWITCH_ERR))
2515                                 return STATUS_SUCCESS;
2516                 }
2517         }
2518
2519         TRACE_RET(chip, STATUS_FAIL);
2520 }
2521
2522 static int mmc_switch_timing_bus(struct rts51x_chip *chip)
2523 {
2524         struct sd_info *sd_card = &(chip->sd_card);
2525         int retval;
2526         u8 card_type, card_type_mask = 0;
2527         u8 buf[6];
2528
2529         CLR_MMC_HS(sd_card);
2530
2531         RTS51X_DEBUGP("SD/MMC CMD %d\n", SEND_EXT_CSD);
2532
2533         rts51x_init_cmd(chip);
2534
2535         /* SEND_EXT_CSD command */
2536         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0, 0xFF,
2537                         0x40 | SEND_EXT_CSD);
2538         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD1, 0xFF, 0);
2539         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD2, 0xFF, 0);
2540         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD3, 0xFF, 0);
2541         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD4, 0xFF, 0);
2542
2543         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0);
2544         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 2);
2545         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
2546         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
2547
2548         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
2549                        SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END
2550                        | SD_CHECK_CRC7 | SD_RSP_LEN_6);
2551         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
2552                        PINGPONG_BUFFER);
2553         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
2554                        SD_TM_NORMAL_READ | SD_TRANSFER_START);
2555         rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END,
2556                        SD_TRANSFER_END);
2557
2558         rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0);
2559         rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0);
2560         rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0);
2561         rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0);
2562         rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0);
2563
2564         retval = rts51x_send_cmd(chip, MODE_CR, 100);
2565         if (retval != STATUS_SUCCESS)
2566                 TRACE_RET(chip, retval);
2567
2568         retval = rts51x_get_rsp(chip, 6, 1000);
2569
2570         if (CHECK_SD_TRANS_FAIL(chip, retval)) {
2571                 if (retval == STATUS_TIMEDOUT) {
2572                         rts51x_clear_sd_error(chip);
2573                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2574                                             SD_RSP_TYPE_R1, NULL, 0);
2575                 }
2576                 TRACE_RET(chip, STATUS_FAIL);
2577         }
2578
2579         rts51x_read_rsp_buf(chip, 0, buf, 6);
2580
2581         if (buf[0] & SD_TRANSFER_ERR) {
2582                 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2583                                     SD_RSP_TYPE_R1, NULL, 0);
2584                 TRACE_RET(chip, STATUS_FAIL);
2585         }
2586         if (CHK_MMC_SECTOR_MODE(sd_card))
2587                 sd_card->capacity =
2588                     ((u32) buf[5] << 24) | ((u32) buf[4] << 16) |
2589                     ((u32) buf[3] << 8) | ((u32) buf[2]);
2590 #ifdef SUPPORT_SD_LOCK
2591         if (!(sd_card->sd_lock_status & SD_SDR_RST) && CHECK_UHS50(chip))
2592                 card_type_mask = 0x07;
2593         else
2594                 card_type_mask = 0x03;
2595 #else
2596         if (CHECK_UHS50(chip))
2597                 card_type_mask = 0x07;
2598         else
2599                 card_type_mask = 0x03;
2600 #endif
2601
2602         card_type = buf[1] & card_type_mask;
2603         if (card_type) {
2604                 /* CARD TYPE FIELD = DDR52MHz, 52MHz or 26MHz */
2605                 u8 rsp[5];
2606
2607                 if (card_type & 0x04)
2608                         SET_MMC_DDR52(sd_card);
2609                 else if (card_type & 0x02)
2610                         SET_MMC_52M(sd_card);
2611                 else
2612                         SET_MMC_26M(sd_card);
2613
2614                 retval =
2615                     sd_send_cmd_get_rsp(chip, SWITCH, 0x03B90100,
2616                                         SD_RSP_TYPE_R1b, rsp, 5);
2617                 if ((retval != STATUS_SUCCESS) || (rsp[4] & MMC_SWITCH_ERR))
2618                         CLR_MMC_HS(sd_card);
2619         }
2620         sd_choose_proper_clock(chip);
2621         retval = switch_clock(chip, sd_card->sd_clock);
2622         if (retval != STATUS_SUCCESS)
2623                 TRACE_RET(chip, retval);
2624
2625         /* Test Bus Procedure */
2626         if (mmc_test_switch_bus(chip, MMC_8BIT_BUS) == STATUS_SUCCESS) {
2627                 SET_MMC_8BIT(sd_card);
2628                 chip->card_bus_width[chip->card2lun[SD_CARD]] = 8;
2629 #ifdef SUPPORT_SD_LOCK
2630                 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2631 #endif
2632         } else if (mmc_test_switch_bus(chip, MMC_4BIT_BUS) == STATUS_SUCCESS) {
2633                 SET_MMC_4BIT(sd_card);
2634                 chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2635 #ifdef SUPPORT_SD_LOCK
2636                 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2637 #endif
2638         } else {
2639                 CLR_MMC_8BIT(sd_card);
2640                 CLR_MMC_4BIT(sd_card);
2641         }
2642
2643         return STATUS_SUCCESS;
2644 }
2645
2646 static int reset_mmc(struct rts51x_chip *chip)
2647 {
2648         struct sd_info *sd_card = &(chip->sd_card);
2649         int retval, i = 0, j = 0, k = 0;
2650         u8 rsp[16];
2651         u8 spec_ver = 0;
2652         u8 change_to_ddr52 = 1;
2653         u8 cmd[5];
2654
2655 #ifdef SUPPORT_SD_LOCK
2656         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2657                 goto MMC_UNLOCK_ENTRY;
2658 #endif
2659
2660 MMC_DDR_FAIL:
2661
2662         retval = sd_prepare_reset(chip);
2663         if (retval != STATUS_SUCCESS)
2664                 TRACE_RET(chip, retval);
2665
2666         SET_MMC(sd_card);
2667
2668 RTY_MMC_RST:
2669         retval =
2670             sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL,
2671                                 0);
2672         if (retval != STATUS_SUCCESS)
2673                 TRACE_RET(chip, retval);
2674
2675         do {
2676                 {
2677                         u8 temp = 0;
2678                         rts51x_read_register(chip, CARD_INT_PEND, &temp);
2679                         if (temp & SD_INT) {
2680                                 chip->reset_need_retry = 1;
2681                                 rts51x_write_register(chip, CARD_INT_PEND,
2682                                                       XD_INT | SD_INT | MS_INT,
2683                                                       XD_INT | SD_INT | MS_INT);
2684                                 sd_set_reset_fail(chip, MMC_RESET_FAIL);
2685                                 TRACE_RET(chip, STATUS_FAIL);
2686                         }
2687                 }
2688
2689                 /* CMD  1 */
2690                 retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND,
2691                                              (SUPPORT_VOLTAGE | 0x40000000),
2692                                              SD_RSP_TYPE_R3, rsp, 5);
2693                 if (retval != STATUS_SUCCESS) {
2694                         if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST) {
2695                                 sd_set_reset_fail(chip, MMC_RESET_FAIL);
2696                                 TRACE_RET(chip, STATUS_FAIL);
2697                         }
2698
2699                         if (sd_check_err_code(chip, SD_BUSY)
2700                             || sd_check_err_code(chip, SD_TO_ERR)) {
2701                                 k++;
2702                                 if (k < 20) {
2703                                         sd_clr_err_code(chip);
2704                                         goto RTY_MMC_RST;
2705                                 } else {
2706                                         TRACE_RET(chip, STATUS_FAIL);
2707                                 }
2708                         } else {
2709                                 j++;
2710                                 if (j < 100) {
2711                                         sd_clr_err_code(chip);
2712                                         goto RTY_MMC_RST;
2713                                 } else {
2714                                         TRACE_RET(chip, STATUS_FAIL);
2715                                 }
2716                         }
2717                 }
2718
2719                 wait_timeout(20);
2720                 i++;
2721         } while (!(rsp[1] & 0x80) && (i < 100)); /* Not complete power on */
2722
2723         if (i == 100) {
2724                 /* Time out */
2725                 TRACE_RET(chip, STATUS_FAIL);
2726         }
2727
2728         if ((rsp[1] & 0x60) == 0x40)
2729                 SET_MMC_SECTOR_MODE(sd_card);
2730         else
2731                 CLR_MMC_SECTOR_MODE(sd_card);
2732
2733         /* CMD 2 */
2734         retval =
2735             sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, NULL, 0);
2736         if (retval != STATUS_SUCCESS)
2737                 TRACE_RET(chip, retval);
2738
2739         /* CMD 3 */
2740         sd_card->sd_addr = 0x00100000;
2741         retval =
2742             sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr,
2743                                 SD_RSP_TYPE_R6, rsp, 5);
2744         if (retval != STATUS_SUCCESS)
2745                 TRACE_RET(chip, retval);
2746
2747         /* Get CSD register for Calculating Timing,Capacity
2748          * Check CSD to determaine as if this is the SD ROM card */
2749         retval = sd_check_csd(chip, 1);
2750         if (retval != STATUS_SUCCESS)
2751                 TRACE_RET(chip, retval);
2752         /* Get MMC Spec_Ver in the CSD register */
2753         spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2;
2754
2755         /* Select MMC card */
2756         retval = sd_select_card(chip, 1);
2757         if (retval != STATUS_SUCCESS)
2758                 TRACE_RET(chip, retval);
2759
2760         /* Set block length 512 bytes for all block commands */
2761         retval =
2762             sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, NULL,
2763                                 0);
2764         if (retval != STATUS_SUCCESS)
2765                 TRACE_RET(chip, retval);
2766 #ifdef SUPPORT_SD_LOCK
2767 MMC_UNLOCK_ENTRY:
2768         /* Get SD lock status */
2769         retval = sd_update_lock_status(chip);
2770         if (retval != STATUS_SUCCESS)
2771                 TRACE_RET(chip, STATUS_FAIL);
2772 #endif
2773
2774         RTS51X_WRITE_REG(chip, SD_CFG1, SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
2775
2776         if (chip->ic_version < 2)
2777                 rts51x_write_register(chip, SD30_DRIVE_SEL, SD30_DRIVE_MASK,
2778                                       0x02);
2779         rts51x_write_register(chip, CARD_DRIVE_SEL, SD20_DRIVE_MASK, DRIVE_8mA);
2780
2781         chip->card_bus_width[chip->card2lun[SD_CARD]] = 1;
2782         if (spec_ver == 4) {
2783                 /* MMC 4.x Cards */
2784                 (void)mmc_switch_timing_bus(chip);
2785         }
2786
2787         if (CHK_MMC_SECTOR_MODE(sd_card) && (sd_card->capacity == 0))
2788                 TRACE_RET(chip, STATUS_FAIL);
2789
2790         if (CHK_MMC_DDR52(sd_card) && change_to_ddr52) {
2791                 /* Card is extracted while identifying */
2792                 if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST)
2793                         TRACE_RET(chip, STATUS_FAIL);
2794
2795                 retval = sd_set_init_para(chip);
2796                 if (retval != STATUS_SUCCESS) {
2797                         CLR_MMC_DDR52(sd_card);
2798                         sd_init_power(chip);
2799                         change_to_ddr52 = 0;
2800                         goto MMC_DDR_FAIL;
2801                 }
2802
2803                 retval = mmc_ddr_tuning(chip);
2804                 if (retval != STATUS_SUCCESS) {
2805                         CLR_MMC_DDR52(sd_card);
2806                         sd_init_power(chip);
2807                         change_to_ddr52 = 0;
2808                         goto MMC_DDR_FAIL;
2809                 }
2810
2811                 if (STATUS_SUCCESS ==
2812                     sd_wait_currentstate_dataready(chip, 0x08, 1, 20)) {
2813                         cmd[0] = 0x40 | READ_SINGLE_BLOCK;
2814                         cmd[1] = 0x00;
2815                         cmd[2] = 0x00;
2816                         cmd[3] = 0x00;
2817                         cmd[4] = 0x00;
2818                         if (CHK_MMC_8BIT(sd_card)) {
2819                                 retval =
2820                                     sd_read_data(chip, SD_TM_NORMAL_READ, cmd,
2821                                                  5, 512, 1, SD_BUS_WIDTH_8,
2822                                                  NULL, 0, 600);
2823                         } else if (CHK_MMC_4BIT(sd_card)) {
2824                                 retval =
2825                                     sd_read_data(chip, SD_TM_NORMAL_READ, cmd,
2826                                                  5, 512, 1, SD_BUS_WIDTH_4,
2827                                                  NULL, 0, 600);
2828                         } else {
2829                                 retval =
2830                                     sd_read_data(chip, SD_TM_NORMAL_READ, cmd,
2831                                                  5, 512, 1, SD_BUS_WIDTH_1,
2832                                                  NULL, 0, 600);
2833                         }
2834
2835                         if (retval != STATUS_SUCCESS) {
2836                                 CLR_MMC_DDR52(sd_card);
2837                                 change_to_ddr52 = 0;
2838                                 RTS51X_DEBUGP("read lba0 fail,"
2839                                                         "goto SD20 mode\n");
2840                                 sd_init_power(chip);
2841                                 goto MMC_DDR_FAIL;
2842                         }
2843                 }
2844         }
2845 #ifdef SUPPORT_SD_LOCK
2846         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
2847                 rts51x_init_cmd(chip);
2848
2849                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0x02);
2850                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 0x00);
2851
2852                 retval = rts51x_send_cmd(chip, MODE_C, 100);
2853                 if (retval != STATUS_SUCCESS)
2854                         TRACE_RET(chip, retval);
2855         }
2856 #endif
2857
2858         retval = rts51x_get_card_status(chip, &(chip->card_status));
2859         if (retval != STATUS_SUCCESS)
2860                 TRACE_RET(chip, retval);
2861         if (chip->card_status & SD_WP)
2862                 chip->card_wp |= SD_CARD;
2863
2864         return STATUS_SUCCESS;
2865 }
2866
2867 int reset_sd_card(struct rts51x_chip *chip)
2868 {
2869         struct sd_info *sd_card = &(chip->sd_card);
2870         int retval;
2871         int i;
2872
2873         memset(sd_card, 0, sizeof(struct sd_info));
2874
2875         /* Init variables */
2876         sd_card->sd_type = 0;
2877         sd_card->seq_mode = 0;
2878         sd_card->sd_data_buf_ready = 0;
2879         sd_card->capacity = 0;
2880         sd_card->sd_switch_fail = 0;
2881
2882 #ifdef SUPPORT_SD_LOCK
2883         sd_card->sd_lock_status = 0;
2884         sd_card->sd_erase_status = 0;
2885 #endif
2886
2887         sd_clear_reset_fail(chip);
2888         enable_card_clock(chip, SD_CARD);
2889
2890         sd_init_power(chip);
2891
2892         chip->reset_need_retry = 0;
2893         for (i = 0; i < 3; i++) {
2894                 if (!chip->option.reset_mmc_first) { /* reset sd first */
2895                         retval = reset_sd(chip);
2896                         if (retval != STATUS_SUCCESS) {
2897                                 /* Switch SD bus to 3V3 signal */
2898                                 RTS51X_WRITE_REG(chip, SD_PAD_CTL,
2899                                                  SD_IO_USING_1V8, 0);
2900                                 if (sd_check_reset_fail(chip, SD_RESET_FAIL))
2901                                         sd_clear_reset_fail(chip);
2902                                 else
2903                                         retval = reset_mmc(chip);
2904                         }
2905                 } else { /* reset MMC first */
2906                         retval = reset_mmc(chip);
2907                         if (retval != STATUS_SUCCESS) {
2908                                 if (sd_check_reset_fail(chip, MMC_RESET_FAIL)) {
2909                                         sd_clear_reset_fail(chip);
2910                                 } else {
2911                                         retval = reset_sd(chip);
2912                                         if (retval != STATUS_SUCCESS) {
2913                                                 /* Switch SD bus to
2914                                                  * 3V3 signal */
2915                                                 RTS51X_WRITE_REG(chip,
2916                                                         SD_PAD_CTL,
2917                                                         SD_IO_USING_1V8, 0);
2918                                         }
2919                                 }
2920                         }
2921                 }
2922
2923                 if ((retval == STATUS_SUCCESS) || (!chip->reset_need_retry)) {
2924                         /* if reset success or don't need retry,then break */
2925                         break;
2926                 }
2927                 if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST) {
2928                         /* card is extracted */
2929                         break;
2930                 }
2931                 RTS51X_DEBUGP("retry reset sd card,%d\n", i);
2932                 chip->reset_need_retry = 0;
2933         }
2934
2935         sd_clear_reset_fail(chip);
2936         chip->reset_need_retry = 0;
2937
2938         if (retval == STATUS_SUCCESS) {
2939                 rts51x_init_cmd(chip);
2940                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, SD_CLK_DIVIDE_MASK,
2941                                SD_CLK_DIVIDE_0);
2942                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0);
2943                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 2);
2944                 retval = rts51x_send_cmd(chip, MODE_C, 100);
2945                 if (retval != STATUS_SUCCESS)
2946                         TRACE_RET(chip, retval);
2947         } else {
2948                 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0;
2949                 if (chip->option.reset_or_rw_fail_set_pad_drive) {
2950                         rts51x_write_register(chip, CARD_DRIVE_SEL,
2951                                               SD20_DRIVE_MASK, DRIVE_8mA);
2952                 }
2953                 TRACE_RET(chip, STATUS_FAIL);
2954         }
2955
2956         chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
2957
2958         if (chip->option.sd_send_status_en) {
2959                 sd_card->sd_send_status_en = 1;
2960         } else {
2961                 if (sd_card->capacity > 0x20000) { /* 64MB */
2962                         sd_card->sd_send_status_en = 0;
2963                 } else {
2964                         sd_card->sd_send_status_en = 1;
2965                 }
2966         }
2967         RTS51X_DEBUGP("sd_card->sd_send_status = %d\n",
2968                        sd_card->sd_send_status_en);
2969
2970         retval = sd_set_init_para(chip);
2971         if (retval != STATUS_SUCCESS)
2972                 TRACE_RET(chip, retval);
2973
2974         RTS51X_DEBUGP("sd_card->sd_type = 0x%x\n", sd_card->sd_type);
2975
2976         return STATUS_SUCCESS;
2977 }
2978
2979 #define WAIT_DATA_READY_RTY_CNT         255
2980
2981 static int wait_data_buf_ready(struct rts51x_chip *chip)
2982 {
2983         struct sd_info *sd_card = &(chip->sd_card);
2984         int i, retval;
2985
2986         for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) {
2987                 if (monitor_card_cd(chip, SD_CARD) == CD_NOT_EXIST)
2988                         TRACE_RET(chip, STATUS_FAIL);
2989
2990                 sd_card->sd_data_buf_ready = 0;
2991
2992                 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
2993                                              sd_card->sd_addr, SD_RSP_TYPE_R1,
2994                                              NULL, 0);
2995                 if (retval != STATUS_SUCCESS)
2996                         TRACE_RET(chip, retval);
2997
2998                 if (sd_card->sd_data_buf_ready)
2999                         return sd_send_cmd_get_rsp(chip, SEND_STATUS,
3000                                                    sd_card->sd_addr,
3001                                                    SD_RSP_TYPE_R1, NULL, 0);
3002         }
3003
3004         sd_set_err_code(chip, SD_TO_ERR);
3005
3006         TRACE_RET(chip, STATUS_FAIL);
3007 }
3008
3009 void sd_stop_seq_mode(struct rts51x_chip *chip)
3010 {
3011         struct sd_info *sd_card = &(chip->sd_card);
3012         int retval;
3013
3014         if (sd_card->seq_mode) {
3015                 retval = sd_switch_clock(chip);
3016                 if (retval != STATUS_SUCCESS)
3017                         return;
3018
3019                 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3020                                              SD_RSP_TYPE_R1b, NULL, 0);
3021                 if (retval != STATUS_SUCCESS)
3022                         sd_set_err_code(chip, SD_STS_ERR);
3023                 sd_card->seq_mode = 0;
3024
3025                 rts51x_ep0_write_register(chip, MC_FIFO_CTL, FIFO_FLUSH,
3026                                           FIFO_FLUSH);
3027         }
3028 }
3029
3030 static inline int sd_auto_tune_clock(struct rts51x_chip *chip)
3031 {
3032         struct sd_info *sd_card = &(chip->sd_card);
3033         int retval;
3034
3035         if (chip->asic_code) {
3036                 if (sd_card->sd_clock > 30)
3037                         sd_card->sd_clock -= 20;
3038         } else {
3039                 if (sd_card->sd_clock == CLK_100)
3040                         sd_card->sd_clock = CLK_80;
3041                 else if (sd_card->sd_clock == CLK_80)
3042                         sd_card->sd_clock = CLK_60;
3043                 else if (sd_card->sd_clock == CLK_60)
3044                         sd_card->sd_clock = CLK_50;
3045         }
3046
3047         retval = sd_switch_clock(chip);
3048         if (retval != STATUS_SUCCESS)
3049                 TRACE_RET(chip, retval);
3050
3051         return STATUS_SUCCESS;
3052 }
3053
3054 int sd_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip, u32 start_sector,
3055           u16 sector_cnt)
3056 {
3057         struct sd_info *sd_card = &(chip->sd_card);
3058         u32 data_addr;
3059         int retval;
3060         u8 flag;
3061         unsigned int pipe;
3062         u8 stageflag;
3063
3064         sd_card->counter = 0;
3065
3066         if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card))
3067                 data_addr = start_sector << 9;
3068         else
3069                 data_addr = start_sector;
3070
3071         RTS51X_DEBUGP("sd_rw, data_addr = 0x%x\n", data_addr);
3072
3073         sd_clr_err_code(chip);
3074
3075         retval = sd_switch_clock(chip);
3076         if (retval != STATUS_SUCCESS)
3077                 TRACE_RET(chip, retval);
3078
3079         if (sd_card->seq_mode && ((sd_card->pre_dir != srb->sc_data_direction)
3080                                   ||
3081                                   ((sd_card->pre_sec_addr +
3082                                     sd_card->pre_sec_cnt) != start_sector))) {
3083                 if ((sd_card->pre_dir == DMA_FROM_DEVICE)
3084                     && !CHK_SD30_SPEED(sd_card)
3085                     && !CHK_SD_HS(sd_card)
3086                     && !CHK_MMC_HS(sd_card)
3087                     && sd_card->sd_send_status_en) {
3088                         sd_send_cmd_get_rsp(chip, SEND_STATUS,
3089                                             sd_card->sd_addr, SD_RSP_TYPE_R1,
3090                                             NULL, 0);
3091                 }
3092
3093                 retval =
3094                     sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3095                                         SD_RSP_TYPE_R1b, NULL, 0);
3096                 if (retval != STATUS_SUCCESS) {
3097                         sd_set_err_code(chip, SD_STS_ERR);
3098                         TRACE_RET(chip, sd_parse_err_code(chip));
3099                 }
3100
3101                 sd_card->seq_mode = 0;
3102
3103                 RTS51X_WRITE_REG(chip, MC_FIFO_CTL, FIFO_FLUSH, FIFO_FLUSH);
3104
3105                 if (!CHK_SD30_SPEED(sd_card)
3106                     && !CHK_SD_HS(sd_card)
3107                     && !CHK_MMC_HS(sd_card)
3108                     && sd_card->sd_send_status_en) {
3109                         /* random rw, so pre_sec_cnt < 0x80 */
3110                         sd_send_cmd_get_rsp(chip, SEND_STATUS,
3111                                             sd_card->sd_addr, SD_RSP_TYPE_R1,
3112                                             NULL, 0);
3113                 }
3114         }
3115
3116         rts51x_init_cmd(chip);
3117
3118         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
3119         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
3120         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF,
3121                        (u8) sector_cnt);
3122         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF,
3123                        (u8) (sector_cnt >> 8));
3124
3125         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
3126                        RING_BUFFER);
3127
3128         if (CHK_MMC_8BIT(sd_card))
3129                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x03,
3130                                SD_BUS_WIDTH_8);
3131         else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card))
3132                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x03,
3133                                SD_BUS_WIDTH_4);
3134         else
3135                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x03,
3136                                SD_BUS_WIDTH_1);
3137
3138         if (sd_card->seq_mode) {
3139                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
3140                                SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3141                                SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 |
3142                                SD_RSP_LEN_0);
3143
3144                 trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512,
3145                                  DMA_512);
3146
3147                 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3148                         flag = MODE_CDIR;
3149                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
3150                                        SD_TM_AUTO_READ_3 | SD_TRANSFER_START);
3151                 } else {
3152                         flag = MODE_CDOR;
3153                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
3154                                        SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3155                 }
3156
3157                 rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER,
3158                                SD_TRANSFER_END, SD_TRANSFER_END);
3159
3160                 retval = rts51x_send_cmd(chip, flag, 100);
3161                 if (retval != STATUS_SUCCESS)
3162                         TRACE_RET(chip, retval);
3163         } else {
3164                 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3165                         RTS51X_DEBUGP("SD/MMC CMD %d\n", READ_MULTIPLE_BLOCK);
3166                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD0, 0xFF,
3167                                        0x40 | READ_MULTIPLE_BLOCK);
3168                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD1, 0xFF,
3169                                        (u8) (data_addr >> 24));
3170                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD2, 0xFF,
3171                                        (u8) (data_addr >> 16));
3172                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD3, 0xFF,
3173                                        (u8) (data_addr >> 8));
3174                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CMD4, 0xFF,
3175                                        (u8) data_addr);
3176
3177                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
3178                                        SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3179                                        SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 |
3180                                        SD_RSP_LEN_6);
3181
3182                         trans_dma_enable(srb->sc_data_direction, chip,
3183                                          sector_cnt * 512, DMA_512);
3184
3185                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
3186                                        SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
3187                         rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER,
3188                                        SD_TRANSFER_END, SD_TRANSFER_END);
3189
3190                         retval = rts51x_send_cmd(chip, MODE_CDIR, 100);
3191                         if (retval != STATUS_SUCCESS)
3192                                 TRACE_RET(chip, retval);
3193                 } else {
3194                         retval = rts51x_send_cmd(chip, MODE_C, 50);
3195                         if (retval != STATUS_SUCCESS) {
3196                                 rts51x_clear_sd_error(chip);
3197
3198                                 sd_set_err_code(chip, SD_TO_ERR);
3199                                 TRACE_RET(chip, sd_parse_err_code(chip));
3200                         }
3201
3202                         retval = wait_data_buf_ready(chip);
3203                         if (retval != STATUS_SUCCESS) {
3204                                 sd_set_err_code(chip, SD_TO_ERR);
3205                                 TRACE_RET(chip, sd_parse_err_code(chip));
3206                         }
3207
3208                         retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK,
3209                                                      data_addr, SD_RSP_TYPE_R1,
3210                                                      NULL, 0);
3211                         if (retval != STATUS_SUCCESS) {
3212                                 sd_set_err_code(chip, SD_CRC_ERR);
3213                                 TRACE_RET(chip, sd_parse_err_code(chip));
3214                         }
3215
3216                         rts51x_init_cmd(chip);
3217
3218                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
3219                                        SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3220                                        SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 |
3221                                        SD_RSP_LEN_0);
3222
3223                         trans_dma_enable(srb->sc_data_direction, chip,
3224                                          sector_cnt * 512, DMA_512);
3225
3226                         rts51x_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
3227                                        SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3228                         rts51x_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER,
3229                                        SD_TRANSFER_END, SD_TRANSFER_END);
3230
3231                         retval = rts51x_send_cmd(chip, MODE_CDOR, 100);
3232                         if (retval != STATUS_SUCCESS)
3233                                 TRACE_RET(chip, retval);
3234                 }
3235
3236                 sd_card->seq_mode = 1;
3237         }
3238
3239         if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3240                 pipe = RCV_BULK_PIPE(chip);
3241                 stageflag = STAGE_DI;
3242         } else {
3243                 pipe = SND_BULK_PIPE(chip);
3244                 stageflag = STAGE_DO;
3245         }
3246
3247         retval =
3248             rts51x_transfer_data_rcc(chip, pipe, scsi_sglist(srb),
3249                                      scsi_bufflen(srb), scsi_sg_count(srb),
3250                                      NULL, 10000, stageflag);
3251         if (retval != STATUS_SUCCESS) {
3252                 u8 stat = 0;
3253                 int err = retval;
3254
3255                 sd_print_debug_reg(chip);
3256
3257                 rts51x_ep0_read_register(chip, SD_STAT1, &stat);
3258                 RTS51X_DEBUGP("SD_STAT1: 0x%x\n", stat);
3259
3260                 rts51x_clear_sd_error(chip);
3261
3262                 retval =
3263                     sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3264                                         SD_RSP_TYPE_R1b, NULL, 0);
3265                 if (retval != STATUS_SUCCESS) {
3266                         sd_set_err_code(chip, SD_STS_ERR);
3267                         TRACE_RET(chip, retval);
3268                 }
3269
3270                 if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) {
3271                         RTS51X_DEBUGP("SD CRC error, tune clock!\n");
3272                         sd_auto_tune_clock(chip);
3273                 }
3274
3275                 sd_card->seq_mode = 0;
3276
3277                 TRACE_RET(chip, err);
3278         }
3279         retval = rts51x_get_rsp(chip, 1, 2000);
3280         if (CHECK_SD_TRANS_FAIL(chip, retval)) {
3281                 rts51x_clear_sd_error(chip);
3282                 TRACE_RET(chip, STATUS_FAIL);
3283         }
3284
3285         sd_card->pre_sec_addr = start_sector;
3286         sd_card->pre_sec_cnt = sector_cnt;
3287         sd_card->pre_dir = srb->sc_data_direction;
3288
3289         return STATUS_SUCCESS;
3290 }
3291
3292 void sd_cleanup_work(struct rts51x_chip *chip)
3293 {
3294         struct sd_info *sd_card = &(chip->sd_card);
3295
3296         if (sd_card->seq_mode) {
3297                 RTS51X_DEBUGP("SD: stop transmission\n");
3298                 sd_stop_seq_mode(chip);
3299                 sd_card->counter = 0;
3300         }
3301 }
3302
3303 inline void sd_fill_power_off_card3v3(struct rts51x_chip *chip)
3304 {
3305         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
3306
3307         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
3308         if (!chip->option.FT2_fast_mode) {
3309 #ifdef SD_XD_IO_FOLLOW_PWR
3310                 if (CHECK_PKG(chip, LQFP48)
3311                     || chip->option.rts5129_D3318_off_enable)
3312                         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL,
3313                                        POWER_MASK | LDO_OFF,
3314                                        POWER_OFF | LDO_OFF);
3315                 else
3316                         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL,
3317                                        POWER_MASK, POWER_OFF);
3318 #else
3319                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
3320                                POWER_OFF);
3321 #endif
3322         }
3323 }
3324
3325 int sd_power_off_card3v3(struct rts51x_chip *chip)
3326 {
3327         int retval;
3328
3329         rts51x_init_cmd(chip);
3330
3331         sd_fill_power_off_card3v3(chip);
3332
3333         retval = rts51x_send_cmd(chip, MODE_C, 100);
3334         if (retval != STATUS_SUCCESS)
3335                 TRACE_RET(chip, retval);
3336 #ifdef SD_XD_IO_FOLLOW_PWR
3337         if (!chip->option.FT2_fast_mode)
3338                 wait_timeout(chip->option.D3318_off_delay);
3339 #endif
3340
3341         return STATUS_SUCCESS;
3342 }
3343
3344 int release_sd_card(struct rts51x_chip *chip)
3345 {
3346         struct sd_info *sd_card = &(chip->sd_card);
3347         int retval;
3348
3349         RTS51X_DEBUGP("elease_sd_card\n");
3350
3351         chip->card_ready &= ~SD_CARD;
3352         chip->card_fail &= ~SD_CARD;
3353         chip->card_wp &= ~SD_CARD;
3354
3355 #ifdef SUPPORT_SD_LOCK
3356         sd_card->sd_lock_status = 0;
3357         sd_card->sd_erase_status = 0;
3358 #endif
3359
3360         memset(sd_card->raw_csd, 0, 16);
3361         memset(sd_card->raw_scr, 0, 8);
3362
3363         rts51x_write_register(chip, SFSM_ED, HW_CMD_STOP, HW_CMD_STOP);
3364         rts51x_write_register(chip, SD_PAD_CTL, SD_IO_USING_1V8, 0);
3365         if (CHECK_PKG(chip, LQFP48) || chip->option.rts5129_D3318_off_enable)
3366                 sd_power_off_card3v3(chip);
3367
3368         rts51x_init_cmd(chip);
3369         if (!(CHECK_PKG(chip, LQFP48) || chip->option.rts5129_D3318_off_enable))
3370                 sd_fill_power_off_card3v3(chip);
3371
3372         if (chip->asic_code)
3373                 sd_pull_ctl_disable(chip);
3374         else
3375                 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL,
3376                                FPGA_SD_PULL_CTL_BIT | 0x20,
3377                                FPGA_SD_PULL_CTL_BIT);
3378
3379         /* Switch LDO3318 to 3.3V */
3380         rts51x_add_cmd(chip, WRITE_REG_CMD, LDO_POWER_CFG, TUNE_SD18_MASK,
3381                        TUNE_SD18_3V3);
3382
3383         if (CHK_MMC_DDR52(sd_card) && CHK_MMC_8BIT(sd_card))
3384                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DMA1_CTL,
3385                                EXTEND_DMA1_ASYNC_SIGNAL,
3386                                EXTEND_DMA1_ASYNC_SIGNAL);
3387         if (CHK_SD30_SPEED(sd_card) || CHK_MMC(sd_card))
3388                 rts51x_add_cmd(chip, WRITE_REG_CMD, SD30_DRIVE_SEL,
3389                                SD30_DRIVE_MASK, chip->option.sd30_pad_drive);
3390         /* Suspend LDO3318 */
3391         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, LDO3318_PWR_MASK,
3392                        LDO_SUSPEND);
3393
3394         retval = rts51x_send_cmd(chip, MODE_C, 100);
3395         if (retval != STATUS_SUCCESS)
3396                 TRACE_RET(chip, retval);
3397         wait_timeout(20);
3398
3399         return STATUS_SUCCESS;
3400 }