drivers/staging/rtl8192su/r8192U.h

   1 /*
   2    This is part of rtl8187 OpenSource driver.
   3    Copyright (C) Andrea Merello 2004-2005  <andreamrl@tiscali.it>
   4    Released under the terms of GPL (General Public Licence)
   5
   6    Parts of this driver are based on the GPL part of the
   7    official realtek driver
   8
   9    Parts of this driver are based on the rtl8192 driver skeleton
  10    from Patric Schenke & Andres Salomon
  11
  12    Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
  13
  14    We want to tanks the Authors of those projects and the Ndiswrapper
  15    project Authors.
  16 */
  17
  18 #ifndef R819xU_H
  19 #define R819xU_H
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 //#include <linux/config.h>
  24 #include <linux/init.h>
  25 #include <linux/ioport.h>
  26 #include <linux/sched.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/netdevice.h>
  30 //#include <linux/pci.h>
  31 #include <linux/usb.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/delay.h>
  34 #include <linux/rtnetlink.h>    //for rtnl_lock()
  35 #include <linux/wireless.h>
  36 #include <linux/timer.h>
  37 #include <linux/proc_fs.h>      // Necessary because we use the proc fs
  38 #include <linux/if_arp.h>
  39 #include <linux/random.h>
  40 #include <linux/version.h>
  41 #include <asm/io.h>
  42
  43 #include "ieee80211/ieee80211.h"
  44
  45 #include "r8192S_firmware.h"
  46 #include "r8192SU_led.h"
  47
  48 /* EEPROM defs for use with linux/eeprom_93cx6.h */
  49 #define RTL819X_EEPROM_CMD_READ         (1 << 0)
  50 #define RTL819X_EEPROM_CMD_WRITE        (1 << 1)
  51 #define RTL819X_EEPROM_CMD_CK           (1 << 2)
  52 #define RTL819X_EEPROM_CMD_CS           (1 << 3)
  53
  54 //#define RTL8192U
  55 #define RTL819xU_MODULE_NAME "rtl819xU"
  56 //added for HW security, john.0629
  57 #define FALSE 0
  58 #define TRUE 1
  59 #define MAX_KEY_LEN     61
  60 #define KEY_BUF_SIZE    5
  61
  62 #define BIT0            0x00000001
  63 #define BIT1            0x00000002
  64 #define BIT2            0x00000004
  65 #define BIT3            0x00000008
  66 #define BIT4            0x00000010
  67 #define BIT5            0x00000020
  68 #define BIT6            0x00000040
  69 #define BIT7            0x00000080
  70 #define BIT8            0x00000100
  71 #define BIT9            0x00000200
  72 #define BIT10           0x00000400
  73 #define BIT11           0x00000800
  74 #define BIT12           0x00001000
  75 #define BIT13           0x00002000
  76 #define BIT14           0x00004000
  77 #define BIT15           0x00008000
  78 #define BIT16           0x00010000
  79 #define BIT17           0x00020000
  80 #define BIT18           0x00040000
  81 #define BIT19           0x00080000
  82 #define BIT20           0x00100000
  83 #define BIT21           0x00200000
  84 #define BIT22           0x00400000
  85 #define BIT23           0x00800000
  86 #define BIT24           0x01000000
  87 #define BIT25           0x02000000
  88 #define BIT26           0x04000000
  89 #define BIT27           0x08000000
  90 #define BIT28           0x10000000
  91 #define BIT29           0x20000000
  92 #define BIT30           0x40000000
  93 #define BIT31           0x80000000
  94
  95 // Rx smooth factor
  96 #define Rx_Smooth_Factor                20
  97 #define DMESG(x,a...)
  98 #define DMESGW(x,a...)
  99 #define DMESGE(x,a...)
 100 extern u32 rt_global_debug_component;
 101 #define RT_TRACE(component, x, args...) \
 102 do { if(rt_global_debug_component & component) \
 103         printk(KERN_DEBUG RTL819xU_MODULE_NAME ":" x "\n" , \
 104                ##args);\
 105 }while(0);
 106 //----------------------------------------------------------------------
 107 //// Get 8192SU  Rx descriptor. Added by Roger, 2008.04.15.
 108 ////----------------------------------------------------------------------
 109 #define RX_DESC_SIZE 24
 110 #define RX_DRV_INFO_SIZE_UNIT   8
 111
 112 #define IS_UNDER_11N_AES_MODE(_ieee)  ((_ieee->pHTInfo->bCurrentHTSupport==TRUE) &&\
 113                                                                         (_ieee->pairwise_key_type==KEY_TYPE_CCMP))
 114
 115 #define COMP_TRACE                              BIT0            // For function call tracing.
 116 #define COMP_DBG                                BIT1            // Only for temporary debug message.
 117 #define COMP_INIT                               BIT2            // during driver initialization / halt / reset.
 118
 119
 120 #define COMP_RECV                               BIT3            // Reveive part data path.
 121 #define COMP_SEND                               BIT4            // Send part path.
 122 #define COMP_IO                                 BIT5            // I/O Related. Added by Annie, 2006-03-02.
 123 #define COMP_POWER                              BIT6            // 802.11 Power Save mode or System/Device Power state related.
 124 #define COMP_EPROM                              BIT7            // 802.11 link related: join/start BSS, leave BSS.
 125 #define COMP_SWBW                               BIT8    // For bandwidth switch.
 126 #define COMP_POWER_TRACKING                     BIT9    //FOR 8190 TX POWER TRACKING
 127 #define COMP_TURBO                              BIT10   // For Turbo Mode related. By Annie, 2005-10-21.
 128 #define COMP_QOS                                BIT11   // For QoS.
 129 #define COMP_RATE                               BIT12   // For Rate Adaptive mechanism, 2006.07.02, by rcnjko.
 130 #define COMP_LPS                                        BIT13   // For Radio Measurement.
 131 #define COMP_DIG                                BIT14   // For DIG, 2006.09.25, by rcnjko.
 132 #define COMP_PHY                                BIT15
 133 #define COMP_CH                                 BIT16   //channel setting debug
 134 #define COMP_TXAGC                              BIT17   // For Tx power, 060928, by rcnjko.
 135 #define COMP_HIPWR                              BIT18   // For High Power Mechanism, 060928, by rcnjko.
 136 #define COMP_HALDM                              BIT19   // For HW Dynamic Mechanism, 061010, by rcnjko.
 137 #define COMP_SEC                                BIT20   // Event handling
 138 #define COMP_LED                                BIT21   // For LED.
 139 #define COMP_RF                                 BIT22   // For RF.
 140 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
 141 #define COMP_RXDESC                             BIT23   // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
 142 //1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
 143 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
 144
 145 #define COMP_FIRMWARE                           BIT24   //for firmware downloading
 146 #define COMP_HT                                 BIT25   // For 802.11n HT related information. by Emily 2006-8-11
 147 #define COMP_AMSDU                              BIT26   // For A-MSDU Debugging
 148
 149 #define COMP_SCAN                               BIT27
 150 #define COMP_CMD                                BIT28
 151 #define COMP_DOWN                               BIT29  //for rm driver module
 152 #define COMP_RESET                              BIT30  //for silent reset
 153 #define COMP_ERR                                BIT31 //for error out, always on
 154
 155 #define RTL819x_DEBUG
 156 #ifdef RTL819x_DEBUG
 157 #define assert(expr) \
 158         if (!(expr)) {                                  \
 159                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
 160                 #expr,__FILE__,__FUNCTION__,__LINE__);          \
 161         }
 162 //wb added to debug out data buf
 163 //if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA
 164 #define RT_DEBUG_DATA(level, data, datalen)      \
 165         do{ if ((rt_global_debug_component & (level)) == (level))   \
 166                 {       \
 167                         int i;                                  \
 168                         u8* pdata = (u8*) data;                 \
 169                         printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__);   \
 170                         for(i=0; i<(int)(datalen); i++)                 \
 171                         {                                               \
 172                                 printk("%2x ", pdata[i]);               \
 173                                 if ((i+1)%16 == 0) printk("\n");        \
 174                         }                               \
 175                         printk("\n");                   \
 176                 }                                       \
 177         } while (0)
 178 #else
 179 #define assert(expr) do {} while (0)
 180 #define RT_DEBUG_DATA(level, data, datalen) do {} while(0)
 181 #endif /* RTL8169_DEBUG */
 182
 183 //#ifdef RTL8192SU
 184         //2TODO: We should define 8192S firmware related macro settings here!!
 185         #define RTL819X_DEFAULT_RF_TYPE                         RF_1T2R
 186         #define RTL819X_TOTAL_RF_PATH                           2
 187
 188         //#define Rtl819XFwBootArray                                    Rtl8192UsbFwBootArray
 189         //#define Rtl819XFwMainArray                                    Rtl8192UsbFwMainArray
 190         //#define Rtl819XFwDataArray                                    Rtl8192UsbFwDataArray
 191
 192         #define Rtl819XMACPHY_Array_PG                          Rtl8192UsbMACPHY_Array_PG
 193         #define Rtl819XMACPHY_Array                                     Rtl8192UsbMACPHY_Array
 194         #define Rtl819XPHY_REGArray                                     Rtl8192UsbPHY_REGArray
 195         #define Rtl819XPHY_REG_1T2RArray                                Rtl8192UsbPHY_REG_1T2RArray
 196         //#define Rtl819XRadioA_Array                                   Rtl8192UsbRadioA_Array
 197         //#define Rtl819XRadioB_Array                                   Rtl8192UsbRadioB_Array
 198         #define Rtl819XRadioC_Array                                     Rtl8192UsbRadioC_Array
 199         #define Rtl819XRadioD_Array                                     Rtl8192UsbRadioD_Array
 200
 201         //2008.11.06 Add.
 202         #define Rtl819XFwImageArray                                     Rtl8192SUFwImgArray
 203         #define Rtl819XMAC_Array                                                Rtl8192SUMAC_2T_Array
 204         #define Rtl819XAGCTAB_Array                                     Rtl8192SUAGCTAB_Array
 205         #define Rtl819XPHY_REG_Array                                    Rtl8192SUPHY_REG_2T2RArray
 206         #define Rtl819XPHY_REG_to1T1R_Array                     Rtl8192SUPHY_ChangeTo_1T1RArray
 207         #define Rtl819XPHY_REG_to1T2R_Array                     Rtl8192SUPHY_ChangeTo_1T2RArray
 208         #define Rtl819XPHY_REG_to2T2R_Array                     Rtl8192SUPHY_ChangeTo_2T2RArray
 209         #define Rtl819XPHY_REG_Array_PG                         Rtl8192SUPHY_REG_Array_PG
 210         #define Rtl819XRadioA_Array                                     Rtl8192SURadioA_1T_Array
 211         #define Rtl819XRadioB_Array                                     Rtl8192SURadioB_Array
 212         #define Rtl819XRadioB_GM_Array                          Rtl8192SURadioB_GM_Array
 213         #define Rtl819XRadioA_to1T_Array                                Rtl8192SURadioA_to1T_Array
 214         #define Rtl819XRadioA_to2T_Array                                Rtl8192SURadioA_to2T_Array
 215 //#endif
 216
 217 //
 218 // Queue Select Value in TxDesc
 219 //
 220 #define QSLT_BK                                 0x1
 221 #define QSLT_BE                                 0x0
 222 #define QSLT_VI                                 0x4
 223 #define QSLT_VO                                 0x6
 224 #define QSLT_BEACON                             0x10
 225 #define QSLT_HIGH                               0x11
 226 #define QSLT_MGNT                               0x12
 227 #define QSLT_CMD                                0x13
 228
 229 #define DESC90_RATE1M                           0x00
 230 #define DESC90_RATE2M                           0x01
 231 #define DESC90_RATE5_5M                         0x02
 232 #define DESC90_RATE11M                          0x03
 233 #define DESC90_RATE6M                           0x04
 234 #define DESC90_RATE9M                           0x05
 235 #define DESC90_RATE12M                          0x06
 236 #define DESC90_RATE18M                          0x07
 237 #define DESC90_RATE24M                          0x08
 238 #define DESC90_RATE36M                          0x09
 239 #define DESC90_RATE48M                          0x0a
 240 #define DESC90_RATE54M                          0x0b
 241 #define DESC90_RATEMCS0                         0x00
 242 #define DESC90_RATEMCS1                         0x01
 243 #define DESC90_RATEMCS2                         0x02
 244 #define DESC90_RATEMCS3                         0x03
 245 #define DESC90_RATEMCS4                         0x04
 246 #define DESC90_RATEMCS5                         0x05
 247 #define DESC90_RATEMCS6                         0x06
 248 #define DESC90_RATEMCS7                         0x07
 249 #define DESC90_RATEMCS8                         0x08
 250 #define DESC90_RATEMCS9                         0x09
 251 #define DESC90_RATEMCS10                        0x0a
 252 #define DESC90_RATEMCS11                        0x0b
 253 #define DESC90_RATEMCS12                        0x0c
 254 #define DESC90_RATEMCS13                        0x0d
 255 #define DESC90_RATEMCS14                        0x0e
 256 #define DESC90_RATEMCS15                        0x0f
 257 #define DESC90_RATEMCS32                        0x20
 258
 259 //#ifdef RTL8192SU
 260 // CCK Rates, TxHT = 0
 261 #define DESC92S_RATE1M                                  0x00
 262 #define DESC92S_RATE2M                                  0x01
 263 #define DESC92S_RATE5_5M                                0x02
 264 #define DESC92S_RATE11M                                 0x03
 265
 266 // OFDM Rates, TxHT = 0
 267 #define DESC92S_RATE6M                                  0x04
 268 #define DESC92S_RATE9M                                  0x05
 269 #define DESC92S_RATE12M                                 0x06
 270 #define DESC92S_RATE18M                                 0x07
 271 #define DESC92S_RATE24M                                 0x08
 272 #define DESC92S_RATE36M                                 0x09
 273 #define DESC92S_RATE48M                                 0x0a
 274 #define DESC92S_RATE54M                                 0x0b
 275
 276 // MCS Rates, TxHT = 1
 277 #define DESC92S_RATEMCS0                                0x0c
 278 #define DESC92S_RATEMCS1                                0x0d
 279 #define DESC92S_RATEMCS2                                0x0e
 280 #define DESC92S_RATEMCS3                                0x0f
 281 #define DESC92S_RATEMCS4                                0x10
 282 #define DESC92S_RATEMCS5                                0x11
 283 #define DESC92S_RATEMCS6                                0x12
 284 #define DESC92S_RATEMCS7                                0x13
 285 #define DESC92S_RATEMCS8                                0x14
 286 #define DESC92S_RATEMCS9                                0x15
 287 #define DESC92S_RATEMCS10                               0x16
 288 #define DESC92S_RATEMCS11                               0x17
 289 #define DESC92S_RATEMCS12                               0x18
 290 #define DESC92S_RATEMCS13                               0x19
 291 #define DESC92S_RATEMCS14                               0x1a
 292 #define DESC92S_RATEMCS15                               0x1b
 293 #define DESC92S_RATEMCS15_SG                    0x1c
 294 #define DESC92S_RATEMCS32                               0x20
 295 //#endif
 296
 297 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
 298
 299 #define IEEE80211_WATCH_DOG_TIME    2000
 300 #define         PHY_Beacon_RSSI_SLID_WIN_MAX            10
 301 //for txpowertracking by amy
 302 #define         OFDM_Table_Length       19
 303 #define CCK_Table_length        12
 304
 305 //
 306 //Tx Descriptor for RLT8192SU(Normal mode)
 307 //
 308 typedef struct _tx_desc_819x_usb {
 309         // DWORD 0
 310         u16             PktSize;//:16;
 311         u8              Offset;//:8;
 312         u8              Type:2; // Reserved for MAC header Frame Type subfield.
 313         u8              LastSeg:1;
 314         u8              FirstSeg:1;
 315         u8              LINIP:1;
 316         u8              AMSDU:1;
 317         u8              GF:1;
 318         u8              OWN:1;
 319
 320         // DWORD 1
 321         u8              MacID:5;
 322         u8              MoreData:1;
 323         u8              MOREFRAG:1;
 324         u8              PIFS:1;
 325         u8              QueueSelect:5;
 326         u8              AckPolicy:2;
 327         u8              NoACM:1;
 328         u8              NonQos:1;
 329         u8              KeyID:2;
 330         u8              OUI:1;
 331         u8              PktType:1;
 332         u8              EnDescID:1;
 333         u8              SecType:2;
 334         u8              HTC:1;  //padding0
 335         u8              WDS:1;  //padding1
 336         u8              PktOffset:5;    //padding_len (hw)
 337         u8              HWPC:1;
 338
 339         // DWORD 2
 340         u32             DataRetryLmt:6;
 341         u32             RetryLmtEn:1;
 342         u32             TSFL:5;
 343         u32             RTSRC:6;        // Reserved for HW RTS Retry Count.
 344         u32             DATARC:6;       // Reserved for HW DATA Retry Count.
 345         u32             Rsvd1:5;
 346         u32             AllowAggregation:1;
 347         u32             BK:1;   //Aggregation break.
 348         u32             OwnMAC:1;
 349
 350         // DWORD 3
 351         u8              NextHeadPage;//:8;
 352         u8              TailPage;//:8;
 353         u16             Seq:12;
 354         u16             Frag:4;
 355
 356         // DWORD 4
 357         u32             RTSRate:6;
 358         u32             DisRTSFB:1;
 359         u32             RTSRateFBLmt:4;
 360         u32             CTS2Self:1;
 361         u32             RTSEn:1;
 362         u32             RaBRSRID:3;     //Rate adaptive BRSR ID.
 363         u32             TxHT:1;
 364         u32             TxShort:1;//for data
 365         u32             TxBandwidth:1;
 366         u32             TxSubCarrier:2;
 367         u32             STBC:2;
 368         u32             RD:1;
 369         u32             RTSHT:1;
 370         u32             RTSShort:1;
 371         u32             RTSBW:1;
 372         u32             RTSSubcarrier:2;
 373         u32             RTSSTBC:2;
 374         u32             USERATE:1;
 375         // DWORD 5
 376         u32             PktID:9;
 377         u32             TxRate:6;
 378         u32             DISFB:1;
 379         u32             DataRateFBLmt:5;
 380         u32             TxAGC:11;
 381
 382         // DWORD 6
 383         u16             IPChkSum;//:16;
 384         u16             TCPChkSum;//:16;
 385
 386         // DWORD 7
 387         //u16           TxBuffSize;//:16;//pcie
 388         u16             TxBufferSize;
 389         u16             IPHdrOffset:8;
 390         u16             Rsvd2:7;
 391         u16             TCPEn:1;
 392 }tx_desc_819x_usb, *ptx_desc_819x_usb;
 393 typedef struct _tx_status_desc_8192s_usb{
 394
 395         //DWORD 0
 396         u8              TxRate:6;
 397         u8              Rsvd1:1;
 398         u8              BandWidth:1;
 399         u8              RTSRate:6;
 400         u8              AGGLS:1;
 401         u8              AGG:1;
 402         u8              RTSRC:6;
 403         u8              DataRC:6;
 404         u8              FailCause:2;
 405         u8              TxOK:1;
 406         u8              Own:1;
 407
 408         //DWORD 1
 409         u16             Seq:12;
 410         u8              QueueSel:5;
 411         u8              MACID:5;
 412         u8              PwrMgt:1;
 413         u8              MoreData:1;
 414         u8              Rsvd2;
 415
 416         //DWORD 2
 417         u8              RxAGC1;
 418         u8              RxAGC2;
 419         u8              RxAGC3;
 420         u8              RxAGC4;
 421 }tx_status_desc_8192s_usb, *ptx_status_desc_8192s_usb;
 422
 423
 424
 425 //
 426 //Tx Descriptor for RLT8192SU(Load FW mode)
 427 //
 428 typedef struct _tx_desc_cmd_819x_usb{
 429        // DWORD 0
 430         u16             PktSize;
 431         u8              Offset;
 432         u8              Rsvd0:4;
 433         u8              LINIP:1;
 434         u8              Rsvd1:2;
 435         u8              OWN:1;
 436
 437         // DWORD 1, 2, 3, 4, 5, 6 are all reserved.
 438         u32             Rsvd2;
 439         u32             Rsvd3;
 440         u32             Rsvd4;
 441         u32             Rsvd5;
 442         u32             Rsvd6;
 443         u32             Rsvd7;
 444
 445         // DWORD 7
 446         u16             TxBuffSize;//pcie
 447         u16             Rsvd8;
 448 }tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
 449 //
 450 //H2C Command for RLT8192SU(Host TxCmd)
 451 //
 452 typedef struct _tx_h2c_desc_cmd_8192s_usb{
 453        // DWORD 0
 454         u32             PktSize:16;
 455         u32             Offset:8;
 456         u32             Rsvd0:7;
 457         u32             OWN:1;
 458
 459         // DWORD 1
 460         u32             Rsvd1:8;
 461         u32             QSEL:5;
 462         u32             Rsvd2:19;
 463
 464         // DWORD 2
 465         u32             Rsvd3;
 466
 467         // DWORD 3
 468         u32             NextHeadPage:8;
 469         u32             TailPage:8;
 470         u32             Rsvd4:16;
 471
 472         // DWORD 4, 5, 6, 7
 473         u32             Rsvd5;
 474         u32             Rsvd6;
 475         u32             Rsvd7;
 476         u32             Rsvd8;
 477 }tx_h2c_desc_cmd_8192s_usb, *ptx_h2c_desc_cmd_8192s_usb;
 478
 479
 480 typedef struct _tx_h2c_cmd_hdr_8192s_usb{
 481        // DWORD 0
 482         u32             CmdLen:16;
 483         u32             ElementID:8;
 484         u32             CmdSeq:8;
 485
 486         // DWORD 1
 487         u32             Rsvd0;
 488 }tx_h2c_cmd_hdr_8192s_usb, *ptx_h2c_cmd_hdr_8192s_usb;
 489
 490 typedef struct _tx_fwinfo_819x_usb{
 491         //DWORD 0
 492         u8                      TxRate:7;
 493         u8                      CtsEnable:1;
 494         u8                      RtsRate:7;
 495         u8                      RtsEnable:1;
 496         u8                      TxHT:1;
 497         u8                      Short:1;                                                //Short PLCP for CCK, or short GI for 11n MCS
 498         u8                      TxBandwidth:1;                          // This is used for HT MCS rate only.
 499         u8                      TxSubCarrier:2;                         // This is used for legacy OFDM rate only.
 500         u8                      STBC:2;
 501         u8                      AllowAggregation:1;
 502         u8                      RtsHT:1;                                                //Interpre RtsRate field as high throughput data rate
 503         u8                      RtsShort:1;                                     //Short PLCP for CCK, or short GI for 11n MCS
 504         u8                      RtsBandwidth:1;                         // This is used for HT MCS rate only.
 505         u8                      RtsSubcarrier:2;                                // This is used for legacy OFDM rate only.
 506         u8                      RtsSTBC:2;
 507         u8                      EnableCPUDur:1;                         //Enable firmware to recalculate and assign packet duration
 508
 509         //DWORD 1
 510         u32                     RxMF:2;
 511         u32                     RxAMD:3;
 512         u32                     Reserved1:3;
 513         u32                     TxAGCOffSet:4;//TxAGCOffset:4;
 514         u32                     TxAGCSign:1;
 515         u32                     Tx_INFO_RSVD:6;
 516         u32                     PacketID:13;
 517 }tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
 518
 519 typedef struct rtl8192_rx_info {
 520         struct urb *urb;
 521         struct net_device *dev;
 522         u8 out_pipe;
 523 }rtl8192_rx_info ;
 524
 525 //typedef struct _RX_DESC_STATUS_8192SU{
 526 typedef struct rx_desc_819x_usb{
 527         //DWORD 0
 528         u16             Length:14;
 529         u16             CRC32:1;
 530         u16             ICV:1;
 531         u8              RxDrvInfoSize:4;
 532         u8              Security:3;
 533         u8              Qos:1;
 534         u8              Shift:2;
 535         u8              PHYStatus:1;
 536         u8              SWDec:1;
 537         u8              LastSeg:1;
 538         u8              FirstSeg:1;
 539         u8              EOR:1;
 540         u8              Own:1;
 541
 542         //DWORD 1
 543         u16             MACID:5;
 544         u16             TID:4;
 545         u16             HwRsvd:5;
 546         u16             PAGGR:1;
 547         u16             FAGGR:1;
 548         u8              A1_FIT:4;
 549         u8              A2_FIT:4;
 550         u8              PAM:1;
 551         u8              PWR:1;
 552         u8              MoreData:1;
 553         u8              MoreFrag:1;
 554         u8              Type:2;
 555         u8              MC:1;
 556         u8              BC:1;
 557
 558         //DWORD 2
 559         u16             Seq:12;
 560         u16             Frag:4;
 561         u8              NextPktLen;//:8;
 562         u8              Rsvd0:6;
 563         u8              NextIND:1;
 564         u8              Rsvd1:1;
 565
 566         //DWORD 3
 567         u8              RxMCS:6;
 568         u8              RxHT:1;
 569         u8              AMSDU:1;
 570         u8              SPLCP:1;
 571         u8              BW:1;
 572         u8              HTC:1;
 573         u8              TCPChkRpt:1;
 574         u8              IPChkRpt:1;
 575         u8              TCPChkValID:1;
 576         u8              HwPCErr:1;
 577         u8              HwPCInd:1;
 578         u16             IV0;//:16;
 579
 580         //DWORD 4
 581         u32             IV1;
 582
 583         //DWORD 5
 584         u32             TSFL;
 585 //}RX_DESC_STATUS_8192SU, *PRX_DESC_STATUS_8192SU;
 586 }rx_desc_819x_usb, *prx_desc_819x_usb;
 587
 588
 589 //
 590 // Driver info are written to the begining of the RxBuffer
 591 //
 592 //typedef struct _RX_DRIVER_INFO_8192S{
 593 typedef struct rx_drvinfo_819x_usb{
 594         //
 595         // Driver info contain PHY status and other variabel size info
 596         // PHY Status content as below
 597         //
 598
 599         //DWORD 0
 600         /*u4Byte                        gain_0:7;
 601         u4Byte                  trsw_0:1;
 602         u4Byte                  gain_1:7;
 603         u4Byte                  trsw_1:1;
 604         u4Byte                  gain_2:7;
 605         u4Byte                  trsw_2:1;
 606         u4Byte                  gain_3:7;
 607         u4Byte                  trsw_3:1;       */
 608         u8                      gain_trsw[4];
 609
 610         //DWORD 1
 611         /*u4Byte                        pwdb_all:8;
 612         u4Byte                  cfosho_0:8;
 613         u4Byte                  cfosho_1:8;
 614         u4Byte                  cfosho_2:8;*/
 615         u8                      pwdb_all;
 616         u8                      cfosho[4];
 617
 618         //DWORD 2
 619         /*u4Byte                        cfosho_3:8;
 620         u4Byte                  cfotail_0:8;
 621         u4Byte                  cfotail_1:8;
 622         u4Byte                  cfotail_2:8;*/
 623         u8                      cfotail[4];
 624
 625         //DWORD 3
 626         /*u4Byte                        cfotail_3:8;
 627         u4Byte                  rxevm_0:8;
 628         u4Byte                  rxevm_1:8;
 629         u4Byte                  rxsnr_0:8;*/
 630         char                            rxevm[2];
 631         char                            rxsnr[4];
 632
 633         //DWORD 4
 634         /*u4Byte                        rxsnr_1:8;
 635         u4Byte                  rxsnr_2:8;
 636         u4Byte                  rxsnr_3:8;
 637         u4Byte                  pdsnr_0:8;*/
 638         u8                      pdsnr[2];
 639
 640         //DWORD 5
 641         /*u4Byte                        pdsnr_1:8;
 642         u4Byte                  csi_current_0:8;
 643         u4Byte                  csi_current_1:8;
 644         u4Byte                  csi_target_0:8;*/
 645         u8                      csi_current[2];
 646         u8                      csi_target[2];
 647
 648         //DWORD 6
 649         /*u4Byte                        csi_target_1:8;
 650         u4Byte                  sigevm:8;
 651         u4Byte                  max_ex_pwr:8;
 652         u4Byte                  ex_intf_flag:1;
 653         u4Byte                  sgi_en:1;
 654         u4Byte                  rxsc:2;
 655         u4Byte                  reserve:4;*/
 656         u8                      sigevm;
 657         u8                      max_ex_pwr;
 658         u8                      ex_intf_flag:1;
 659         u8                      sgi_en:1;
 660         u8                      rxsc:2;
 661         u8                      reserve:4;
 662
 663 }rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
 664
 665         #define HWSET_MAX_SIZE_92S      128
 666         #define MAX_802_11_HEADER_LENGTH 40
 667         #define MAX_PKT_AGG_NUM         256
 668         #define TX_PACKET_SHIFT_BYTES USB_HWDESC_HEADER_LEN
 669
 670 #define MAX_DEV_ADDR_SIZE               8  /* support till 64 bit bus width OS */
 671 #define MAX_FIRMWARE_INFORMATION_SIZE   32 /*2006/04/30 by Emily forRTL8190*/
 672 //#define MAX_802_11_HEADER_LENGTH        (40 + MAX_FIRMWARE_INFORMATION_SIZE)
 673 #define ENCRYPTION_MAX_OVERHEAD         128
 674 #define USB_HWDESC_HEADER_LEN           sizeof(tx_desc_819x_usb)
 675 //#define TX_PACKET_SHIFT_BYTES                 (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
 676 #define MAX_FRAGMENT_COUNT              8
 677 #ifdef RTL8192U
 678 #define MAX_TRANSMIT_BUFFER_SIZE                        8000
 679 #else
 680 #define MAX_TRANSMIT_BUFFER_SIZE        (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
 681 #endif
 682 #define scrclng                                 4               // octets for crc32 (FCS, ICV)
 683
 684 typedef enum rf_optype
 685 {
 686         RF_OP_By_SW_3wire = 0,
 687         RF_OP_By_FW,
 688         RF_OP_MAX
 689 }rf_op_type;
 690 /* 8190 Loopback Mode definition */
 691 typedef enum _rtl819xUsb_loopback{
 692         RTL819xU_NO_LOOPBACK = 0,
 693         RTL819xU_MAC_LOOPBACK = 1,
 694         RTL819xU_DMA_LOOPBACK = 2,
 695         RTL819xU_CCK_LOOPBACK = 3,
 696 }rtl819xUsb_loopback_e;
 697
 698 /* for rtl819x */
 699 typedef enum _RT_STATUS{
 700         RT_STATUS_SUCCESS = 0,
 701         RT_STATUS_FAILURE = 1,
 702         RT_STATUS_PENDING = 2,
 703         RT_STATUS_RESOURCE = 3
 704 }RT_STATUS,*PRT_STATUS;
 705
 706 //#ifdef RTL8192SU
 707 typedef enum _RTL8192SUSB_LOOPBACK{
 708         RTL8192SU_NO_LOOPBACK = 0,
 709         RTL8192SU_MAC_LOOPBACK = 1,
 710         RTL8192SU_DMA_LOOPBACK = 2,
 711         RTL8192SU_CCK_LOOPBACK = 3,
 712 }RTL8192SUSB_LOOPBACK_E;
 713 //#endif
 714
 715 //+by amy 080507
 716 #define MAX_RECEIVE_BUFFER_SIZE 9100    // Add this to 9100 bytes to receive A-MSDU from RT-AP
 717
 718
 719 /* Firmware Queue Layout */
 720 #define NUM_OF_FIRMWARE_QUEUE           10
 721 #define NUM_OF_PAGES_IN_FW              0x100
 722
 723
 724 #define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x020
 725 #define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x020
 726 #define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x040
 727 #define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x040
 728 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 729 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x4
 730 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x20
 731 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 732 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x4
 733 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x18
 734
 735
 736 #define APPLIED_RESERVED_QUEUE_IN_FW    0x80000000
 737 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT     0x00
 738 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT     0x08
 739 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT     0x10
 740 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT     0x18
 741 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT   0x10
 742 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT    0x08
 743 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT    0x00
 744 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT    0x08
 745
 746 #define DEFAULT_FRAG_THRESHOLD 2342U
 747 #define MIN_FRAG_THRESHOLD     256U
 748 #define DEFAULT_BEACONINTERVAL 0x64U
 749 #define DEFAULT_BEACON_ESSID "Rtl819xU"
 750
 751 #define DEFAULT_SSID ""
 752 #define DEFAULT_RETRY_RTS 7
 753 #define DEFAULT_RETRY_DATA 7
 754 #define PRISM_HDR_SIZE 64
 755
 756 #define         PHY_RSSI_SLID_WIN_MAX                           100
 757
 758
 759 typedef enum _WIRELESS_MODE {
 760         WIRELESS_MODE_UNKNOWN = 0x00,
 761         WIRELESS_MODE_A = 0x01,
 762         WIRELESS_MODE_B = 0x02,
 763         WIRELESS_MODE_G = 0x04,
 764         WIRELESS_MODE_AUTO = 0x08,
 765         WIRELESS_MODE_N_24G = 0x10,
 766         WIRELESS_MODE_N_5G = 0x20
 767 } WIRELESS_MODE;
 768
 769
 770 #define RTL_IOCTL_WPA_SUPPLICANT                SIOCIWFIRSTPRIV+30
 771
 772 typedef struct buffer
 773 {
 774         struct buffer *next;
 775         u32 *buf;
 776
 777 } buffer;
 778
 779 typedef struct rtl_reg_debug{
 780         unsigned int  cmd;
 781         struct {
 782                 unsigned char type;
 783                 unsigned char addr;
 784                 unsigned char page;
 785                 unsigned char length;
 786         } head;
 787         unsigned char buf[0xff];
 788 }rtl_reg_debug;
 789
 790 typedef struct _rt_9x_tx_rate_history {
 791         u32             cck[4];
 792         u32             ofdm[8];
 793         // HT_MCS[0][]: BW=0 SG=0
 794         // HT_MCS[1][]: BW=1 SG=0
 795         // HT_MCS[2][]: BW=0 SG=1
 796         // HT_MCS[3][]: BW=1 SG=1
 797         u32             ht_mcs[4][16];
 798 }rt_tx_rahis_t, *prt_tx_rahis_t;
 799 typedef struct _RT_SMOOTH_DATA_4RF {
 800         char    elements[4][100];//array to store values
 801         u32     index;                  //index to current array to store
 802         u32     TotalNum;               //num of valid elements
 803         u32     TotalVal[4];            //sum of valid elements
 804 }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
 805
 806 #define MAX_8192U_RX_SIZE                       8192    // This maybe changed for D-cut larger aggregation size
 807 //stats seems messed up, clean it ASAP
 808 typedef struct Stats
 809 {
 810         unsigned long txrdu;
 811 //      unsigned long rxrdu;
 812         //unsigned long rxnolast;
 813         //unsigned long rxnodata;
 814 //      unsigned long rxreset;
 815 //      unsigned long rxnopointer;
 816         unsigned long rxok;
 817         unsigned long rxframgment;
 818         unsigned long rxcmdpkt[4];              //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query
 819         unsigned long rxurberr;
 820         unsigned long rxstaterr;
 821         unsigned long received_rate_histogram[4][32];   //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa
 822         unsigned long received_preamble_GI[2][32];              //0: Long preamble/GI, 1:Short preamble/GI
 823         unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K)
 824         unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40)
 825         unsigned long numpacket_matchbssid;     // debug use only.
 826         unsigned long numpacket_toself;         // debug use only.
 827         unsigned long num_process_phyinfo;              // debug use only.
 828         unsigned long numqry_phystatus;
 829         unsigned long numqry_phystatusCCK;
 830         unsigned long numqry_phystatusHT;
 831         unsigned long received_bwtype[5];              //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate
 832         unsigned long txnperr;
 833         unsigned long txnpdrop;
 834         unsigned long txresumed;
 835 //      unsigned long rxerr;
 836 //      unsigned long rxoverflow;
 837 //      unsigned long rxint;
 838         unsigned long txnpokint;
 839 //      unsigned long txhpokint;
 840 //      unsigned long txhperr;
 841 //      unsigned long ints;
 842 //      unsigned long shints;
 843         unsigned long txoverflow;
 844 //      unsigned long rxdmafail;
 845 //      unsigned long txbeacon;
 846 //      unsigned long txbeaconerr;
 847         unsigned long txlpokint;
 848         unsigned long txlpdrop;
 849         unsigned long txlperr;
 850         unsigned long txbeokint;
 851         unsigned long txbedrop;
 852         unsigned long txbeerr;
 853         unsigned long txbkokint;
 854         unsigned long txbkdrop;
 855         unsigned long txbkerr;
 856         unsigned long txviokint;
 857         unsigned long txvidrop;
 858         unsigned long txvierr;
 859         unsigned long txvookint;
 860         unsigned long txvodrop;
 861         unsigned long txvoerr;
 862         unsigned long txbeaconokint;
 863         unsigned long txbeacondrop;
 864         unsigned long txbeaconerr;
 865         unsigned long txmanageokint;
 866         unsigned long txmanagedrop;
 867         unsigned long txmanageerr;
 868         unsigned long txdatapkt;
 869         unsigned long txfeedback;
 870         unsigned long txfeedbackok;
 871
 872         unsigned long txoktotal;
 873         unsigned long txokbytestotal;
 874         unsigned long txokinperiod;
 875         unsigned long txmulticast;
 876         unsigned long txbytesmulticast;
 877         unsigned long txbroadcast;
 878         unsigned long txbytesbroadcast;
 879         unsigned long txunicast;
 880         unsigned long txbytesunicast;
 881
 882         unsigned long rxoktotal;
 883         unsigned long rxbytesunicast;
 884         unsigned long txfeedbackfail;
 885         unsigned long txerrtotal;
 886         unsigned long txerrbytestotal;
 887         unsigned long txerrmulticast;
 888         unsigned long txerrbroadcast;
 889         unsigned long txerrunicast;
 890         unsigned long txretrycount;
 891         unsigned long txfeedbackretry;
 892         u8            last_packet_rate;
 893         unsigned long slide_signal_strength[100];
 894         unsigned long slide_evm[100];
 895         unsigned long slide_rssi_total; // For recording sliding window's RSSI value
 896         unsigned long slide_evm_total;  // For recording sliding window's EVM value
 897         long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
 898         long signal_quality;
 899         long last_signal_strength_inpercent;
 900         long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now.
 901         u8 rx_rssi_percentage[4];
 902         u8 rx_evm_percentage[2];
 903         long rxSNRdB[4];
 904         rt_tx_rahis_t txrate;
 905         u32 Slide_Beacon_pwdb[100];     //cosa add for beacon rssi
 906         u32 Slide_Beacon_Total;         //cosa add for beacon rssi
 907         RT_SMOOTH_DATA_4RF              cck_adc_pwdb;
 908
 909         u32     CurrentShowTxate;
 910 } Stats;
 911
 912
 913 // Bandwidth Offset
 914 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
 915 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
 916 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
 917
 918 //+by amy 080507
 919
 920 typedef struct  ChnlAccessSetting {
 921         u16 SIFS_Timer;
 922         u16 DIFS_Timer;
 923         u16 SlotTimeTimer;
 924         u16 EIFS_Timer;
 925         u16 CWminIndex;
 926         u16 CWmaxIndex;
 927 }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
 928
 929 typedef struct _BB_REGISTER_DEFINITION{
 930         u32 rfintfs;                    // set software control: //             0x870~0x877[8 bytes]
 931         u32 rfintfi;                    // readback data: //            0x8e0~0x8e7[8 bytes]
 932         u32 rfintfo;                    // output data: //              0x860~0x86f [16 bytes]
 933         u32 rfintfe;                    // output enable: //            0x860~0x86f [16 bytes]
 934         u32 rf3wireOffset;              // LSSI data: //                0x840~0x84f [16 bytes]
 935         u32 rfLSSI_Select;              // BB Band Select: //           0x878~0x87f [8 bytes]
 936         u32 rfTxGainStage;              // Tx gain stage: //            0x80c~0x80f [4 bytes]
 937         u32 rfHSSIPara1;                // wire parameter control1 : //         0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
 938         u32 rfHSSIPara2;                // wire parameter control2 : //         0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
 939         u32 rfSwitchControl;    //Tx Rx antenna control : //            0x858~0x85f [16 bytes]
 940         u32 rfAGCControl1;      //AGC parameter control1 : //           0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
 941         u32 rfAGCControl2;      //AGC parameter control2 : //           0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
 942         u32 rfRxIQImbalance;    //OFDM Rx IQ imbalance matrix : //              0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
 943         u32 rfRxAFE;                    //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : //         0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
 944         u32 rfTxIQImbalance;    //OFDM Tx IQ imbalance matrix //                0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
 945         u32 rfTxAFE;                    //Tx IQ DC Offset and Tx DFIR type //           0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
 946         u32 rfLSSIReadBack;     //LSSI RF readback data //              0x8a0~0x8af [16 bytes]
 947         u32 rfLSSIReadBackPi;   //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
 948 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
 949
 950 typedef enum _RT_RF_TYPE_819xU{
 951         RF_TYPE_MIN = 0,
 952         RF_8225,
 953         RF_8256,
 954         RF_8258,
 955         RF_6052=4,              // 4 11b/g/n RF
 956         RF_PSEUDO_11N = 5,
 957 }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
 958
 959 //#ifdef RTL8192SU
 960 typedef enum _RF_POWER_STATE{
 961         RF_ON,
 962         RF_SLEEP,
 963         RF_OFF,
 964         RF_SHUT_DOWN,
 965 }RF_POWER_STATE, *PRF_POWER_STATE;
 966 //#endif
 967
 968 typedef struct _rate_adaptive
 969 {
 970         u8                              rate_adaptive_disabled;
 971         u8                              ratr_state;
 972         u16                             reserve;
 973
 974         u32                             high_rssi_thresh_for_ra;
 975         u32                             high2low_rssi_thresh_for_ra;
 976         u8                              low2high_rssi_thresh_for_ra40M;
 977         u32                             low_rssi_thresh_for_ra40M;
 978         u8                              low2high_rssi_thresh_for_ra20M;
 979         u32                             low_rssi_thresh_for_ra20M;
 980         u32                             upper_rssi_threshold_ratr;
 981         u32                             middle_rssi_threshold_ratr;
 982         u32                             low_rssi_threshold_ratr;
 983         u32                             low_rssi_threshold_ratr_40M;
 984         u32                             low_rssi_threshold_ratr_20M;
 985         u8                              ping_rssi_enable;       //cosa add for test
 986         u32                             ping_rssi_ratr; //cosa add for test
 987         u32                             ping_rssi_thresh_for_ra;//cosa add for test
 988         u32                             last_ratr;
 989
 990 } rate_adaptive, *prate_adaptive;
 991
 992 #define TxBBGainTableLength 37
 993 #define CCKTxBBGainTableLength 23
 994
 995 typedef struct _txbbgain_struct
 996 {
 997         long    txbb_iq_amplifygain;
 998         u32     txbbgain_value;
 999 } txbbgain_struct, *ptxbbgain_struct;
1000
1001 typedef struct _ccktxbbgain_struct
1002 {
1003         //The Value is from a22 to a29 one Byte one time is much Safer
1004         u8      ccktxbb_valuearray[8];
1005 } ccktxbbgain_struct,*pccktxbbgain_struct;
1006
1007
1008 typedef struct _init_gain
1009 {
1010         u8                              xaagccore1;
1011         u8                              xbagccore1;
1012         u8                              xcagccore1;
1013         u8                              xdagccore1;
1014         u8                              cca;
1015
1016 } init_gain, *pinit_gain;
1017 //by amy 0606
1018
1019 typedef struct _phy_ofdm_rx_status_report_819xusb
1020 {
1021         u8      trsw_gain_X[4];
1022         u8      pwdb_all;
1023         u8      cfosho_X[4];
1024         u8      cfotail_X[4];
1025         u8      rxevm_X[2];
1026         u8      rxsnr_X[4];
1027         u8      pdsnr_X[2];
1028         u8      csi_current_X[2];
1029         u8      csi_target_X[2];
1030         u8      sigevm;
1031         u8      max_ex_pwr;
1032         u8      sgi_en;
1033         u8  rxsc_sgien_exflg;
1034 }phy_sts_ofdm_819xusb_t;
1035
1036 typedef struct _phy_cck_rx_status_report_819xusb
1037 {
1038         /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
1039            0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
1040         u8      adc_pwdb_X[4];
1041         u8      sq_rpt;
1042         u8      cck_agc_rpt;
1043 }phy_sts_cck_819xusb_t;
1044
1045
1046 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
1047         u8                      reserved:4;
1048         u8                      rxsc:2;
1049         u8                      sgi_en:1;
1050         u8                      ex_intf_flag:1;
1051 }phy_ofdm_rx_status_rxsc_sgien_exintfflag;
1052
1053 typedef enum _RT_CUSTOMER_ID
1054 {
1055         RT_CID_DEFAULT = 0,
1056         RT_CID_8187_ALPHA0 = 1,
1057         RT_CID_8187_SERCOMM_PS = 2,
1058         RT_CID_8187_HW_LED = 3,
1059         RT_CID_8187_NETGEAR = 4,
1060         RT_CID_WHQL = 5,
1061         RT_CID_819x_CAMEO  = 6,
1062         RT_CID_819x_RUNTOP = 7,
1063         RT_CID_819x_Senao = 8,
1064         RT_CID_TOSHIBA = 9,     // Merge by Jacken, 2008/01/31.
1065         RT_CID_819x_Netcore = 10,
1066         RT_CID_Nettronix = 11,
1067         RT_CID_DLINK = 12,
1068         RT_CID_PRONET = 13,
1069 }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
1070
1071 typedef enum _RESET_TYPE {
1072         RESET_TYPE_NORESET = 0x00,
1073         RESET_TYPE_NORMAL = 0x01,
1074         RESET_TYPE_SILENT = 0x02
1075 } RESET_TYPE;
1076
1077 /* The simple tx command OP code. */
1078 typedef enum _tag_TxCmd_Config_Index{
1079         TXCMD_TXRA_HISTORY_CTRL                         = 0xFF900000,
1080         TXCMD_RESET_TX_PKT_BUFF                         = 0xFF900001,
1081         TXCMD_RESET_RX_PKT_BUFF                         = 0xFF900002,
1082         TXCMD_SET_TX_DURATION                           = 0xFF900003,
1083         TXCMD_SET_RX_RSSI                                               = 0xFF900004,
1084         TXCMD_SET_TX_PWR_TRACKING                       = 0xFF900005,
1085         TXCMD_XXXX_CTRL,
1086 }DCMD_TXCMD_OP;
1087
1088 typedef enum{
1089         NIC_8192U = 1,
1090         NIC_8190P = 2,
1091         NIC_8192E = 3,
1092         NIC_8192SE = 4,
1093         NIC_8192SU = 5,
1094         } nic_t;
1095
1096 //definded by WB. Ready to fill handlers for different NIC types.
1097 //add handle here when necessary.
1098 struct rtl819x_ops{
1099         nic_t nic_type;
1100         void (* rtl819x_read_eeprom_info)(struct net_device *dev);
1101         short (* rtl819x_tx)(struct net_device *dev, struct sk_buff* skb);
1102         short (* rtl819x_tx_cmd)(struct net_device *dev, struct sk_buff *skb);
1103         void (* rtl819x_rx_nomal)(struct sk_buff* skb);
1104         void (* rtl819x_rx_cmd)(struct sk_buff *skb);
1105         bool (* rtl819x_adapter_start)(struct net_device *dev);
1106         void (* rtl819x_link_change)(struct net_device *dev);
1107         void (* rtl819x_initial_gain)(struct net_device *dev,u8 Operation);
1108         void (* rtl819x_query_rxdesc_status)(struct sk_buff *skb, struct ieee80211_rx_stats *stats, bool bIsRxAggrSubframe);
1109 };
1110
1111 typedef struct r8192_priv
1112 {
1113         struct rtl819x_ops* ops;
1114         struct usb_device *udev;
1115         /* added for maintain info from eeprom */
1116         u16 eeprom_vid;
1117         u16 eeprom_pid;
1118         u8  eeprom_CustomerID;
1119         u8  eeprom_SubCustomerID;
1120         u8  eeprom_ChannelPlan;
1121         RT_CUSTOMER_ID CustomerID;
1122         LED_STRATEGY_819xUsb    LedStrategy;
1123         u8  txqueue_to_outpipemap[9];
1124         u8  RtOutPipes[16];
1125         u8  RtInPipes[16];
1126         u8  ep_in_num;
1127         u8  ep_out_num;
1128         u8  ep_num;
1129         int irq;
1130         struct ieee80211_device *ieee80211;
1131
1132         short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */
1133         u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
1134 //      short phy_ver; /* meaningful for rtl8225 1:A 2:B 3:C */
1135         short enable_gpio0;
1136         enum card_type {PCI,MINIPCI,CARDBUS,USB}card_type;
1137         short hw_plcp_len;
1138         short plcp_preamble_mode;
1139
1140         spinlock_t irq_lock;
1141 //      spinlock_t irq_th_lock;
1142         spinlock_t tx_lock;
1143         spinlock_t ps_lock;
1144         struct mutex mutex;
1145         spinlock_t rf_lock; //used to lock rf write operation added by wb
1146
1147         u16 irq_mask;
1148 //      short irq_enabled;
1149 //      struct net_device *dev; //comment this out.
1150         short chan;
1151         short sens;
1152         short max_sens;
1153
1154
1155         //      u8 chtxpwr[15]; //channels from 1 to 14, 0 not used
1156 //      u8 chtxpwr_ofdm[15]; //channels from 1 to 14, 0 not used
1157 //      u8 cck_txpwr_base;
1158 //      u8 ofdm_txpwr_base;
1159 //      u8 challow[15]; //channels from 1 to 14, 0 not used
1160         short up;
1161         short crcmon; //if 1 allow bad crc frame reception in monitor mode
1162 //      short prism_hdr;
1163
1164 //      struct timer_list scan_timer;
1165         /*short scanpending;
1166         short stopscan;*/
1167 //      spinlock_t scan_lock;
1168 //      u8 active_probe;
1169         //u8 active_scan_num;
1170         struct semaphore wx_sem;
1171         struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
1172 //      short hw_wep;
1173
1174 //      short digphy;
1175 //      short antb;
1176 //      short diversity;
1177 //      u8 cs_treshold;
1178 //      short rcr_csense;
1179         u8 rf_type; //0 means 1T2R, 1 means 2T4R
1180         RT_RF_TYPE_819xU rf_chip;
1181
1182 //      u32 key0[4];
1183         short (*rf_set_sens)(struct net_device *dev,short sens);
1184         u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
1185         void (*rf_close)(struct net_device *dev);
1186         void (*rf_init)(struct net_device *dev);
1187         //short rate;
1188         short promisc;
1189         /*stats*/
1190         struct Stats stats;
1191         struct iw_statistics wstats;
1192         struct proc_dir_entry *dir_dev;
1193
1194         /*RX stuff*/
1195 //      u32 *rxring;
1196 //      u32 *rxringtail;
1197 //      dma_addr_t rxringdma;
1198         struct urb **rx_urb;
1199         struct urb **rx_cmd_urb;
1200
1201 /* modified by davad for Rx process */
1202        struct sk_buff_head rx_queue;
1203        struct sk_buff_head skb_queue;
1204
1205        struct work_struct qos_activate;
1206
1207         short  tx_urb_index;
1208         atomic_t tx_pending[0x10];//UART_PRIORITY+1
1209
1210
1211         struct tasklet_struct irq_rx_tasklet;
1212         struct urb *rxurb_task;
1213
1214         //2 Tx Related variables
1215         u16     ShortRetryLimit;
1216         u16     LongRetryLimit;
1217         u32     TransmitConfig;
1218         u8      RegCWinMin;             // For turbo mode CW adaptive. Added by Annie, 2005-10-27.
1219
1220         u32     LastRxDescTSFHigh;
1221         u32     LastRxDescTSFLow;
1222
1223
1224         //2 Rx Related variables
1225         u16     EarlyRxThreshold;
1226         u32     ReceiveConfig;
1227         u8      AcmControl;
1228
1229         u8      RFProgType;
1230
1231         u8 retry_data;
1232         u8 retry_rts;
1233         u16 rts;
1234
1235         struct  ChnlAccessSetting  ChannelAccessSetting;
1236
1237         struct work_struct reset_wq;
1238
1239 /**********************************************************/
1240         //for rtl819xUsb
1241         u16     basic_rate;
1242         u8      short_preamble;
1243         u8      slot_time;
1244         bool    bDcut;
1245         bool bCurrentRxAggrEnable;
1246         u8 Rf_Mode; //add for Firmware RF -R/W switch
1247         prt_firmware            pFirmware;
1248         rtl819xUsb_loopback_e   LoopbackMode;
1249         bool usb_error;
1250
1251         u16 EEPROMTxPowerDiff;
1252         u8 EEPROMThermalMeter;
1253         u8 EEPROMPwDiff;
1254         u8 EEPROMCrystalCap;
1255         u8 EEPROM_Def_Ver;
1256         u8 EEPROMTxPowerLevelCCK;// CCK channel 1~14
1257         u8 EEPROMTxPowerLevelCCK_V1[3];
1258         u8 EEPROMTxPowerLevelOFDM24G[3]; // OFDM 2.4G channel 1~14
1259         u8 EEPROMTxPowerLevelOFDM5G[24];        // OFDM 5G
1260
1261 //RTL8192SU
1262         bool    bDmDisableProtect;
1263         bool    bIgnoreDiffRateTxPowerOffset;
1264
1265         // For EEPROM TX Power Index like 8190 series
1266         u8  EEPROMRfACCKChnl1TxPwLevel[3];      //RF-A CCK Tx Power Level at channel 7
1267         u8  EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1268         u8  EEPROMRfCCCKChnl1TxPwLevel[3];      //RF-C CCK Tx Power Level at channel 7
1269         u8  EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1270
1271         // F92S new definition
1272         //RF-A&B CCK/OFDM Tx Power Level at three channel are [1-3] [4-9] [10-14]
1273         u8  RfCckChnlAreaTxPwr[2][3];
1274         u8  RfOfdmChnlAreaTxPwr1T[2][3];
1275         u8  RfOfdmChnlAreaTxPwr2T[2][3];
1276
1277         // Add For EEPROM Efuse switch and  Efuse Shadow map Setting
1278         bool            EepromOrEfuse;
1279         bool            bBootFromEfuse; // system boot form EFUSE
1280         u8              EfuseMap[2][HWSET_MAX_SIZE_92S];
1281
1282         u8              EEPROMUsbOption;
1283         u8              EEPROMUsbPhyParam[5];
1284         u8              EEPROMTxPwrBase;
1285         u8              EEPROMBoardType;
1286         bool            bBootFromEEPROM;   // system boot from EEPROM
1287         u8              EEPROMTSSI_A;
1288         u8              EEPROMTSSI_B;
1289         u8              EEPROMHT2T_TxPwr[6];                    // For channel 1, 7 and 13 on path A/B.
1290         u8              EEPROMTxPwrTkMode;
1291
1292         u8              bTXPowerDataReadFromEEPORM;
1293
1294         u8              EEPROMVersion;
1295         u8              EEPROMUsbEndPointNumber;
1296
1297         bool            AutoloadFailFlag;
1298         u8      RfTxPwrLevelCck[2][14];
1299         u8      RfTxPwrLevelOfdm1T[2][14];
1300         u8      RfTxPwrLevelOfdm2T[2][14];
1301         // 2009/01/20 MH Add for new EEPROM format.
1302         u8                                      TxPwrHt20Diff[2][14];                           // HT 20<->40 Pwr diff
1303         u8                                      TxPwrLegacyHtDiff[2][14];               // For HT<->legacy pwr diff
1304         u8                                      TxPwrbandEdgeHt40[2][2];                // Band edge for HY 40MHZlow/up channel
1305         u8                                      TxPwrbandEdgeHt20[2][2];                // Band edge for HY 40MHZ low/up channel
1306         u8                                      TxPwrbandEdgeLegacyOfdm[2][2];  // Band edge for legacy ofdm low/up channel
1307         u8                                      TxPwrbandEdgeFlag;                              // Band edge enable flag
1308
1309         // L1 and L2 high power threshold.
1310         u8                              MidHighPwrTHR_L1;
1311         u8                              MidHighPwrTHR_L2;
1312         u8                              TxPwrSafetyFlag;                                // for Tx power safety spec
1313 //RTL8192SU
1314
1315 /*PHY related*/
1316         BB_REGISTER_DEFINITION_T        PHYRegDef[4];   //Radio A/B/C/D
1317         // Read/write are allow for following hardware information variables
1318         u32     MCSTxPowerLevelOriginalOffset[7];//FIXLZM
1319         u32     CCKTxPowerLevelOriginalOffset;
1320         u8      TxPowerLevelCCK[14];                    // CCK channel 1~14
1321         u8      TxPowerLevelOFDM24G[14];                // OFDM 2.4G channel 1~14
1322         u8      TxPowerLevelOFDM5G[14];                 // OFDM 5G
1323         u32     Pwr_Track;
1324         u8      TxPowerDiff;
1325         u8      AntennaTxPwDiff[2];                             // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
1326         u8      CrystalCap;                                             // CrystalCap.
1327         u8      ThermalMeter[2];                                // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
1328
1329         u8      CckPwEnl;
1330         // Use to calculate PWBD.
1331         u8      bCckHighPower;
1332         long    undecorated_smoothed_pwdb;
1333
1334         //for set channel
1335         u8      SwChnlInProgress;
1336         u8      SwChnlStage;
1337         u8      SwChnlStep;
1338         u8      SetBWModeInProgress;
1339         HT_CHANNEL_WIDTH                CurrentChannelBW;
1340         u8      ChannelPlan;
1341         u8      pwrGroupCnt;
1342         // 8190 40MHz mode
1343         //
1344         u8      nCur40MhzPrimeSC;       // Control channel sub-carrier
1345         // Joseph test for shorten RF configuration time.
1346         // We save RF reg0 in this variable to reduce RF reading.
1347         //
1348         u32                                     RfReg0Value[4];
1349         u8                                      NumTotalRFPath;
1350         bool                            brfpath_rxenable[4];
1351         //RF set related
1352         bool                            SetRFPowerStateInProgress;
1353 //+by amy 080507
1354         struct timer_list watch_dog_timer;
1355
1356 //+by amy 080515 for dynamic mechenism
1357         //Add by amy Tx Power Control for Near/Far Range 2008/05/15
1358         bool    bdynamic_txpower;  //bDynamicTxPower
1359         bool    bDynamicTxHighPower;  // Tx high power state
1360         bool    bDynamicTxLowPower;  // Tx low power state
1361         bool    bLastDTPFlag_High;
1362         bool    bLastDTPFlag_Low;
1363
1364         bool    bstore_last_dtpflag;
1365         bool    bstart_txctrl_bydtp;   //Define to discriminate on High power State or on sitesuvey to change Tx gain index
1366         //Add by amy for Rate Adaptive
1367         rate_adaptive rate_adaptive;
1368         //Add by amy for TX power tracking
1369         //2008/05/15  Mars OPEN/CLOSE TX POWER TRACKING
1370        txbbgain_struct txbbgain_table[TxBBGainTableLength];
1371        u8       EEPROMTxPowerTrackEnable;
1372         u8                         txpower_count;//For 6 sec do tracking again
1373         bool                       btxpower_trackingInit;
1374         u8                         OFDM_index;
1375         u8                         CCK_index;
1376         //2007/09/10 Mars Add CCK TX Power Tracking
1377         ccktxbbgain_struct      cck_txbbgain_table[CCKTxBBGainTableLength];
1378         ccktxbbgain_struct      cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1379         u8 rfa_txpowertrackingindex;
1380         u8 rfa_txpowertrackingindex_real;
1381         u8 rfa_txpowertracking_default;
1382         u8 rfc_txpowertrackingindex;
1383         u8 rfc_txpowertrackingindex_real;
1384
1385         s8 cck_present_attentuation;
1386         u8 cck_present_attentuation_20Mdefault;
1387         u8 cck_present_attentuation_40Mdefault;
1388         char cck_present_attentuation_difference;
1389         bool btxpower_tracking;
1390         bool bcck_in_ch14;
1391         bool btxpowerdata_readfromEEPORM;
1392         u16     TSSI_13dBm;
1393         //For Backup Initial Gain
1394         init_gain initgain_backup;
1395         u8 DefaultInitialGain[4];
1396         // For EDCA Turbo mode, Added by amy 080515.
1397         bool            bis_any_nonbepkts;
1398         bool            bcurrent_turbo_EDCA;
1399         bool            bis_cur_rdlstate;
1400         struct timer_list fsync_timer;
1401         bool bfsync_processing; // 500ms Fsync timer is active or not
1402         u32     rate_record;
1403         u32     rateCountDiffRecord;
1404         u32     ContiuneDiffCount;
1405         bool bswitch_fsync;
1406
1407         u8      framesync;
1408         u32     framesyncC34;
1409         u8      framesyncMonitor;
1410                 //Added by amy 080516  for RX related
1411         u16     nrxAMPDU_size;
1412         u8      nrxAMPDU_aggr_num;
1413
1414         //by amy for gpio
1415          bool bHwRadioOff;
1416
1417         //by amy for reset_count
1418         u32 reset_count;
1419         bool bpbc_pressed;
1420         //by amy for debug
1421         u32 txpower_checkcnt;
1422         u32 txpower_tracking_callback_cnt;
1423         u8 thermal_read_val[40];
1424         u8 thermal_readback_index;
1425         u32 ccktxpower_adjustcnt_not_ch14;
1426         u32 ccktxpower_adjustcnt_ch14;
1427         u8 tx_fwinfo_force_subcarriermode;
1428         u8 tx_fwinfo_force_subcarrierval;
1429         //by amy for silent reset
1430         RESET_TYPE      ResetProgress;
1431         bool            bForcedSilentReset;
1432         bool            bDisableNormalResetCheck;
1433         u16             TxCounter;
1434         u16             RxCounter;
1435         int             IrpPendingCount;
1436         bool            bResetInProgress;
1437         bool            force_reset;
1438         u8              InitialGainOperateType;
1439
1440         u16             SifsTime;
1441
1442         //define work item by amy 080526
1443         struct delayed_work update_beacon_wq;
1444         struct delayed_work watch_dog_wq;
1445         struct delayed_work txpower_tracking_wq;
1446         struct delayed_work rfpath_check_wq;
1447         struct delayed_work gpio_change_rf_wq;
1448         struct delayed_work initialgain_operate_wq;
1449
1450         struct workqueue_struct *priv_wq;
1451 //#ifdef RTL8192SU
1452         //lzm add for 8192S
1453          u32                    IntrMask;
1454         // RF and BB access related synchronization flags.
1455         bool                            bChangeBBInProgress; // BaseBand RW is still in progress.
1456         bool                            bChangeRFInProgress; // RF RW is still in progress.
1457
1458         u32                             CCKTxPowerAdjustCntCh14;                //debug only
1459         u32                             CCKTxPowerAdjustCntNotCh14;     //debug only
1460         u32                             TXPowerTrackingCallbackCnt;             //debug only
1461         u32                             TxPowerCheckCnt;                                //debug only
1462         u32                             RFWritePageCnt[3];                              //debug only
1463         u32                             RFReadPageCnt[3];                               //debug only
1464         u8                              ThermalReadBackIndex;                   //debug only
1465         u8                              ThermalReadVal[40];                             //debug only
1466
1467         // For HCT test, 2005.07.15, by rcnjko.
1468         // not realize true, just define it, set it 0 default, because some func use it
1469         bool                            bInHctTest;
1470
1471         // The current Tx Power Level
1472         u8                              CurrentCckTxPwrIdx;
1473         u8                              CurrentOfdm24GTxPwrIdx;
1474
1475         // For pass 92S common phycfg.c compiler
1476         u8                                      TxPowerLevelCCK_A[14];                  // RF-A, CCK channel 1~14
1477         u8                                      TxPowerLevelOFDM24G_A[14];      // RF-A, OFDM 2.4G channel 1~14
1478         u8                                      TxPowerLevelCCK_C[14];                  // RF-C, CCK channel 1~14
1479         u8                                      TxPowerLevelOFDM24G_C[14];      // RF-C, OFDM 2.4G channel 1~14
1480         u8                                      LegacyHTTxPowerDiff;                    // Legacy to HT rate power diff
1481         char                                    RF_C_TxPwDiff;                                  // Antenna gain offset, rf-c to rf-a
1482
1483         bool    bRFSiOrPi;//0=si, 1=pi.
1484         //lzm add for 8192S
1485
1486         bool SetFwCmdInProgress; //is set FW CMD in Progress? 92S only
1487         u8 CurrentFwCmdIO;
1488
1489         u8 MinSpaceCfg;
1490
1491         u16 rf_pathmap;
1492
1493         /* added for led control */
1494         PLED_819xUsb                    pLed;
1495         LED_819xUsb                     SwLed0;
1496         LED_819xUsb                     SwLed1;
1497         u8                              bRegUseLed;
1498         struct work_struct              BlinkWorkItem;
1499         /* added for led control */
1500         u16                             FwCmdIOMap;
1501         u32                             FwCmdIOParam;
1502         u8                              DMFlag;
1503
1504
1505
1506
1507 }r8192_priv;
1508
1509 // for rtl8187
1510 // now mirging to rtl8187B
1511 /*
1512 typedef enum{
1513         LOW_PRIORITY = 0x02,
1514         NORM_PRIORITY
1515         } priority_t;
1516 */
1517 //for rtl8187B
1518 typedef enum{
1519         BULK_PRIORITY = 0x01,
1520         //RSVD0,
1521         //RSVD1,
1522         LOW_PRIORITY,
1523         NORM_PRIORITY,
1524         VO_PRIORITY,
1525         VI_PRIORITY, //0x05
1526         BE_PRIORITY,
1527         BK_PRIORITY,
1528         RSVD2,
1529         RSVD3,
1530         BEACON_PRIORITY, //0x0A
1531         HIGH_PRIORITY,
1532         MANAGE_PRIORITY,
1533         RSVD4,
1534         RSVD5,
1535         UART_PRIORITY //0x0F
1536 } priority_t;
1537
1538 #ifdef JOHN_HWSEC
1539 struct ssid_thread {
1540         struct net_device *dev;
1541         u8 name[IW_ESSID_MAX_SIZE + 1];
1542 };
1543 #endif
1544
1545 short rtl8192SU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1546 short rtl8192SU_tx(struct net_device *dev, struct sk_buff* skb);
1547 bool FirmwareDownload92S(struct net_device *dev);
1548
1549 short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1550 short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
1551
1552 u32 read_cam(struct net_device *dev, u8 addr);
1553 void write_cam(struct net_device *dev, u8 addr, u32 data);
1554
1555 u8 read_nic_byte(struct net_device *dev, int x);
1556 u8 read_nic_byte_E(struct net_device *dev, int x);
1557 u32 read_nic_dword(struct net_device *dev, int x);
1558 u16 read_nic_word(struct net_device *dev, int x) ;
1559 void write_nic_byte(struct net_device *dev, int x,u8 y);
1560 void write_nic_byte_E(struct net_device *dev, int x,u8 y);
1561 void write_nic_word(struct net_device *dev, int x,u16 y);
1562 void write_nic_dword(struct net_device *dev, int x,u32 y);
1563 void force_pci_posting(struct net_device *dev);
1564
1565 void rtl8192_rtx_disable(struct net_device *);
1566 void rtl8192_rx_enable(struct net_device *);
1567 void rtl8192_tx_enable(struct net_device *);
1568
1569 void rtl8192_disassociate(struct net_device *dev);
1570 //void fix_rx_fifo(struct net_device *dev);
1571 void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a);
1572
1573 void rtl8192_set_anaparam(struct net_device *dev,u32 a);
1574 void rtl8185_set_anaparam2(struct net_device *dev,u32 a);
1575 void rtl8192_update_msr(struct net_device *dev);
1576 int rtl8192_down(struct net_device *dev);
1577 int rtl8192_up(struct net_device *dev);
1578 void rtl8192_commit(struct net_device *dev);
1579 void rtl8192_set_chan(struct net_device *dev,short ch);
1580 void write_phy(struct net_device *dev, u8 adr, u8 data);
1581 void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1582 void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1583 void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
1584 void rtl8192_set_rxconf(struct net_device *dev);
1585 //short check_nic_enough_desc(struct net_device *dev, priority_t priority);
1586 extern void rtl819xusb_beacon_tx(struct net_device *dev,u16  tx_rate);
1587 void CamResetAllEntry(struct net_device* dev);
1588 void EnableHWSecurityConfig8192(struct net_device *dev);
1589 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent );
1590 short rtl8192_is_tx_queue_empty(struct net_device *dev);
1591
1592 #endif