2 This is part of rtl8187 OpenSource driver.
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public Licence)
6 Parts of this driver are based on the GPL part of the
7 official realtek driver
9 Parts of this driver are based on the rtl8192 driver skeleton
10 from Patric Schenke & Andres Salomon
12 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
14 We want to tanks the Authors of those projects and the Ndiswrapper
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/types.h>
27 #include <linux/slab.h>
28 #include <linux/netdevice.h>
29 #include <linux/pci.h>
30 #include <linux/etherdevice.h>
31 #include <linux/delay.h>
32 #include <linux/rtnetlink.h> //for rtnl_lock()
33 #include <linux/wireless.h>
34 #include <linux/timer.h>
35 #include <linux/proc_fs.h> // Necessary because we use the proc fs
36 #include <linux/if_arp.h>
37 #include <linux/random.h>
38 #include <linux/version.h>
39 #include <linux/interrupt.h>
41 #include "ieee80211/rtl819x_HT.h"
42 #include "ieee80211/ieee80211.h"
47 #define RTL819xE_MODULE_NAME "rtl819xE"
51 #define MAX_KEY_LEN 61
52 #define KEY_BUF_SIZE 5
54 #define BIT0 0x00000001
55 #define BIT1 0x00000002
56 #define BIT2 0x00000004
57 #define BIT3 0x00000008
58 #define BIT4 0x00000010
59 #define BIT5 0x00000020
60 #define BIT6 0x00000040
61 #define BIT7 0x00000080
62 #define BIT8 0x00000100
63 #define BIT9 0x00000200
64 #define BIT10 0x00000400
65 #define BIT11 0x00000800
66 #define BIT12 0x00001000
67 #define BIT13 0x00002000
68 #define BIT14 0x00004000
69 #define BIT15 0x00008000
70 #define BIT16 0x00010000
71 #define BIT17 0x00020000
72 #define BIT18 0x00040000
73 #define BIT19 0x00080000
74 #define BIT20 0x00100000
75 #define BIT21 0x00200000
76 #define BIT22 0x00400000
77 #define BIT23 0x00800000
78 #define BIT24 0x01000000
79 #define BIT25 0x02000000
80 #define BIT26 0x04000000
81 #define BIT27 0x08000000
82 #define BIT28 0x10000000
83 #define BIT29 0x20000000
84 #define BIT30 0x40000000
85 #define BIT31 0x80000000
87 #define Rx_Smooth_Factor 20
88 /* 2007/06/04 MH Define sliding window for RSSI history. */
89 #define PHY_RSSI_SLID_WIN_MAX 100
90 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10
92 #define IC_VersionCut_D 0x3
93 #define IC_VersionCut_E 0x4
95 #if 0 //we need to use RT_TRACE instead DMESG as RT_TRACE will clearly show debug level wb.
96 #define DMESG(x,a...) printk(KERN_INFO RTL819xE_MODULE_NAME ": " x "\n", ## a)
99 extern u32 rt_global_debug_component;
100 #define RT_TRACE(component, x, args...) \
101 do { if(rt_global_debug_component & component) \
102 printk(KERN_DEBUG RTL819xE_MODULE_NAME ":" x , \
106 #define COMP_TRACE BIT0 // For function call tracing.
107 #define COMP_DBG BIT1 // Only for temporary debug message.
108 #define COMP_INIT BIT2 // during driver initialization / halt / reset.
111 #define COMP_RECV BIT3 // Reveive part data path.
112 #define COMP_SEND BIT4 // Send part path.
113 #define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02.
114 #define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related.
115 #define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS.
116 #define COMP_SWBW BIT8 // For bandwidth switch.
117 #define COMP_SEC BIT9// For Security.
120 #define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21.
121 #define COMP_QOS BIT11 // For QoS.
123 #define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS 0x00000080 // Event handling
124 #define COMP_RXDESC BIT13 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
125 #define COMP_PHY BIT14
126 #define COMP_DIG BIT15 // For DIG, 2006.09.25, by rcnjko.
127 #define COMP_TXAGC BIT16 // For Tx power, 060928, by rcnjko.
128 #define COMP_HALDM BIT17 // For HW Dynamic Mechanism, 061010, by rcnjko.
129 #define COMP_POWER_TRACKING BIT18 //FOR 8190 TX POWER TRACKING
130 #define COMP_EVENTS BIT19 // Event handling
132 #define COMP_RF BIT20 // For RF.
134 /* 11n or 8190 specific code should be put below this line */
137 #define COMP_FIRMWARE BIT21 //for firmware downloading
138 #define COMP_HT BIT22 // For 802.11n HT related information. by Emily 2006-8-11
140 #define COMP_RESET BIT23
141 #define COMP_CMDPKT BIT24
142 #define COMP_SCAN BIT25
143 #define COMP_IPS BIT26
144 #define COMP_DOWN BIT27 // for rm driver module
145 #define COMP_INTR BIT28 // for interrupt
146 #define COMP_ERR BIT31 // for error out, always on
151 // Queue Select Value in TxDesc
157 #define QSLT_BEACON 0x10
158 #define QSLT_HIGH 0x11
159 #define QSLT_MGNT 0x12
160 #define QSLT_CMD 0x13
162 #define DESC90_RATE1M 0x00
163 #define DESC90_RATE2M 0x01
164 #define DESC90_RATE5_5M 0x02
165 #define DESC90_RATE11M 0x03
166 #define DESC90_RATE6M 0x04
167 #define DESC90_RATE9M 0x05
168 #define DESC90_RATE12M 0x06
169 #define DESC90_RATE18M 0x07
170 #define DESC90_RATE24M 0x08
171 #define DESC90_RATE36M 0x09
172 #define DESC90_RATE48M 0x0a
173 #define DESC90_RATE54M 0x0b
174 #define DESC90_RATEMCS0 0x00
175 #define DESC90_RATEMCS1 0x01
176 #define DESC90_RATEMCS2 0x02
177 #define DESC90_RATEMCS3 0x03
178 #define DESC90_RATEMCS4 0x04
179 #define DESC90_RATEMCS5 0x05
180 #define DESC90_RATEMCS6 0x06
181 #define DESC90_RATEMCS7 0x07
182 #define DESC90_RATEMCS8 0x08
183 #define DESC90_RATEMCS9 0x09
184 #define DESC90_RATEMCS10 0x0a
185 #define DESC90_RATEMCS11 0x0b
186 #define DESC90_RATEMCS12 0x0c
187 #define DESC90_RATEMCS13 0x0d
188 #define DESC90_RATEMCS14 0x0e
189 #define DESC90_RATEMCS15 0x0f
190 #define DESC90_RATEMCS32 0x20
192 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
193 #define EEPROM_Default_LegacyHTTxPowerDiff 0x4
194 #define IEEE80211_WATCH_DOG_TIME 2000
196 typedef u32 RT_RF_CHANGE_SOURCE;
197 #define RF_CHANGE_BY_SW BIT31
198 #define RF_CHANGE_BY_HW BIT30
199 #define RF_CHANGE_BY_PS BIT29
200 #define RF_CHANGE_BY_IPS BIT28
201 #define RF_CHANGE_BY_INIT 0 // Do not change the RFOff reason. Defined by Bruce, 2008-01-17.
204 typedef enum _RT_RF_POWER_STATE {
210 typedef enum _RT_JOIN_ACTION {
217 typedef enum _IPS_CALLBACK_FUNCION {
218 IPS_CALLBACK_NONE = 0,
219 IPS_CALLBACK_MGNT_LINK_REQUEST = 1,
220 IPS_CALLBACK_JOIN_REQUEST = 2,
221 } IPS_CALLBACK_FUNCION;
223 typedef struct _RT_POWER_SAVE_CONTROL {
224 /* Inactive Power Save(IPS) : Disable RF when disconnected */
227 bool bSwRfProcessing;
228 RT_RF_POWER_STATE eInactivePowerState;
229 struct work_struct InactivePsWorkItem;
230 struct timer_list InactivePsTimer;
232 /* Return point for join action */
233 IPS_CALLBACK_FUNCION ReturnPoint;
235 /* Recored Parameters for rescheduled JoinRequest */
237 RT_JOIN_ACTION tmpJoinAction;
238 struct ieee80211_network tmpBssDesc;
240 /* Recored Parameters for rescheduled MgntLinkRequest */
243 bool bTmpFilterHiddenAP;
244 bool bTmpUpdateParms;
246 OCTET_STRING tmpSsid2Scan;
253 OCTET_STRING tmpSuppRateSet;
254 u8 tmpSuppRateBuf[MAX_NUM_RATES];
260 * Leisure Power Save:
261 * Disable RF if connected but traffic is not busy
273 bool LinkReqInIPSRFOffPgs;
274 bool BufConnectinfoBefore;
275 } RT_POWER_SAVE_CONTROL, *PRT_POWER_SAVE_CONTROL;
278 typedef struct _tx_desc_819x_pci {
320 }tx_desc_819x_pci, *ptx_desc_819x_pci;
323 typedef struct _tx_desc_cmd_819x_pci {
348 }tx_desc_cmd_819x_pci, *ptx_desc_cmd_819x_pci;
351 typedef struct _tx_fwinfo_819x_pci {
358 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
359 u8 TxBandwidth:1; // This is used for HT MCS rate only.
360 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
362 u8 AllowAggregation:1;
363 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
364 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
365 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
366 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
368 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
379 }tx_fwinfo_819x_pci, *ptx_fwinfo_819x_pci;
381 typedef struct _rx_desc_819x_pci{
404 }rx_desc_819x_pci, *prx_desc_819x_pci;
406 typedef struct _rx_fwinfo_819x_pci{
427 }rx_fwinfo_819x_pci, *prx_fwinfo_819x_pci;
429 #define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */
430 #define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/
431 #define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
432 #define ENCRYPTION_MAX_OVERHEAD 128
433 #define MAX_FRAGMENT_COUNT 8
434 #define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
436 #define scrclng 4 // octets for crc32 (FCS, ICV)
437 /* 8190 Loopback Mode definition */
438 typedef enum _rtl819x_loopback{
439 RTL819X_NO_LOOPBACK = 0,
440 RTL819X_MAC_LOOPBACK = 1,
441 RTL819X_DMA_LOOPBACK = 2,
442 RTL819X_CCK_LOOPBACK = 3,
445 /* due to rtl8192 firmware */
446 typedef enum _desc_packet_type_e{
447 DESC_PACKET_TYPE_INIT = 0,
448 DESC_PACKET_TYPE_NORMAL = 1,
451 typedef enum _firmware_status{
452 FW_STATUS_0_INIT = 0,
453 FW_STATUS_1_MOVE_BOOT_CODE = 1,
454 FW_STATUS_2_MOVE_MAIN_CODE = 2,
455 FW_STATUS_3_TURNON_CPU = 3,
456 FW_STATUS_4_MOVE_DATA_CODE = 4,
457 FW_STATUS_5_READY = 5,
460 typedef struct _rt_firmware{
461 firmware_status_e firmware_status;
462 u16 cmdpacket_frag_thresold;
463 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
464 #define MAX_FW_INIT_STEP 3
465 u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
466 u16 firmware_buf_size[MAX_FW_INIT_STEP];
467 }rt_firmware, *prt_firmware;
469 #define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP
471 /* Firmware Queue Layout */
472 #define NUM_OF_FIRMWARE_QUEUE 10
473 #define NUM_OF_PAGES_IN_FW 0x100
474 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x0aa
475 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x007
476 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x024
477 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x007
478 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
479 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x2
480 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x10
481 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
482 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
483 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xd
484 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
485 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
486 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
487 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
488 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
489 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
490 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08
491 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
492 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
494 #define DCAM 0xAC // Debug CAM Interface
495 #define AESMSK_FC 0xB2 // AES Mask register for frame control (0xB2~0xB3). Added by Annie, 2006-03-06.
498 #define CAM_CONTENT_COUNT 8
499 #define CFG_VALID BIT15
500 #define EPROM_93c46 0
501 #define EPROM_93c56 1
503 #define DEFAULT_FRAG_THRESHOLD 2342U
504 #define MIN_FRAG_THRESHOLD 256U
505 #define DEFAULT_BEACONINTERVAL 0x64U
507 #define DEFAULT_RETRY_RTS 7
508 #define DEFAULT_RETRY_DATA 7
510 #define PHY_RSSI_SLID_WIN_MAX 100
513 typedef enum _WIRELESS_MODE {
514 WIRELESS_MODE_UNKNOWN = 0x00,
515 WIRELESS_MODE_A = 0x01,
516 WIRELESS_MODE_B = 0x02,
517 WIRELESS_MODE_G = 0x04,
518 WIRELESS_MODE_AUTO = 0x08,
519 WIRELESS_MODE_N_24G = 0x10,
520 WIRELESS_MODE_N_5G = 0x20
523 #define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30
525 typedef struct buffer
533 typedef struct _rt_9x_tx_rate_history {
536 // HT_MCS[0][]: BW=0 SG=0
537 // HT_MCS[1][]: BW=1 SG=0
538 // HT_MCS[2][]: BW=0 SG=1
539 // HT_MCS[3][]: BW=1 SG=1
541 }rt_tx_rahis_t, *prt_tx_rahis_t;
543 typedef struct _RT_SMOOTH_DATA_4RF {
544 char elements[4][100];//array to store values
545 u32 index; //index to current array to store
546 u32 TotalNum; //num of valid elements
547 u32 TotalVal[4]; //sum of valid elements
548 }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
550 typedef enum _tag_TxCmd_Config_Index{
551 TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
552 TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
553 TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
554 TXCMD_SET_TX_DURATION = 0xFF900003,
555 TXCMD_SET_RX_RSSI = 0xFF900004,
556 TXCMD_SET_TX_PWR_TRACKING = 0xFF900005,
564 unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV
565 unsigned long rxoverflow;
567 unsigned long txoverflow;
568 unsigned long txbeokint;
569 unsigned long txbkokint;
570 unsigned long txviokint;
571 unsigned long txvookint;
572 unsigned long txbeaconokint;
573 unsigned long txbeaconerr;
574 unsigned long txmanageokint;
575 unsigned long txcmdpktokint;
576 unsigned long txfeedback;
577 unsigned long txfeedbackok;
578 unsigned long txoktotal;
579 unsigned long txbytesunicast;
580 unsigned long rxbytesunicast;
582 unsigned long slide_signal_strength[100];
583 unsigned long slide_evm[100];
584 unsigned long slide_rssi_total; // For recording sliding window's RSSI value
585 unsigned long slide_evm_total; // For recording sliding window's EVM value
586 long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
587 u8 rx_rssi_percentage[4];
588 u8 rx_evm_percentage[2];
589 u32 Slide_Beacon_pwdb[100];
590 u32 Slide_Beacon_Total;
591 RT_SMOOTH_DATA_4RF cck_adc_pwdb;
596 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
597 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
598 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
600 typedef struct ChnlAccessSetting {
607 }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
609 typedef struct _BB_REGISTER_DEFINITION{
610 u32 rfintfs; // set software control: // 0x870~0x877[8 bytes]
611 u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes]
612 u32 rfintfo; // output data: // 0x860~0x86f [16 bytes]
613 u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes]
614 u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes]
615 u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes]
616 u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes]
617 u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
618 u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
619 u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes]
620 u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
621 u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
622 u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
623 u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
624 u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
625 u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
626 u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes]
627 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
629 typedef struct _rate_adaptive
631 u8 rate_adaptive_disabled;
635 u32 high_rssi_thresh_for_ra;
636 u32 high2low_rssi_thresh_for_ra;
637 u8 low2high_rssi_thresh_for_ra40M;
638 u32 low_rssi_thresh_for_ra40M;
639 u8 low2high_rssi_thresh_for_ra20M;
640 u32 low_rssi_thresh_for_ra20M;
641 u32 upper_rssi_threshold_ratr;
642 u32 middle_rssi_threshold_ratr;
643 u32 low_rssi_threshold_ratr;
644 u32 low_rssi_threshold_ratr_40M;
645 u32 low_rssi_threshold_ratr_20M;
646 u8 ping_rssi_enable; //cosa add for test
647 u32 ping_rssi_ratr; //cosa add for test
648 u32 ping_rssi_thresh_for_ra;//cosa add for test
651 } rate_adaptive, *prate_adaptive;
652 #define TxBBGainTableLength 37
653 #define CCKTxBBGainTableLength 23
654 typedef struct _txbbgain_struct
656 long txbb_iq_amplifygain;
658 } txbbgain_struct, *ptxbbgain_struct;
660 typedef struct _ccktxbbgain_struct
662 //The Value is from a22 to a29 one Byte one time is much Safer
663 u8 ccktxbb_valuearray[8];
664 } ccktxbbgain_struct,*pccktxbbgain_struct;
667 typedef struct _init_gain
675 } init_gain, *pinit_gain;
677 /* 2007/11/02 MH Define RF mode temporarily for test. */
678 typedef enum tag_Rf_Operatetion_State
685 typedef enum _RT_STATUS{
690 }RT_STATUS,*PRT_STATUS;
692 typedef enum _RT_CUSTOMER_ID
695 RT_CID_8187_ALPHA0 = 1,
696 RT_CID_8187_SERCOMM_PS = 2,
697 RT_CID_8187_HW_LED = 3,
698 RT_CID_8187_NETGEAR = 4,
700 RT_CID_819x_CAMEO = 6,
701 RT_CID_819x_RUNTOP = 7,
702 RT_CID_819x_Senao = 8,
703 RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31.
704 RT_CID_819x_Netcore = 10,
705 RT_CID_Nettronix = 11,
709 }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
711 /* LED customization. */
713 typedef enum _LED_STRATEGY_8190{
714 SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
715 SW_LED_MODE1, // SW control for PCI Express
716 SW_LED_MODE2, // SW control for Cameo.
717 SW_LED_MODE3, // SW contorl for RunTop.
718 SW_LED_MODE4, // SW control for Netcore
719 SW_LED_MODE5, //added by vivi, for led new mode, DLINK
720 SW_LED_MODE6, //added by vivi, for led new mode, PRONET
721 HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
722 }LED_STRATEGY_8190, *PLED_STRATEGY_8190;
724 #define CHANNEL_PLAN_LEN 10
728 typedef struct _TX_FWINFO_STRUCUTRE{
739 u8 AllowAggregation:1;
758 typedef struct _TX_FWINFO_8190PCI{
765 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
766 u8 TxBandwidth:1; // This is used for HT MCS rate only.
767 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
769 u8 AllowAggregation:1;
770 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
771 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
772 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
773 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
775 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
780 u32 TxPerPktInfoFeedback:1; // 1: indicate that the transimission info of this packet should be gathered by Firmware and retured by Rx Cmd.
782 u32 TxAGCOffset:4; // Only 90 support
783 u32 TxAGCSign:1; // Only 90 support
784 u32 RAW_TXD:1; // MAC will send data in txpktbuffer without any processing,such as CRC check
785 u32 Retry_Limit:4; // CCX Support relative retry limit FW page only support 4 bits now.
791 }TX_FWINFO_8190PCI, *PTX_FWINFO_8190PCI;
793 typedef struct _phy_ofdm_rx_status_report_819xpci
808 }phy_sts_ofdm_819xpci_t;
810 typedef struct _phy_cck_rx_status_report_819xpci
812 /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
813 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
817 }phy_sts_cck_819xpci_t;
819 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
824 }phy_ofdm_rx_status_rxsc_sgien_exintfflag;
826 typedef enum _RT_OP_MODE{
828 RT_OP_MODE_INFRASTRUCTURE,
831 }RT_OP_MODE, *PRT_OP_MODE;
834 /* 2007/11/02 MH Define RF mode temporarily for test. */
835 typedef enum tag_Rf_OpType
837 RF_OP_By_SW_3wire = 0,
842 typedef enum _RESET_TYPE {
843 RESET_TYPE_NORESET = 0x00,
844 RESET_TYPE_NORMAL = 0x01,
845 RESET_TYPE_SILENT = 0x02
848 typedef struct _tx_ring{
851 struct _tx_ring * next;
852 }__attribute__ ((packed)) tx_ring, * ptx_ring;
854 struct rtl8192_tx_ring {
855 tx_desc_819x_pci *desc;
858 unsigned int entries;
859 struct sk_buff_head queue;
862 #define NIC_SEND_HANG_THRESHOLD_NORMAL 4
863 #define NIC_SEND_HANG_THRESHOLD_POWERSAVE 8
864 #define MAX_TX_QUEUE 9 // BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
866 #define MAX_RX_COUNT 64
867 #define MAX_TX_QUEUE_COUNT 9
869 typedef struct r8192_priv
871 struct pci_dev *pdev;
874 /* maintain info from eeprom */
878 u8 eeprom_CustomerID;
879 u16 eeprom_ChannelPlan;
880 RT_CUSTOMER_ID CustomerID;
883 struct ieee80211_device *ieee80211;
889 bool being_init_adapter;
891 u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
892 spinlock_t irq_th_lock;
893 spinlock_t rf_ps_lock;
899 rx_desc_819x_pci *rx_ring;
900 dma_addr_t rx_ring_dma;
902 struct sk_buff *rx_buf[MAX_RX_COUNT];
907 struct rtl8192_tx_ring tx_ring[MAX_TX_QUEUE_COUNT];
910 struct tasklet_struct irq_rx_tasklet;
911 struct tasklet_struct irq_tx_tasklet;
912 struct tasklet_struct irq_prepare_beacon_tasklet;
915 short crcmon; //if 1 allow bad crc frame reception in monitor mode
916 struct semaphore wx_sem;
917 struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
918 u8 rf_type; /* 0 means 1T2R, 1 means 2T4R */
920 short (*rf_set_sens)(struct net_device *dev, short sens);
921 u8 (*rf_set_chan)(struct ieee80211_device *ieee80211, u8 ch);
925 struct iw_statistics wstats;
926 struct proc_dir_entry *dir_dev;
927 struct ieee80211_rx_stats previous_stats;
930 struct sk_buff_head skb_queue;
931 struct work_struct qos_activate;
933 //2 Tx Related variables
937 u32 LastRxDescTSFHigh;
938 u32 LastRxDescTSFLow;
941 //2 Rx Related variables
947 struct work_struct reset_wq;
951 // Data Rate Config. Added by Annie, 2006-04-13.
959 prt_firmware pFirmware;
960 rtl819x_loopback_e LoopbackMode;
961 bool AutoloadFailFlag;
962 u16 EEPROMAntPwDiff; // Antenna gain offset from B/C/D to A
963 u8 EEPROMThermalMeter;
965 u8 EEPROMTxPowerLevelCCK[14];// CCK channel 1~14
966 // The following definition is for eeprom 93c56
967 u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7
968 u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
969 u8 EEPROMRfCCCKChnl1TxPwLevel[3]; //RF-C CCK Tx Power Level at channel 7
970 u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
971 u8 EEPROMTxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
972 u8 EEPROMLegacyHTTxPowerDiff; // Legacy to HT rate power diff
973 bool bTXPowerDataReadFromEEPORM;
975 u16 RegChannelPlan; // Channel Plan specifed by user, 15: following setting of EEPROM, 0-14: default channel plan index specified by user.
978 // Rf off action for power save
979 u8 bHwRfOffAction; //0:No action, 1:By GPIO, 2:By Disable
981 BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
982 // Read/write are allow for following hardware information variables
983 u32 MCSTxPowerLevelOriginalOffset[6];
984 u32 CCKTxPowerLevelOriginalOffset;
985 u8 TxPowerLevelCCK[14]; // CCK channel 1~14
986 u8 TxPowerLevelCCK_A[14]; // RF-A, CCK channel 1~14
987 u8 TxPowerLevelCCK_C[14];
988 u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
989 u8 TxPowerLevelOFDM5G[14]; // OFDM 5G
990 u8 TxPowerLevelOFDM24G_A[14]; // RF-A, OFDM 2.4G channel 1~14
991 u8 TxPowerLevelOFDM24G_C[14]; // RF-C, OFDM 2.4G channel 1~14
992 u8 LegacyHTTxPowerDiff; // Legacy to HT rate power diff
993 u8 AntennaTxPwDiff[3]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
994 u8 CrystalCap; // CrystalCap.
995 u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
996 //05/27/2008 cck power enlarge
1000 u8 CCKPresentAttentuation_20Mdefault;
1001 u8 CCKPresentAttentuation_40Mdefault;
1002 char CCKPresentAttentuation_difference;
1003 char CCKPresentAttentuation;
1004 // Use to calculate PWBD.
1005 RT_RF_POWER_STATE eRFPowerState;
1006 RT_RF_CHANGE_SOURCE RfOffReason;
1007 RT_POWER_SAVE_CONTROL PowerSaveControl;
1009 long undecorated_smoothed_pwdb;
1010 long undecorated_smoothed_cck_adc_pwdb[4];
1012 u8 SwChnlInProgress;
1015 u8 SetBWModeInProgress;
1016 HT_CHANNEL_WIDTH CurrentChannelBW;
1020 u8 nCur40MhzPrimeSC; // Control channel sub-carrier
1021 // Joseph test for shorten RF configuration time.
1022 // We save RF reg0 in this variable to reduce RF reading.
1026 bool brfpath_rxenable[4];
1028 struct timer_list watch_dog_timer;
1029 u8 watchdog_last_time;
1030 u8 watchdog_check_reset_cnt;
1032 //+by amy 080515 for dynamic mechenism
1033 //Add by amy Tx Power Control for Near/Far Range 2008/05/15
1034 bool bDynamicTxHighPower; // Tx high power state
1035 bool bDynamicTxLowPower; // Tx low power state
1036 bool bLastDTPFlag_High;
1037 bool bLastDTPFlag_Low;
1039 /* OFDM RSSI. For high power or not */
1040 u8 phy_check_reg824;
1041 u32 phy_reg824_bit9;
1043 //Add by amy for Rate Adaptive
1044 rate_adaptive rate_adaptive;
1045 //Add by amy for TX power tracking
1046 //2008/05/15 Mars OPEN/CLOSE TX POWER TRACKING
1047 const txbbgain_struct * txbbgain_table;
1048 u8 txpower_count;//For 6 sec do tracking again
1049 bool btxpower_trackingInit;
1052 u8 Record_CCK_20Mindex;
1053 u8 Record_CCK_40Mindex;
1054 //2007/09/10 Mars Add CCK TX Power Tracking
1055 const ccktxbbgain_struct *cck_txbbgain_table;
1056 const ccktxbbgain_struct *cck_txbbgain_ch14_table;
1057 u8 rfa_txpowertrackingindex;
1058 u8 rfa_txpowertrackingindex_real;
1059 u8 rfa_txpowertracking_default;
1060 u8 rfc_txpowertrackingindex;
1061 u8 rfc_txpowertrackingindex_real;
1062 u8 rfc_txpowertracking_default;
1063 bool btxpower_tracking;
1066 //For Backup Initial Gain
1067 init_gain initgain_backup;
1068 u8 DefaultInitialGain[4];
1069 // For EDCA Turbo mode, Added by amy 080515.
1070 bool bis_any_nonbepkts;
1071 bool bcurrent_turbo_EDCA;
1073 bool bis_cur_rdlstate;
1074 struct timer_list fsync_timer;
1076 u32 rateCountDiffRecord;
1077 u32 ContiuneDiffCount;
1082 u8 framesyncMonitor;
1088 //by amy for reset_count
1091 //by amy for silent reset
1092 RESET_TYPE ResetProgress;
1093 bool bForcedSilentReset;
1094 bool bDisableNormalResetCheck;
1097 int IrpPendingCount;
1098 bool bResetInProgress;
1100 u8 InitialGainOperateType;
1102 //define work item by amy 080526
1103 struct delayed_work update_beacon_wq;
1104 struct delayed_work watch_dog_wq;
1105 struct delayed_work txpower_tracking_wq;
1106 struct delayed_work rfpath_check_wq;
1107 struct delayed_work gpio_change_rf_wq;
1108 struct delayed_work initialgain_operate_wq;
1109 struct workqueue_struct *priv_wq;
1112 bool init_firmware(struct r8192_priv *priv);
1113 u32 read_cam(struct r8192_priv *priv, u8 addr);
1114 void write_cam(struct r8192_priv *priv, u8 addr, u32 data);
1115 u8 read_nic_byte(struct r8192_priv *priv, int x);
1116 u32 read_nic_dword(struct r8192_priv *priv, int x);
1117 u16 read_nic_word(struct r8192_priv *priv, int x) ;
1118 void write_nic_byte(struct r8192_priv *priv, int x,u8 y);
1119 void write_nic_word(struct r8192_priv *priv, int x,u16 y);
1120 void write_nic_dword(struct r8192_priv *priv, int x,u32 y);
1122 int rtl8192_down(struct net_device *dev);
1123 int rtl8192_up(struct net_device *dev);
1124 void rtl8192_commit(struct r8192_priv *priv);
1125 void write_phy(struct net_device *dev, u8 adr, u8 data);
1126 void CamResetAllEntry(struct r8192_priv *priv);
1127 void EnableHWSecurityConfig8192(struct r8192_priv *priv);
1128 void setKey(struct r8192_priv *priv, u8 EntryNo, u8 KeyIndex, u16 KeyType,
1129 const u8 *MacAddr, u8 DefaultKey, u32 *KeyContent);
1130 void firmware_init_param(struct r8192_priv *priv);
1131 RT_STATUS cmpk_message_handle_tx(struct r8192_priv *priv, u8 *codevirtualaddress, u32 packettype, u32 buffer_len);
1134 void IPSEnter(struct r8192_priv *priv);
1135 void IPSLeave(struct r8192_priv *priv);
1136 void IPSLeave_wq(struct work_struct *work);
1137 void ieee80211_ips_leave_wq(struct ieee80211_device *ieee80211);
1138 void ieee80211_ips_leave(struct ieee80211_device *ieee80211);
1141 void LeisurePSEnter(struct ieee80211_device *ieee80211);
1142 void LeisurePSLeave(struct ieee80211_device *ieee80211);
1145 bool NicIFEnableNIC(struct r8192_priv *priv);
1146 bool NicIFDisableNIC(struct r8192_priv *priv);
1148 void PHY_SetRtl8192eRfOff(struct r8192_priv *priv);