2 *************************************************************************
4 * 5F., No.36, Taiyuan St., Jhubei City,
8 * (c) Copyright 2002-2007, Ralink Technology, Inc.
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 *************************************************************************
31 Ralink Wireless Chip MAC related definition & structures
35 Justin P. Mattock 11/07/2010 Fix a comments, and typos
36 -------- ---------- ----------------------------------------------
39 #ifndef __RTMP_MAC_H__
40 #define __RTMP_MAC_H__
42 /* ================================================================================= */
43 /* TX / RX ring descriptor format */
44 /* ================================================================================= */
46 /* the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO. */
47 /* MAC block uses this TXINFO to control the transmission behavior of this frame. */
53 /* TXD Wireless Information format for Tx ring and Mgmt Ring */
55 /*txop : for txop mode */
56 /* 0:txop for the MPDU frame will be handles by ASIC by register */
57 /* 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS */
58 struct PACKED rt_txwi {
60 /* ex: 00 03 00 40 means txop = 3, PHYMODE = 1 */
61 u32 FRAG:1; /* 1 to inform TKIP engine this is a fragment. */
62 u32 MIMOps:1; /* the remote peer is in dynamic MIMO-PS mode */
68 u32 txop:2; /*FOR "THIS" frame. 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful. */
72 u32 BW:1; /*channel bandwidth 20MHz or 40 MHz */
74 u32 STBC:2; /* 1: STBC support MCS =0-7, 2,3 : RESERVE */
76 /* u32 rsv2:2; //channel bandwidth 20MHz or 40 MHz */
81 /* ex: 1c ff 38 00 means ACK=0, BAWinSize=7, MPDUtotalByteCount = 0x38 */
86 u32 MPDUtotalByteCount:12;
95 /* RXWI wireless information format, in PBF. invisible in driver. */
97 struct PACKED rt_rxwi {
103 u32 MPDUtotalByteCount:12;
113 u32 PHYMODE:2; /* 1: this RX frame is unicast to me */
122 u32 FOFFSET:8; /* RT35xx */
127 /* ================================================================================= */
128 /* Register format */
129 /* ================================================================================= */
132 /* SCH/DMA registers - base address 0x0200 */
134 /* INT_SOURCE_CSR: Interrupt source register. Write one to clear corresponding bit */
136 #define DMA_CSR0 0x200
137 #define INT_SOURCE_CSR 0x200
138 typedef union _INT_SOURCE_CSR_STRUC {
143 u32 Ac0DmaDone:1; /*4 */
147 u32 HccaDmaDone:1; /* bit7 */
149 u32 MCUCommandINT:1; /*bit 9 */
153 u32 TXFifoStatusInt:1; /*FIFO Statistics is full, sw should read 0x171c */
154 u32 AutoWakeup:1; /*bit14 */
156 u32 RxCoherent:1; /*bit16 */
161 } INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;
164 /* INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF */
166 #define INT_MASK_CSR 0x204
167 typedef union _INT_MASK_CSR_STRUC {
169 u32 RXDelay_INT_MSK:1;
184 } INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;
186 #define WPDMA_GLO_CFG 0x208
187 typedef union _WPDMA_GLO_CFG_STRUC {
193 u32 WPDMABurstSIZE:2;
194 u32 EnTXWriteBackDDONE:1;
200 } WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;
202 #define WPDMA_RST_IDX 0x20c
203 typedef union _WPDMA_RST_IDX_STRUC {
216 } WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;
217 #define DELAY_INT_CFG 0x0210
218 typedef union _DELAY_INT_CFG_STRUC {
228 } DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;
229 #define WMM_AIFSN_CFG 0x0214
230 typedef union _AIFSN_CSR_STRUC {
232 u32 Aifsn0:4; /* for AC_BE */
233 u32 Aifsn1:4; /* for AC_BK */
234 u32 Aifsn2:4; /* for AC_VI */
235 u32 Aifsn3:4; /* for AC_VO */
239 } AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;
241 /* CWMIN_CSR: CWmin for each EDCA AC */
243 #define WMM_CWMIN_CFG 0x0218
244 typedef union _CWMIN_CSR_STRUC {
246 u32 Cwmin0:4; /* for AC_BE */
247 u32 Cwmin1:4; /* for AC_BK */
248 u32 Cwmin2:4; /* for AC_VI */
249 u32 Cwmin3:4; /* for AC_VO */
253 } CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
256 /* CWMAX_CSR: CWmin for each EDCA AC */
258 #define WMM_CWMAX_CFG 0x021c
259 typedef union _CWMAX_CSR_STRUC {
261 u32 Cwmax0:4; /* for AC_BE */
262 u32 Cwmax1:4; /* for AC_BK */
263 u32 Cwmax2:4; /* for AC_VI */
264 u32 Cwmax3:4; /* for AC_VO */
268 } CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
271 /* AC_TXOP_CSR0: AC_BK/AC_BE TXOP register */
273 #define WMM_TXOP0_CFG 0x0220
274 typedef union _AC_TXOP_CSR0_STRUC {
276 u16 Ac0Txop; /* for AC_BK, in unit of 32us */
277 u16 Ac1Txop; /* for AC_BE, in unit of 32us */
280 } AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
283 /* AC_TXOP_CSR1: AC_VO/AC_VI TXOP register */
285 #define WMM_TXOP1_CFG 0x0224
286 typedef union _AC_TXOP_CSR1_STRUC {
288 u16 Ac2Txop; /* for AC_VI, in unit of 32us */
289 u16 Ac3Txop; /* for AC_VO, in unit of 32us */
292 } AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
294 #define RINGREG_DIFF 0x10
295 #define GPIO_CTRL_CFG 0x0228 /*MAC_CSR13 */
296 #define MCU_CMD_CFG 0x022c
297 #define TX_BASE_PTR0 0x0230 /*AC_BK base address */
298 #define TX_MAX_CNT0 0x0234
299 #define TX_CTX_IDX0 0x0238
300 #define TX_DTX_IDX0 0x023c
301 #define TX_BASE_PTR1 0x0240 /*AC_BE base address */
302 #define TX_MAX_CNT1 0x0244
303 #define TX_CTX_IDX1 0x0248
304 #define TX_DTX_IDX1 0x024c
305 #define TX_BASE_PTR2 0x0250 /*AC_VI base address */
306 #define TX_MAX_CNT2 0x0254
307 #define TX_CTX_IDX2 0x0258
308 #define TX_DTX_IDX2 0x025c
309 #define TX_BASE_PTR3 0x0260 /*AC_VO base address */
310 #define TX_MAX_CNT3 0x0264
311 #define TX_CTX_IDX3 0x0268
312 #define TX_DTX_IDX3 0x026c
313 #define TX_BASE_PTR4 0x0270 /*HCCA base address */
314 #define TX_MAX_CNT4 0x0274
315 #define TX_CTX_IDX4 0x0278
316 #define TX_DTX_IDX4 0x027c
317 #define TX_BASE_PTR5 0x0280 /*MGMT base address */
318 #define TX_MAX_CNT5 0x0284
319 #define TX_CTX_IDX5 0x0288
320 #define TX_DTX_IDX5 0x028c
321 #define TX_MGMTMAX_CNT TX_MAX_CNT5
322 #define TX_MGMTCTX_IDX TX_CTX_IDX5
323 #define TX_MGMTDTX_IDX TX_DTX_IDX5
324 #define RX_BASE_PTR 0x0290 /*RX base address */
325 #define RX_MAX_CNT 0x0294
326 #define RX_CRX_IDX 0x0298
327 #define RX_DRX_IDX 0x029c
329 #define USB_DMA_CFG 0x02a0
330 typedef union _USB_DMA_CFG_STRUC {
332 u32 RxBulkAggTOut:8; /*Rx Bulk Aggregation TimeOut in unit of 33ns */
333 u32 RxBulkAggLmt:8; /*Rx Bulk Aggregation Limit in unit of 256 bytes */
334 u32 phyclear:1; /*phy watch dog enable. write 1 */
336 u32 TxClear:1; /*Clear USB DMA TX path */
337 u32 TxopHalt:1; /*Halt TXOP count down when TX buffer is full. */
338 u32 RxBulkAggEn:1; /*Enable Rx Bulk Aggregation */
339 u32 RxBulkEn:1; /*Enable USB DMA Rx */
340 u32 TxBulkEn:1; /*Enable USB DMA Tx */
341 u32 EpoutValid:6; /*OUT endpoint data valid */
342 u32 RxBusy:1; /*USB DMA RX FSM busy */
343 u32 TxBusy:1; /*USB DMA TX FSM busy */
346 } USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
349 /* 3 PBF registers */
352 /* Most are for debug. Driver doesn't touch PBF register. */
353 #define PBF_SYS_CTRL 0x0400
354 #define PBF_CFG 0x0408
355 #define PBF_MAX_PCNT 0x040C
356 #define PBF_CTRL 0x0410
357 #define PBF_INT_STA 0x0414
358 #define PBF_INT_ENA 0x0418
359 #define TXRXQ_PCNT 0x0438
360 #define PBF_DBG 0x043c
361 #define PBF_CAP_CTRL 0x0440
364 #ifdef RTMP_EFUSE_SUPPORT
365 /* eFuse registers */
366 #define EFUSE_CTRL 0x0580
367 #define EFUSE_DATA0 0x0590
368 #define EFUSE_DATA1 0x0594
369 #define EFUSE_DATA2 0x0598
370 #define EFUSE_DATA3 0x059c
371 #endif /* RTMP_EFUSE_SUPPORT // */
372 #endif /* RT30xx // */
374 #define OSC_CTRL 0x5a4
375 #define PCIE_PHY_TX_ATTENUATION_CTRL 0x05C8
376 #define LDO_CFG0 0x05d4
377 #define GPIO_SWITCH 0x05dc
380 /* 4 MAC registers */
383 /* 4.1 MAC SYSTEM configuration registers (offset:0x1000) */
385 #define MAC_CSR0 0x1000
386 typedef union _ASIC_VER_ID_STRUC {
388 u16 ASICRev; /* reversion : 0 */
389 u16 ASICVer; /* version : 2860 */
392 } ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
393 #define MAC_SYS_CTRL 0x1004 /*MAC_CSR1 */
394 #define MAC_ADDR_DW0 0x1008 /* MAC ADDR DW0 */
395 #define MAC_ADDR_DW1 0x100c /* MAC ADDR DW1 */
397 /* MAC_CSR2: STA MAC register 0 */
399 typedef union _MAC_DW0_STRUC {
401 u8 Byte0; /* MAC address byte 0 */
402 u8 Byte1; /* MAC address byte 1 */
403 u8 Byte2; /* MAC address byte 2 */
404 u8 Byte3; /* MAC address byte 3 */
407 } MAC_DW0_STRUC, *PMAC_DW0_STRUC;
410 /* MAC_CSR3: STA MAC register 1 */
412 typedef union _MAC_DW1_STRUC {
414 u8 Byte4; /* MAC address byte 4 */
415 u8 Byte5; /* MAC address byte 5 */
420 } MAC_DW1_STRUC, *PMAC_DW1_STRUC;
422 #define MAC_BSSID_DW0 0x1010 /* MAC BSSID DW0 */
423 #define MAC_BSSID_DW1 0x1014 /* MAC BSSID DW1 */
426 /* MAC_CSR5: BSSID register 1 */
428 typedef union _MAC_CSR5_STRUC {
430 u8 Byte4; /* BSSID byte 4 */
431 u8 Byte5; /* BSSID byte 5 */
432 u16 BssIdMask:2; /* 0: one BSSID, 10: 4 BSSID, 01: 2 BSSID , 11: 8BSSID */
437 } MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
439 #define MAX_LEN_CFG 0x1018 /* rt2860b max 16k bytes. bit12:13 Maximum PSDU length (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16 */
440 #define BBP_CSR_CFG 0x101c /* */
442 /* BBP_CSR_CFG: BBP serial control register */
444 typedef union _BBP_CSR_CFG_STRUC {
446 u32 Value:8; /* Register value to program into BBP */
447 u32 RegNum:8; /* Selected BBP register */
448 u32 fRead:1; /* 0: Write BBP, 1: Read BBP */
449 u32 Busy:1; /* 1: ASIC is busy execute BBP programming. */
450 u32 BBP_PAR_DUR:1; /* 0: 4 MAC clock cycles 1: 8 MAC clock cycles */
451 u32 BBP_RW_MODE:1; /* 0: use serial mode 1:parallel */
455 } BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
456 #define RF_CSR_CFG0 0x1020
458 /* RF_CSR_CFG: RF control register */
460 typedef union _RF_CSR_CFG0_STRUC {
462 u32 RegIdAndContent:24; /* Register value to program into BBP */
463 u32 bitwidth:5; /* Selected BBP register */
464 u32 StandbyMode:1; /* 0: high when stand by 1: low when standby */
465 u32 Sel:1; /* 0:RF_LE0 activate 1:RF_LE1 activate */
466 u32 Busy:1; /* 0: idle 1: 8busy */
469 } RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
470 #define RF_CSR_CFG1 0x1024
471 typedef union _RF_CSR_CFG1_STRUC {
473 u32 RegIdAndContent:24; /* Register value to program into BBP */
474 u32 RFGap:5; /* Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec) */
475 u32 rsv:7; /* 0: idle 1: 8busy */
478 } RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
479 #define RF_CSR_CFG2 0x1028 /* */
480 typedef union _RF_CSR_CFG2_STRUC {
482 u32 RegIdAndContent:24; /* Register value to program into BBP */
483 u32 rsv:8; /* 0: idle 1: 8busy */
486 } RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
487 #define LED_CFG 0x102c /* MAC_CSR14 */
488 typedef union _LED_CFG_STRUC {
490 u32 OnPeriod:8; /* blinking on period unit 1ms */
491 u32 OffPeriod:8; /* blinking off period unit 1ms */
492 u32 SlowBlinkPeriod:6; /* slow blinking period. unit:1ms */
494 u32 RLedMode:2; /* red Led Mode 0: off1: blinking upon TX2: periodic slow blinking3: always on */
495 u32 GLedMode:2; /* green Led Mode */
496 u32 YLedMode:2; /* yellow Led Mode */
497 u32 LedPolar:1; /* Led Polarity. 0: active low1: active high */
501 } LED_CFG_STRUC, *PLED_CFG_STRUC;
503 /* 4.2 MAC TIMING configuration registers (offset:0x1100) */
505 #define XIFS_TIME_CFG 0x1100 /* MAC_CSR8 MAC_CSR9 */
506 typedef union _IFS_SLOT_CFG_STRUC {
508 u32 CckmSifsTime:8; /* unit 1us. Applied after CCK RX/TX */
509 u32 OfdmSifsTime:8; /* unit 1us. Applied after OFDM RX/TX */
510 u32 OfdmXifsTime:4; /*OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND */
511 u32 EIFS:9; /* unit 1us */
512 u32 BBRxendEnable:1; /* reference RXEND signal to begin XIFS defer */
516 } IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
518 #define BKOFF_SLOT_CFG 0x1104 /* mac_csr9 last 8 bits */
519 #define NAV_TIME_CFG 0x1108 /* NAV (MAC_CSR15) */
520 #define CH_TIME_CFG 0x110C /* Count as channel busy */
521 #define PBF_LIFE_TIMER 0x1110 /*TX/RX MPDU timestamp timer (free run)Unit: 1us */
522 #define BCN_TIME_CFG 0x1114 /* TXRX_CSR9 */
524 #define BCN_OFFSET0 0x042C
525 #define BCN_OFFSET1 0x0430
528 /* BCN_TIME_CFG : Synchronization control register */
530 typedef union _BCN_TIME_CFG_STRUC {
532 u32 BeaconInterval:16; /* in unit of 1/16 TU */
533 u32 bTsfTicking:1; /* Enable TSF auto counting */
534 u32 TsfSyncMode:2; /* Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode */
536 u32 bBeaconGen:1; /* Enable beacon generator */
538 u32 TxTimestampCompensate:8;
541 } BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
542 #define TBTT_SYNC_CFG 0x1118 /* txrx_csr10 */
543 #define TSF_TIMER_DW0 0x111C /* Local TSF timer lsb 32 bits. Read-only */
544 #define TSF_TIMER_DW1 0x1120 /* msb 32 bits. Read-only. */
545 #define TBTT_TIMER 0x1124 /* TImer remains till next TBTT. Read-only. TXRX_CSR14 */
546 #define INT_TIMER_CFG 0x1128 /* */
547 #define INT_TIMER_EN 0x112c /* GP-timer and pre-tbtt Int enable */
548 #define CH_IDLE_STA 0x1130 /* channel idle time */
549 #define CH_BUSY_STA 0x1134 /* channle busy time */
551 /* 4.2 MAC POWER configuration registers (offset:0x1200) */
553 #define MAC_STATUS_CFG 0x1200 /* old MAC_CSR12 */
554 #define PWR_PIN_CFG 0x1204 /* old MAC_CSR12 */
555 #define AUTO_WAKEUP_CFG 0x1208 /* old MAC_CSR10 */
557 /* AUTO_WAKEUP_CFG: Manual power control / status register */
559 typedef union _AUTO_WAKEUP_STRUC {
562 u32 NumofSleepingTbtt:7; /* ForceWake has high privilege than PutToSleep when both set */
563 u32 EnableAutoWakeup:1; /* 0:sleep, 1:awake */
567 } AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
569 /* 4.3 MAC TX configuration registers (offset:0x1300) */
572 #define EDCA_AC0_CFG 0x1300 /*AC_TXOP_CSR0 0x3474 */
573 #define EDCA_AC1_CFG 0x1304
574 #define EDCA_AC2_CFG 0x1308
575 #define EDCA_AC3_CFG 0x130c
576 typedef union _EDCA_AC_CFG_STRUC {
578 u32 AcTxop:8; /* in unit of 32us */
579 u32 Aifsn:4; /* # of slot time */
581 u32 Cwmax:4; /*unit power of 2 */
585 } EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
587 #define EDCA_TID_AC_MAP 0x1310
588 #define TX_PWR_CFG_0 0x1314
589 #define TX_PWR_CFG_1 0x1318
590 #define TX_PWR_CFG_2 0x131C
591 #define TX_PWR_CFG_3 0x1320
592 #define TX_PWR_CFG_4 0x1324
593 #define TX_PIN_CFG 0x1328
594 #define TX_BAND_CFG 0x132c /* 0x1 use upper 20MHz. 0 juse lower 20MHz */
595 #define TX_SW_CFG0 0x1330
596 #define TX_SW_CFG1 0x1334
597 #define TX_SW_CFG2 0x1338
598 #define TXOP_THRES_CFG 0x133c
599 #define TXOP_CTRL_CFG 0x1340
600 #define TX_RTS_CFG 0x1344
602 typedef union _TX_RTS_CFG_STRUC {
604 u32 AutoRtsRetryLimit:8;
605 u32 RtsThres:16; /* unit:byte */
606 u32 RtsFbkEn:1; /* enable rts rate fallback */
607 u32 rsv:7; /* 1: HT non-STBC control frame enable */
610 } TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
611 #define TX_TIMEOUT_CFG 0x1348
612 typedef union _TX_TIMEOUT_CFG_STRUC {
615 u32 MpduLifeTime:4; /* expiration time = 2^(9+MPDU LIFE TIME) us */
616 u32 RxAckTimeout:8; /* unit:slot. Used for TX precedure */
617 u32 TxopTimeout:8; /*TXOP timeout value for TXOP truncation. It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT) */
618 u32 rsv2:8; /* 1: HT non-STBC control frame enable */
621 } TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
622 #define TX_RTY_CFG 0x134c
623 typedef union PACKED _TX_RTY_CFG_STRUC {
625 u32 ShortRtyLimit:8; /* short retry limit */
626 u32 LongRtyLimit:8; /* long retry limit */
627 u32 LongRtyThre:12; /* Long retry threshold */
628 u32 NonAggRtyMode:1; /* Non-Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer */
629 u32 AggRtyMode:1; /* Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer */
630 u32 TxautoFBEnable:1; /* Tx retry PHY rate auto fallback enable */
631 u32 rsv:1; /* 1: HT non-STBC control frame enable */
634 } TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
635 #define TX_LINK_CFG 0x1350
636 typedef union PACKED _TX_LINK_CFG_STRUC {
638 u32 RemoteMFBLifeTime:8; /*remote MFB life time. unit : 32us */
639 u32 MFBEnable:1; /* TX apply remote MFB 1:enable */
640 u32 RemoteUMFSEnable:1; /* remote unsolicit MFB enable. 0: not apply remote remote unsolicit (MFS=7) */
641 u32 TxMRQEn:1; /* MCS request TX enable */
642 u32 TxRDGEn:1; /* RDG TX enable */
643 u32 TxCFAckEn:1; /* Piggyback CF-ACK enable */
645 u32 RemotMFB:8; /* remote MCS feedback */
646 u32 RemotMFS:8; /*remote MCS feedback sequence number */
649 } TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
650 #define HT_FBK_CFG0 0x1354
651 typedef union PACKED _HT_FBK_CFG0_STRUC {
663 } HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
664 #define HT_FBK_CFG1 0x1358
665 typedef union _HT_FBK_CFG1_STRUC {
677 } HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
678 #define LG_FBK_CFG0 0x135c
679 typedef union _LG_FBK_CFG0_STRUC {
681 u32 OFDMMCS0FBK:4; /*initial value is 0 */
682 u32 OFDMMCS1FBK:4; /*initial value is 0 */
683 u32 OFDMMCS2FBK:4; /*initial value is 1 */
684 u32 OFDMMCS3FBK:4; /*initial value is 2 */
685 u32 OFDMMCS4FBK:4; /*initial value is 3 */
686 u32 OFDMMCS5FBK:4; /*initial value is 4 */
687 u32 OFDMMCS6FBK:4; /*initial value is 5 */
688 u32 OFDMMCS7FBK:4; /*initial value is 6 */
691 } LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
692 #define LG_FBK_CFG1 0x1360
693 typedef union _LG_FBK_CFG1_STRUC {
695 u32 CCKMCS0FBK:4; /*initial value is 0 */
696 u32 CCKMCS1FBK:4; /*initial value is 0 */
697 u32 CCKMCS2FBK:4; /*initial value is 1 */
698 u32 CCKMCS3FBK:4; /*initial value is 2 */
702 } LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
704 /*======================================================= */
705 /*================ Protection Paramater================================ */
706 /*======================================================= */
707 #define CCK_PROT_CFG 0x1364 /*CCK Protection */
708 #define ASIC_SHORTNAV 1
709 #define ASIC_longNAV 2
712 typedef union _PROT_CFG_STRUC {
714 u32 ProtectRate:16; /*Protection control frame rate for CCK TX(RTS/CTS/CFEnd). */
715 u32 ProtectCtrl:2; /*Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv */
716 u32 ProtectNav:2; /*TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect, 2:LongNAVProtect, 3:rsv */
717 u32 TxopAllowCck:1; /*CCK TXOP allowance.0:disallow. */
718 u32 TxopAllowOfdm:1; /*CCK TXOP allowance.0:disallow. */
719 u32 TxopAllowMM20:1; /*CCK TXOP allowance. 0:disallow. */
720 u32 TxopAllowMM40:1; /*CCK TXOP allowance.0:disallow. */
721 u32 TxopAllowGF20:1; /*CCK TXOP allowance.0:disallow. */
722 u32 TxopAllowGF40:1; /*CCK TXOP allowance.0:disallow. */
723 u32 RTSThEn:1; /*RTS threshold enable on CCK TX */
727 } PROT_CFG_STRUC, *PPROT_CFG_STRUC;
729 #define OFDM_PROT_CFG 0x1368 /*OFDM Protection */
730 #define MM20_PROT_CFG 0x136C /*MM20 Protection */
731 #define MM40_PROT_CFG 0x1370 /*MM40 Protection */
732 #define GF20_PROT_CFG 0x1374 /*GF20 Protection */
733 #define GF40_PROT_CFG 0x1378 /*GR40 Protection */
734 #define EXP_CTS_TIME 0x137C /* */
735 #define EXP_ACK_TIME 0x1380 /* */
738 /* 4.4 MAC RX configuration registers (offset:0x1400) */
740 #define RX_FILTR_CFG 0x1400 /*TXRX_CSR0 */
741 #define AUTO_RSP_CFG 0x1404 /*TXRX_CSR4 */
743 /* TXRX_CSR4: Auto-Responder/ */
745 typedef union _AUTO_RSP_CFG_STRUC {
747 u32 AutoResponderEnable:1;
748 u32 BACAckPolicyEnable:1; /* 0:long, 1:short preamble */
749 u32 CTS40MMode:1; /* Response CTS 40MHz duplicate mode */
750 u32 CTS40MRef:1; /* Response CTS 40MHz duplicate mode */
751 u32 AutoResponderPreamble:1; /* 0:long, 1:short preamble */
752 u32 rsv:1; /* Power bit value in conrtrol frame */
753 u32 DualCTSEn:1; /* Power bit value in conrtrol frame */
754 u32 AckCtsPsmBit:1; /* Power bit value in conrtrol frame */
758 } AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
760 #define LEGACY_BASIC_RATE 0x1408 /* TXRX_CSR5 0x3054 */
761 #define HT_BASIC_RATE 0x140c
762 #define HT_CTRL_CFG 0x1410
763 #define SIFS_COST_CFG 0x1414
764 #define RX_PARSER_CFG 0x1418 /*Set NAV for all received frames */
767 /* 4.5 MAC Security configuration (offset:0x1500) */
769 #define TX_SEC_CNT0 0x1500 /* */
770 #define RX_SEC_CNT0 0x1504 /* */
771 #define CCMP_FC_MUTE 0x1508 /* */
773 /* 4.6 HCCA/PSMP (offset:0x1600) */
775 #define TXOP_HLDR_ADDR0 0x1600
776 #define TXOP_HLDR_ADDR1 0x1604
777 #define TXOP_HLDR_ET 0x1608
778 #define QOS_CFPOLL_RA_DW0 0x160c
779 #define QOS_CFPOLL_A1_DW1 0x1610
780 #define QOS_CFPOLL_QC 0x1614
782 /* 4.7 MAC Statistis registers (offset:0x1700) */
784 #define RX_STA_CNT0 0x1700 /* */
785 #define RX_STA_CNT1 0x1704 /* */
786 #define RX_STA_CNT2 0x1708 /* */
789 /* RX_STA_CNT0_STRUC: RX PLCP error count & RX CRC error count */
791 typedef union _RX_STA_CNT0_STRUC {
797 } RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC;
800 /* RX_STA_CNT1_STRUC: RX False CCA count & RX long frame count */
802 typedef union _RX_STA_CNT1_STRUC {
808 } RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC;
811 /* RX_STA_CNT2_STRUC: */
813 typedef union _RX_STA_CNT2_STRUC {
816 u16 RxFifoOverflowCount;
819 } RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC;
820 #define TX_STA_CNT0 0x170C /* */
822 /* STA_CSR3: TX Beacon count */
824 typedef union _TX_STA_CNT0_STRUC {
830 } TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC;
831 #define TX_STA_CNT1 0x1710 /* */
833 /* TX_STA_CNT1: TX tx count */
835 typedef union _TX_STA_CNT1_STRUC {
841 } TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC;
842 #define TX_STA_CNT2 0x1714 /* */
844 /* TX_STA_CNT2: TX tx count */
846 typedef union _TX_STA_CNT2_STRUC {
849 u16 TxUnderFlowCount;
852 } TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC;
853 #define TX_STA_FIFO 0x1718 /* */
855 /* TX_STA_FIFO_STRUC: TX Result for specific PID status fifo register */
857 typedef union PACKED _TX_STA_FIFO_STRUC {
859 u32 bValid:1; /* 1:This register contains a valid TX result */
861 u32 TxSuccess:1; /* Tx No retry success */
862 u32 TxAggre:1; /* Tx Retry Success */
863 u32 TxAckRequired:1; /* Tx fail */
864 u32 wcid:8; /*wireless client index */
865 /* u32 SuccessRate:16; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16. */
866 u32 SuccessRate:13; /*include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16. */
871 } TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC;
873 #define TX_AGG_CNT 0x171c
874 typedef union _TX_AGG_CNT_STRUC {
880 } TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC;
882 #define TX_AGG_CNT0 0x1720
883 typedef union _TX_AGG_CNT0_STRUC {
889 } TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC;
891 #define TX_AGG_CNT1 0x1724
892 typedef union _TX_AGG_CNT1_STRUC {
898 } TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC;
899 #define TX_AGG_CNT2 0x1728
900 typedef union _TX_AGG_CNT2_STRUC {
906 } TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC;
908 #define TX_AGG_CNT3 0x172c
909 typedef union _TX_AGG_CNT3_STRUC {
915 } TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC;
917 #define TX_AGG_CNT4 0x1730
918 typedef union _TX_AGG_CNT4_STRUC {
924 } TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC;
925 #define TX_AGG_CNT5 0x1734
926 typedef union _TX_AGG_CNT5_STRUC {
932 } TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC;
933 #define TX_AGG_CNT6 0x1738
934 typedef union _TX_AGG_CNT6_STRUC {
940 } TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC;
941 #define TX_AGG_CNT7 0x173c
942 typedef union _TX_AGG_CNT7_STRUC {
948 } TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC;
949 #define MPDU_DENSITY_CNT 0x1740
950 typedef union _MPDU_DEN_CNT_STRUC {
952 u16 TXZeroDelCount; /*TX zero length delimiter count */
953 u16 RXZeroDelCount; /*RX zero length delimiter count */
956 } MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC;
958 /* TXRX control registers - base address 0x3000 */
960 /* rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first.. */
961 #define TXRX_CSR1 0x77d0
964 /* Security key table memory, base address = 0x1000 */
966 #define MAC_WCID_BASE 0x1800 /*8-bytes(use only 6-bytes) * 256 entry = */
967 #define HW_WCID_ENTRY_SIZE 8
968 #define PAIRWISE_KEY_TABLE_BASE 0x4000 /* 32-byte * 256-entry = -byte */
969 #define HW_KEY_ENTRY_SIZE 0x20
970 #define PAIRWISE_IVEIV_TABLE_BASE 0x6000 /* 8-byte * 256-entry = -byte */
971 #define MAC_IVEIV_TABLE_BASE 0x6000 /* 8-byte * 256-entry = -byte */
972 #define HW_IVEIV_ENTRY_SIZE 8
973 #define MAC_WCID_ATTRIBUTE_BASE 0x6800 /* 4-byte * 256-entry = -byte */
974 #define HW_WCID_ATTRI_SIZE 4
975 #define WCID_RESERVED 0x6bfc
976 #define SHARED_KEY_TABLE_BASE 0x6c00 /* 32-byte * 16-entry = 512-byte */
977 #define SHARED_KEY_MODE_BASE 0x7000 /* 32-byte * 16-entry = 512-byte */
978 #define HW_SHARED_KEY_MODE_SIZE 4
979 #define SHAREDKEYTABLE 0
980 #define PAIRWISEKEYTABLE 1
982 typedef union _SHAREDKEY_MODE_STRUC {
984 u32 Bss0Key0CipherAlg:3;
986 u32 Bss0Key1CipherAlg:3;
988 u32 Bss0Key2CipherAlg:3;
990 u32 Bss0Key3CipherAlg:3;
992 u32 Bss1Key0CipherAlg:3;
994 u32 Bss1Key1CipherAlg:3;
996 u32 Bss1Key2CipherAlg:3;
998 u32 Bss1Key3CipherAlg:3;
1002 } SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
1004 /* 8-byte per entry, 64-entry for pairwise key table */
1005 struct rt_hw_wcid_entry {
1010 /* ================================================================================= */
1012 /* ================================================================================= */
1013 /*7.1 WCID ENTRY format : 8bytes */
1014 struct rt_wcid_entry {
1015 u8 RXBABitmap7; /* bit0 for TID8, bit7 for TID 15 */
1016 u8 RXBABitmap0; /* bit0 for TID0, bit7 for TID 7 */
1017 u8 MAC[6]; /* 0 for shared key table. 1 for pairwise key table */
1020 /*8.1.1 SECURITY KEY format : 8DW */
1021 /* 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table */
1022 struct rt_hw_key_entry {
1028 /*8.1.2 IV/EIV format : 2DW */
1030 /*8.1.3 RX attribute entry format : 1DW */
1031 struct rt_mac_attribute {
1032 u32 KeyTab:1; /* 0 for shared key table. 1 for pairwise key table */
1034 u32 BSSIDIdx:3; /*multipleBSS index for the WCID */
1039 /* ================================================================================= */
1040 /* HOST-MCU communication data structure */
1041 /* ================================================================================= */
1044 /* H2M_MAILBOX_CSR: Host-to-MCU Mailbox */
1046 typedef union _H2M_MAILBOX_STRUC {
1054 } H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
1057 /* M2H_CMD_DONE_CSR: MCU-to-Host command complete indication */
1059 typedef union _M2H_CMD_DONE_STRUC {
1067 } M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
1069 /*NAV_TIME_CFG :NAV */
1070 typedef union _NAV_TIME_CFG_STRUC {
1072 u8 Sifs; /* in unit of 1-us */
1073 u8 SlotTime; /* in unit of 1-us */
1074 u16 Eifs:9; /* in unit of 1-us */
1075 u16 ZeroSifs:1; /* Applied zero SIFS timer after OFDM RX 0: disable */
1079 } NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
1082 /* RX_FILTR_CFG: /RX configuration register */
1084 typedef union _RX_FILTR_CFG_STRUC {
1086 u32 DropCRCErr:1; /* Drop CRC error */
1087 u32 DropPhyErr:1; /* Drop physical error */
1088 u32 DropNotToMe:1; /* Drop not to me unicast frame */
1089 u32 DropNotMyBSSID:1; /* Drop fram ToDs bit is true */
1091 u32 DropVerErr:1; /* Drop version error frame */
1092 u32 DropMcast:1; /* Drop multicast frames */
1093 u32 DropBcast:1; /* Drop broadcast frames */
1094 u32 DropDuplicate:1; /* Drop duplicate frame */
1096 u32 DropCFEndAck:1; /* Drop Ps-Poll */
1097 u32 DropCFEnd:1; /* Drop Ps-Poll */
1098 u32 DropAck:1; /* Drop Ps-Poll */
1099 u32 DropCts:1; /* Drop Ps-Poll */
1101 u32 DropRts:1; /* Drop Ps-Poll */
1102 u32 DropPsPoll:1; /* Drop Ps-Poll */
1104 u32 DropBAR:1; /* */
1106 u32 DropRsvCntlType:1;
1110 } RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
1113 /* PHY_CSR4: RF serial control register */
1115 typedef union _PHY_CSR4_STRUC {
1117 u32 RFRegValue:24; /* Register value (include register id) serial out to RF/IF chip. */
1118 u32 NumberOfBits:5; /* Number of bits used in RFRegValue (I:20, RFMD:22) */
1119 u32 IFSelect:1; /* 1: select IF to program, 0: select RF to program */
1120 u32 PLL_LD:1; /* RF PLL_LD status */
1121 u32 Busy:1; /* 1: ASIC is busy execute RF programming. */
1124 } PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
1127 /* SEC_CSR5: shared key table security mode register */
1129 typedef union _SEC_CSR5_STRUC {
1131 u32 Bss2Key0CipherAlg:3;
1133 u32 Bss2Key1CipherAlg:3;
1135 u32 Bss2Key2CipherAlg:3;
1137 u32 Bss2Key3CipherAlg:3;
1139 u32 Bss3Key0CipherAlg:3;
1141 u32 Bss3Key1CipherAlg:3;
1143 u32 Bss3Key2CipherAlg:3;
1145 u32 Bss3Key3CipherAlg:3;
1149 } SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
1152 /* HOST_CMD_CSR: For HOST to interrupt embedded processor */
1154 typedef union _HOST_CMD_CSR_STRUC {
1160 } HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
1163 /* AIFSN_CSR: AIFSN for each EDCA AC */
1167 /* E2PROM_CSR: EEPROM control register */
1169 typedef union _E2PROM_CSR_STRUC {
1171 u32 Reload:1; /* Reload EEPROM content, write one to reload, self-cleared. */
1176 u32 Type:1; /* 1: 93C46, 0:93C66 */
1177 u32 LoadStatus:1; /* 1:loading, 0:done */
1181 } E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
1184 /* QOS_CSR0: TXOP holder address0 register */
1186 typedef union _QOS_CSR0_STRUC {
1188 u8 Byte0; /* MAC address byte 0 */
1189 u8 Byte1; /* MAC address byte 1 */
1190 u8 Byte2; /* MAC address byte 2 */
1191 u8 Byte3; /* MAC address byte 3 */
1194 } QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
1197 /* QOS_CSR1: TXOP holder address1 register */
1199 typedef union _QOS_CSR1_STRUC {
1201 u8 Byte4; /* MAC address byte 4 */
1202 u8 Byte5; /* MAC address byte 5 */
1207 } QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
1209 #define RF_CSR_CFG 0x500
1210 typedef union _RF_CSR_CFG_STRUC {
1212 u32 RF_CSR_DATA:8; /* DATA */
1213 u32 TESTCSR_RFACC_REGNUM:5; /* RF register ID */
1214 u32 Rsvd2:3; /* Reserved */
1215 u32 RF_CSR_WR:1; /* 0: read 1: write */
1216 u32 RF_CSR_KICK:1; /* kick RF register read/write */
1217 u32 Rsvd1:14; /* Reserved */
1220 } RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
1223 /* Other on-chip shared memory space, base = 0x2000 */
1226 /* CIS space - base address = 0x2000 */
1227 #define HW_CIS_BASE 0x2000
1229 /* Carrier-sense CTS frame base address. It's where mac stores carrier-sense frame for carrier-sense function. */
1230 #define HW_CS_CTS_BASE 0x7700
1231 /* DFS CTS frame base address. It's where mac stores CTS frame for DFS. */
1232 #define HW_DFS_CTS_BASE 0x7780
1233 #define HW_CTS_FRAME_SIZE 0x80
1235 /* 2004-11-08 john - since NULL frame won't be that long (256 byte). We steal 16 tail bytes */
1236 /* to save debugging settings */
1237 #define HW_DEBUG_SETTING_BASE 0x77f0 /* 0x77f0~0x77ff total 16 bytes */
1238 #define HW_DEBUG_SETTING_BASE2 0x7770 /* 0x77f0~0x77ff total 16 bytes */
1240 /* In order to support maximum 8 MBSS and its maximum length is 512 for each beacon */
1241 /* Three section discontinue memory segments will be used. */
1242 /* 1. The original region for BCN 0~3 */
1243 /* 2. Extract memory from FCE table for BCN 4~5 */
1244 /* 3. Extract memory from Pair-wise key table for BCN 6~7 */
1245 /* It occupied those memory of wcid 238~253 for BCN 6 */
1246 /* and wcid 222~237 for BCN 7 */
1247 #define HW_BEACON_MAX_SIZE 0x1000 /* unit: byte */
1248 #define HW_BEACON_BASE0 0x7800
1249 #define HW_BEACON_BASE1 0x7A00
1250 #define HW_BEACON_BASE2 0x7C00
1251 #define HW_BEACON_BASE3 0x7E00
1252 #define HW_BEACON_BASE4 0x7200
1253 #define HW_BEACON_BASE5 0x7400
1254 #define HW_BEACON_BASE6 0x5DC0
1255 #define HW_BEACON_BASE7 0x5BC0
1257 #define HW_BEACON_MAX_COUNT 8
1258 #define HW_BEACON_OFFSET 0x0200
1259 #define HW_BEACON_CONTENT_LEN (HW_BEACON_OFFSET - TXWI_SIZE)
1261 /* HOST-MCU shared memory - base address = 0x2100 */
1262 #define HOST_CMD_CSR 0x404
1263 #define H2M_MAILBOX_CSR 0x7010
1264 #define H2M_MAILBOX_CID 0x7014
1265 #define H2M_MAILBOX_STATUS 0x701c
1266 #define H2M_INT_SRC 0x7024
1267 #define H2M_BBP_AGENT 0x7028
1268 #define M2H_CMD_DONE_CSR 0x000c
1269 #define MCU_TXOP_ARRAY_BASE 0x000c /* TODO: to be provided by Albert */
1270 #define MCU_TXOP_ENTRY_SIZE 32 /* TODO: to be provided by Albert */
1271 #define MAX_NUM_OF_TXOP_ENTRY 16 /* TODO: must be same with 8051 firmware */
1272 #define MCU_MBOX_VERSION 0x01 /* TODO: to be confirmed by Albert */
1273 #define MCU_MBOX_VERSION_OFFSET 5 /* TODO: to be provided by Albert */
1276 /* Host DMA registers - base address 0x200 . TX0-3=EDCAQid0-3, TX4=HCCA, TX5=MGMT, */
1279 /* DMA RING DESCRIPTOR */
1281 #define E2PROM_CSR 0x0004
1282 #define IO_CNTL_CSR 0x77d0
1284 /* ================================================================ */
1285 /* Tx / Rx / Mgmt ring descriptor definition */
1286 /* ================================================================ */
1288 /* the following PID values are used to mark outgoing frame type in TXD->PID so that */
1289 /* proper TX statistics can be collected based on these categories */
1290 /* b3-2 of PID field - */
1291 #define PID_MGMT 0x05
1292 #define PID_BEACON 0x0c
1293 #define PID_DATA_NORMALUCAST 0x02
1294 #define PID_DATA_AMPDU 0x04
1295 #define PID_DATA_NO_ACK 0x08
1296 #define PID_DATA_NOT_NORM_ACK 0x03
1297 /* value domain of pTxD->HostQId (4-bit: 0~15) */
1298 #define QID_AC_BK 1 /* meet ACI definition in 802.11e */
1299 #define QID_AC_BE 0 /* meet ACI definition in 802.11e */
1303 #define NUM_OF_TX_RING 4
1306 #define QID_OTHER 15
1308 #endif /* __RTMP_MAC_H__ // */