drivers/staging/iio/accel/lis3l02dq_ring.c

   1 #include <linux/interrupt.h>
   2 #include <linux/gpio.h>
   3 #include <linux/mutex.h>
   4 #include <linux/kernel.h>
   5 #include <linux/spi/spi.h>
   6 #include <linux/slab.h>
   7
   8 #include "../iio.h"
   9 #include "../ring_sw.h"
  10 #include "../kfifo_buf.h"
  11 #include "../trigger.h"
  12 #include "../trigger_consumer.h"
  13 #include "lis3l02dq.h"
  14
  15 /**
  16  * combine_8_to_16() utility function to munge to u8s into u16
  17  **/
  18 static inline u16 combine_8_to_16(u8 lower, u8 upper)
  19 {
  20         u16 _lower = lower;
  21         u16 _upper = upper;
  22         return _lower | (_upper << 8);
  23 }
  24
  25 /**
  26  * lis3l02dq_data_rdy_trig_poll() the event handler for the data rdy trig
  27  **/
  28 irqreturn_t lis3l02dq_data_rdy_trig_poll(int irq, void *private)
  29 {
  30         struct iio_dev *indio_dev = private;
  31         struct lis3l02dq_state *st = iio_priv(indio_dev);
  32
  33         if (st->trigger_on) {
  34                 iio_trigger_poll(st->trig, iio_get_time_ns());
  35                 return IRQ_HANDLED;
  36         } else
  37                 return IRQ_WAKE_THREAD;
  38 }
  39
  40 /**
  41  * lis3l02dq_read_accel_from_ring() individual acceleration read from ring
  42  **/
  43 ssize_t lis3l02dq_read_accel_from_ring(struct iio_ring_buffer *ring,
  44                                        int index,
  45                                        int *val)
  46 {
  47         int ret;
  48         s16 *data;
  49
  50         if (!iio_scan_mask_query(ring, index))
  51                 return -EINVAL;
  52
  53         if (!ring->access->read_last)
  54                 return -EBUSY;
  55
  56         data = kmalloc(ring->access->get_bytes_per_datum(ring),
  57                        GFP_KERNEL);
  58         if (data == NULL)
  59                 return -ENOMEM;
  60
  61         ret = ring->access->read_last(ring, (u8 *)data);
  62         if (ret)
  63                 goto error_free_data;
  64         *val = data[bitmap_weight(&ring->scan_mask, index)];
  65 error_free_data:
  66         kfree(data);
  67
  68         return ret;
  69 }
  70
  71 static const u8 read_all_tx_array[] = {
  72         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_L_ADDR), 0,
  73         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_H_ADDR), 0,
  74         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_L_ADDR), 0,
  75         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_H_ADDR), 0,
  76         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_L_ADDR), 0,
  77         LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_H_ADDR), 0,
  78 };
  79
  80 /**
  81  * lis3l02dq_read_all() Reads all channels currently selected
  82  * @st:         device specific state
  83  * @rx_array:   (dma capable) receive array, must be at least
  84  *              4*number of channels
  85  **/
  86 static int lis3l02dq_read_all(struct iio_dev *indio_dev, u8 *rx_array)
  87 {
  88         struct iio_ring_buffer *ring = indio_dev->ring;
  89         struct lis3l02dq_state *st = iio_priv(indio_dev);
  90         struct spi_transfer *xfers;
  91         struct spi_message msg;
  92         int ret, i, j = 0;
  93
  94         xfers = kzalloc((ring->scan_count) * 2
  95                         * sizeof(*xfers), GFP_KERNEL);
  96         if (!xfers)
  97                 return -ENOMEM;
  98
  99         mutex_lock(&st->buf_lock);
 100
 101         for (i = 0; i < ARRAY_SIZE(read_all_tx_array)/4; i++)
 102                 if (ring->scan_mask & (1 << i)) {
 103                         /* lower byte */
 104                         xfers[j].tx_buf = st->tx + 2*j;
 105                         st->tx[2*j] = read_all_tx_array[i*4];
 106                         st->tx[2*j + 1] = 0;
 107                         if (rx_array)
 108                                 xfers[j].rx_buf = rx_array + j*2;
 109                         xfers[j].bits_per_word = 8;
 110                         xfers[j].len = 2;
 111                         xfers[j].cs_change = 1;
 112                         j++;
 113
 114                         /* upper byte */
 115                         xfers[j].tx_buf = st->tx + 2*j;
 116                         st->tx[2*j] = read_all_tx_array[i*4 + 2];
 117                         st->tx[2*j + 1] = 0;
 118                         if (rx_array)
 119                                 xfers[j].rx_buf = rx_array + j*2;
 120                         xfers[j].bits_per_word = 8;
 121                         xfers[j].len = 2;
 122                         xfers[j].cs_change = 1;
 123                         j++;
 124                 }
 125
 126         /* After these are transmitted, the rx_buff should have
 127          * values in alternate bytes
 128          */
 129         spi_message_init(&msg);
 130         for (j = 0; j < ring->scan_count * 2; j++)
 131                 spi_message_add_tail(&xfers[j], &msg);
 132
 133         ret = spi_sync(st->us, &msg);
 134         mutex_unlock(&st->buf_lock);
 135         kfree(xfers);
 136
 137         return ret;
 138 }
 139
 140 static int lis3l02dq_get_ring_element(struct iio_dev *indio_dev,
 141                                 u8 *buf)
 142 {
 143         int ret, i;
 144         u8 *rx_array ;
 145         s16 *data = (s16 *)buf;
 146
 147         rx_array = kzalloc(4 * (indio_dev->ring->scan_count), GFP_KERNEL);
 148         if (rx_array == NULL)
 149                 return -ENOMEM;
 150         ret = lis3l02dq_read_all(indio_dev, rx_array);
 151         if (ret < 0)
 152                 return ret;
 153         for (i = 0; i < indio_dev->ring->scan_count; i++)
 154                 data[i] = combine_8_to_16(rx_array[i*4+1],
 155                                         rx_array[i*4+3]);
 156         kfree(rx_array);
 157
 158         return i*sizeof(data[0]);
 159 }
 160
 161 static irqreturn_t lis3l02dq_trigger_handler(int irq, void *p)
 162 {
 163         struct iio_poll_func *pf = p;
 164         struct iio_dev *indio_dev = pf->indio_dev;
 165         struct iio_ring_buffer *ring = indio_dev->ring;
 166         int len = 0;
 167         size_t datasize = ring->access->get_bytes_per_datum(ring);
 168         char *data = kmalloc(datasize, GFP_KERNEL);
 169
 170         if (data == NULL) {
 171                 dev_err(indio_dev->dev.parent,
 172                         "memory alloc failed in ring bh");
 173                 return -ENOMEM;
 174         }
 175
 176         if (ring->scan_count)
 177                 len = lis3l02dq_get_ring_element(indio_dev, data);
 178
 179           /* Guaranteed to be aligned with 8 byte boundary */
 180         if (ring->scan_timestamp)
 181                 *(s64 *)(((phys_addr_t)data + len
 182                                 + sizeof(s64) - 1) & ~(sizeof(s64) - 1))
 183                         = pf->timestamp;
 184         ring->access->store_to(ring, (u8 *)data, pf->timestamp);
 185
 186         iio_trigger_notify_done(indio_dev->trig);
 187         kfree(data);
 188         return IRQ_HANDLED;
 189 }
 190
 191 /* Caller responsible for locking as necessary. */
 192 static int
 193 __lis3l02dq_write_data_ready_config(struct device *dev, bool state)
 194 {
 195         int ret;
 196         u8 valold;
 197         bool currentlyset;
 198         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 199         struct lis3l02dq_state *st = iio_priv(indio_dev);
 200
 201 /* Get the current event mask register */
 202         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 203                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 204                                        &valold);
 205         if (ret)
 206                 goto error_ret;
 207 /* Find out if data ready is already on */
 208         currentlyset
 209                 = valold & LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
 210
 211 /* Disable requested */
 212         if (!state && currentlyset) {
 213                 /* disable the data ready signal */
 214                 valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
 215
 216                 /* The double write is to overcome a hardware bug?*/
 217                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 218                                                 LIS3L02DQ_REG_CTRL_2_ADDR,
 219                                                 valold);
 220                 if (ret)
 221                         goto error_ret;
 222                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 223                                                 LIS3L02DQ_REG_CTRL_2_ADDR,
 224                                                 valold);
 225                 if (ret)
 226                         goto error_ret;
 227                 st->trigger_on = false;
 228 /* Enable requested */
 229         } else if (state && !currentlyset) {
 230                 /* if not set, enable requested */
 231                 /* first disable all events */
 232                 ret = lis3l02dq_disable_all_events(indio_dev);
 233                 if (ret < 0)
 234                         goto error_ret;
 235
 236                 valold = ret |
 237                         LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
 238
 239                 st->trigger_on = true;
 240                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 241                                                 LIS3L02DQ_REG_CTRL_2_ADDR,
 242                                                 valold);
 243                 if (ret)
 244                         goto error_ret;
 245         }
 246
 247         return 0;
 248 error_ret:
 249         return ret;
 250 }
 251
 252 /**
 253  * lis3l02dq_data_rdy_trigger_set_state() set datardy interrupt state
 254  *
 255  * If disabling the interrupt also does a final read to ensure it is clear.
 256  * This is only important in some cases where the scan enable elements are
 257  * switched before the ring is reenabled.
 258  **/
 259 static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
 260                                                 bool state)
 261 {
 262         struct iio_dev *indio_dev = trig->private_data;
 263         int ret = 0;
 264         u8 t;
 265
 266         __lis3l02dq_write_data_ready_config(&indio_dev->dev, state);
 267         if (state == false) {
 268                 /*
 269                  * A possible quirk with teh handler is currently worked around
 270                  *  by ensuring outstanding read events are cleared.
 271                  */
 272                 ret = lis3l02dq_read_all(indio_dev, NULL);
 273         }
 274         lis3l02dq_spi_read_reg_8(indio_dev,
 275                                  LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
 276                                  &t);
 277         return ret;
 278 }
 279
 280 /**
 281  * lis3l02dq_trig_try_reen() try renabling irq for data rdy trigger
 282  * @trig:       the datardy trigger
 283  */
 284 static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
 285 {
 286         struct iio_dev *indio_dev = trig->private_data;
 287         struct lis3l02dq_state *st = iio_priv(indio_dev);
 288         int i;
 289
 290         /* If gpio still high (or high again) */
 291         /* In theory possible we will need to do this several times */
 292         for (i = 0; i < 5; i++)
 293                 if (gpio_get_value(irq_to_gpio(st->us->irq)))
 294                         lis3l02dq_read_all(indio_dev, NULL);
 295                 else
 296                         break;
 297         if (i == 5)
 298                 printk(KERN_INFO
 299                        "Failed to clear the interrupt for lis3l02dq\n");
 300
 301         /* irq reenabled so success! */
 302         return 0;
 303 }
 304
 305 static const struct iio_trigger_ops lis3l02dq_trigger_ops = {
 306         .owner = THIS_MODULE,
 307         .set_trigger_state = &lis3l02dq_data_rdy_trigger_set_state,
 308         .try_reenable = &lis3l02dq_trig_try_reen,
 309 };
 310
 311 int lis3l02dq_probe_trigger(struct iio_dev *indio_dev)
 312 {
 313         int ret;
 314         struct lis3l02dq_state *st = iio_priv(indio_dev);
 315
 316         st->trig = iio_allocate_trigger("lis3l02dq-dev%d", indio_dev->id);
 317         if (!st->trig) {
 318                 ret = -ENOMEM;
 319                 goto error_ret;
 320         }
 321
 322         st->trig->dev.parent = &st->us->dev;
 323         st->trig->ops = &lis3l02dq_trigger_ops;
 324         st->trig->private_data = indio_dev;
 325         ret = iio_trigger_register(st->trig);
 326         if (ret)
 327                 goto error_free_trig;
 328
 329         return 0;
 330
 331 error_free_trig:
 332         iio_free_trigger(st->trig);
 333 error_ret:
 334         return ret;
 335 }
 336
 337 void lis3l02dq_remove_trigger(struct iio_dev *indio_dev)
 338 {
 339         struct lis3l02dq_state *st = iio_priv(indio_dev);
 340
 341         iio_trigger_unregister(st->trig);
 342         iio_free_trigger(st->trig);
 343 }
 344
 345 void lis3l02dq_unconfigure_ring(struct iio_dev *indio_dev)
 346 {
 347         iio_dealloc_pollfunc(indio_dev->pollfunc);
 348         lis3l02dq_free_buf(indio_dev->ring);
 349 }
 350
 351 static int lis3l02dq_ring_postenable(struct iio_dev *indio_dev)
 352 {
 353         /* Disable unwanted channels otherwise the interrupt will not clear */
 354         u8 t;
 355         int ret;
 356         bool oneenabled = false;
 357
 358         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 359                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 360                                        &t);
 361         if (ret)
 362                 goto error_ret;
 363
 364         if (iio_scan_mask_query(indio_dev->ring, 0)) {
 365                 t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
 366                 oneenabled = true;
 367         } else
 368                 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
 369         if (iio_scan_mask_query(indio_dev->ring, 1)) {
 370                 t |= LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
 371                 oneenabled = true;
 372         } else
 373                 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
 374         if (iio_scan_mask_query(indio_dev->ring, 2)) {
 375                 t |= LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
 376                 oneenabled = true;
 377         } else
 378                 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
 379
 380         if (!oneenabled) /* what happens in this case is unknown */
 381                 return -EINVAL;
 382         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 383                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 384                                         t);
 385         if (ret)
 386                 goto error_ret;
 387
 388         return iio_triggered_ring_postenable(indio_dev);
 389 error_ret:
 390         return ret;
 391 }
 392
 393 /* Turn all channels on again */
 394 static int lis3l02dq_ring_predisable(struct iio_dev *indio_dev)
 395 {
 396         u8 t;
 397         int ret;
 398
 399         ret = iio_triggered_ring_predisable(indio_dev);
 400         if (ret)
 401                 goto error_ret;
 402
 403         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 404                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 405                                        &t);
 406         if (ret)
 407                 goto error_ret;
 408         t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE |
 409                 LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE |
 410                 LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
 411
 412         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 413                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 414                                         t);
 415
 416 error_ret:
 417         return ret;
 418 }
 419
 420 static const struct iio_ring_setup_ops lis3l02dq_ring_setup_ops = {
 421         .preenable = &iio_sw_ring_preenable,
 422         .postenable = &lis3l02dq_ring_postenable,
 423         .predisable = &lis3l02dq_ring_predisable,
 424 };
 425
 426 int lis3l02dq_configure_ring(struct iio_dev *indio_dev)
 427 {
 428         int ret;
 429         struct iio_ring_buffer *ring;
 430
 431         ring = lis3l02dq_alloc_buf(indio_dev);
 432         if (!ring)
 433                 return -ENOMEM;
 434
 435         indio_dev->ring = ring;
 436         /* Effectively select the ring buffer implementation */
 437         indio_dev->ring->access = &lis3l02dq_access_funcs;
 438         ring->bpe = 2;
 439
 440         ring->scan_timestamp = true;
 441         ring->setup_ops = &lis3l02dq_ring_setup_ops;
 442         ring->owner = THIS_MODULE;
 443
 444         /* Functions are NULL as we set handler below */
 445         indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
 446                                                  &lis3l02dq_trigger_handler,
 447                                                  0,
 448                                                  indio_dev,
 449                                                  "lis3l02dq_consumer%d",
 450                                                  indio_dev->id);
 451
 452         if (indio_dev->pollfunc == NULL) {
 453                 ret = -ENOMEM;
 454                 goto error_iio_sw_rb_free;
 455         }
 456
 457         indio_dev->modes |= INDIO_RING_TRIGGERED;
 458         return 0;
 459
 460 error_iio_sw_rb_free:
 461         lis3l02dq_free_buf(indio_dev->ring);
 462         return ret;
 463 }