drivers/staging/iio/accel/lis3l02dq_core.c

   1 /*
   2  * lis3l02dq.c  support STMicroelectronics LISD02DQ
   3  *              3d 2g Linear Accelerometers via SPI
   4  *
   5  * Copyright (c) 2007 Jonathan Cameron <jic23@cam.ac.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Settings:
  12  * 16 bit left justified mode used.
  13  */
  14
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/gpio.h>
  18 #include <linux/workqueue.h>
  19 #include <linux/mutex.h>
  20 #include <linux/device.h>
  21 #include <linux/kernel.h>
  22 #include <linux/spi/spi.h>
  23
  24 #include <linux/sysfs.h>
  25 #include <linux/list.h>
  26
  27 #include "../iio.h"
  28 #include "../sysfs.h"
  29 #include "accel.h"
  30
  31 #include "lis3l02dq.h"
  32
  33 /* At the moment the spi framework doesn't allow global setting of cs_change.
  34  * It's in the likely to be added comment at the top of spi.h.
  35  * This means that use cannot be made of spi_write etc.
  36  */
  37
  38 /**
  39  * lis3l02dq_spi_read_reg_8() - read single byte from a single register
  40  * @dev: device asosciated with child of actual device (iio_dev or iio_trig)
  41  * @reg_address: the address of the register to be read
  42  * @val: pass back the resulting value
  43  **/
  44 int lis3l02dq_spi_read_reg_8(struct device *dev, u8 reg_address, u8 *val)
  45 {
  46         int ret;
  47         struct spi_message msg;
  48         struct iio_dev *indio_dev = dev_get_drvdata(dev);
  49         struct lis3l02dq_state *st = iio_dev_get_devdata(indio_dev);
  50         struct spi_transfer xfer = {
  51                 .tx_buf = st->tx,
  52                 .rx_buf = st->rx,
  53                 .bits_per_word = 8,
  54                 .len = 2,
  55                 .cs_change = 1,
  56         };
  57
  58         mutex_lock(&st->buf_lock);
  59         st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
  60         st->tx[1] = 0;
  61
  62         spi_message_init(&msg);
  63         spi_message_add_tail(&xfer, &msg);
  64         ret = spi_sync(st->us, &msg);
  65         *val = st->rx[1];
  66         mutex_unlock(&st->buf_lock);
  67
  68         return ret;
  69 }
  70
  71 /**
  72  * lis3l02dq_spi_write_reg_8() - write single byte to a register
  73  * @dev: device associated with child of actual device (iio_dev or iio_trig)
  74  * @reg_address: the address of the register to be writen
  75  * @val: the value to write
  76  **/
  77 int lis3l02dq_spi_write_reg_8(struct device *dev,
  78                               u8 reg_address,
  79                               u8 *val)
  80 {
  81         int ret;
  82         struct spi_message msg;
  83         struct iio_dev *indio_dev = dev_get_drvdata(dev);
  84         struct lis3l02dq_state *st = iio_dev_get_devdata(indio_dev);
  85         struct spi_transfer xfer = {
  86                 .tx_buf = st->tx,
  87                 .bits_per_word = 8,
  88                 .len = 2,
  89                 .cs_change = 1,
  90         };
  91
  92         mutex_lock(&st->buf_lock);
  93         st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
  94         st->tx[1] = *val;
  95
  96         spi_message_init(&msg);
  97         spi_message_add_tail(&xfer, &msg);
  98         ret =  spi_sync(st->us, &msg);
  99         mutex_unlock(&st->buf_lock);
 100
 101         return ret;
 102 }
 103
 104 /**
 105  * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
 106  * @dev: device associated with child of actual device (iio_dev or iio_trig)
 107  * @reg_address: the address of the lower of the two registers. Second register
 108  *               is assumed to have address one greater.
 109  * @val: value to be written
 110  **/
 111 static int lis3l02dq_spi_write_reg_s16(struct device *dev,
 112                                        u8 lower_reg_address,
 113                                        s16 value)
 114 {
 115         int ret;
 116         struct spi_message msg;
 117         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 118         struct lis3l02dq_state *st = iio_dev_get_devdata(indio_dev);
 119         struct spi_transfer xfers[] = { {
 120                         .tx_buf = st->tx,
 121                         .bits_per_word = 8,
 122                         .len = 2,
 123                         .cs_change = 1,
 124                 }, {
 125                         .tx_buf = st->tx + 2,
 126                         .bits_per_word = 8,
 127                         .len = 2,
 128                         .cs_change = 1,
 129                 },
 130         };
 131
 132         mutex_lock(&st->buf_lock);
 133         st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
 134         st->tx[1] = value & 0xFF;
 135         st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
 136         st->tx[3] = (value >> 8) & 0xFF;
 137
 138         spi_message_init(&msg);
 139         spi_message_add_tail(&xfers[0], &msg);
 140         spi_message_add_tail(&xfers[1], &msg);
 141         ret = spi_sync(st->us, &msg);
 142         mutex_unlock(&st->buf_lock);
 143
 144         return ret;
 145 }
 146
 147 /**
 148  * lisl302dq_spi_read_reg_s16() - write 2 bytes to a pair of registers
 149  * @dev: device associated with child of actual device (iio_dev or iio_trig)
 150  * @reg_address: the address of the lower of the two registers. Second register
 151  *               is assumed to have address one greater.
 152  * @val: somewhere to pass back the value read
 153  **/
 154 static int lis3l02dq_spi_read_reg_s16(struct device *dev,
 155                                       u8 lower_reg_address,
 156                                       s16 *val)
 157 {
 158         struct spi_message msg;
 159         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 160         struct lis3l02dq_state *st = iio_dev_get_devdata(indio_dev);
 161         int ret;
 162         struct spi_transfer xfers[] = { {
 163                         .tx_buf = st->tx,
 164                         .rx_buf = st->rx,
 165                         .bits_per_word = 8,
 166                         .len = 2,
 167                         .cs_change = 1,
 168                 }, {
 169                         .tx_buf = st->tx + 2,
 170                         .rx_buf = st->rx + 2,
 171                         .bits_per_word = 8,
 172                         .len = 2,
 173                         .cs_change = 1,
 174
 175                 },
 176         };
 177
 178         mutex_lock(&st->buf_lock);
 179         st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
 180         st->tx[1] = 0;
 181         st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address+1);
 182         st->tx[3] = 0;
 183
 184         spi_message_init(&msg);
 185         spi_message_add_tail(&xfers[0], &msg);
 186         spi_message_add_tail(&xfers[1], &msg);
 187         ret = spi_sync(st->us, &msg);
 188         if (ret) {
 189                 dev_err(&st->us->dev, "problem when reading 16 bit register");
 190                 goto error_ret;
 191         }
 192         *val = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
 193
 194 error_ret:
 195         mutex_unlock(&st->buf_lock);
 196         return ret;
 197 }
 198
 199 /**
 200  * lis3l02dq_read_signed() - attribute function used for 8 bit signed values
 201  * @dev: the child device associated with the iio_dev or iio_trigger
 202  * @attr: the attribute being processed
 203  * @buf: buffer into which put the output string
 204  **/
 205 static ssize_t lis3l02dq_read_signed(struct device *dev,
 206                                      struct device_attribute *attr,
 207                                      char *buf)
 208 {
 209         int ret;
 210         s8 val;
 211         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 212
 213         ret = lis3l02dq_spi_read_reg_8(dev, this_attr->address, (u8 *)&val);
 214
 215         return ret ? ret : sprintf(buf, "%d\n", val);
 216 }
 217
 218 static ssize_t lis3l02dq_read_unsigned(struct device *dev,
 219                                        struct device_attribute *attr,
 220                                        char *buf)
 221 {
 222         int ret;
 223         u8 val;
 224         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 225
 226         ret = lis3l02dq_spi_read_reg_8(dev, this_attr->address, &val);
 227
 228         return ret ? ret : sprintf(buf, "%d\n", val);
 229 }
 230
 231 static ssize_t lis3l02dq_write_signed(struct device *dev,
 232                                       struct device_attribute *attr,
 233                                       const char *buf,
 234                                       size_t len)
 235 {
 236         long valin;
 237         s8 val;
 238         int ret;
 239         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 240
 241         ret = strict_strtol(buf, 10, &valin);
 242         if (ret)
 243                 goto error_ret;
 244         val = valin;
 245         ret = lis3l02dq_spi_write_reg_8(dev, this_attr->address, (u8 *)&val);
 246
 247 error_ret:
 248         return ret ? ret : len;
 249 }
 250
 251 static ssize_t lis3l02dq_write_unsigned(struct device *dev,
 252                                         struct device_attribute *attr,
 253                                         const char *buf,
 254                                         size_t len)
 255 {
 256         int ret;
 257         ulong valin;
 258         u8 val;
 259         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 260
 261         ret = strict_strtoul(buf, 10, &valin);
 262         if (ret)
 263                 goto err_ret;
 264         val = valin;
 265         ret = lis3l02dq_spi_write_reg_8(dev, this_attr->address, &val);
 266
 267 err_ret:
 268         return ret ? ret : len;
 269 }
 270
 271 static ssize_t lis3l02dq_read_16bit_signed(struct device *dev,
 272                                            struct device_attribute *attr,
 273                                            char *buf)
 274 {
 275         int ret;
 276         s16 val = 0;
 277         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 278
 279         ret = lis3l02dq_spi_read_reg_s16(dev, this_attr->address, &val);
 280
 281         if (ret)
 282                 return ret;
 283
 284         return sprintf(buf, "%d\n", val);
 285 }
 286
 287 static ssize_t lis3l02dq_read_accel(struct device *dev,
 288                                     struct device_attribute *attr,
 289                                     char *buf)
 290 {
 291         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 292         ssize_t ret;
 293
 294         /* Take the iio_dev status lock */
 295         mutex_lock(&indio_dev->mlock);
 296         if (indio_dev->currentmode == INDIO_RING_TRIGGERED)
 297                 ret = lis3l02dq_read_accel_from_ring(dev, attr, buf);
 298         else
 299                 ret =  lis3l02dq_read_16bit_signed(dev, attr, buf);
 300         mutex_unlock(&indio_dev->mlock);
 301
 302         return ret;
 303 }
 304
 305 static ssize_t lis3l02dq_write_16bit_signed(struct device *dev,
 306                                             struct device_attribute *attr,
 307                                             const char *buf,
 308                                             size_t len)
 309 {
 310         struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
 311         int ret;
 312         long val;
 313
 314         ret = strict_strtol(buf, 10, &val);
 315         if (ret)
 316                 goto error_ret;
 317         ret = lis3l02dq_spi_write_reg_s16(dev, this_attr->address, val);
 318
 319 error_ret:
 320         return ret ? ret : len;
 321 }
 322
 323 static ssize_t lis3l02dq_read_frequency(struct device *dev,
 324                                         struct device_attribute *attr,
 325                                         char *buf)
 326 {
 327         int ret, len = 0;
 328         s8 t;
 329         ret = lis3l02dq_spi_read_reg_8(dev,
 330                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 331                                        (u8 *)&t);
 332         if (ret)
 333                 return ret;
 334         t &= LIS3L02DQ_DEC_MASK;
 335         switch (t) {
 336         case LIS3L02DQ_REG_CTRL_1_DF_128:
 337                 len = sprintf(buf, "280\n");
 338                 break;
 339         case LIS3L02DQ_REG_CTRL_1_DF_64:
 340                 len = sprintf(buf, "560\n");
 341                 break;
 342         case LIS3L02DQ_REG_CTRL_1_DF_32:
 343                 len = sprintf(buf, "1120\n");
 344                 break;
 345         case LIS3L02DQ_REG_CTRL_1_DF_8:
 346                 len = sprintf(buf, "4480\n");
 347                 break;
 348         }
 349         return len;
 350 }
 351
 352 static ssize_t lis3l02dq_write_frequency(struct device *dev,
 353                                          struct device_attribute *attr,
 354                                          const char *buf,
 355                                          size_t len)
 356 {
 357         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 358         long val;
 359         int ret;
 360         u8 t;
 361
 362         ret = strict_strtol(buf, 10, &val);
 363         if (ret)
 364                 return ret;
 365
 366         mutex_lock(&indio_dev->mlock);
 367         ret = lis3l02dq_spi_read_reg_8(dev,
 368                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 369                                        &t);
 370         if (ret)
 371                 goto error_ret_mutex;
 372         /* Wipe the bits clean */
 373         t &= ~LIS3L02DQ_DEC_MASK;
 374         switch (val) {
 375         case 280:
 376                 t |= LIS3L02DQ_REG_CTRL_1_DF_128;
 377                 break;
 378         case 560:
 379                 t |= LIS3L02DQ_REG_CTRL_1_DF_64;
 380                 break;
 381         case 1120:
 382                 t |= LIS3L02DQ_REG_CTRL_1_DF_32;
 383                 break;
 384         case 4480:
 385                 t |= LIS3L02DQ_REG_CTRL_1_DF_8;
 386                 break;
 387         default:
 388                 ret = -EINVAL;
 389                 goto error_ret_mutex;
 390         };
 391
 392         ret = lis3l02dq_spi_write_reg_8(dev,
 393                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 394                                         &t);
 395
 396 error_ret_mutex:
 397         mutex_unlock(&indio_dev->mlock);
 398
 399         return ret ? ret : len;
 400 }
 401
 402 static int lis3l02dq_initial_setup(struct lis3l02dq_state *st)
 403 {
 404         int ret;
 405         u8 val, valtest;
 406
 407         st->us->mode = SPI_MODE_3;
 408
 409         spi_setup(st->us);
 410
 411         val = LIS3L02DQ_DEFAULT_CTRL1;
 412         /* Write suitable defaults to ctrl1 */
 413         ret = lis3l02dq_spi_write_reg_8(&st->indio_dev->dev,
 414                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 415                                         &val);
 416         if (ret) {
 417                 dev_err(&st->us->dev, "problem with setup control register 1");
 418                 goto err_ret;
 419         }
 420         /* Repeat as sometimes doesn't work first time?*/
 421         ret = lis3l02dq_spi_write_reg_8(&st->indio_dev->dev,
 422                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 423                                         &val);
 424         if (ret) {
 425                 dev_err(&st->us->dev, "problem with setup control register 1");
 426                 goto err_ret;
 427         }
 428
 429         /* Read back to check this has worked acts as loose test of correct
 430          * chip */
 431         ret = lis3l02dq_spi_read_reg_8(&st->indio_dev->dev,
 432                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 433                                        &valtest);
 434         if (ret || (valtest != val)) {
 435                 dev_err(&st->indio_dev->dev, "device not playing ball");
 436                 ret = -EINVAL;
 437                 goto err_ret;
 438         }
 439
 440         val = LIS3L02DQ_DEFAULT_CTRL2;
 441         ret = lis3l02dq_spi_write_reg_8(&st->indio_dev->dev,
 442                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 443                                         &val);
 444         if (ret) {
 445                 dev_err(&st->us->dev, "problem with setup control register 2");
 446                 goto err_ret;
 447         }
 448
 449         val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
 450         ret = lis3l02dq_spi_write_reg_8(&st->indio_dev->dev,
 451                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 452                                         &val);
 453         if (ret)
 454                 dev_err(&st->us->dev, "problem with interrupt cfg register");
 455 err_ret:
 456
 457         return ret;
 458 }
 459
 460 static IIO_DEV_ATTR_ACCEL_X_OFFSET(S_IWUSR | S_IRUGO,
 461                                    lis3l02dq_read_signed,
 462                                    lis3l02dq_write_signed,
 463                                    LIS3L02DQ_REG_OFFSET_X_ADDR);
 464
 465 static IIO_DEV_ATTR_ACCEL_Y_OFFSET(S_IWUSR | S_IRUGO,
 466                                    lis3l02dq_read_signed,
 467                                    lis3l02dq_write_signed,
 468                                    LIS3L02DQ_REG_OFFSET_Y_ADDR);
 469
 470 static IIO_DEV_ATTR_ACCEL_Z_OFFSET(S_IWUSR | S_IRUGO,
 471                                    lis3l02dq_read_signed,
 472                                    lis3l02dq_write_signed,
 473                                    LIS3L02DQ_REG_OFFSET_Z_ADDR);
 474
 475 static IIO_DEV_ATTR_ACCEL_X_GAIN(S_IWUSR | S_IRUGO,
 476                                  lis3l02dq_read_unsigned,
 477                                  lis3l02dq_write_unsigned,
 478                                  LIS3L02DQ_REG_GAIN_X_ADDR);
 479
 480 static IIO_DEV_ATTR_ACCEL_Y_GAIN(S_IWUSR | S_IRUGO,
 481                                  lis3l02dq_read_unsigned,
 482                                  lis3l02dq_write_unsigned,
 483                                  LIS3L02DQ_REG_GAIN_Y_ADDR);
 484
 485 static IIO_DEV_ATTR_ACCEL_Z_GAIN(S_IWUSR | S_IRUGO,
 486                                  lis3l02dq_read_unsigned,
 487                                  lis3l02dq_write_unsigned,
 488                                  LIS3L02DQ_REG_GAIN_Z_ADDR);
 489
 490 static IIO_DEV_ATTR_ACCEL_THRESH(S_IWUSR | S_IRUGO,
 491                                  lis3l02dq_read_16bit_signed,
 492                                  lis3l02dq_write_16bit_signed,
 493                                  LIS3L02DQ_REG_THS_L_ADDR);
 494
 495 /* RFC The reading method for these will change depending on whether
 496  * ring buffer capture is in use. Is it worth making these take two
 497  * functions and let the core handle which to call, or leave as in this
 498  * driver where it is the drivers problem to manage this?
 499  */
 500
 501 static IIO_DEV_ATTR_ACCEL_X(lis3l02dq_read_accel,
 502                             LIS3L02DQ_REG_OUT_X_L_ADDR);
 503
 504 static IIO_DEV_ATTR_ACCEL_Y(lis3l02dq_read_accel,
 505                             LIS3L02DQ_REG_OUT_Y_L_ADDR);
 506
 507 static IIO_DEV_ATTR_ACCEL_Z(lis3l02dq_read_accel,
 508                             LIS3L02DQ_REG_OUT_Z_L_ADDR);
 509
 510 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
 511                               lis3l02dq_read_frequency,
 512                               lis3l02dq_write_frequency);
 513
 514 static IIO_CONST_ATTR_AVAIL_SAMP_FREQ("280 560 1120 4480");
 515
 516 static ssize_t lis3l02dq_read_interrupt_config(struct device *dev,
 517                                                struct device_attribute *attr,
 518                                                char *buf)
 519 {
 520         int ret;
 521         s8 val;
 522         struct iio_event_attr *this_attr = to_iio_event_attr(attr);
 523
 524         ret = lis3l02dq_spi_read_reg_8(dev,
 525                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 526                                        (u8 *)&val);
 527
 528         return ret ? ret : sprintf(buf, "%d\n",
 529                                    (val & this_attr->mask) ? 1 : 0);;
 530 }
 531
 532 static ssize_t lis3l02dq_write_interrupt_config(struct device *dev,
 533                                                 struct device_attribute *attr,
 534                                                 const char *buf,
 535                                                 size_t len)
 536 {
 537         struct iio_event_attr *this_attr = to_iio_event_attr(attr);
 538         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 539         int ret, currentlyset, changed = 0;
 540         u8 valold, controlold;
 541         bool val;
 542
 543         val = !(buf[0] == '0');
 544
 545         mutex_lock(&indio_dev->mlock);
 546         /* read current value */
 547         ret = lis3l02dq_spi_read_reg_8(dev,
 548                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 549                                        &valold);
 550         if (ret)
 551                 goto error_mutex_unlock;
 552
 553         /* read current control */
 554         ret = lis3l02dq_spi_read_reg_8(dev,
 555                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 556                                        &controlold);
 557         if (ret)
 558                 goto error_mutex_unlock;
 559         currentlyset = !!(valold & this_attr->mask);
 560         if (val == false && currentlyset) {
 561                 valold &= ~this_attr->mask;
 562                 changed = 1;
 563                 iio_remove_event_from_list(this_attr->listel,
 564                                                  &indio_dev->interrupts[0]
 565                                                  ->ev_list);
 566         } else if (val == true && !currentlyset) {
 567                 changed = 1;
 568                 valold |= this_attr->mask;
 569                 iio_add_event_to_list(this_attr->listel,
 570                                             &indio_dev->interrupts[0]->ev_list);
 571         }
 572
 573         if (changed) {
 574                 ret = lis3l02dq_spi_write_reg_8(dev,
 575                                                 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 576                                                 &valold);
 577                 if (ret)
 578                         goto error_mutex_unlock;
 579                 /* This always enables the interrupt, even if we've remove the
 580                  * last thing using it. For this device we can use the reference
 581                  * count on the handler to tell us if anyone wants the interrupt
 582                  */
 583                 controlold = this_attr->listel->refcount ?
 584                         (controlold | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
 585                         (controlold & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
 586                 ret = lis3l02dq_spi_write_reg_8(dev,
 587                                                 LIS3L02DQ_REG_CTRL_2_ADDR,
 588                                                 &controlold);
 589                 if (ret)
 590                         goto error_mutex_unlock;
 591         }
 592 error_mutex_unlock:
 593         mutex_unlock(&indio_dev->mlock);
 594
 595         return ret ? ret : len;
 596 }
 597
 598
 599 static int lis3l02dq_thresh_handler_th(struct iio_dev *dev_info,
 600                                        int index,
 601                                        s64 timestamp,
 602                                        int no_test)
 603 {
 604         struct lis3l02dq_state *st = dev_info->dev_data;
 605
 606         /* Stash the timestamp somewhere convenient for the bh */
 607         st->last_timestamp = timestamp;
 608         schedule_work(&st->work_cont_thresh.ws);
 609
 610         return 0;
 611 }
 612
 613
 614 /* Unforunately it appears the interrupt won't clear unless you read from the
 615  * src register.
 616  */
 617 static void lis3l02dq_thresh_handler_bh_no_check(struct work_struct *work_s)
 618 {
 619         struct iio_work_cont *wc
 620                 = container_of(work_s, struct iio_work_cont, ws_nocheck);
 621         struct lis3l02dq_state *st = wc->st;
 622         u8 t;
 623
 624         lis3l02dq_spi_read_reg_8(&st->indio_dev->dev,
 625                                  LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
 626                                  &t);
 627
 628         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
 629                 iio_push_event(st->indio_dev, 0,
 630                                IIO_EVENT_CODE_ACCEL_Z_HIGH,
 631                                st->last_timestamp);
 632
 633         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
 634                 iio_push_event(st->indio_dev, 0,
 635                                IIO_EVENT_CODE_ACCEL_Z_LOW,
 636                                st->last_timestamp);
 637
 638         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
 639                 iio_push_event(st->indio_dev, 0,
 640                                IIO_EVENT_CODE_ACCEL_Y_HIGH,
 641                                st->last_timestamp);
 642
 643         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
 644                 iio_push_event(st->indio_dev, 0,
 645                                IIO_EVENT_CODE_ACCEL_Y_LOW,
 646                                st->last_timestamp);
 647
 648         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
 649                 iio_push_event(st->indio_dev, 0,
 650                                IIO_EVENT_CODE_ACCEL_X_HIGH,
 651                                st->last_timestamp);
 652
 653         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
 654                 iio_push_event(st->indio_dev, 0,
 655                                IIO_EVENT_CODE_ACCEL_X_LOW,
 656                                st->last_timestamp);
 657         /* reenable the irq */
 658         enable_irq(st->us->irq);
 659         /* Ack and allow for new interrupts */
 660         lis3l02dq_spi_read_reg_8(&st->indio_dev->dev,
 661                                  LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
 662                                  &t);
 663
 664         return;
 665 }
 666
 667 /* A shared handler for a number of threshold types */
 668 IIO_EVENT_SH(threshold, &lis3l02dq_thresh_handler_th);
 669
 670 IIO_EVENT_ATTR_ACCEL_X_HIGH_SH(iio_event_threshold,
 671                                lis3l02dq_read_interrupt_config,
 672                                lis3l02dq_write_interrupt_config,
 673                                LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_X_HIGH);
 674
 675 IIO_EVENT_ATTR_ACCEL_Y_HIGH_SH(iio_event_threshold,
 676                                lis3l02dq_read_interrupt_config,
 677                                lis3l02dq_write_interrupt_config,
 678                                LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Y_HIGH);
 679
 680 IIO_EVENT_ATTR_ACCEL_Z_HIGH_SH(iio_event_threshold,
 681                                lis3l02dq_read_interrupt_config,
 682                                lis3l02dq_write_interrupt_config,
 683                                LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_HIGH);
 684
 685 IIO_EVENT_ATTR_ACCEL_X_LOW_SH(iio_event_threshold,
 686                               lis3l02dq_read_interrupt_config,
 687                               lis3l02dq_write_interrupt_config,
 688                               LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_X_LOW);
 689
 690 IIO_EVENT_ATTR_ACCEL_Y_LOW_SH(iio_event_threshold,
 691                               lis3l02dq_read_interrupt_config,
 692                               lis3l02dq_write_interrupt_config,
 693                               LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Y_LOW);
 694
 695 IIO_EVENT_ATTR_ACCEL_Z_LOW_SH(iio_event_threshold,
 696                               lis3l02dq_read_interrupt_config,
 697                               lis3l02dq_write_interrupt_config,
 698                               LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_LOW);
 699
 700 static struct attribute *lis3l02dq_event_attributes[] = {
 701         &iio_event_attr_accel_x_high.dev_attr.attr,
 702         &iio_event_attr_accel_y_high.dev_attr.attr,
 703         &iio_event_attr_accel_z_high.dev_attr.attr,
 704         &iio_event_attr_accel_x_low.dev_attr.attr,
 705         &iio_event_attr_accel_y_low.dev_attr.attr,
 706         &iio_event_attr_accel_z_low.dev_attr.attr,
 707         NULL
 708 };
 709
 710 static struct attribute_group lis3l02dq_event_attribute_group = {
 711         .attrs = lis3l02dq_event_attributes,
 712 };
 713
 714 static IIO_CONST_ATTR(name, "lis3l02dq");
 715
 716 static struct attribute *lis3l02dq_attributes[] = {
 717         &iio_dev_attr_accel_x_offset.dev_attr.attr,
 718         &iio_dev_attr_accel_y_offset.dev_attr.attr,
 719         &iio_dev_attr_accel_z_offset.dev_attr.attr,
 720         &iio_dev_attr_accel_x_gain.dev_attr.attr,
 721         &iio_dev_attr_accel_y_gain.dev_attr.attr,
 722         &iio_dev_attr_accel_z_gain.dev_attr.attr,
 723         &iio_dev_attr_thresh.dev_attr.attr,
 724         &iio_dev_attr_accel_x.dev_attr.attr,
 725         &iio_dev_attr_accel_y.dev_attr.attr,
 726         &iio_dev_attr_accel_z.dev_attr.attr,
 727         &iio_dev_attr_sampling_frequency.dev_attr.attr,
 728         &iio_const_attr_available_sampling_frequency.dev_attr.attr,
 729         &iio_const_attr_name.dev_attr.attr,
 730         NULL
 731 };
 732
 733 static const struct attribute_group lis3l02dq_attribute_group = {
 734         .attrs = lis3l02dq_attributes,
 735 };
 736
 737 static int __devinit lis3l02dq_probe(struct spi_device *spi)
 738 {
 739         int ret, regdone = 0;
 740         struct lis3l02dq_state *st = kzalloc(sizeof *st, GFP_KERNEL);
 741         if (!st) {
 742                 ret =  -ENOMEM;
 743                 goto error_ret;
 744         }
 745         /* this is only used tor removal purposes */
 746         spi_set_drvdata(spi, st);
 747
 748         /* Allocate the comms buffers */
 749         st->rx = kzalloc(sizeof(*st->rx)*LIS3L02DQ_MAX_RX, GFP_KERNEL);
 750         if (st->rx == NULL) {
 751                 ret = -ENOMEM;
 752                 goto error_free_st;
 753         }
 754         st->tx = kzalloc(sizeof(*st->tx)*LIS3L02DQ_MAX_TX, GFP_KERNEL);
 755         if (st->tx == NULL) {
 756                 ret = -ENOMEM;
 757                 goto error_free_rx;
 758         }
 759         st->us = spi;
 760         mutex_init(&st->buf_lock);
 761         /* setup the industrialio driver allocated elements */
 762         st->indio_dev = iio_allocate_device();
 763         if (st->indio_dev == NULL) {
 764                 ret = -ENOMEM;
 765                 goto error_free_tx;
 766         }
 767
 768         st->indio_dev->dev.parent = &spi->dev;
 769         st->indio_dev->num_interrupt_lines = 1;
 770         st->indio_dev->event_attrs = &lis3l02dq_event_attribute_group;
 771         st->indio_dev->attrs = &lis3l02dq_attribute_group;
 772         st->indio_dev->dev_data = (void *)(st);
 773         st->indio_dev->driver_module = THIS_MODULE;
 774         st->indio_dev->modes = INDIO_DIRECT_MODE;
 775
 776         ret = lis3l02dq_configure_ring(st->indio_dev);
 777         if (ret)
 778                 goto error_free_dev;
 779
 780         ret = iio_device_register(st->indio_dev);
 781         if (ret)
 782                 goto error_unreg_ring_funcs;
 783         regdone = 1;
 784
 785         ret = lis3l02dq_initialize_ring(st->indio_dev->ring);
 786         if (ret) {
 787                 printk(KERN_ERR "failed to initialize the ring\n");
 788                 goto error_unreg_ring_funcs;
 789         }
 790
 791         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) {
 792                 /* This is a little unusual, in that the device seems
 793                    to need a full read of the interrupt source reg before
 794                    the interrupt will reset.
 795                    Hence the two handlers are the same */
 796                 iio_init_work_cont(&st->work_cont_thresh,
 797                                    lis3l02dq_thresh_handler_bh_no_check,
 798                                    lis3l02dq_thresh_handler_bh_no_check,
 799                                    LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
 800                                    0,
 801                                    st);
 802                 st->inter = 0;
 803                 ret = iio_register_interrupt_line(spi->irq,
 804                                                   st->indio_dev,
 805                                                   0,
 806                                                   IRQF_TRIGGER_RISING,
 807                                                   "lis3l02dq");
 808                 if (ret)
 809                         goto error_uninitialize_ring;
 810
 811                 ret = lis3l02dq_probe_trigger(st->indio_dev);
 812                 if (ret)
 813                         goto error_unregister_line;
 814         }
 815
 816         /* Get the device into a sane initial state */
 817         ret = lis3l02dq_initial_setup(st);
 818         if (ret)
 819                 goto error_remove_trigger;
 820         return 0;
 821
 822 error_remove_trigger:
 823         if (st->indio_dev->modes & INDIO_RING_TRIGGERED)
 824                 lis3l02dq_remove_trigger(st->indio_dev);
 825 error_unregister_line:
 826         if (st->indio_dev->modes & INDIO_RING_TRIGGERED)
 827                 iio_unregister_interrupt_line(st->indio_dev, 0);
 828 error_uninitialize_ring:
 829         lis3l02dq_uninitialize_ring(st->indio_dev->ring);
 830 error_unreg_ring_funcs:
 831         lis3l02dq_unconfigure_ring(st->indio_dev);
 832 error_free_dev:
 833         if (regdone)
 834                 iio_device_unregister(st->indio_dev);
 835         else
 836                 iio_free_device(st->indio_dev);
 837 error_free_tx:
 838         kfree(st->tx);
 839 error_free_rx:
 840         kfree(st->rx);
 841 error_free_st:
 842         kfree(st);
 843 error_ret:
 844         return ret;
 845 }
 846
 847 /* Power down the device */
 848 static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
 849 {
 850         int ret;
 851         struct lis3l02dq_state *st = indio_dev->dev_data;
 852         u8 val = 0;
 853
 854         mutex_lock(&indio_dev->mlock);
 855         ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev,
 856                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 857                                         &val);
 858         if (ret) {
 859                 dev_err(&st->us->dev, "problem with turning device off: ctrl1");
 860                 goto err_ret;
 861         }
 862
 863         ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev,
 864                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 865                                         &val);
 866         if (ret)
 867                 dev_err(&st->us->dev, "problem with turning device off: ctrl2");
 868 err_ret:
 869         mutex_unlock(&indio_dev->mlock);
 870         return ret;
 871 }
 872
 873 /* fixme, confirm ordering in this function */
 874 static int lis3l02dq_remove(struct spi_device *spi)
 875 {
 876         int ret;
 877         struct lis3l02dq_state *st = spi_get_drvdata(spi);
 878         struct iio_dev *indio_dev = st->indio_dev;
 879
 880         ret = lis3l02dq_stop_device(indio_dev);
 881         if (ret)
 882                 goto err_ret;
 883
 884         flush_scheduled_work();
 885
 886         lis3l02dq_remove_trigger(indio_dev);
 887         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
 888                 iio_unregister_interrupt_line(indio_dev, 0);
 889
 890         lis3l02dq_uninitialize_ring(indio_dev->ring);
 891         lis3l02dq_unconfigure_ring(indio_dev);
 892         iio_device_unregister(indio_dev);
 893         kfree(st->tx);
 894         kfree(st->rx);
 895         kfree(st);
 896
 897         return 0;
 898
 899 err_ret:
 900         return ret;
 901 }
 902
 903 static struct spi_driver lis3l02dq_driver = {
 904         .driver = {
 905                 .name = "lis3l02dq",
 906                 .owner = THIS_MODULE,
 907         },
 908         .probe = lis3l02dq_probe,
 909         .remove = __devexit_p(lis3l02dq_remove),
 910 };
 911
 912 static __init int lis3l02dq_init(void)
 913 {
 914         return spi_register_driver(&lis3l02dq_driver);
 915 }
 916 module_init(lis3l02dq_init);
 917
 918 static __exit void lis3l02dq_exit(void)
 919 {
 920         spi_unregister_driver(&lis3l02dq_driver);
 921 }
 922 module_exit(lis3l02dq_exit);
 923
 924 MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
 925 MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
 926 MODULE_LICENSE("GPL v2");