drivers/staging/gma500/psb_drv.c

   1 /**************************************************************************
   2  * Copyright (c) 2007, Intel Corporation.
   3  * All Rights Reserved.
   4  * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA.
   5  * All Rights Reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  **************************************************************************/
  21
  22 #include <drm/drmP.h>
  23 #include <drm/drm.h>
  24 #include "psb_drm.h"
  25 #include "psb_drv.h"
  26 #include "psb_fb.h"
  27 #include "psb_reg.h"
  28 #include "psb_intel_reg.h"
  29 #include "psb_intel_bios.h"
  30 #include <drm/drm_pciids.h>
  31 #include "psb_powermgmt.h"
  32 #include <linux/cpu.h>
  33 #include <linux/notifier.h>
  34 #include <linux/spinlock.h>
  35 #include <linux/pm_runtime.h>
  36 #include <acpi/video.h>
  37
  38 int drm_psb_debug;
  39 static int drm_psb_trap_pagefaults;
  40
  41 int drm_psb_no_fb;
  42
  43 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
  44
  45 MODULE_PARM_DESC(debug, "Enable debug output");
  46 MODULE_PARM_DESC(no_fb, "Disable FBdev");
  47 MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults");
  48 module_param_named(debug, drm_psb_debug, int, 0600);
  49 module_param_named(no_fb, drm_psb_no_fb, int, 0600);
  50 module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
  51
  52
  53 static struct pci_device_id pciidlist[] = {
  54         { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8108 },
  55         { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8109 },
  56         { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
  57         { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
  58         { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
  59         { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
  60         { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
  61         { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
  62         { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
  63         { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
  64         { 0, 0, 0}
  65 };
  66 MODULE_DEVICE_TABLE(pci, pciidlist);
  67
  68 /*
  69  * Standard IOCTLs.
  70  */
  71
  72 #define DRM_IOCTL_PSB_KMS_OFF   \
  73                 DRM_IO(DRM_PSB_KMS_OFF + DRM_COMMAND_BASE)
  74 #define DRM_IOCTL_PSB_KMS_ON    \
  75                 DRM_IO(DRM_PSB_KMS_ON + DRM_COMMAND_BASE)
  76 #define DRM_IOCTL_PSB_SIZES     \
  77                 DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \
  78                         struct drm_psb_sizes_arg)
  79 #define DRM_IOCTL_PSB_FUSE_REG  \
  80                 DRM_IOWR(DRM_PSB_FUSE_REG + DRM_COMMAND_BASE, uint32_t)
  81 #define DRM_IOCTL_PSB_DC_STATE  \
  82                 DRM_IOW(DRM_PSB_DC_STATE + DRM_COMMAND_BASE, \
  83                         struct drm_psb_dc_state_arg)
  84 #define DRM_IOCTL_PSB_ADB       \
  85                 DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t)
  86 #define DRM_IOCTL_PSB_MODE_OPERATION    \
  87                 DRM_IOWR(DRM_PSB_MODE_OPERATION + DRM_COMMAND_BASE, \
  88                          struct drm_psb_mode_operation_arg)
  89 #define DRM_IOCTL_PSB_STOLEN_MEMORY     \
  90                 DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \
  91                          struct drm_psb_stolen_memory_arg)
  92 #define DRM_IOCTL_PSB_REGISTER_RW       \
  93                 DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \
  94                          struct drm_psb_register_rw_arg)
  95 #define DRM_IOCTL_PSB_DPST      \
  96                 DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \
  97                          uint32_t)
  98 #define DRM_IOCTL_PSB_GAMMA     \
  99                 DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \
 100                          struct drm_psb_dpst_lut_arg)
 101 #define DRM_IOCTL_PSB_DPST_BL   \
 102                 DRM_IOWR(DRM_PSB_DPST_BL + DRM_COMMAND_BASE, \
 103                          uint32_t)
 104 #define DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID     \
 105                 DRM_IOWR(DRM_PSB_GET_PIPE_FROM_CRTC_ID + DRM_COMMAND_BASE, \
 106                          struct drm_psb_get_pipe_from_crtc_id_arg)
 107
 108 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
 109                            struct drm_file *file_priv);
 110 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
 111                               struct drm_file *file_priv);
 112 static int psb_adb_ioctl(struct drm_device *dev, void *data,
 113                          struct drm_file *file_priv);
 114 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
 115                                     struct drm_file *file_priv);
 116 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
 117                                    struct drm_file *file_priv);
 118 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
 119                                  struct drm_file *file_priv);
 120 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
 121                           struct drm_file *file_priv);
 122 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
 123                            struct drm_file *file_priv);
 124 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
 125                              struct drm_file *file_priv);
 126
 127 #define PSB_IOCTL_DEF(ioctl, func, flags) \
 128         [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}
 129
 130 static struct drm_ioctl_desc psb_ioctls[] = {
 131         PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_OFF, psbfb_kms_off_ioctl,
 132                       DRM_ROOT_ONLY),
 133         PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_ON,
 134                         psbfb_kms_on_ioctl,
 135                         DRM_ROOT_ONLY),
 136         PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH),
 137         PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH),
 138         PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),
 139         PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl,
 140                       DRM_AUTH),
 141         PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl,
 142                       DRM_AUTH),
 143         PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl,
 144                       DRM_AUTH),
 145         PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH),
 146         PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),
 147         PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),
 148         PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,
 149                                         psb_intel_get_pipe_from_crtc_id, 0),
 150
 151 };
 152
 153 static void psb_lastclose(struct drm_device *dev)
 154 {
 155         return;
 156 }
 157
 158 static void psb_do_takedown(struct drm_device *dev)
 159 {
 160         /* FIXME: do we need to clean up the gtt here ? */
 161 }
 162
 163 void mrst_get_fuse_settings(struct drm_device *dev)
 164 {
 165         struct drm_psb_private *dev_priv = dev->dev_private;
 166         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 167         uint32_t fuse_value = 0;
 168         uint32_t fuse_value_tmp = 0;
 169
 170 #define FB_REG06 0xD0810600
 171 #define FB_MIPI_DISABLE  (1 << 11)
 172 #define FB_REG09 0xD0810900
 173 #define FB_REG09 0xD0810900
 174 #define FB_SKU_MASK  0x7000
 175 #define FB_SKU_SHIFT 12
 176 #define FB_SKU_100 0
 177 #define FB_SKU_100L 1
 178 #define FB_SKU_83 2
 179         pci_write_config_dword(pci_root, 0xD0, FB_REG06);
 180         pci_read_config_dword(pci_root, 0xD4, &fuse_value);
 181
 182         dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
 183
 184         DRM_INFO("internal display is %s\n",
 185                  dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
 186
 187          /*prevent Runtime suspend at start*/
 188          if (dev_priv->iLVDS_enable) {
 189                 dev_priv->is_lvds_on = true;
 190                 dev_priv->is_mipi_on = false;
 191         }
 192         else {
 193                 dev_priv->is_mipi_on = true;
 194                 dev_priv->is_lvds_on = false;
 195         }
 196
 197         dev_priv->video_device_fuse = fuse_value;
 198
 199         pci_write_config_dword(pci_root, 0xD0, FB_REG09);
 200         pci_read_config_dword(pci_root, 0xD4, &fuse_value);
 201
 202         DRM_INFO("SKU values is 0x%x. \n", fuse_value);
 203         fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
 204
 205         dev_priv->fuse_reg_value = fuse_value;
 206
 207         switch (fuse_value_tmp) {
 208         case FB_SKU_100:
 209                 dev_priv->core_freq = 200;
 210                 break;
 211         case FB_SKU_100L:
 212                 dev_priv->core_freq = 100;
 213                 break;
 214         case FB_SKU_83:
 215                 dev_priv->core_freq = 166;
 216                 break;
 217         default:
 218                 DRM_ERROR("Invalid SKU values, SKU value = 0x%08x\n", fuse_value_tmp);
 219                 dev_priv->core_freq = 0;
 220         }
 221         DRM_INFO("LNC core clk is %dMHz.\n", dev_priv->core_freq);
 222         pci_dev_put(pci_root);
 223 }
 224
 225 void mid_get_pci_revID (struct drm_psb_private *dev_priv)
 226 {
 227         uint32_t platform_rev_id = 0;
 228         struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
 229
 230         /*get the revison ID, B0:D2:F0;0x08 */
 231         pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
 232         dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
 233         pci_dev_put(pci_gfx_root);
 234         PSB_DEBUG_ENTRY("platform_rev_id is %x\n",      dev_priv->platform_rev_id);
 235 }
 236
 237 void mrst_get_vbt_data(struct drm_psb_private *dev_priv)
 238 {
 239         struct mrst_vbt *vbt = &dev_priv->vbt_data;
 240         u32 platform_config_address;
 241         u16 new_size;
 242         u8 *vbt_virtual;
 243         u8 bpi;
 244         u8 number_desc = 0;
 245         struct mrst_timing_info *dp_ti = &dev_priv->gct_data.DTD;
 246         struct gct_r10_timing_info ti;
 247         void *pGCT;
 248         struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
 249
 250         /*get the address of the platform config vbt, B0:D2:F0;0xFC */
 251         pci_read_config_dword(pci_gfx_root, 0xFC, &platform_config_address);
 252         pci_dev_put(pci_gfx_root);
 253         DRM_INFO("drm platform config address is %x\n",
 254                         platform_config_address);
 255
 256         /* check for platform config address == 0. */
 257         /* this means fw doesn't support vbt */
 258
 259         if (platform_config_address == 0) {
 260                 vbt->size = 0;
 261                 return;
 262         }
 263
 264         /* get the virtual address of the vbt */
 265         vbt_virtual = ioremap(platform_config_address, sizeof(*vbt));
 266
 267         memcpy(vbt, vbt_virtual, sizeof(*vbt));
 268         iounmap(vbt_virtual); /* Free virtual address space */
 269
 270         printk(KERN_ALERT "GCT revision is %x\n", vbt->revision);
 271
 272         switch (vbt->revision) {
 273         case 0:
 274                 vbt->mrst_gct = NULL;
 275                 vbt->mrst_gct = \
 276                         ioremap(platform_config_address + sizeof(*vbt) - 4,
 277                                         vbt->size - sizeof(*vbt) + 4);
 278                 pGCT = vbt->mrst_gct;
 279                 bpi = ((struct mrst_gct_v1 *)pGCT)->PD.BootPanelIndex;
 280                 dev_priv->gct_data.bpi = bpi;
 281                 dev_priv->gct_data.pt =
 282                         ((struct mrst_gct_v1 *)pGCT)->PD.PanelType;
 283                 memcpy(&dev_priv->gct_data.DTD,
 284                         &((struct mrst_gct_v1 *)pGCT)->panel[bpi].DTD,
 285                                 sizeof(struct mrst_timing_info));
 286                 dev_priv->gct_data.Panel_Port_Control =
 287                   ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_Port_Control;
 288                 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
 289                   ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
 290                 break;
 291         case 1:
 292                 vbt->mrst_gct = NULL;
 293                 vbt->mrst_gct = \
 294                         ioremap(platform_config_address + sizeof(*vbt) - 4,
 295                                         vbt->size - sizeof(*vbt) + 4);
 296                 pGCT = vbt->mrst_gct;
 297                 bpi = ((struct mrst_gct_v2 *)pGCT)->PD.BootPanelIndex;
 298                 dev_priv->gct_data.bpi = bpi;
 299                 dev_priv->gct_data.pt =
 300                         ((struct mrst_gct_v2 *)pGCT)->PD.PanelType;
 301                 memcpy(&dev_priv->gct_data.DTD,
 302                         &((struct mrst_gct_v2 *)pGCT)->panel[bpi].DTD,
 303                                 sizeof(struct mrst_timing_info));
 304                 dev_priv->gct_data.Panel_Port_Control =
 305                   ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_Port_Control;
 306                 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
 307                   ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
 308                 break;
 309         case 0x10:
 310                 /*header definition changed from rev 01 (v2) to rev 10h. */
 311                 /*so, some values have changed location*/
 312                 new_size = vbt->checksum; /*checksum contains lo size byte*/
 313                 /*LSB of mrst_gct contains hi size byte*/
 314                 new_size |= ((0xff & (unsigned int)vbt->mrst_gct)) << 8;
 315
 316                 vbt->checksum = vbt->size; /*size contains the checksum*/
 317                 if (new_size > 0xff)
 318                         vbt->size = 0xff; /*restrict size to 255*/
 319                 else
 320                         vbt->size = new_size;
 321
 322                 /* number of descriptors defined in the GCT */
 323                 number_desc = ((0xff00 & (unsigned int)vbt->mrst_gct)) >> 8;
 324                 bpi = ((0xff0000 & (unsigned int)vbt->mrst_gct)) >> 16;
 325                 vbt->mrst_gct = NULL;
 326                 vbt->mrst_gct = \
 327                         ioremap(platform_config_address + GCT_R10_HEADER_SIZE,
 328                                 GCT_R10_DISPLAY_DESC_SIZE * number_desc);
 329                 pGCT = vbt->mrst_gct;
 330                 pGCT = (u8 *)pGCT + (bpi*GCT_R10_DISPLAY_DESC_SIZE);
 331                 dev_priv->gct_data.bpi = bpi; /*save boot panel id*/
 332
 333                 /*copy the GCT display timings into a temp structure*/
 334                 memcpy(&ti, pGCT, sizeof(struct gct_r10_timing_info));
 335
 336                 /*now copy the temp struct into the dev_priv->gct_data*/
 337                 dp_ti->pixel_clock = ti.pixel_clock;
 338                 dp_ti->hactive_hi = ti.hactive_hi;
 339                 dp_ti->hactive_lo = ti.hactive_lo;
 340                 dp_ti->hblank_hi = ti.hblank_hi;
 341                 dp_ti->hblank_lo = ti.hblank_lo;
 342                 dp_ti->hsync_offset_hi = ti.hsync_offset_hi;
 343                 dp_ti->hsync_offset_lo = ti.hsync_offset_lo;
 344                 dp_ti->hsync_pulse_width_hi = ti.hsync_pulse_width_hi;
 345                 dp_ti->hsync_pulse_width_lo = ti.hsync_pulse_width_lo;
 346                 dp_ti->vactive_hi = ti.vactive_hi;
 347                 dp_ti->vactive_lo = ti.vactive_lo;
 348                 dp_ti->vblank_hi = ti.vblank_hi;
 349                 dp_ti->vblank_lo = ti.vblank_lo;
 350                 dp_ti->vsync_offset_hi = ti.vsync_offset_hi;
 351                 dp_ti->vsync_offset_lo = ti.vsync_offset_lo;
 352                 dp_ti->vsync_pulse_width_hi = ti.vsync_pulse_width_hi;
 353                 dp_ti->vsync_pulse_width_lo = ti.vsync_pulse_width_lo;
 354
 355                 /*mov the MIPI_Display_Descriptor data from GCT to dev priv*/
 356                 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
 357                                                         *((u8 *)pGCT + 0x0d);
 358                 dev_priv->gct_data.Panel_MIPI_Display_Descriptor |=
 359                                                 (*((u8 *)pGCT + 0x0e)) << 8;
 360                 break;
 361         default:
 362                 printk(KERN_ERR "Unknown revision of GCT!\n");
 363                 vbt->size = 0;
 364         }
 365 }
 366
 367 static void psb_get_core_freq(struct drm_device *dev)
 368 {
 369         uint32_t clock;
 370         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 371         struct drm_psb_private *dev_priv = dev->dev_private;
 372
 373         /*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
 374         /*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/
 375
 376         pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
 377         pci_read_config_dword(pci_root, 0xD4, &clock);
 378         pci_dev_put(pci_root);
 379
 380         switch (clock & 0x07) {
 381         case 0:
 382                 dev_priv->core_freq = 100;
 383                 break;
 384         case 1:
 385                 dev_priv->core_freq = 133;
 386                 break;
 387         case 2:
 388                 dev_priv->core_freq = 150;
 389                 break;
 390         case 3:
 391                 dev_priv->core_freq = 178;
 392                 break;
 393         case 4:
 394                 dev_priv->core_freq = 200;
 395                 break;
 396         case 5:
 397         case 6:
 398         case 7:
 399                 dev_priv->core_freq = 266;
 400         default:
 401                 dev_priv->core_freq = 0;
 402         }
 403 }
 404
 405 static int psb_do_init(struct drm_device *dev)
 406 {
 407         struct drm_psb_private *dev_priv =
 408             (struct drm_psb_private *) dev->dev_private;
 409         struct psb_gtt *pg = dev_priv->pg;
 410
 411         uint32_t stolen_gtt;
 412         uint32_t tt_start;
 413         uint32_t tt_pages;
 414
 415         int ret = -ENOMEM;
 416
 417         if (pg->mmu_gatt_start & 0x0FFFFFFF) {
 418                 DRM_ERROR("Gatt must be 256M aligned. This is a bug.\n");
 419                 ret = -EINVAL;
 420                 goto out_err;
 421         }
 422
 423
 424         stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4;
 425         stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT;
 426         stolen_gtt =
 427             (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages;
 428
 429         dev_priv->gatt_free_offset = pg->mmu_gatt_start +
 430             (stolen_gtt << PAGE_SHIFT) * 1024;
 431
 432         if (1 || drm_debug) {
 433                 uint32_t core_id = PSB_RSGX32(PSB_CR_CORE_ID);
 434                 uint32_t core_rev = PSB_RSGX32(PSB_CR_CORE_REVISION);
 435                 DRM_INFO("SGX core id = 0x%08x\n", core_id);
 436                 DRM_INFO("SGX core rev major = 0x%02x, minor = 0x%02x\n",
 437                          (core_rev & _PSB_CC_REVISION_MAJOR_MASK) >>
 438                          _PSB_CC_REVISION_MAJOR_SHIFT,
 439                          (core_rev & _PSB_CC_REVISION_MINOR_MASK) >>
 440                          _PSB_CC_REVISION_MINOR_SHIFT);
 441                 DRM_INFO
 442                     ("SGX core rev maintenance = 0x%02x, designer = 0x%02x\n",
 443                      (core_rev & _PSB_CC_REVISION_MAINTENANCE_MASK) >>
 444                      _PSB_CC_REVISION_MAINTENANCE_SHIFT,
 445                      (core_rev & _PSB_CC_REVISION_DESIGNER_MASK) >>
 446                      _PSB_CC_REVISION_DESIGNER_SHIFT);
 447         }
 448
 449
 450         spin_lock_init(&dev_priv->irqmask_lock);
 451
 452         tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
 453             pg->gatt_pages : PSB_TT_PRIV0_PLIMIT;
 454         tt_start = dev_priv->gatt_free_offset - pg->mmu_gatt_start;
 455         tt_pages -= tt_start >> PAGE_SHIFT;
 456         /* FIXME: can we kill ta_mem_size ? */
 457         dev_priv->sizes.ta_mem_size = 0;
 458
 459         PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
 460         PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
 461         PSB_RSGX32(PSB_CR_BIF_BANK1);
 462         PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_MMU_ER_MASK,
 463                                                         PSB_CR_BIF_CTRL);
 464         psb_spank(dev_priv);
 465
 466         /* mmu_gatt ?? */
 467         PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
 468
 469         return 0;
 470 out_err:
 471         psb_do_takedown(dev);
 472         return ret;
 473 }
 474
 475 static int psb_driver_unload(struct drm_device *dev)
 476 {
 477         struct drm_psb_private *dev_priv =
 478             (struct drm_psb_private *) dev->dev_private;
 479
 480         /* Kill vblank etc here */
 481
 482         psb_backlight_exit(); /*writes minimum value to backlight HW reg */
 483
 484         if (drm_psb_no_fb == 0)
 485                 psb_modeset_cleanup(dev);
 486
 487         if (dev_priv) {
 488                 psb_lid_timer_takedown(dev_priv);
 489
 490                 psb_do_takedown(dev);
 491
 492
 493                 if (dev_priv->pf_pd) {
 494                         psb_mmu_free_pagedir(dev_priv->pf_pd);
 495                         dev_priv->pf_pd = NULL;
 496                 }
 497                 if (dev_priv->mmu) {
 498                         struct psb_gtt *pg = dev_priv->pg;
 499
 500                         down_read(&pg->sem);
 501                         psb_mmu_remove_pfn_sequence(
 502                                 psb_mmu_get_default_pd
 503                                 (dev_priv->mmu),
 504                                 pg->mmu_gatt_start,
 505                                 dev_priv->vram_stolen_size >> PAGE_SHIFT);
 506                         up_read(&pg->sem);
 507                         psb_mmu_driver_takedown(dev_priv->mmu);
 508                         dev_priv->mmu = NULL;
 509                 }
 510                 psb_gtt_takedown(dev);
 511                 if (dev_priv->scratch_page) {
 512                         __free_page(dev_priv->scratch_page);
 513                         dev_priv->scratch_page = NULL;
 514                 }
 515                 if (dev_priv->vdc_reg) {
 516                         iounmap(dev_priv->vdc_reg);
 517                         dev_priv->vdc_reg = NULL;
 518                 }
 519                 if (dev_priv->sgx_reg) {
 520                         iounmap(dev_priv->sgx_reg);
 521                         dev_priv->sgx_reg = NULL;
 522                 }
 523
 524                 kfree(dev_priv);
 525                 dev->dev_private = NULL;
 526
 527                 /*destroy VBT data*/
 528                 psb_intel_destroy_bios(dev);
 529         }
 530
 531         gma_power_uninit(dev);
 532
 533         return 0;
 534 }
 535
 536
 537 static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
 538 {
 539         struct drm_psb_private *dev_priv;
 540         unsigned long resource_start;
 541         struct psb_gtt *pg;
 542         unsigned long irqflags;
 543         int ret = -ENOMEM;
 544         uint32_t tt_pages;
 545
 546         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 547         if (dev_priv == NULL)
 548                 return -ENOMEM;
 549
 550         if (IS_MRST(dev))
 551                 dev_priv->num_pipe = 1;
 552         else
 553                 dev_priv->num_pipe = 2;
 554
 555         dev_priv->dev = dev;
 556
 557         dev->dev_private = (void *) dev_priv;
 558         dev_priv->chipset = chipset;
 559
 560         PSB_DEBUG_INIT("Mapping MMIO\n");
 561         resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
 562
 563         dev_priv->vdc_reg =
 564             ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
 565         if (!dev_priv->vdc_reg)
 566                 goto out_err;
 567
 568         if (IS_MRST(dev))
 569                 dev_priv->sgx_reg = ioremap(resource_start + MRST_SGX_OFFSET,
 570                                                         PSB_SGX_SIZE);
 571         else
 572                 dev_priv->sgx_reg = ioremap(resource_start + PSB_SGX_OFFSET,
 573                                                         PSB_SGX_SIZE);
 574
 575         if (!dev_priv->sgx_reg)
 576                 goto out_err;
 577
 578         if (IS_MRST(dev)) {
 579                 mrst_get_fuse_settings(dev);
 580                 mrst_get_vbt_data(dev_priv);
 581                 mid_get_pci_revID(dev_priv);
 582         } else {
 583                 psb_get_core_freq(dev);
 584                 psb_intel_opregion_init(dev);
 585                 psb_intel_init_bios(dev);
 586         }
 587
 588         /* Init OSPM support */
 589         gma_power_init(dev);
 590
 591         ret = -ENOMEM;
 592
 593         dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);
 594         if (!dev_priv->scratch_page)
 595                 goto out_err;
 596
 597         set_pages_uc(dev_priv->scratch_page, 1);
 598
 599         ret = psb_gtt_init(dev, 0);
 600         if (ret)
 601                 goto out_err;
 602
 603         dev_priv->mmu = psb_mmu_driver_init((void *)0,
 604                                         drm_psb_trap_pagefaults, 0,
 605                                         dev_priv);
 606         if (!dev_priv->mmu)
 607                 goto out_err;
 608
 609         pg = dev_priv->pg;
 610
 611         tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
 612                 (pg->gatt_pages) : PSB_TT_PRIV0_PLIMIT;
 613
 614
 615         dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
 616         if (!dev_priv->pf_pd)
 617                 goto out_err;
 618
 619         psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
 620         psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
 621
 622         ret = psb_do_init(dev);
 623         if (ret)
 624                 return ret;
 625
 626         PSB_WSGX32(0x20000000, PSB_CR_PDS_EXEC_BASE);
 627         PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE);
 628
 629 /*      igd_opregion_init(&dev_priv->opregion_dev); */
 630         acpi_video_register();
 631         if (dev_priv->lid_state)
 632                 psb_lid_timer_init(dev_priv);
 633
 634         ret = drm_vblank_init(dev, dev_priv->num_pipe);
 635         if (ret)
 636                 goto out_err;
 637
 638         /*
 639          * Install interrupt handlers prior to powering off SGX or else we will
 640          * crash.
 641          */
 642         dev_priv->vdc_irq_mask = 0;
 643         dev_priv->pipestat[0] = 0;
 644         dev_priv->pipestat[1] = 0;
 645         dev_priv->pipestat[2] = 0;
 646         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 647         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 648         PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
 649         PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
 650         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 651         if (drm_core_check_feature(dev, DRIVER_MODESET))
 652                 drm_irq_install(dev);
 653
 654         dev->vblank_disable_allowed = 1;
 655
 656         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
 657
 658         dev->driver->get_vblank_counter = psb_get_vblank_counter;
 659
 660         if (drm_psb_no_fb == 0) {
 661                 psb_modeset_init(dev);
 662                 psb_fbdev_init(dev);
 663                 drm_kms_helper_poll_init(dev);
 664         }
 665
 666         ret = psb_backlight_init(dev);
 667         if (ret)
 668                 return ret;
 669 #if 0
 670         /*enable runtime pm at last*/
 671         pm_runtime_enable(&dev->pdev->dev);
 672         pm_runtime_set_active(&dev->pdev->dev);
 673 #endif
 674         /*Intel drm driver load is done, continue doing pvr load*/
 675         DRM_DEBUG("Pvr driver load\n");
 676         return 0;
 677 out_err:
 678         psb_driver_unload(dev);
 679         return ret;
 680 }
 681
 682 int psb_driver_device_is_agp(struct drm_device *dev)
 683 {
 684         return 0;
 685 }
 686
 687
 688 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
 689                            struct drm_file *file_priv)
 690 {
 691         struct drm_psb_private *dev_priv = psb_priv(dev);
 692         struct drm_psb_sizes_arg *arg =
 693                 (struct drm_psb_sizes_arg *) data;
 694
 695         *arg = dev_priv->sizes;
 696         return 0;
 697 }
 698
 699 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
 700                                 struct drm_file *file_priv)
 701 {
 702         uint32_t flags;
 703         uint32_t obj_id;
 704         struct drm_mode_object *obj;
 705         struct drm_connector *connector;
 706         struct drm_crtc *crtc;
 707         struct drm_psb_dc_state_arg *arg =
 708                 (struct drm_psb_dc_state_arg *)data;
 709
 710         flags = arg->flags;
 711         obj_id = arg->obj_id;
 712
 713         if (flags & PSB_DC_CRTC_MASK) {
 714                 obj = drm_mode_object_find(dev, obj_id,
 715                                 DRM_MODE_OBJECT_CRTC);
 716                 if (!obj) {
 717                         DRM_DEBUG("Invalid CRTC object.\n");
 718                         return -EINVAL;
 719                 }
 720
 721                 crtc = obj_to_crtc(obj);
 722
 723                 mutex_lock(&dev->mode_config.mutex);
 724                 if (drm_helper_crtc_in_use(crtc)) {
 725                         if (flags & PSB_DC_CRTC_SAVE)
 726                                 crtc->funcs->save(crtc);
 727                         else
 728                                 crtc->funcs->restore(crtc);
 729                 }
 730                 mutex_unlock(&dev->mode_config.mutex);
 731
 732                 return 0;
 733         } else if (flags & PSB_DC_OUTPUT_MASK) {
 734                 obj = drm_mode_object_find(dev, obj_id,
 735                                 DRM_MODE_OBJECT_CONNECTOR);
 736                 if (!obj) {
 737                         DRM_DEBUG("Invalid connector id.\n");
 738                         return -EINVAL;
 739                 }
 740
 741                 connector = obj_to_connector(obj);
 742                 if (flags & PSB_DC_OUTPUT_SAVE)
 743                         connector->funcs->save(connector);
 744                 else
 745                         connector->funcs->restore(connector);
 746
 747                 return 0;
 748         }
 749
 750         DRM_DEBUG("Bad flags 0x%x\n", flags);
 751         return -EINVAL;
 752 }
 753
 754 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
 755                        struct drm_file *file_priv)
 756 {
 757         struct drm_psb_private *dev_priv = psb_priv(dev);
 758         uint32_t *arg = data;
 759         struct backlight_device bd;
 760         dev_priv->blc_adj2 = *arg;
 761
 762 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 763         bd.props.brightness = psb_get_brightness(&bd);
 764         psb_set_brightness(&bd);
 765 #endif
 766         return 0;
 767 }
 768
 769 static int psb_adb_ioctl(struct drm_device *dev, void *data,
 770                         struct drm_file *file_priv)
 771 {
 772         struct drm_psb_private *dev_priv = psb_priv(dev);
 773         uint32_t *arg = data;
 774         struct backlight_device bd;
 775         dev_priv->blc_adj1 = *arg;
 776
 777 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 778         bd.props.brightness = psb_get_brightness(&bd);
 779         psb_set_brightness(&bd);
 780 #endif
 781         return 0;
 782 }
 783
 784 /* return the current mode to the dpst module */
 785 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
 786                           struct drm_file *file_priv)
 787 {
 788         struct drm_psb_private *dev_priv = psb_priv(dev);
 789         uint32_t *arg = data;
 790         uint32_t x;
 791         uint32_t y;
 792         uint32_t reg;
 793
 794         if (!gma_power_begin(dev, 0))
 795                 return -EIO;
 796
 797         reg = PSB_RVDC32(PIPEASRC);
 798
 799         gma_power_end(dev);
 800
 801         /* horizontal is the left 16 bits */
 802         x = reg >> 16;
 803         /* vertical is the right 16 bits */
 804         y = reg & 0x0000ffff;
 805
 806         /* the values are the image size minus one */
 807         x++;
 808         y++;
 809
 810         *arg = (x << 16) | y;
 811
 812         return 0;
 813 }
 814 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
 815                            struct drm_file *file_priv)
 816 {
 817         struct drm_psb_dpst_lut_arg *lut_arg = data;
 818         struct drm_mode_object *obj;
 819         struct drm_crtc *crtc;
 820         struct drm_connector *connector;
 821         struct psb_intel_crtc *psb_intel_crtc;
 822         int i = 0;
 823         int32_t obj_id;
 824
 825         obj_id = lut_arg->output_id;
 826         obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_CONNECTOR);
 827         if (!obj) {
 828                 DRM_DEBUG("Invalid Connector object.\n");
 829                 return -EINVAL;
 830         }
 831
 832         connector = obj_to_connector(obj);
 833         crtc = connector->encoder->crtc;
 834         psb_intel_crtc = to_psb_intel_crtc(crtc);
 835
 836         for (i = 0; i < 256; i++)
 837                 psb_intel_crtc->lut_adj[i] = lut_arg->lut[i];
 838
 839         psb_intel_crtc_load_lut(crtc);
 840
 841         return 0;
 842 }
 843
 844 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
 845                                 struct drm_file *file_priv)
 846 {
 847         uint32_t obj_id;
 848         uint16_t op;
 849         struct drm_mode_modeinfo *umode;
 850         struct drm_display_mode *mode = NULL;
 851         struct drm_psb_mode_operation_arg *arg;
 852         struct drm_mode_object *obj;
 853         struct drm_connector *connector;
 854         struct drm_framebuffer *drm_fb;
 855         struct psb_framebuffer *psb_fb;
 856         struct drm_connector_helper_funcs *connector_funcs;
 857         int ret = 0;
 858         int resp = MODE_OK;
 859         struct drm_psb_private *dev_priv = psb_priv(dev);
 860
 861         arg = (struct drm_psb_mode_operation_arg *)data;
 862         obj_id = arg->obj_id;
 863         op = arg->operation;
 864
 865         switch (op) {
 866         case PSB_MODE_OPERATION_SET_DC_BASE:
 867                 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_FB);
 868                 if (!obj) {
 869                         DRM_ERROR("Invalid FB id %d\n", obj_id);
 870                         return -EINVAL;
 871                 }
 872
 873                 drm_fb = obj_to_fb(obj);
 874                 psb_fb = to_psb_fb(drm_fb);
 875
 876                 if (gma_power_begin(dev, 0)) {
 877                         REG_WRITE(DSPASURF, psb_fb->gtt->offset);
 878                         REG_READ(DSPASURF);
 879                         gma_power_end(dev);
 880                 } else {
 881                         dev_priv->saveDSPASURF = psb_fb->gtt->offset;
 882                 }
 883
 884                 return 0;
 885         case PSB_MODE_OPERATION_MODE_VALID:
 886                 umode = &arg->mode;
 887
 888                 mutex_lock(&dev->mode_config.mutex);
 889
 890                 obj = drm_mode_object_find(dev, obj_id,
 891                                         DRM_MODE_OBJECT_CONNECTOR);
 892                 if (!obj) {
 893                         ret = -EINVAL;
 894                         goto mode_op_out;
 895                 }
 896
 897                 connector = obj_to_connector(obj);
 898
 899                 mode = drm_mode_create(dev);
 900                 if (!mode) {
 901                         ret = -ENOMEM;
 902                         goto mode_op_out;
 903                 }
 904
 905                 /* drm_crtc_convert_umode(mode, umode); */
 906                 {
 907                         mode->clock = umode->clock;
 908                         mode->hdisplay = umode->hdisplay;
 909                         mode->hsync_start = umode->hsync_start;
 910                         mode->hsync_end = umode->hsync_end;
 911                         mode->htotal = umode->htotal;
 912                         mode->hskew = umode->hskew;
 913                         mode->vdisplay = umode->vdisplay;
 914                         mode->vsync_start = umode->vsync_start;
 915                         mode->vsync_end = umode->vsync_end;
 916                         mode->vtotal = umode->vtotal;
 917                         mode->vscan = umode->vscan;
 918                         mode->vrefresh = umode->vrefresh;
 919                         mode->flags = umode->flags;
 920                         mode->type = umode->type;
 921                         strncpy(mode->name, umode->name, DRM_DISPLAY_MODE_LEN);
 922                         mode->name[DRM_DISPLAY_MODE_LEN-1] = 0;
 923                 }
 924
 925                 connector_funcs = (struct drm_connector_helper_funcs *)
 926                                    connector->helper_private;
 927
 928                 if (connector_funcs->mode_valid) {
 929                         resp = connector_funcs->mode_valid(connector, mode);
 930                         arg->data = (void *)resp;
 931                 }
 932
 933                 /*do some clean up work*/
 934                 if (mode)
 935                         drm_mode_destroy(dev, mode);
 936 mode_op_out:
 937                 mutex_unlock(&dev->mode_config.mutex);
 938                 return ret;
 939
 940         default:
 941                 DRM_DEBUG("Unsupported psb mode operation");
 942                 return -EOPNOTSUPP;
 943         }
 944
 945         return 0;
 946 }
 947
 948 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
 949                                    struct drm_file *file_priv)
 950 {
 951         struct drm_psb_private *dev_priv = psb_priv(dev);
 952         struct drm_psb_stolen_memory_arg *arg = data;
 953
 954         arg->base = dev_priv->stolen_base;
 955         arg->size = dev_priv->vram_stolen_size;
 956
 957         return 0;
 958 }
 959
 960 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
 961                                  struct drm_file *file_priv)
 962 {
 963         struct drm_psb_private *dev_priv = psb_priv(dev);
 964         struct drm_psb_register_rw_arg *arg = data;
 965         bool usage = arg->b_force_hw_on ? true : false;
 966
 967         if (arg->display_write_mask != 0) {
 968                 if (gma_power_begin(dev, usage)) {
 969                         if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
 970                                 PSB_WVDC32(arg->display.pfit_controls,
 971                                            PFIT_CONTROL);
 972                         if (arg->display_write_mask &
 973                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
 974                                 PSB_WVDC32(arg->display.pfit_autoscale_ratios,
 975                                            PFIT_AUTO_RATIOS);
 976                         if (arg->display_write_mask &
 977                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
 978                                 PSB_WVDC32(
 979                                    arg->display.pfit_programmed_scale_ratios,
 980                                    PFIT_PGM_RATIOS);
 981                         if (arg->display_write_mask & REGRWBITS_PIPEASRC)
 982                                 PSB_WVDC32(arg->display.pipeasrc,
 983                                            PIPEASRC);
 984                         if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
 985                                 PSB_WVDC32(arg->display.pipebsrc,
 986                                            PIPEBSRC);
 987                         if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
 988                                 PSB_WVDC32(arg->display.vtotal_a,
 989                                            VTOTAL_A);
 990                         if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
 991                                 PSB_WVDC32(arg->display.vtotal_b,
 992                                            VTOTAL_B);
 993                         gma_power_end(dev);
 994                 } else {
 995                         if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
 996                                 dev_priv->savePFIT_CONTROL =
 997                                                 arg->display.pfit_controls;
 998                         if (arg->display_write_mask &
 999                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1000                                 dev_priv->savePFIT_AUTO_RATIOS =
1001                                         arg->display.pfit_autoscale_ratios;
1002                         if (arg->display_write_mask &
1003                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1004                                 dev_priv->savePFIT_PGM_RATIOS =
1005                                    arg->display.pfit_programmed_scale_ratios;
1006                         if (arg->display_write_mask & REGRWBITS_PIPEASRC)
1007                                 dev_priv->savePIPEASRC = arg->display.pipeasrc;
1008                         if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
1009                                 dev_priv->savePIPEBSRC = arg->display.pipebsrc;
1010                         if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
1011                                 dev_priv->saveVTOTAL_A = arg->display.vtotal_a;
1012                         if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
1013                                 dev_priv->saveVTOTAL_B = arg->display.vtotal_b;
1014                 }
1015         }
1016
1017         if (arg->display_read_mask != 0) {
1018                 if (gma_power_begin(dev, usage)) {
1019                         if (arg->display_read_mask &
1020                             REGRWBITS_PFIT_CONTROLS)
1021                                 arg->display.pfit_controls =
1022                                                 PSB_RVDC32(PFIT_CONTROL);
1023                         if (arg->display_read_mask &
1024                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1025                                 arg->display.pfit_autoscale_ratios =
1026                                                 PSB_RVDC32(PFIT_AUTO_RATIOS);
1027                         if (arg->display_read_mask &
1028                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1029                                 arg->display.pfit_programmed_scale_ratios =
1030                                                 PSB_RVDC32(PFIT_PGM_RATIOS);
1031                         if (arg->display_read_mask & REGRWBITS_PIPEASRC)
1032                                 arg->display.pipeasrc = PSB_RVDC32(PIPEASRC);
1033                         if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
1034                                 arg->display.pipebsrc = PSB_RVDC32(PIPEBSRC);
1035                         if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
1036                                 arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A);
1037                         if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
1038                                 arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B);
1039                         gma_power_end(dev);
1040                 } else {
1041                         if (arg->display_read_mask &
1042                             REGRWBITS_PFIT_CONTROLS)
1043                                 arg->display.pfit_controls =
1044                                                 dev_priv->savePFIT_CONTROL;
1045                         if (arg->display_read_mask &
1046                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1047                                 arg->display.pfit_autoscale_ratios =
1048                                                 dev_priv->savePFIT_AUTO_RATIOS;
1049                         if (arg->display_read_mask &
1050                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1051                                 arg->display.pfit_programmed_scale_ratios =
1052                                                 dev_priv->savePFIT_PGM_RATIOS;
1053                         if (arg->display_read_mask & REGRWBITS_PIPEASRC)
1054                                 arg->display.pipeasrc = dev_priv->savePIPEASRC;
1055                         if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
1056                                 arg->display.pipebsrc = dev_priv->savePIPEBSRC;
1057                         if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
1058                                 arg->display.vtotal_a = dev_priv->saveVTOTAL_A;
1059                         if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
1060                                 arg->display.vtotal_b = dev_priv->saveVTOTAL_B;
1061                 }
1062         }
1063
1064         if (arg->overlay_write_mask != 0) {
1065                 if (gma_power_begin(dev, usage)) {
1066                         if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
1067                                 PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
1068                                 PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
1069                                 PSB_WVDC32(arg->overlay.OGAMC3, OV_OGAMC3);
1070                                 PSB_WVDC32(arg->overlay.OGAMC2, OV_OGAMC2);
1071                                 PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1);
1072                                 PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0);
1073                         }
1074                         if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
1075                                 PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5);
1076                                 PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4);
1077                                 PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3);
1078                                 PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2);
1079                                 PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1);
1080                                 PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0);
1081                         }
1082
1083                         if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) {
1084                                 PSB_WVDC32(arg->overlay.OVADD, OV_OVADD);
1085
1086                                 if (arg->overlay.b_wait_vblank) {
1087                                         /* Wait for 20ms.*/
1088                                         unsigned long vblank_timeout = jiffies
1089                                                                 + HZ/50;
1090                                         uint32_t temp;
1091                                         while (time_before_eq(jiffies,
1092                                                         vblank_timeout)) {
1093                                                 temp = PSB_RVDC32(OV_DOVASTA);
1094                                                 if ((temp & (0x1 << 31)) != 0)
1095                                                         break;
1096                                                 cpu_relax();
1097                                         }
1098                                 }
1099                         }
1100                         if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) {
1101                                 PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD);
1102                                 if (arg->overlay.b_wait_vblank) {
1103                                         /* Wait for 20ms.*/
1104                                         unsigned long vblank_timeout =
1105                                                         jiffies + HZ/50;
1106                                         uint32_t temp;
1107                                         while (time_before_eq(jiffies,
1108                                                         vblank_timeout)) {
1109                                                 temp = PSB_RVDC32(OVC_DOVCSTA);
1110                                                 if ((temp & (0x1 << 31)) != 0)
1111                                                         break;
1112                                                 cpu_relax();
1113                                         }
1114                                 }
1115                         }
1116                         gma_power_end(dev);
1117                 } else {
1118                         if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
1119                                 dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5;
1120                                 dev_priv->saveOV_OGAMC4 = arg->overlay.OGAMC4;
1121                                 dev_priv->saveOV_OGAMC3 = arg->overlay.OGAMC3;
1122                                 dev_priv->saveOV_OGAMC2 = arg->overlay.OGAMC2;
1123                                 dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1;
1124                                 dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0;
1125                         }
1126                         if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
1127                                 dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5;
1128                                 dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4;
1129                                 dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3;
1130                                 dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2;
1131                                 dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1;
1132                                 dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0;
1133                         }
1134                         if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
1135                                 dev_priv->saveOV_OVADD = arg->overlay.OVADD;
1136                         if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
1137                                 dev_priv->saveOVC_OVADD = arg->overlay.OVADD;
1138                 }
1139         }
1140
1141         if (arg->overlay_read_mask != 0) {
1142                 if (gma_power_begin(dev, usage)) {
1143                         if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
1144                                 arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
1145                                 arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
1146                                 arg->overlay.OGAMC3 = PSB_RVDC32(OV_OGAMC3);
1147                                 arg->overlay.OGAMC2 = PSB_RVDC32(OV_OGAMC2);
1148                                 arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1);
1149                                 arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0);
1150                         }
1151                         if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
1152                                 arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5);
1153                                 arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4);
1154                                 arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3);
1155                                 arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2);
1156                                 arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1);
1157                                 arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0);
1158                         }
1159                         if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
1160                                 arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
1161                         if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
1162                                 arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
1163                         gma_power_end(dev);
1164                 } else {
1165                         if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
1166                                 arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5;
1167                                 arg->overlay.OGAMC4 = dev_priv->saveOV_OGAMC4;
1168                                 arg->overlay.OGAMC3 = dev_priv->saveOV_OGAMC3;
1169                                 arg->overlay.OGAMC2 = dev_priv->saveOV_OGAMC2;
1170                                 arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1;
1171                                 arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0;
1172                         }
1173                         if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
1174                                 arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5;
1175                                 arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4;
1176                                 arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3;
1177                                 arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2;
1178                                 arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1;
1179                                 arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0;
1180                         }
1181                         if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
1182                                 arg->overlay.OVADD = dev_priv->saveOV_OVADD;
1183                         if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
1184                                 arg->overlay.OVADD = dev_priv->saveOVC_OVADD;
1185                 }
1186         }
1187
1188         if (arg->sprite_enable_mask != 0) {
1189                 if (gma_power_begin(dev, usage)) {
1190                         PSB_WVDC32(0x1F3E, DSPARB);
1191                         PSB_WVDC32(arg->sprite.dspa_control
1192                                         | PSB_RVDC32(DSPACNTR), DSPACNTR);
1193                         PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
1194                         PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK);
1195                         PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF);
1196                         PSB_RVDC32(DSPASURF);
1197                         PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR);
1198                         PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE);
1199                         PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS);
1200                         PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF);
1201                         PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
1202                         PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
1203                         PSB_RVDC32(DSPCSURF);
1204                         gma_power_end(dev);
1205                 }
1206         }
1207
1208         if (arg->sprite_disable_mask != 0) {
1209                 if (gma_power_begin(dev, usage)) {
1210                         PSB_WVDC32(0x3F3E, DSPARB);
1211                         PSB_WVDC32(0x0, DSPCCNTR);
1212                         PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
1213                         PSB_RVDC32(DSPCSURF);
1214                         gma_power_end(dev);
1215                 }
1216         }
1217
1218         if (arg->subpicture_enable_mask != 0) {
1219                 if (gma_power_begin(dev, usage)) {
1220                         uint32_t temp;
1221                         if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
1222                                 temp =  PSB_RVDC32(DSPACNTR);
1223                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1224                                 temp &= ~DISPPLANE_BOTTOM;
1225                                 temp |= DISPPLANE_32BPP;
1226                                 PSB_WVDC32(temp, DSPACNTR);
1227
1228                                 temp =  PSB_RVDC32(DSPABASE);
1229                                 PSB_WVDC32(temp, DSPABASE);
1230                                 PSB_RVDC32(DSPABASE);
1231                                 temp =  PSB_RVDC32(DSPASURF);
1232                                 PSB_WVDC32(temp, DSPASURF);
1233                                 PSB_RVDC32(DSPASURF);
1234                         }
1235                         if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) {
1236                                 temp =  PSB_RVDC32(DSPBCNTR);
1237                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1238                                 temp &= ~DISPPLANE_BOTTOM;
1239                                 temp |= DISPPLANE_32BPP;
1240                                 PSB_WVDC32(temp, DSPBCNTR);
1241
1242                                 temp =  PSB_RVDC32(DSPBBASE);
1243                                 PSB_WVDC32(temp, DSPBBASE);
1244                                 PSB_RVDC32(DSPBBASE);
1245                                 temp =  PSB_RVDC32(DSPBSURF);
1246                                 PSB_WVDC32(temp, DSPBSURF);
1247                                 PSB_RVDC32(DSPBSURF);
1248                         }
1249                         if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) {
1250                                 temp =  PSB_RVDC32(DSPCCNTR);
1251                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1252                                 temp &= ~DISPPLANE_BOTTOM;
1253                                 temp |= DISPPLANE_32BPP;
1254                                 PSB_WVDC32(temp, DSPCCNTR);
1255
1256                                 temp =  PSB_RVDC32(DSPCBASE);
1257                                 PSB_WVDC32(temp, DSPCBASE);
1258                                 PSB_RVDC32(DSPCBASE);
1259                                 temp =  PSB_RVDC32(DSPCSURF);
1260                                 PSB_WVDC32(temp, DSPCSURF);
1261                                 PSB_RVDC32(DSPCSURF);
1262                         }
1263                         gma_power_end(dev);
1264                 }
1265         }
1266
1267         if (arg->subpicture_disable_mask != 0) {
1268                 if (gma_power_begin(dev, usage)) {
1269                         uint32_t temp;
1270                         if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
1271                                 temp =  PSB_RVDC32(DSPACNTR);
1272                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1273                                 temp |= DISPPLANE_32BPP_NO_ALPHA;
1274                                 PSB_WVDC32(temp, DSPACNTR);
1275
1276                                 temp =  PSB_RVDC32(DSPABASE);
1277                                 PSB_WVDC32(temp, DSPABASE);
1278                                 PSB_RVDC32(DSPABASE);
1279                                 temp =  PSB_RVDC32(DSPASURF);
1280                                 PSB_WVDC32(temp, DSPASURF);
1281                                 PSB_RVDC32(DSPASURF);
1282                         }
1283                         if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) {
1284                                 temp =  PSB_RVDC32(DSPBCNTR);
1285                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1286                                 temp |= DISPPLANE_32BPP_NO_ALPHA;
1287                                 PSB_WVDC32(temp, DSPBCNTR);
1288
1289                                 temp =  PSB_RVDC32(DSPBBASE);
1290                                 PSB_WVDC32(temp, DSPBBASE);
1291                                 PSB_RVDC32(DSPBBASE);
1292                                 temp =  PSB_RVDC32(DSPBSURF);
1293                                 PSB_WVDC32(temp, DSPBSURF);
1294                                 PSB_RVDC32(DSPBSURF);
1295                         }
1296                         if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) {
1297                                 temp =  PSB_RVDC32(DSPCCNTR);
1298                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1299                                 temp |= DISPPLANE_32BPP_NO_ALPHA;
1300                                 PSB_WVDC32(temp, DSPCCNTR);
1301
1302                                 temp =  PSB_RVDC32(DSPCBASE);
1303                                 PSB_WVDC32(temp, DSPCBASE);
1304                                 PSB_RVDC32(DSPCBASE);
1305                                 temp =  PSB_RVDC32(DSPCSURF);
1306                                 PSB_WVDC32(temp, DSPCSURF);
1307                                 PSB_RVDC32(DSPCSURF);
1308                         }
1309                         gma_power_end(dev);
1310                 }
1311         }
1312
1313         return 0;
1314 }
1315
1316 static int psb_driver_open(struct drm_device *dev, struct drm_file *priv)
1317 {
1318         return 0;
1319 }
1320
1321 static void psb_driver_close(struct drm_device *dev, struct drm_file *priv)
1322 {
1323 }
1324
1325 static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd,
1326                                unsigned long arg)
1327 {
1328         struct drm_file *file_priv = filp->private_data;
1329         struct drm_device *dev = file_priv->minor->dev;
1330         struct drm_psb_private *dev_priv = dev->dev_private;
1331         static unsigned int runtime_allowed;
1332         unsigned int nr = DRM_IOCTL_NR(cmd);
1333
1334         DRM_DEBUG("cmd = %x, nr = %x\n", cmd, nr);
1335
1336         if (runtime_allowed == 1 && dev_priv->is_lvds_on) {
1337                 runtime_allowed++;
1338                 pm_runtime_allow(&dev->pdev->dev);
1339                 dev_priv->rpm_enabled = 1;
1340         }
1341         return drm_ioctl(filp, cmd, arg);
1342
1343         /* FIXME: do we need to wrap the other side of this */
1344 }
1345
1346
1347 /* When a client dies:
1348  *    - Check for and clean up flipped page state
1349  */
1350 void psb_driver_preclose(struct drm_device *dev, struct drm_file *priv)
1351 {
1352 }
1353
1354 static void psb_remove(struct pci_dev *pdev)
1355 {
1356         struct drm_device *dev = pci_get_drvdata(pdev);
1357         drm_put_dev(dev);
1358 }
1359
1360 static const struct dev_pm_ops psb_pm_ops = {
1361         .runtime_suspend = psb_runtime_suspend,
1362         .runtime_resume = psb_runtime_resume,
1363         .runtime_idle = psb_runtime_idle,
1364 };
1365
1366 static struct vm_operations_struct psb_gem_vm_ops = {
1367         .fault = psb_gem_fault,
1368         .open = drm_gem_vm_open,
1369         .close = drm_gem_vm_close,
1370 };
1371
1372 static struct drm_driver driver = {
1373         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \
1374                            DRIVER_IRQ_VBL | DRIVER_MODESET| DRIVER_GEM ,
1375         .load = psb_driver_load,
1376         .unload = psb_driver_unload,
1377
1378         .ioctls = psb_ioctls,
1379         .num_ioctls = DRM_ARRAY_SIZE(psb_ioctls),
1380         .device_is_agp = psb_driver_device_is_agp,
1381         .irq_preinstall = psb_irq_preinstall,
1382         .irq_postinstall = psb_irq_postinstall,
1383         .irq_uninstall = psb_irq_uninstall,
1384         .irq_handler = psb_irq_handler,
1385         .enable_vblank = psb_enable_vblank,
1386         .disable_vblank = psb_disable_vblank,
1387         .get_vblank_counter = psb_get_vblank_counter,
1388         .lastclose = psb_lastclose,
1389         .open = psb_driver_open,
1390         .preclose = psb_driver_preclose,
1391         .postclose = psb_driver_close,
1392         .reclaim_buffers = drm_core_reclaim_buffers,
1393
1394         .gem_init_object = psb_gem_init_object,
1395         .gem_free_object = psb_gem_free_object,
1396         .gem_vm_ops = &psb_gem_vm_ops,
1397         .dumb_create = psb_gem_dumb_create,
1398         .dumb_map_offset = psb_gem_dumb_map_gtt,
1399         .dumb_destroy = psb_gem_dumb_destroy,
1400
1401         .fops = {
1402                  .owner = THIS_MODULE,
1403                  .open = drm_open,
1404                  .release = drm_release,
1405                  .unlocked_ioctl = psb_unlocked_ioctl,
1406                  .mmap = drm_gem_mmap,
1407                  .poll = drm_poll,
1408                  .fasync = drm_fasync,
1409                  .read = drm_read,
1410          },
1411         .name = DRIVER_NAME,
1412         .desc = DRIVER_DESC,
1413         .date = PSB_DRM_DRIVER_DATE,
1414         .major = PSB_DRM_DRIVER_MAJOR,
1415         .minor = PSB_DRM_DRIVER_MINOR,
1416         .patchlevel = PSB_DRM_DRIVER_PATCHLEVEL
1417 };
1418
1419 static struct pci_driver psb_pci_driver = {
1420         .name = DRIVER_NAME,
1421         .id_table = pciidlist,
1422         .resume = gma_power_resume,
1423         .suspend = gma_power_suspend,
1424         .probe = psb_probe,
1425         .remove = psb_remove,
1426 #ifdef CONFIG_PM
1427         .driver.pm = &psb_pm_ops,
1428 #endif
1429 };
1430
1431 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1432 {
1433         /* MLD Added this from Inaky's patch */
1434         if (pci_enable_msi(pdev))
1435                 DRM_ERROR("Enable MSI failed!\n");
1436         return drm_get_pci_dev(pdev, ent, &driver);
1437 }
1438
1439 static int __init psb_init(void)
1440 {
1441         return drm_pci_init(&driver, &psb_pci_driver);
1442 }
1443
1444 static void __exit psb_exit(void)
1445 {
1446         drm_pci_exit(&driver, &psb_pci_driver);
1447 }
1448
1449 late_initcall(psb_init);
1450 module_exit(psb_exit);
1451
1452 MODULE_AUTHOR(DRIVER_AUTHOR);
1453 MODULE_DESCRIPTION(DRIVER_DESC);
1454 MODULE_LICENSE("GPL");