drivers/staging/cx25821/cx25821-video-upstream-ch2.c

   1 /*
   2  *  Driver for the Conexant CX25821 PCIe bridge
   3  *
   4  *  Copyright (C) 2009 Conexant Systems Inc.
   5  *  Authors  <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include "cx25821-video.h"
  24 #include "cx25821-video-upstream-ch2.h"
  25
  26 #include <linux/fs.h>
  27 #include <linux/errno.h>
  28 #include <linux/kernel.h>
  29 #include <linux/init.h>
  30 #include <linux/module.h>
  31 #include <linux/syscalls.h>
  32 #include <linux/file.h>
  33 #include <linux/fcntl.h>
  34 #include <linux/slab.h>
  35 #include <asm/uaccess.h>
  36
  37 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
  38 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
  39 MODULE_LICENSE("GPL");
  40
  41 static int _intr_msk =
  42     FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
  43
  44 static __le32 *cx25821_update_riscprogram_ch2(struct cx25821_dev *dev,
  45                                               __le32 * rp, unsigned int offset,
  46                                               unsigned int bpl, u32 sync_line,
  47                                               unsigned int lines,
  48                                               int fifo_enable, int field_type)
  49 {
  50         unsigned int line, i;
  51         int dist_betwn_starts = bpl * 2;
  52
  53         *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
  54
  55         if (USE_RISC_NOOP_VIDEO) {
  56                 for (i = 0; i < NUM_NO_OPS; i++) {
  57                         *(rp++) = cpu_to_le32(RISC_NOOP);
  58                 }
  59         }
  60
  61         /* scan lines */
  62         for (line = 0; line < lines; line++) {
  63                 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
  64                 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr_ch2 + offset);
  65                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
  66
  67                 if ((lines <= NTSC_FIELD_HEIGHT)
  68                     || (line < (NTSC_FIELD_HEIGHT - 1))
  69                     || !(dev->_isNTSC_ch2)) {
  70                         offset += dist_betwn_starts;
  71                 }
  72         }
  73
  74         return rp;
  75 }
  76
  77 static __le32 *cx25821_risc_field_upstream_ch2(struct cx25821_dev *dev,
  78                                                __le32 * rp,
  79                                                dma_addr_t databuf_phys_addr,
  80                                                unsigned int offset,
  81                                                u32 sync_line, unsigned int bpl,
  82                                                unsigned int lines,
  83                                                int fifo_enable, int field_type)
  84 {
  85         unsigned int line, i;
  86         struct sram_channel *sram_ch =
  87            dev->channels[dev->_channel2_upstream_select].sram_channels;
  88         int dist_betwn_starts = bpl * 2;
  89
  90         /* sync instruction */
  91         if (sync_line != NO_SYNC_LINE) {
  92                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
  93         }
  94
  95         if (USE_RISC_NOOP_VIDEO) {
  96                 for (i = 0; i < NUM_NO_OPS; i++) {
  97                         *(rp++) = cpu_to_le32(RISC_NOOP);
  98                 }
  99         }
 100
 101         /* scan lines */
 102         for (line = 0; line < lines; line++) {
 103                 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
 104                 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
 105                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
 106
 107                 if ((lines <= NTSC_FIELD_HEIGHT)
 108                     || (line < (NTSC_FIELD_HEIGHT - 1))
 109                     || !(dev->_isNTSC_ch2)) {
 110                         offset += dist_betwn_starts;
 111                 }
 112
 113                /*
 114                  check if we need to enable the FIFO after the first 4 lines
 115                   For the upstream video channel, the risc engine will enable
 116                   the FIFO.
 117                */
 118                 if (fifo_enable && line == 3) {
 119                         *(rp++) = RISC_WRITECR;
 120                         *(rp++) = sram_ch->dma_ctl;
 121                         *(rp++) = FLD_VID_FIFO_EN;
 122                         *(rp++) = 0x00000001;
 123                 }
 124         }
 125
 126         return rp;
 127 }
 128
 129 int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev,
 130                                      struct pci_dev *pci,
 131                                      unsigned int top_offset, unsigned int bpl,
 132                                      unsigned int lines)
 133 {
 134         __le32 *rp;
 135         int fifo_enable = 0;
 136        int singlefield_lines = lines >> 1; /*get line count for single field */
 137         int odd_num_lines = singlefield_lines;
 138         int frame = 0;
 139         int frame_size = 0;
 140         int databuf_offset = 0;
 141         int risc_program_size = 0;
 142         int risc_flag = RISC_CNT_RESET;
 143         unsigned int bottom_offset = bpl;
 144         dma_addr_t risc_phys_jump_addr;
 145
 146         if (dev->_isNTSC_ch2) {
 147                 odd_num_lines = singlefield_lines + 1;
 148                 risc_program_size = FRAME1_VID_PROG_SIZE;
 149                 frame_size =
 150                     (bpl ==
 151                      Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
 152                     FRAME_SIZE_NTSC_Y422;
 153         } else {
 154                 risc_program_size = PAL_VID_PROG_SIZE;
 155                 frame_size =
 156                     (bpl ==
 157                      Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
 158         }
 159
 160         /* Virtual address of Risc buffer program */
 161         rp = dev->_dma_virt_addr_ch2;
 162
 163         for (frame = 0; frame < NUM_FRAMES; frame++) {
 164                 databuf_offset = frame_size * frame;
 165
 166                 if (UNSET != top_offset) {
 167                         fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
 168                         rp = cx25821_risc_field_upstream_ch2(dev, rp,
 169                                                              dev->
 170                                                              _data_buf_phys_addr_ch2
 171                                                              + databuf_offset,
 172                                                              top_offset, 0, bpl,
 173                                                              odd_num_lines,
 174                                                              fifo_enable,
 175                                                              ODD_FIELD);
 176                 }
 177
 178                 fifo_enable = FIFO_DISABLE;
 179
 180                /* Even field */
 181                 rp = cx25821_risc_field_upstream_ch2(dev, rp,
 182                                                      dev->
 183                                                      _data_buf_phys_addr_ch2 +
 184                                                      databuf_offset,
 185                                                      bottom_offset, 0x200, bpl,
 186                                                      singlefield_lines,
 187                                                      fifo_enable, EVEN_FIELD);
 188
 189                 if (frame == 0) {
 190                         risc_flag = RISC_CNT_RESET;
 191                         risc_phys_jump_addr =
 192                             dev->_dma_phys_start_addr_ch2 + risc_program_size;
 193                 } else {
 194                         risc_flag = RISC_CNT_INC;
 195                         risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2;
 196                 }
 197
 198                /*
 199                   Loop to 2ndFrameRISC or to Start of
 200                   Risc program & generate IRQ
 201                */
 202                 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
 203                 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
 204                 *(rp++) = cpu_to_le32(0);
 205         }
 206
 207         return 0;
 208 }
 209
 210 void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev)
 211 {
 212         struct sram_channel *sram_ch =
 213            dev->channels[VID_UPSTREAM_SRAM_CHANNEL_J].sram_channels;
 214         u32 tmp = 0;
 215
 216         if (!dev->_is_running_ch2) {
 217                 printk
 218                     ("cx25821: No video file is currently running so return!\n");
 219                 return;
 220         }
 221        /* Disable RISC interrupts */
 222         tmp = cx_read(sram_ch->int_msk);
 223         cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
 224
 225        /* Turn OFF risc and fifo */
 226         tmp = cx_read(sram_ch->dma_ctl);
 227         cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
 228
 229        /* Clear data buffer memory */
 230         if (dev->_data_buf_virt_addr_ch2)
 231                 memset(dev->_data_buf_virt_addr_ch2, 0,
 232                        dev->_data_buf_size_ch2);
 233
 234         dev->_is_running_ch2 = 0;
 235         dev->_is_first_frame_ch2 = 0;
 236         dev->_frame_count_ch2 = 0;
 237         dev->_file_status_ch2 = END_OF_FILE;
 238
 239         if (dev->_irq_queues_ch2) {
 240                 kfree(dev->_irq_queues_ch2);
 241                 dev->_irq_queues_ch2 = NULL;
 242         }
 243
 244         if (dev->_filename_ch2 != NULL)
 245                 kfree(dev->_filename_ch2);
 246
 247         tmp = cx_read(VID_CH_MODE_SEL);
 248         cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
 249 }
 250
 251 void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev)
 252 {
 253         if (dev->_is_running_ch2) {
 254                 cx25821_stop_upstream_video_ch2(dev);
 255         }
 256
 257         if (dev->_dma_virt_addr_ch2) {
 258                 pci_free_consistent(dev->pci, dev->_risc_size_ch2,
 259                                     dev->_dma_virt_addr_ch2,
 260                                     dev->_dma_phys_addr_ch2);
 261                 dev->_dma_virt_addr_ch2 = NULL;
 262         }
 263
 264         if (dev->_data_buf_virt_addr_ch2) {
 265                 pci_free_consistent(dev->pci, dev->_data_buf_size_ch2,
 266                                     dev->_data_buf_virt_addr_ch2,
 267                                     dev->_data_buf_phys_addr_ch2);
 268                 dev->_data_buf_virt_addr_ch2 = NULL;
 269         }
 270 }
 271
 272 int cx25821_get_frame_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
 273 {
 274         struct file *myfile;
 275         int frame_index_temp = dev->_frame_index_ch2;
 276         int i = 0;
 277         int line_size =
 278             (dev->_pixel_format_ch2 ==
 279              PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
 280         int frame_size = 0;
 281         int frame_offset = 0;
 282         ssize_t vfs_read_retval = 0;
 283         char mybuf[line_size];
 284         loff_t file_offset;
 285         loff_t pos;
 286         mm_segment_t old_fs;
 287
 288         if (dev->_file_status_ch2 == END_OF_FILE)
 289                 return 0;
 290
 291         if (dev->_isNTSC_ch2) {
 292                 frame_size =
 293                     (line_size ==
 294                      Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
 295                     FRAME_SIZE_NTSC_Y422;
 296         } else {
 297                 frame_size =
 298                     (line_size ==
 299                      Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
 300         }
 301
 302         frame_offset = (frame_index_temp > 0) ? frame_size : 0;
 303         file_offset = dev->_frame_count_ch2 * frame_size;
 304
 305         myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
 306
 307         if (IS_ERR(myfile)) {
 308                 const int open_errno = -PTR_ERR(myfile);
 309                 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
 310                        __func__, dev->_filename_ch2, open_errno);
 311                 return PTR_ERR(myfile);
 312         } else {
 313                 if (!(myfile->f_op)) {
 314                         printk("%s: File has no file operations registered!",
 315                                __func__);
 316                         filp_close(myfile, NULL);
 317                         return -EIO;
 318                 }
 319
 320                 if (!myfile->f_op->read) {
 321                         printk("%s: File has no READ operations registered!",
 322                                __func__);
 323                         filp_close(myfile, NULL);
 324                         return -EIO;
 325                 }
 326
 327                 pos = myfile->f_pos;
 328                 old_fs = get_fs();
 329                 set_fs(KERNEL_DS);
 330
 331                 for (i = 0; i < dev->_lines_count_ch2; i++) {
 332                         pos = file_offset;
 333
 334                         vfs_read_retval =
 335                             vfs_read(myfile, mybuf, line_size, &pos);
 336
 337                         if (vfs_read_retval > 0 && vfs_read_retval == line_size
 338                             && dev->_data_buf_virt_addr_ch2 != NULL) {
 339                                 memcpy((void *)(dev->_data_buf_virt_addr_ch2 +
 340                                                 frame_offset / 4), mybuf,
 341                                        vfs_read_retval);
 342                         }
 343
 344                         file_offset += vfs_read_retval;
 345                         frame_offset += vfs_read_retval;
 346
 347                         if (vfs_read_retval < line_size) {
 348                                 printk(KERN_INFO
 349                                        "Done: exit %s() since no more bytes to read from Video file.\n",
 350                                        __func__);
 351                                 break;
 352                         }
 353                 }
 354
 355                 if (i > 0)
 356                         dev->_frame_count_ch2++;
 357
 358                 dev->_file_status_ch2 =
 359                     (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
 360
 361                 set_fs(old_fs);
 362                 filp_close(myfile, NULL);
 363         }
 364
 365         return 0;
 366 }
 367
 368 static void cx25821_vidups_handler_ch2(struct work_struct *work)
 369 {
 370         struct cx25821_dev *dev =
 371             container_of(work, struct cx25821_dev, _irq_work_entry_ch2);
 372
 373         if (!dev) {
 374                 printk("ERROR %s(): since container_of(work_struct) FAILED! \n",
 375                        __func__);
 376                 return;
 377         }
 378
 379         cx25821_get_frame_ch2(dev,
 380                              dev->channels[dev->
 381                                _channel2_upstream_select].sram_channels);
 382 }
 383
 384 int cx25821_openfile_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
 385 {
 386         struct file *myfile;
 387         int i = 0, j = 0;
 388         int line_size =
 389             (dev->_pixel_format_ch2 ==
 390              PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
 391         ssize_t vfs_read_retval = 0;
 392         char mybuf[line_size];
 393         loff_t pos;
 394         loff_t offset = (unsigned long)0;
 395         mm_segment_t old_fs;
 396
 397         myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
 398
 399         if (IS_ERR(myfile)) {
 400                 const int open_errno = -PTR_ERR(myfile);
 401                 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
 402                        __func__, dev->_filename_ch2, open_errno);
 403                 return PTR_ERR(myfile);
 404         } else {
 405                 if (!(myfile->f_op)) {
 406                         printk("%s: File has no file operations registered!",
 407                                __func__);
 408                         filp_close(myfile, NULL);
 409                         return -EIO;
 410                 }
 411
 412                 if (!myfile->f_op->read) {
 413                         printk
 414                             ("%s: File has no READ operations registered!  Returning.",
 415                              __func__);
 416                         filp_close(myfile, NULL);
 417                         return -EIO;
 418                 }
 419
 420                 pos = myfile->f_pos;
 421                 old_fs = get_fs();
 422                 set_fs(KERNEL_DS);
 423
 424                 for (j = 0; j < NUM_FRAMES; j++) {
 425                         for (i = 0; i < dev->_lines_count_ch2; i++) {
 426                                 pos = offset;
 427
 428                                 vfs_read_retval =
 429                                     vfs_read(myfile, mybuf, line_size, &pos);
 430
 431                                 if (vfs_read_retval > 0
 432                                     && vfs_read_retval == line_size
 433                                     && dev->_data_buf_virt_addr_ch2 != NULL) {
 434                                         memcpy((void *)(dev->
 435                                                         _data_buf_virt_addr_ch2
 436                                                         + offset / 4), mybuf,
 437                                                vfs_read_retval);
 438                                 }
 439
 440                                 offset += vfs_read_retval;
 441
 442                                 if (vfs_read_retval < line_size) {
 443                                         printk(KERN_INFO
 444                                                "Done: exit %s() since no more bytes to read from Video file.\n",
 445                                                __func__);
 446                                         break;
 447                                 }
 448                         }
 449
 450                         if (i > 0)
 451                                 dev->_frame_count_ch2++;
 452
 453                         if (vfs_read_retval < line_size) {
 454                                 break;
 455                         }
 456                 }
 457
 458                 dev->_file_status_ch2 =
 459                     (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
 460
 461                 set_fs(old_fs);
 462                 myfile->f_pos = 0;
 463                 filp_close(myfile, NULL);
 464         }
 465
 466         return 0;
 467 }
 468
 469 static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev,
 470                                                struct sram_channel *sram_ch,
 471                                                int bpl)
 472 {
 473         int ret = 0;
 474         dma_addr_t dma_addr;
 475         dma_addr_t data_dma_addr;
 476
 477         if (dev->_dma_virt_addr_ch2 != NULL) {
 478                 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
 479                                     dev->_dma_virt_addr_ch2,
 480                                     dev->_dma_phys_addr_ch2);
 481         }
 482
 483         dev->_dma_virt_addr_ch2 =
 484             pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
 485                                  &dma_addr);
 486         dev->_dma_virt_start_addr_ch2 = dev->_dma_virt_addr_ch2;
 487         dev->_dma_phys_start_addr_ch2 = dma_addr;
 488         dev->_dma_phys_addr_ch2 = dma_addr;
 489         dev->_risc_size_ch2 = dev->upstream_riscbuf_size_ch2;
 490
 491         if (!dev->_dma_virt_addr_ch2) {
 492                 printk
 493                     ("cx25821: FAILED to allocate memory for Risc buffer! Returning.\n");
 494                 return -ENOMEM;
 495         }
 496
 497        /* Iniitize at this address until n bytes to 0 */
 498         memset(dev->_dma_virt_addr_ch2, 0, dev->_risc_size_ch2);
 499
 500         if (dev->_data_buf_virt_addr_ch2 != NULL) {
 501                 pci_free_consistent(dev->pci, dev->upstream_databuf_size_ch2,
 502                                     dev->_data_buf_virt_addr_ch2,
 503                                     dev->_data_buf_phys_addr_ch2);
 504         }
 505        /* For Video Data buffer allocation */
 506         dev->_data_buf_virt_addr_ch2 =
 507             pci_alloc_consistent(dev->pci, dev->upstream_databuf_size_ch2,
 508                                  &data_dma_addr);
 509         dev->_data_buf_phys_addr_ch2 = data_dma_addr;
 510         dev->_data_buf_size_ch2 = dev->upstream_databuf_size_ch2;
 511
 512         if (!dev->_data_buf_virt_addr_ch2) {
 513                 printk
 514                     ("cx25821: FAILED to allocate memory for data buffer! Returning.\n");
 515                 return -ENOMEM;
 516         }
 517
 518        /* Initialize at this address until n bytes to 0 */
 519         memset(dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2);
 520
 521         ret = cx25821_openfile_ch2(dev, sram_ch);
 522         if (ret < 0)
 523                 return ret;
 524
 525        /* Creating RISC programs */
 526         ret =
 527             cx25821_risc_buffer_upstream_ch2(dev, dev->pci, 0, bpl,
 528                                              dev->_lines_count_ch2);
 529         if (ret < 0) {
 530                 printk(KERN_INFO
 531                        "cx25821: Failed creating Video Upstream Risc programs! \n");
 532                 goto error;
 533         }
 534
 535         return 0;
 536
 537       error:
 538         return ret;
 539 }
 540
 541 int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev, int chan_num,
 542                                    u32 status)
 543 {
 544         u32 int_msk_tmp;
 545        struct sram_channel *channel = dev->channels[chan_num].sram_channels;
 546         int singlefield_lines = NTSC_FIELD_HEIGHT;
 547         int line_size_in_bytes = Y422_LINE_SZ;
 548         int odd_risc_prog_size = 0;
 549         dma_addr_t risc_phys_jump_addr;
 550         __le32 *rp;
 551
 552         if (status & FLD_VID_SRC_RISC1) {
 553                /* We should only process one program per call */
 554                 u32 prog_cnt = cx_read(channel->gpcnt);
 555
 556                /*
 557                   Since we've identified our IRQ, clear our bits from the
 558                   interrupt mask and interrupt status registers
 559                */
 560                 int_msk_tmp = cx_read(channel->int_msk);
 561                 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
 562                 cx_write(channel->int_stat, _intr_msk);
 563
 564                 spin_lock(&dev->slock);
 565
 566                 dev->_frame_index_ch2 = prog_cnt;
 567
 568                 queue_work(dev->_irq_queues_ch2, &dev->_irq_work_entry_ch2);
 569
 570                 if (dev->_is_first_frame_ch2) {
 571                         dev->_is_first_frame_ch2 = 0;
 572
 573                         if (dev->_isNTSC_ch2) {
 574                                 singlefield_lines += 1;
 575                                 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
 576                         } else {
 577                                 singlefield_lines = PAL_FIELD_HEIGHT;
 578                                 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
 579                         }
 580
 581                         if (dev->_dma_virt_start_addr_ch2 != NULL) {
 582                                 line_size_in_bytes =
 583                                     (dev->_pixel_format_ch2 ==
 584                                      PIXEL_FRMT_411) ? Y411_LINE_SZ :
 585                                     Y422_LINE_SZ;
 586                                 risc_phys_jump_addr =
 587                                     dev->_dma_phys_start_addr_ch2 +
 588                                     odd_risc_prog_size;
 589
 590                                 rp = cx25821_update_riscprogram_ch2(dev,
 591                                                                     dev->
 592                                                                     _dma_virt_start_addr_ch2,
 593                                                                     TOP_OFFSET,
 594                                                                     line_size_in_bytes,
 595                                                                     0x0,
 596                                                                     singlefield_lines,
 597                                                                     FIFO_DISABLE,
 598                                                                     ODD_FIELD);
 599
 600                                /* Jump to Even Risc program of 1st Frame */
 601                                 *(rp++) = cpu_to_le32(RISC_JUMP);
 602                                 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
 603                                 *(rp++) = cpu_to_le32(0);
 604                         }
 605                 }
 606
 607                 spin_unlock(&dev->slock);
 608         }
 609
 610         if (dev->_file_status_ch2 == END_OF_FILE) {
 611                 printk("cx25821: EOF Channel 2 Framecount = %d\n",
 612                        dev->_frame_count_ch2);
 613                 return -1;
 614         }
 615        /* ElSE, set the interrupt mask register, re-enable irq. */
 616         int_msk_tmp = cx_read(channel->int_msk);
 617         cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
 618
 619         return 0;
 620 }
 621
 622 static irqreturn_t cx25821_upstream_irq_ch2(int irq, void *dev_id)
 623 {
 624         struct cx25821_dev *dev = dev_id;
 625         u32 msk_stat, vid_status;
 626         int handled = 0;
 627         int channel_num = 0;
 628         struct sram_channel *sram_ch;
 629
 630         if (!dev)
 631                 return -1;
 632
 633         channel_num = VID_UPSTREAM_SRAM_CHANNEL_J;
 634
 635        sram_ch = dev->channels[channel_num].sram_channels;
 636
 637         msk_stat = cx_read(sram_ch->int_mstat);
 638         vid_status = cx_read(sram_ch->int_stat);
 639
 640        /* Only deal with our interrupt */
 641         if (vid_status) {
 642                 handled =
 643                     cx25821_video_upstream_irq_ch2(dev, channel_num,
 644                                                    vid_status);
 645         }
 646
 647         if (handled < 0) {
 648                 cx25821_stop_upstream_video_ch2(dev);
 649         } else {
 650                 handled += handled;
 651         }
 652
 653         return IRQ_RETVAL(handled);
 654 }
 655
 656 static void cx25821_set_pixelengine_ch2(struct cx25821_dev *dev,
 657                                         struct sram_channel *ch, int pix_format)
 658 {
 659         int width = WIDTH_D1;
 660         int height = dev->_lines_count_ch2;
 661         int num_lines, odd_num_lines;
 662         u32 value;
 663         int vip_mode = PIXEL_ENGINE_VIP1;
 664
 665         value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
 666         value &= 0xFFFFFFEF;
 667         value |= dev->_isNTSC_ch2 ? 0 : 0x10;
 668         cx_write(ch->vid_fmt_ctl, value);
 669
 670        /*
 671           set number of active pixels in each line. Default is 720
 672           pixels in both NTSC and PAL format
 673        */
 674         cx_write(ch->vid_active_ctl1, width);
 675
 676         num_lines = (height / 2) & 0x3FF;
 677         odd_num_lines = num_lines;
 678
 679         if (dev->_isNTSC_ch2) {
 680                 odd_num_lines += 1;
 681         }
 682
 683         value = (num_lines << 16) | odd_num_lines;
 684
 685        /* set number of active lines in field 0 (top) and field 1 (bottom) */
 686         cx_write(ch->vid_active_ctl2, value);
 687
 688         cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
 689 }
 690
 691 int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev,
 692                                          struct sram_channel *sram_ch)
 693 {
 694         u32 tmp = 0;
 695         int err = 0;
 696
 697        /*
 698           656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface
 699           for channel A-C
 700        */
 701         tmp = cx_read(VID_CH_MODE_SEL);
 702         cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
 703
 704        /*
 705           Set the physical start address of the RISC program in the initial
 706           program counter(IPC) member of the cmds.
 707        */
 708         cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2);
 709        cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
 710
 711         /* reset counter */
 712         cx_write(sram_ch->gpcnt_ctl, 3);
 713
 714        /* Clear our bits from the interrupt status register. */
 715         cx_write(sram_ch->int_stat, _intr_msk);
 716
 717        /* Set the interrupt mask register, enable irq. */
 718         cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
 719         tmp = cx_read(sram_ch->int_msk);
 720         cx_write(sram_ch->int_msk, tmp |= _intr_msk);
 721
 722         err =
 723             request_irq(dev->pci->irq, cx25821_upstream_irq_ch2,
 724                         IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
 725         if (err < 0) {
 726                 printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name,
 727                        dev->pci->irq);
 728                 goto fail_irq;
 729         }
 730        /* Start the DMA  engine */
 731         tmp = cx_read(sram_ch->dma_ctl);
 732         cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
 733
 734         dev->_is_running_ch2 = 1;
 735         dev->_is_first_frame_ch2 = 1;
 736
 737         return 0;
 738
 739       fail_irq:
 740         cx25821_dev_unregister(dev);
 741         return err;
 742 }
 743
 744 int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select,
 745                                  int pixel_format)
 746 {
 747         struct sram_channel *sram_ch;
 748         u32 tmp;
 749         int retval = 0;
 750         int err = 0;
 751         int data_frame_size = 0;
 752         int risc_buffer_size = 0;
 753         int str_length = 0;
 754
 755         if (dev->_is_running_ch2) {
 756                 printk("Video Channel is still running so return!\n");
 757                 return 0;
 758         }
 759
 760         dev->_channel2_upstream_select = channel_select;
 761        sram_ch = dev->channels[channel_select].sram_channels;
 762
 763         INIT_WORK(&dev->_irq_work_entry_ch2, cx25821_vidups_handler_ch2);
 764         dev->_irq_queues_ch2 =
 765             create_singlethread_workqueue("cx25821_workqueue2");
 766
 767         if (!dev->_irq_queues_ch2) {
 768                 printk
 769                     ("cx25821: create_singlethread_workqueue() for Video FAILED!\n");
 770                 return -ENOMEM;
 771         }
 772        /*
 773           656/VIP SRC Upstream Channel I & J and 7 -
 774           Host Bus Interface for channel A-C
 775        */
 776         tmp = cx_read(VID_CH_MODE_SEL);
 777         cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
 778
 779         dev->_is_running_ch2 = 0;
 780         dev->_frame_count_ch2 = 0;
 781         dev->_file_status_ch2 = RESET_STATUS;
 782         dev->_lines_count_ch2 = dev->_isNTSC_ch2 ? 480 : 576;
 783         dev->_pixel_format_ch2 = pixel_format;
 784         dev->_line_size_ch2 =
 785             (dev->_pixel_format_ch2 ==
 786              PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
 787         data_frame_size = dev->_isNTSC_ch2 ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
 788         risc_buffer_size =
 789             dev->_isNTSC_ch2 ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
 790
 791         if (dev->input_filename_ch2) {
 792                 str_length = strlen(dev->input_filename_ch2);
 793                 dev->_filename_ch2 = kmalloc(str_length + 1, GFP_KERNEL);
 794
 795                 if (!dev->_filename_ch2)
 796                         goto error;
 797
 798                 memcpy(dev->_filename_ch2, dev->input_filename_ch2,
 799                        str_length + 1);
 800         } else {
 801                 str_length = strlen(dev->_defaultname_ch2);
 802                 dev->_filename_ch2 = kmalloc(str_length + 1, GFP_KERNEL);
 803
 804                 if (!dev->_filename_ch2)
 805                         goto error;
 806
 807                 memcpy(dev->_filename_ch2, dev->_defaultname_ch2,
 808                        str_length + 1);
 809         }
 810
 811        /* Default if filename is empty string */
 812         if (strcmp(dev->input_filename_ch2, "") == 0) {
 813                 if (dev->_isNTSC_ch2) {
 814                         dev->_filename_ch2 =
 815                             (dev->_pixel_format_ch2 ==
 816                              PIXEL_FRMT_411) ? "/root/vid411.yuv" :
 817                             "/root/vidtest.yuv";
 818                 } else {
 819                         dev->_filename_ch2 =
 820                             (dev->_pixel_format_ch2 ==
 821                              PIXEL_FRMT_411) ? "/root/pal411.yuv" :
 822                             "/root/pal422.yuv";
 823                 }
 824         }
 825
 826         retval =
 827             cx25821_sram_channel_setup_upstream(dev, sram_ch,
 828                                                 dev->_line_size_ch2, 0);
 829
 830         /* setup fifo + format */
 831         cx25821_set_pixelengine_ch2(dev, sram_ch, dev->_pixel_format_ch2);
 832
 833         dev->upstream_riscbuf_size_ch2 = risc_buffer_size * 2;
 834         dev->upstream_databuf_size_ch2 = data_frame_size * 2;
 835
 836        /* Allocating buffers and prepare RISC program */
 837         retval =
 838             cx25821_upstream_buffer_prepare_ch2(dev, sram_ch,
 839                                                 dev->_line_size_ch2);
 840         if (retval < 0) {
 841                 printk(KERN_ERR
 842                        "%s: Failed to set up Video upstream buffers!\n",
 843                        dev->name);
 844                 goto error;
 845         }
 846
 847         cx25821_start_video_dma_upstream_ch2(dev, sram_ch);
 848
 849         return 0;
 850
 851       error:
 852         cx25821_dev_unregister(dev);
 853
 854         return err;
 855 }