drivers/staging/cx25821/cx25821-video-upstream-ch2.c

   1 /*
   2  *  Driver for the Conexant CX25821 PCIe bridge
   3  *
   4  *  Copyright (C) 2009 Conexant Systems Inc.
   5  *  Authors  <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include "cx25821-video.h"
  24 #include "cx25821-video-upstream-ch2.h"
  25
  26 #include <linux/fs.h>
  27 #include <linux/errno.h>
  28 #include <linux/kernel.h>
  29 #include <linux/init.h>
  30 #include <linux/module.h>
  31 #include <linux/syscalls.h>
  32 #include <linux/file.h>
  33 #include <linux/fcntl.h>
  34 #include <linux/slab.h>
  35 #include <linux/uaccess.h>
  36
  37 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
  38 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
  39 MODULE_LICENSE("GPL");
  40
  41 static int _intr_msk =
  42         FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
  43
  44 static __le32 *cx25821_update_riscprogram_ch2(struct cx25821_dev *dev,
  45                                               __le32 *rp, unsigned int offset,
  46                                               unsigned int bpl, u32 sync_line,
  47                                               unsigned int lines,
  48                                               int fifo_enable, int field_type)
  49 {
  50         unsigned int line, i;
  51         int dist_betwn_starts = bpl * 2;
  52
  53         *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
  54
  55         if (USE_RISC_NOOP_VIDEO) {
  56                 for (i = 0; i < NUM_NO_OPS; i++)
  57                         *(rp++) = cpu_to_le32(RISC_NOOP);
  58         }
  59
  60         /* scan lines */
  61         for (line = 0; line < lines; line++) {
  62                 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
  63                 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr_ch2 + offset);
  64                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
  65
  66                 if ((lines <= NTSC_FIELD_HEIGHT)
  67                     || (line < (NTSC_FIELD_HEIGHT - 1))
  68                     || !(dev->_isNTSC_ch2)) {
  69                         offset += dist_betwn_starts;
  70                 }
  71         }
  72
  73         return rp;
  74 }
  75
  76 static __le32 *cx25821_risc_field_upstream_ch2(struct cx25821_dev *dev,
  77                                                __le32 *rp,
  78                                                dma_addr_t databuf_phys_addr,
  79                                                unsigned int offset,
  80                                                u32 sync_line, unsigned int bpl,
  81                                                unsigned int lines,
  82                                                int fifo_enable, int field_type)
  83 {
  84         unsigned int line, i;
  85         struct sram_channel *sram_ch =
  86            dev->channels[dev->_channel2_upstream_select].sram_channels;
  87         int dist_betwn_starts = bpl * 2;
  88
  89         /* sync instruction */
  90         if (sync_line != NO_SYNC_LINE)
  91                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
  92
  93         if (USE_RISC_NOOP_VIDEO) {
  94                 for (i = 0; i < NUM_NO_OPS; i++)
  95                         *(rp++) = cpu_to_le32(RISC_NOOP);
  96         }
  97
  98         /* scan lines */
  99         for (line = 0; line < lines; line++) {
 100                 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
 101                 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
 102                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
 103
 104                 if ((lines <= NTSC_FIELD_HEIGHT)
 105                     || (line < (NTSC_FIELD_HEIGHT - 1))
 106                     || !(dev->_isNTSC_ch2)) {
 107                         offset += dist_betwn_starts;
 108                 }
 109
 110                /*
 111                  check if we need to enable the FIFO after the first 4 lines
 112                   For the upstream video channel, the risc engine will enable
 113                   the FIFO.
 114                */
 115                 if (fifo_enable && line == 3) {
 116                         *(rp++) = RISC_WRITECR;
 117                         *(rp++) = sram_ch->dma_ctl;
 118                         *(rp++) = FLD_VID_FIFO_EN;
 119                         *(rp++) = 0x00000001;
 120                 }
 121         }
 122
 123         return rp;
 124 }
 125
 126 int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev,
 127                                      struct pci_dev *pci,
 128                                      unsigned int top_offset, unsigned int bpl,
 129                                      unsigned int lines)
 130 {
 131         __le32 *rp;
 132         int fifo_enable = 0;
 133         int singlefield_lines = lines >> 1; /*get line count for single field */
 134         int odd_num_lines = singlefield_lines;
 135         int frame = 0;
 136         int frame_size = 0;
 137         int databuf_offset = 0;
 138         int risc_program_size = 0;
 139         int risc_flag = RISC_CNT_RESET;
 140         unsigned int bottom_offset = bpl;
 141         dma_addr_t risc_phys_jump_addr;
 142
 143         if (dev->_isNTSC_ch2) {
 144                 odd_num_lines = singlefield_lines + 1;
 145                 risc_program_size = FRAME1_VID_PROG_SIZE;
 146                 frame_size =
 147                     (bpl ==
 148                      Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
 149                     FRAME_SIZE_NTSC_Y422;
 150         } else {
 151                 risc_program_size = PAL_VID_PROG_SIZE;
 152                 frame_size =
 153                     (bpl ==
 154                      Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
 155         }
 156
 157         /* Virtual address of Risc buffer program */
 158         rp = dev->_dma_virt_addr_ch2;
 159
 160         for (frame = 0; frame < NUM_FRAMES; frame++) {
 161                 databuf_offset = frame_size * frame;
 162
 163                 if (UNSET != top_offset) {
 164                         fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
 165                         rp = cx25821_risc_field_upstream_ch2(dev, rp,
 166                                                              dev->
 167                                                              _data_buf_phys_addr_ch2
 168                                                              + databuf_offset,
 169                                                              top_offset, 0, bpl,
 170                                                              odd_num_lines,
 171                                                              fifo_enable,
 172                                                              ODD_FIELD);
 173                 }
 174
 175                 fifo_enable = FIFO_DISABLE;
 176
 177                /* Even field */
 178                 rp = cx25821_risc_field_upstream_ch2(dev, rp,
 179                                                      dev->
 180                                                      _data_buf_phys_addr_ch2 +
 181                                                      databuf_offset,
 182                                                      bottom_offset, 0x200, bpl,
 183                                                      singlefield_lines,
 184                                                      fifo_enable, EVEN_FIELD);
 185
 186                 if (frame == 0) {
 187                         risc_flag = RISC_CNT_RESET;
 188                         risc_phys_jump_addr =
 189                             dev->_dma_phys_start_addr_ch2 + risc_program_size;
 190                 } else {
 191                         risc_flag = RISC_CNT_INC;
 192                         risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2;
 193                 }
 194
 195                /*
 196                   Loop to 2ndFrameRISC or to Start of
 197                   Risc program & generate IRQ
 198                */
 199                 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
 200                 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
 201                 *(rp++) = cpu_to_le32(0);
 202         }
 203
 204         return 0;
 205 }
 206
 207 void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev)
 208 {
 209         struct sram_channel *sram_ch =
 210            dev->channels[VID_UPSTREAM_SRAM_CHANNEL_J].sram_channels;
 211         u32 tmp = 0;
 212
 213         if (!dev->_is_running_ch2) {
 214                 printk
 215                     ("cx25821: No video file is currently running so return!\n");
 216                 return;
 217         }
 218         /* Disable RISC interrupts */
 219         tmp = cx_read(sram_ch->int_msk);
 220         cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
 221
 222         /* Turn OFF risc and fifo */
 223         tmp = cx_read(sram_ch->dma_ctl);
 224         cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
 225
 226         /* Clear data buffer memory */
 227         if (dev->_data_buf_virt_addr_ch2)
 228                 memset(dev->_data_buf_virt_addr_ch2, 0,
 229                        dev->_data_buf_size_ch2);
 230
 231         dev->_is_running_ch2 = 0;
 232         dev->_is_first_frame_ch2 = 0;
 233         dev->_frame_count_ch2 = 0;
 234         dev->_file_status_ch2 = END_OF_FILE;
 235
 236         if (dev->_irq_queues_ch2) {
 237                 kfree(dev->_irq_queues_ch2);
 238                 dev->_irq_queues_ch2 = NULL;
 239         }
 240
 241         if (dev->_filename_ch2 != NULL)
 242                 kfree(dev->_filename_ch2);
 243
 244         tmp = cx_read(VID_CH_MODE_SEL);
 245         cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
 246 }
 247
 248 void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev)
 249 {
 250         if (dev->_is_running_ch2)
 251                 cx25821_stop_upstream_video_ch2(dev);
 252
 253         if (dev->_dma_virt_addr_ch2) {
 254                 pci_free_consistent(dev->pci, dev->_risc_size_ch2,
 255                                     dev->_dma_virt_addr_ch2,
 256                                     dev->_dma_phys_addr_ch2);
 257                 dev->_dma_virt_addr_ch2 = NULL;
 258         }
 259
 260         if (dev->_data_buf_virt_addr_ch2) {
 261                 pci_free_consistent(dev->pci, dev->_data_buf_size_ch2,
 262                                     dev->_data_buf_virt_addr_ch2,
 263                                     dev->_data_buf_phys_addr_ch2);
 264                 dev->_data_buf_virt_addr_ch2 = NULL;
 265         }
 266 }
 267
 268 int cx25821_get_frame_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
 269 {
 270         struct file *myfile;
 271         int frame_index_temp = dev->_frame_index_ch2;
 272         int i = 0;
 273         int line_size =
 274             (dev->_pixel_format_ch2 ==
 275              PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
 276         int frame_size = 0;
 277         int frame_offset = 0;
 278         ssize_t vfs_read_retval = 0;
 279         char mybuf[line_size];
 280         loff_t file_offset;
 281         loff_t pos;
 282         mm_segment_t old_fs;
 283
 284         if (dev->_file_status_ch2 == END_OF_FILE)
 285                 return 0;
 286
 287         if (dev->_isNTSC_ch2) {
 288                 frame_size =
 289                     (line_size ==
 290                      Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
 291                     FRAME_SIZE_NTSC_Y422;
 292         } else {
 293                 frame_size =
 294                     (line_size ==
 295                      Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
 296         }
 297
 298         frame_offset = (frame_index_temp > 0) ? frame_size : 0;
 299         file_offset = dev->_frame_count_ch2 * frame_size;
 300
 301         myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
 302         if (IS_ERR(myfile)) {
 303                 const int open_errno = -PTR_ERR(myfile);
 304                 printk("%s(): ERROR opening file(%s) with errno = %d!\n",
 305                         __func__, dev->_filename_ch2, open_errno);
 306                 return PTR_ERR(myfile);
 307         } else {
 308                 if (!(myfile->f_op)) {
 309                         printk("%s: File has no file operations registered!",
 310                                __func__);
 311                         filp_close(myfile, NULL);
 312                         return -EIO;
 313                 }
 314
 315                 if (!myfile->f_op->read) {
 316                         printk("%s: File has no READ operations registered!",
 317                                __func__);
 318                         filp_close(myfile, NULL);
 319                         return -EIO;
 320                 }
 321
 322                 pos = myfile->f_pos;
 323                 old_fs = get_fs();
 324                 set_fs(KERNEL_DS);
 325
 326                 for (i = 0; i < dev->_lines_count_ch2; i++) {
 327                         pos = file_offset;
 328
 329                         vfs_read_retval =
 330                             vfs_read(myfile, mybuf, line_size, &pos);
 331
 332                         if (vfs_read_retval > 0 && vfs_read_retval == line_size
 333                             && dev->_data_buf_virt_addr_ch2 != NULL) {
 334                                 memcpy((void *)(dev->_data_buf_virt_addr_ch2 +
 335                                                 frame_offset / 4), mybuf,
 336                                        vfs_read_retval);
 337                         }
 338
 339                         file_offset += vfs_read_retval;
 340                         frame_offset += vfs_read_retval;
 341
 342                         if (vfs_read_retval < line_size) {
 343                                 printk(KERN_INFO
 344                                        "Done: exit %s() since no more bytes to read from Video file.\n",
 345                                        __func__);
 346                                 break;
 347                         }
 348                 }
 349
 350                 if (i > 0)
 351                         dev->_frame_count_ch2++;
 352
 353                 dev->_file_status_ch2 =
 354                     (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
 355
 356                 set_fs(old_fs);
 357                 filp_close(myfile, NULL);
 358         }
 359
 360         return 0;
 361 }
 362
 363 static void cx25821_vidups_handler_ch2(struct work_struct *work)
 364 {
 365         struct cx25821_dev *dev =
 366             container_of(work, struct cx25821_dev, _irq_work_entry_ch2);
 367
 368         if (!dev) {
 369                 printk("ERROR %s(): since container_of(work_struct) FAILED!\n",
 370                         __func__);
 371                 return;
 372         }
 373
 374         cx25821_get_frame_ch2(dev,
 375                              dev->channels[dev->
 376                                _channel2_upstream_select].sram_channels);
 377 }
 378
 379 int cx25821_openfile_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
 380 {
 381         struct file *myfile;
 382         int i = 0, j = 0;
 383         int line_size =
 384             (dev->_pixel_format_ch2 ==
 385              PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
 386         ssize_t vfs_read_retval = 0;
 387         char mybuf[line_size];
 388         loff_t pos;
 389         loff_t offset = (unsigned long)0;
 390         mm_segment_t old_fs;
 391
 392         myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
 393
 394         if (IS_ERR(myfile)) {
 395                 const int open_errno = -PTR_ERR(myfile);
 396                 printk("%s(): ERROR opening file(%s) with errno = %d!\n",
 397                         __func__, dev->_filename_ch2, open_errno);
 398                 return PTR_ERR(myfile);
 399         } else {
 400                 if (!(myfile->f_op)) {
 401                         printk("%s: File has no file operations registered!",
 402                                __func__);
 403                         filp_close(myfile, NULL);
 404                         return -EIO;
 405                 }
 406
 407                 if (!myfile->f_op->read) {
 408                         printk
 409                             ("%s: File has no READ operations registered!  Returning.",
 410                              __func__);
 411                         filp_close(myfile, NULL);
 412                         return -EIO;
 413                 }
 414
 415                 pos = myfile->f_pos;
 416                 old_fs = get_fs();
 417                 set_fs(KERNEL_DS);
 418
 419                 for (j = 0; j < NUM_FRAMES; j++) {
 420                         for (i = 0; i < dev->_lines_count_ch2; i++) {
 421                                 pos = offset;
 422
 423                                 vfs_read_retval =
 424                                     vfs_read(myfile, mybuf, line_size, &pos);
 425
 426                                 if (vfs_read_retval > 0
 427                                     && vfs_read_retval == line_size
 428                                     && dev->_data_buf_virt_addr_ch2 != NULL) {
 429                                         memcpy((void *)(dev->
 430                                                         _data_buf_virt_addr_ch2
 431                                                         + offset / 4), mybuf,
 432                                                vfs_read_retval);
 433                                 }
 434
 435                                 offset += vfs_read_retval;
 436
 437                                 if (vfs_read_retval < line_size) {
 438                                         printk(KERN_INFO
 439                                                "Done: exit %s() since no more bytes to read from Video file.\n",
 440                                                __func__);
 441                                         break;
 442                                 }
 443                         }
 444
 445                         if (i > 0)
 446                                 dev->_frame_count_ch2++;
 447
 448                         if (vfs_read_retval < line_size)
 449                                 break;
 450                 }
 451
 452                 dev->_file_status_ch2 =
 453                     (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
 454
 455                 set_fs(old_fs);
 456                 myfile->f_pos = 0;
 457                 filp_close(myfile, NULL);
 458         }
 459
 460         return 0;
 461 }
 462
 463 static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev,
 464                                                struct sram_channel *sram_ch,
 465                                                int bpl)
 466 {
 467         int ret = 0;
 468         dma_addr_t dma_addr;
 469         dma_addr_t data_dma_addr;
 470
 471         if (dev->_dma_virt_addr_ch2 != NULL) {
 472                 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
 473                                     dev->_dma_virt_addr_ch2,
 474                                     dev->_dma_phys_addr_ch2);
 475         }
 476
 477         dev->_dma_virt_addr_ch2 =
 478             pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
 479                                  &dma_addr);
 480         dev->_dma_virt_start_addr_ch2 = dev->_dma_virt_addr_ch2;
 481         dev->_dma_phys_start_addr_ch2 = dma_addr;
 482         dev->_dma_phys_addr_ch2 = dma_addr;
 483         dev->_risc_size_ch2 = dev->upstream_riscbuf_size_ch2;
 484
 485         if (!dev->_dma_virt_addr_ch2) {
 486                 printk
 487                     ("cx25821: FAILED to allocate memory for Risc buffer! Returning.\n");
 488                 return -ENOMEM;
 489         }
 490
 491         /* Iniitize at this address until n bytes to 0 */
 492         memset(dev->_dma_virt_addr_ch2, 0, dev->_risc_size_ch2);
 493
 494         if (dev->_data_buf_virt_addr_ch2 != NULL) {
 495                 pci_free_consistent(dev->pci, dev->upstream_databuf_size_ch2,
 496                                     dev->_data_buf_virt_addr_ch2,
 497                                     dev->_data_buf_phys_addr_ch2);
 498         }
 499         /* For Video Data buffer allocation */
 500         dev->_data_buf_virt_addr_ch2 =
 501             pci_alloc_consistent(dev->pci, dev->upstream_databuf_size_ch2,
 502                                  &data_dma_addr);
 503         dev->_data_buf_phys_addr_ch2 = data_dma_addr;
 504         dev->_data_buf_size_ch2 = dev->upstream_databuf_size_ch2;
 505
 506         if (!dev->_data_buf_virt_addr_ch2) {
 507                 printk
 508                     ("cx25821: FAILED to allocate memory for data buffer! Returning.\n");
 509                 return -ENOMEM;
 510         }
 511
 512         /* Initialize at this address until n bytes to 0 */
 513         memset(dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2);
 514
 515         ret = cx25821_openfile_ch2(dev, sram_ch);
 516         if (ret < 0)
 517                 return ret;
 518
 519         /* Creating RISC programs */
 520         ret =
 521             cx25821_risc_buffer_upstream_ch2(dev, dev->pci, 0, bpl,
 522                                              dev->_lines_count_ch2);
 523         if (ret < 0) {
 524                 printk(KERN_INFO
 525                         "cx25821: Failed creating Video Upstream Risc programs!\n");
 526                 goto error;
 527         }
 528
 529         return 0;
 530
 531         error:
 532         return ret;
 533 }
 534
 535 int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev, int chan_num,
 536                                    u32 status)
 537 {
 538         u32 int_msk_tmp;
 539         struct sram_channel *channel = dev->channels[chan_num].sram_channels;
 540         int singlefield_lines = NTSC_FIELD_HEIGHT;
 541         int line_size_in_bytes = Y422_LINE_SZ;
 542         int odd_risc_prog_size = 0;
 543         dma_addr_t risc_phys_jump_addr;
 544         __le32 *rp;
 545
 546         if (status & FLD_VID_SRC_RISC1) {
 547                 /* We should only process one program per call */
 548                 u32 prog_cnt = cx_read(channel->gpcnt);
 549
 550                 /*
 551                  *  Since we've identified our IRQ, clear our bits from the
 552                  *  interrupt mask and interrupt status registers
 553                  */
 554                 int_msk_tmp = cx_read(channel->int_msk);
 555                 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
 556                 cx_write(channel->int_stat, _intr_msk);
 557
 558                 spin_lock(&dev->slock);
 559
 560                 dev->_frame_index_ch2 = prog_cnt;
 561
 562                 queue_work(dev->_irq_queues_ch2, &dev->_irq_work_entry_ch2);
 563
 564                 if (dev->_is_first_frame_ch2) {
 565                         dev->_is_first_frame_ch2 = 0;
 566
 567                         if (dev->_isNTSC_ch2) {
 568                                 singlefield_lines += 1;
 569                                 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
 570                         } else {
 571                                 singlefield_lines = PAL_FIELD_HEIGHT;
 572                                 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
 573                         }
 574
 575                         if (dev->_dma_virt_start_addr_ch2 != NULL) {
 576                                 line_size_in_bytes =
 577                                     (dev->_pixel_format_ch2 ==
 578                                      PIXEL_FRMT_411) ? Y411_LINE_SZ :
 579                                     Y422_LINE_SZ;
 580                                 risc_phys_jump_addr =
 581                                     dev->_dma_phys_start_addr_ch2 +
 582                                     odd_risc_prog_size;
 583
 584                                 rp = cx25821_update_riscprogram_ch2(dev,
 585                                                                     dev->
 586                                                                     _dma_virt_start_addr_ch2,
 587                                                                     TOP_OFFSET,
 588                                                                     line_size_in_bytes,
 589                                                                     0x0,
 590                                                                     singlefield_lines,
 591                                                                     FIFO_DISABLE,
 592                                                                     ODD_FIELD);
 593
 594                                /* Jump to Even Risc program of 1st Frame */
 595                                 *(rp++) = cpu_to_le32(RISC_JUMP);
 596                                 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
 597                                 *(rp++) = cpu_to_le32(0);
 598                         }
 599                 }
 600
 601                 spin_unlock(&dev->slock);
 602         }
 603
 604         if (dev->_file_status_ch2 == END_OF_FILE) {
 605                 printk("cx25821: EOF Channel 2 Framecount = %d\n",
 606                        dev->_frame_count_ch2);
 607                 return -1;
 608         }
 609         /* ElSE, set the interrupt mask register, re-enable irq. */
 610         int_msk_tmp = cx_read(channel->int_msk);
 611         cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
 612
 613         return 0;
 614 }
 615
 616 static irqreturn_t cx25821_upstream_irq_ch2(int irq, void *dev_id)
 617 {
 618         struct cx25821_dev *dev = dev_id;
 619         u32 msk_stat, vid_status;
 620         int handled = 0;
 621         int channel_num = 0;
 622         struct sram_channel *sram_ch;
 623
 624         if (!dev)
 625                 return -1;
 626
 627         channel_num = VID_UPSTREAM_SRAM_CHANNEL_J;
 628         sram_ch = dev->channels[channel_num].sram_channels;
 629
 630         msk_stat = cx_read(sram_ch->int_mstat);
 631         vid_status = cx_read(sram_ch->int_stat);
 632
 633         /* Only deal with our interrupt */
 634         if (vid_status) {
 635                 handled =
 636                     cx25821_video_upstream_irq_ch2(dev, channel_num,
 637                                                    vid_status);
 638         }
 639
 640         if (handled < 0)
 641                 cx25821_stop_upstream_video_ch2(dev);
 642         else
 643                 handled += handled;
 644
 645         return IRQ_RETVAL(handled);
 646 }
 647
 648 static void cx25821_set_pixelengine_ch2(struct cx25821_dev *dev,
 649                                         struct sram_channel *ch, int pix_format)
 650 {
 651         int width = WIDTH_D1;
 652         int height = dev->_lines_count_ch2;
 653         int num_lines, odd_num_lines;
 654         u32 value;
 655         int vip_mode = PIXEL_ENGINE_VIP1;
 656
 657         value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
 658         value &= 0xFFFFFFEF;
 659         value |= dev->_isNTSC_ch2 ? 0 : 0x10;
 660         cx_write(ch->vid_fmt_ctl, value);
 661
 662         /*
 663          *  set number of active pixels in each line. Default is 720
 664          * pixels in both NTSC and PAL format
 665          */
 666         cx_write(ch->vid_active_ctl1, width);
 667
 668         num_lines = (height / 2) & 0x3FF;
 669         odd_num_lines = num_lines;
 670
 671         if (dev->_isNTSC_ch2)
 672                 odd_num_lines += 1;
 673
 674         value = (num_lines << 16) | odd_num_lines;
 675
 676         /* set number of active lines in field 0 (top) and field 1 (bottom) */
 677         cx_write(ch->vid_active_ctl2, value);
 678
 679         cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
 680 }
 681
 682 int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev,
 683                                          struct sram_channel *sram_ch)
 684 {
 685         u32 tmp = 0;
 686         int err = 0;
 687
 688         /*
 689          *  656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface
 690          * for channel A-C
 691          */
 692         tmp = cx_read(VID_CH_MODE_SEL);
 693         cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
 694
 695         /*
 696          *  Set the physical start address of the RISC program in the initial
 697          *  program counter(IPC) member of the cmds.
 698          */
 699         cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2);
 700         cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
 701
 702         /* reset counter */
 703         cx_write(sram_ch->gpcnt_ctl, 3);
 704
 705         /* Clear our bits from the interrupt status register. */
 706         cx_write(sram_ch->int_stat, _intr_msk);
 707
 708         /* Set the interrupt mask register, enable irq. */
 709         cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
 710         tmp = cx_read(sram_ch->int_msk);
 711         cx_write(sram_ch->int_msk, tmp |= _intr_msk);
 712
 713         err =
 714             request_irq(dev->pci->irq, cx25821_upstream_irq_ch2,
 715                         IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
 716         if (err < 0) {
 717                 printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name,
 718                        dev->pci->irq);
 719                 goto fail_irq;
 720         }
 721         /* Start the DMA  engine */
 722         tmp = cx_read(sram_ch->dma_ctl);
 723         cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
 724
 725         dev->_is_running_ch2 = 1;
 726         dev->_is_first_frame_ch2 = 1;
 727
 728         return 0;
 729
 730         fail_irq:
 731         cx25821_dev_unregister(dev);
 732         return err;
 733 }
 734
 735 int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select,
 736                                  int pixel_format)
 737 {
 738         struct sram_channel *sram_ch;
 739         u32 tmp;
 740         int retval = 0;
 741         int err = 0;
 742         int data_frame_size = 0;
 743         int risc_buffer_size = 0;
 744         int str_length = 0;
 745
 746         if (dev->_is_running_ch2) {
 747                 printk("Video Channel is still running so return!\n");
 748                 return 0;
 749         }
 750
 751         dev->_channel2_upstream_select = channel_select;
 752         sram_ch = dev->channels[channel_select].sram_channels;
 753
 754         INIT_WORK(&dev->_irq_work_entry_ch2, cx25821_vidups_handler_ch2);
 755         dev->_irq_queues_ch2 =
 756             create_singlethread_workqueue("cx25821_workqueue2");
 757
 758         if (!dev->_irq_queues_ch2) {
 759                 printk
 760                     ("cx25821: create_singlethread_workqueue() for Video FAILED!\n");
 761                 return -ENOMEM;
 762         }
 763         /*
 764          * 656/VIP SRC Upstream Channel I & J and 7 -
 765          * Host Bus Interface for channel A-C
 766          */
 767         tmp = cx_read(VID_CH_MODE_SEL);
 768         cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
 769
 770         dev->_is_running_ch2 = 0;
 771         dev->_frame_count_ch2 = 0;
 772         dev->_file_status_ch2 = RESET_STATUS;
 773         dev->_lines_count_ch2 = dev->_isNTSC_ch2 ? 480 : 576;
 774         dev->_pixel_format_ch2 = pixel_format;
 775         dev->_line_size_ch2 =
 776             (dev->_pixel_format_ch2 ==
 777              PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
 778         data_frame_size = dev->_isNTSC_ch2 ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
 779         risc_buffer_size =
 780             dev->_isNTSC_ch2 ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
 781
 782         if (dev->input_filename_ch2) {
 783                 str_length = strlen(dev->input_filename_ch2);
 784                 dev->_filename_ch2 = kmalloc(str_length + 1, GFP_KERNEL);
 785
 786                 if (!dev->_filename_ch2)
 787                         goto error;
 788
 789                 memcpy(dev->_filename_ch2, dev->input_filename_ch2,
 790                        str_length + 1);
 791         } else {
 792                 str_length = strlen(dev->_defaultname_ch2);
 793                 dev->_filename_ch2 = kmalloc(str_length + 1, GFP_KERNEL);
 794
 795                 if (!dev->_filename_ch2)
 796                         goto error;
 797
 798                 memcpy(dev->_filename_ch2, dev->_defaultname_ch2,
 799                        str_length + 1);
 800         }
 801
 802         /* Default if filename is empty string */
 803         if (strcmp(dev->input_filename_ch2, "") == 0) {
 804                 if (dev->_isNTSC_ch2) {
 805                         dev->_filename_ch2 =
 806                             (dev->_pixel_format_ch2 ==
 807                              PIXEL_FRMT_411) ? "/root/vid411.yuv" :
 808                             "/root/vidtest.yuv";
 809                 } else {
 810                         dev->_filename_ch2 =
 811                             (dev->_pixel_format_ch2 ==
 812                              PIXEL_FRMT_411) ? "/root/pal411.yuv" :
 813                             "/root/pal422.yuv";
 814                 }
 815         }
 816
 817         retval =
 818             cx25821_sram_channel_setup_upstream(dev, sram_ch,
 819                                                 dev->_line_size_ch2, 0);
 820
 821         /* setup fifo + format */
 822         cx25821_set_pixelengine_ch2(dev, sram_ch, dev->_pixel_format_ch2);
 823
 824         dev->upstream_riscbuf_size_ch2 = risc_buffer_size * 2;
 825         dev->upstream_databuf_size_ch2 = data_frame_size * 2;
 826
 827         /* Allocating buffers and prepare RISC program */
 828         retval =
 829             cx25821_upstream_buffer_prepare_ch2(dev, sram_ch,
 830                                                 dev->_line_size_ch2);
 831         if (retval < 0) {
 832                 printk(KERN_ERR
 833                        "%s: Failed to set up Video upstream buffers!\n",
 834                        dev->name);
 835                 goto error;
 836         }
 837
 838         cx25821_start_video_dma_upstream_ch2(dev, sram_ch);
 839
 840         return 0;
 841
 842         error:
 843         cx25821_dev_unregister(dev);
 844
 845         return err;
 846 }