2 * Driver for the Conexant CX25821 PCIe bridge
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 #include <linux/i2c.h>
27 #include <linux/slab.h>
29 #include "cx25821-sram.h"
30 #include "cx25821-video.h"
32 MODULE_DESCRIPTION("Driver for Athena cards");
33 MODULE_AUTHOR("Shu Lin - Hiep Huynh");
34 MODULE_LICENSE("GPL");
36 struct list_head cx25821_devlist;
37 EXPORT_SYMBOL(cx25821_devlist);
39 static unsigned int debug;
40 module_param(debug, int, 0644);
41 MODULE_PARM_DESC(debug, "enable debug messages");
43 static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
44 module_param_array(card, int, NULL, 0444);
45 MODULE_PARM_DESC(card, "card type");
47 static unsigned int cx25821_devcount;
49 static DEFINE_MUTEX(devlist);
50 LIST_HEAD(cx25821_devlist);
52 struct sram_channel cx25821_sram_channels[] = {
56 .cmds_start = VID_A_DOWN_CMDS,
57 .ctrl_start = VID_A_IQ,
59 .fifo_start = VID_A_DOWN_CLUSTER_1,
60 .fifo_size = (VID_CLUSTER_SIZE << 2),
61 .ptr1_reg = DMA1_PTR1,
62 .ptr2_reg = DMA1_PTR2,
63 .cnt1_reg = DMA1_CNT1,
64 .cnt2_reg = DMA1_CNT2,
65 .int_msk = VID_A_INT_MSK,
66 .int_stat = VID_A_INT_STAT,
67 .int_mstat = VID_A_INT_MSTAT,
68 .dma_ctl = VID_DST_A_DMA_CTL,
69 .gpcnt_ctl = VID_DST_A_GPCNT_CTL,
70 .gpcnt = VID_DST_A_GPCNT,
71 .vip_ctl = VID_DST_A_VIP_CTL,
72 .pix_frmt = VID_DST_A_PIX_FRMT,
78 .cmds_start = VID_B_DOWN_CMDS,
79 .ctrl_start = VID_B_IQ,
81 .fifo_start = VID_B_DOWN_CLUSTER_1,
82 .fifo_size = (VID_CLUSTER_SIZE << 2),
83 .ptr1_reg = DMA2_PTR1,
84 .ptr2_reg = DMA2_PTR2,
85 .cnt1_reg = DMA2_CNT1,
86 .cnt2_reg = DMA2_CNT2,
87 .int_msk = VID_B_INT_MSK,
88 .int_stat = VID_B_INT_STAT,
89 .int_mstat = VID_B_INT_MSTAT,
90 .dma_ctl = VID_DST_B_DMA_CTL,
91 .gpcnt_ctl = VID_DST_B_GPCNT_CTL,
92 .gpcnt = VID_DST_B_GPCNT,
93 .vip_ctl = VID_DST_B_VIP_CTL,
94 .pix_frmt = VID_DST_B_PIX_FRMT,
100 .cmds_start = VID_C_DOWN_CMDS,
101 .ctrl_start = VID_C_IQ,
103 .fifo_start = VID_C_DOWN_CLUSTER_1,
104 .fifo_size = (VID_CLUSTER_SIZE << 2),
105 .ptr1_reg = DMA3_PTR1,
106 .ptr2_reg = DMA3_PTR2,
107 .cnt1_reg = DMA3_CNT1,
108 .cnt2_reg = DMA3_CNT2,
109 .int_msk = VID_C_INT_MSK,
110 .int_stat = VID_C_INT_STAT,
111 .int_mstat = VID_C_INT_MSTAT,
112 .dma_ctl = VID_DST_C_DMA_CTL,
113 .gpcnt_ctl = VID_DST_C_GPCNT_CTL,
114 .gpcnt = VID_DST_C_GPCNT,
115 .vip_ctl = VID_DST_C_VIP_CTL,
116 .pix_frmt = VID_DST_C_PIX_FRMT,
122 .cmds_start = VID_D_DOWN_CMDS,
123 .ctrl_start = VID_D_IQ,
125 .fifo_start = VID_D_DOWN_CLUSTER_1,
126 .fifo_size = (VID_CLUSTER_SIZE << 2),
127 .ptr1_reg = DMA4_PTR1,
128 .ptr2_reg = DMA4_PTR2,
129 .cnt1_reg = DMA4_CNT1,
130 .cnt2_reg = DMA4_CNT2,
131 .int_msk = VID_D_INT_MSK,
132 .int_stat = VID_D_INT_STAT,
133 .int_mstat = VID_D_INT_MSTAT,
134 .dma_ctl = VID_DST_D_DMA_CTL,
135 .gpcnt_ctl = VID_DST_D_GPCNT_CTL,
136 .gpcnt = VID_DST_D_GPCNT,
137 .vip_ctl = VID_DST_D_VIP_CTL,
138 .pix_frmt = VID_DST_D_PIX_FRMT,
144 .cmds_start = VID_E_DOWN_CMDS,
145 .ctrl_start = VID_E_IQ,
147 .fifo_start = VID_E_DOWN_CLUSTER_1,
148 .fifo_size = (VID_CLUSTER_SIZE << 2),
149 .ptr1_reg = DMA5_PTR1,
150 .ptr2_reg = DMA5_PTR2,
151 .cnt1_reg = DMA5_CNT1,
152 .cnt2_reg = DMA5_CNT2,
153 .int_msk = VID_E_INT_MSK,
154 .int_stat = VID_E_INT_STAT,
155 .int_mstat = VID_E_INT_MSTAT,
156 .dma_ctl = VID_DST_E_DMA_CTL,
157 .gpcnt_ctl = VID_DST_E_GPCNT_CTL,
158 .gpcnt = VID_DST_E_GPCNT,
159 .vip_ctl = VID_DST_E_VIP_CTL,
160 .pix_frmt = VID_DST_E_PIX_FRMT,
166 .cmds_start = VID_F_DOWN_CMDS,
167 .ctrl_start = VID_F_IQ,
169 .fifo_start = VID_F_DOWN_CLUSTER_1,
170 .fifo_size = (VID_CLUSTER_SIZE << 2),
171 .ptr1_reg = DMA6_PTR1,
172 .ptr2_reg = DMA6_PTR2,
173 .cnt1_reg = DMA6_CNT1,
174 .cnt2_reg = DMA6_CNT2,
175 .int_msk = VID_F_INT_MSK,
176 .int_stat = VID_F_INT_STAT,
177 .int_mstat = VID_F_INT_MSTAT,
178 .dma_ctl = VID_DST_F_DMA_CTL,
179 .gpcnt_ctl = VID_DST_F_GPCNT_CTL,
180 .gpcnt = VID_DST_F_GPCNT,
181 .vip_ctl = VID_DST_F_VIP_CTL,
182 .pix_frmt = VID_DST_F_PIX_FRMT,
188 .cmds_start = VID_G_DOWN_CMDS,
189 .ctrl_start = VID_G_IQ,
191 .fifo_start = VID_G_DOWN_CLUSTER_1,
192 .fifo_size = (VID_CLUSTER_SIZE << 2),
193 .ptr1_reg = DMA7_PTR1,
194 .ptr2_reg = DMA7_PTR2,
195 .cnt1_reg = DMA7_CNT1,
196 .cnt2_reg = DMA7_CNT2,
197 .int_msk = VID_G_INT_MSK,
198 .int_stat = VID_G_INT_STAT,
199 .int_mstat = VID_G_INT_MSTAT,
200 .dma_ctl = VID_DST_G_DMA_CTL,
201 .gpcnt_ctl = VID_DST_G_GPCNT_CTL,
202 .gpcnt = VID_DST_G_GPCNT,
203 .vip_ctl = VID_DST_G_VIP_CTL,
204 .pix_frmt = VID_DST_G_PIX_FRMT,
210 .cmds_start = VID_H_DOWN_CMDS,
211 .ctrl_start = VID_H_IQ,
213 .fifo_start = VID_H_DOWN_CLUSTER_1,
214 .fifo_size = (VID_CLUSTER_SIZE << 2),
215 .ptr1_reg = DMA8_PTR1,
216 .ptr2_reg = DMA8_PTR2,
217 .cnt1_reg = DMA8_CNT1,
218 .cnt2_reg = DMA8_CNT2,
219 .int_msk = VID_H_INT_MSK,
220 .int_stat = VID_H_INT_STAT,
221 .int_mstat = VID_H_INT_MSTAT,
222 .dma_ctl = VID_DST_H_DMA_CTL,
223 .gpcnt_ctl = VID_DST_H_GPCNT_CTL,
224 .gpcnt = VID_DST_H_GPCNT,
225 .vip_ctl = VID_DST_H_VIP_CTL,
226 .pix_frmt = VID_DST_H_PIX_FRMT,
230 .name = "audio from",
231 .cmds_start = AUD_A_DOWN_CMDS,
232 .ctrl_start = AUD_A_IQ,
234 .fifo_start = AUD_A_DOWN_CLUSTER_1,
235 .fifo_size = AUDIO_CLUSTER_SIZE * 3,
236 .ptr1_reg = DMA17_PTR1,
237 .ptr2_reg = DMA17_PTR2,
238 .cnt1_reg = DMA17_CNT1,
239 .cnt2_reg = DMA17_CNT2,
244 .name = "VID Upstream I",
245 .cmds_start = VID_I_UP_CMDS,
246 .ctrl_start = VID_I_IQ,
248 .fifo_start = VID_I_UP_CLUSTER_1,
249 .fifo_size = (VID_CLUSTER_SIZE << 2),
250 .ptr1_reg = DMA15_PTR1,
251 .ptr2_reg = DMA15_PTR2,
252 .cnt1_reg = DMA15_CNT1,
253 .cnt2_reg = DMA15_CNT2,
254 .int_msk = VID_I_INT_MSK,
255 .int_stat = VID_I_INT_STAT,
256 .int_mstat = VID_I_INT_MSTAT,
257 .dma_ctl = VID_SRC_I_DMA_CTL,
258 .gpcnt_ctl = VID_SRC_I_GPCNT_CTL,
259 .gpcnt = VID_SRC_I_GPCNT,
261 .vid_fmt_ctl = VID_SRC_I_FMT_CTL,
262 .vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1,
263 .vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2,
264 .vid_cdt_size = VID_SRC_I_CDT_SZ,
270 .name = "VID Upstream J",
271 .cmds_start = VID_J_UP_CMDS,
272 .ctrl_start = VID_J_IQ,
274 .fifo_start = VID_J_UP_CLUSTER_1,
275 .fifo_size = (VID_CLUSTER_SIZE << 2),
276 .ptr1_reg = DMA16_PTR1,
277 .ptr2_reg = DMA16_PTR2,
278 .cnt1_reg = DMA16_CNT1,
279 .cnt2_reg = DMA16_CNT2,
280 .int_msk = VID_J_INT_MSK,
281 .int_stat = VID_J_INT_STAT,
282 .int_mstat = VID_J_INT_MSTAT,
283 .dma_ctl = VID_SRC_J_DMA_CTL,
284 .gpcnt_ctl = VID_SRC_J_GPCNT_CTL,
285 .gpcnt = VID_SRC_J_GPCNT,
287 .vid_fmt_ctl = VID_SRC_J_FMT_CTL,
288 .vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1,
289 .vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2,
290 .vid_cdt_size = VID_SRC_J_CDT_SZ,
296 .name = "Audio Upstream Channel B",
297 .cmds_start = AUD_B_UP_CMDS,
298 .ctrl_start = AUD_B_IQ,
300 .fifo_start = AUD_B_UP_CLUSTER_1,
301 .fifo_size = (AUDIO_CLUSTER_SIZE * 3),
302 .ptr1_reg = DMA22_PTR1,
303 .ptr2_reg = DMA22_PTR2,
304 .cnt1_reg = DMA22_CNT1,
305 .cnt2_reg = DMA22_CNT2,
306 .int_msk = AUD_B_INT_MSK,
307 .int_stat = AUD_B_INT_STAT,
308 .int_mstat = AUD_B_INT_MSTAT,
309 .dma_ctl = AUD_INT_DMA_CTL,
310 .gpcnt_ctl = AUD_B_GPCNT_CTL,
311 .gpcnt = AUD_B_GPCNT,
312 .aud_length = AUD_B_LNGTH,
313 .aud_cfg = AUD_B_CFG,
314 .fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN,
315 .fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN,
319 EXPORT_SYMBOL(cx25821_sram_channels);
321 struct sram_channel *channel0 = &cx25821_sram_channels[SRAM_CH00];
322 struct sram_channel *channel1 = &cx25821_sram_channels[SRAM_CH01];
323 struct sram_channel *channel2 = &cx25821_sram_channels[SRAM_CH02];
324 struct sram_channel *channel3 = &cx25821_sram_channels[SRAM_CH03];
325 struct sram_channel *channel4 = &cx25821_sram_channels[SRAM_CH04];
326 struct sram_channel *channel5 = &cx25821_sram_channels[SRAM_CH05];
327 struct sram_channel *channel6 = &cx25821_sram_channels[SRAM_CH06];
328 struct sram_channel *channel7 = &cx25821_sram_channels[SRAM_CH07];
329 struct sram_channel *channel9 = &cx25821_sram_channels[SRAM_CH09];
330 struct sram_channel *channel10 = &cx25821_sram_channels[SRAM_CH10];
331 struct sram_channel *channel11 = &cx25821_sram_channels[SRAM_CH11];
333 struct cx25821_dmaqueue mpegq;
335 static int cx25821_risc_decode(u32 risc)
337 static const char * const instr[16] = {
338 [RISC_SYNC >> 28] = "sync",
339 [RISC_WRITE >> 28] = "write",
340 [RISC_WRITEC >> 28] = "writec",
341 [RISC_READ >> 28] = "read",
342 [RISC_READC >> 28] = "readc",
343 [RISC_JUMP >> 28] = "jump",
344 [RISC_SKIP >> 28] = "skip",
345 [RISC_WRITERM >> 28] = "writerm",
346 [RISC_WRITECM >> 28] = "writecm",
347 [RISC_WRITECR >> 28] = "writecr",
349 static const int incr[16] = {
350 [RISC_WRITE >> 28] = 3,
351 [RISC_JUMP >> 28] = 3,
352 [RISC_SKIP >> 28] = 1,
353 [RISC_SYNC >> 28] = 1,
354 [RISC_WRITERM >> 28] = 3,
355 [RISC_WRITECM >> 28] = 3,
356 [RISC_WRITECR >> 28] = 4,
358 static const char * const bits[] = {
359 "12", "13", "14", "resync",
360 "cnt0", "cnt1", "18", "19",
361 "20", "21", "22", "23",
362 "irq1", "irq2", "eol", "sol",
366 pr_cont("0x%08x [ %s",
367 risc, instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
368 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) {
369 if (risc & (1 << (i + 12)))
370 pr_cont(" %s", bits[i]);
372 pr_cont(" count=%d ]\n", risc & 0xfff);
373 return incr[risc >> 28] ? incr[risc >> 28] : 1;
376 static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap)
378 struct cx25821_i2c *bus = i2c_adap->algo_data;
379 struct cx25821_dev *dev = bus->dev;
380 return cx_read(bus->reg_stat) & 0x01;
383 void cx_i2c_read_print(struct cx25821_dev *dev, u32 reg, const char *reg_string)
388 value = cx25821_i2c_read(&dev->i2c_bus[0], reg, &tmp);
391 static void cx25821_registers_init(struct cx25821_dev *dev)
395 /* enable RUN_RISC in Pecos */
396 cx_write(DEV_CNTRL2, 0x20);
398 /* Set the master PCI interrupt masks to enable video, audio, MBIF,
399 * and GPIO interrupts
400 * I2C interrupt masking is handled by the I2C objects themselves. */
401 cx_write(PCI_INT_MSK, 0x2001FFFF);
403 tmp = cx_read(RDR_TLCTL0);
404 tmp &= ~FLD_CFG_RCB_CK_EN; /* Clear the RCB_CK_EN bit */
405 cx_write(RDR_TLCTL0, tmp);
407 /* PLL-A setting for the Audio Master Clock */
408 cx_write(PLL_A_INT_FRAC, 0x9807A58B);
410 /* PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1 */
411 cx_write(PLL_A_POST_STAT_BIST, 0x8000019C);
413 /* clear reset bit [31] */
414 tmp = cx_read(PLL_A_INT_FRAC);
415 cx_write(PLL_A_INT_FRAC, tmp & 0x7FFFFFFF);
417 /* PLL-B setting for Mobilygen Host Bus Interface */
418 cx_write(PLL_B_INT_FRAC, 0x9883A86F);
420 /* PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0 */
421 cx_write(PLL_B_POST_STAT_BIST, 0x8000018D);
423 /* clear reset bit [31] */
424 tmp = cx_read(PLL_B_INT_FRAC);
425 cx_write(PLL_B_INT_FRAC, tmp & 0x7FFFFFFF);
427 /* PLL-C setting for video upstream channel */
428 cx_write(PLL_C_INT_FRAC, 0x96A0EA3F);
430 /* PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0 */
431 cx_write(PLL_C_POST_STAT_BIST, 0x80000103);
433 /* clear reset bit [31] */
434 tmp = cx_read(PLL_C_INT_FRAC);
435 cx_write(PLL_C_INT_FRAC, tmp & 0x7FFFFFFF);
437 /* PLL-D setting for audio upstream channel */
438 cx_write(PLL_D_INT_FRAC, 0x98757F5B);
440 /* PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0 */
441 cx_write(PLL_D_POST_STAT_BIST, 0x80000113);
443 /* clear reset bit [31] */
444 tmp = cx_read(PLL_D_INT_FRAC);
445 cx_write(PLL_D_INT_FRAC, tmp & 0x7FFFFFFF);
447 /* This selects the PLL C clock source for the video upstream channel
449 tmp = cx_read(VID_CH_CLK_SEL);
450 cx_write(VID_CH_CLK_SEL, (tmp & 0x00FFFFFF) | 0x24000000);
452 /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
454 * select 656/VIP DST for downstream Channel A - C */
455 tmp = cx_read(VID_CH_MODE_SEL);
456 /* cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); */
457 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
459 /* enables 656 port I and J as output */
460 tmp = cx_read(CLK_RST);
461 /* use external ALT_PLL_REF pin as its reference clock instead */
462 tmp |= FLD_USE_ALT_PLL_REF;
463 cx_write(CLK_RST, tmp & ~(FLD_VID_I_CLK_NOE | FLD_VID_J_CLK_NOE));
468 int cx25821_sram_channel_setup(struct cx25821_dev *dev,
469 struct sram_channel *ch,
470 unsigned int bpl, u32 risc)
472 unsigned int i, lines;
475 if (ch->cmds_start == 0) {
476 cx_write(ch->ptr1_reg, 0);
477 cx_write(ch->ptr2_reg, 0);
478 cx_write(ch->cnt2_reg, 0);
479 cx_write(ch->cnt1_reg, 0);
483 bpl = (bpl + 7) & ~7; /* alignment */
485 lines = ch->fifo_size / bpl;
492 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
497 for (i = 0; i < lines; i++) {
498 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
499 cx_write(cdt + 16 * i + 4, 0);
500 cx_write(cdt + 16 * i + 8, 0);
501 cx_write(cdt + 16 * i + 12, 0);
504 /* init the first cdt buffer */
505 for (i = 0; i < 128; i++)
506 cx_write(ch->fifo_start + 4 * i, i);
510 cx_write(ch->cmds_start + 0, 8);
512 cx_write(ch->cmds_start + 0, risc);
514 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
515 cx_write(ch->cmds_start + 8, cdt);
516 cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
517 cx_write(ch->cmds_start + 16, ch->ctrl_start);
520 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
522 cx_write(ch->cmds_start + 20, 64 >> 2);
524 for (i = 24; i < 80; i += 4)
525 cx_write(ch->cmds_start + i, 0);
528 cx_write(ch->ptr1_reg, ch->fifo_start);
529 cx_write(ch->ptr2_reg, cdt);
530 cx_write(ch->cnt2_reg, (lines * 16) >> 3);
531 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
535 EXPORT_SYMBOL(cx25821_sram_channel_setup);
537 int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
538 struct sram_channel *ch,
539 unsigned int bpl, u32 risc)
541 unsigned int i, lines;
544 if (ch->cmds_start == 0) {
545 cx_write(ch->ptr1_reg, 0);
546 cx_write(ch->ptr2_reg, 0);
547 cx_write(ch->cnt2_reg, 0);
548 cx_write(ch->cnt1_reg, 0);
552 bpl = (bpl + 7) & ~7; /* alignment */
554 lines = ch->fifo_size / bpl;
557 lines = 3; /* for AUDIO */
561 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
566 for (i = 0; i < lines; i++) {
567 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
568 cx_write(cdt + 16 * i + 4, 0);
569 cx_write(cdt + 16 * i + 8, 0);
570 cx_write(cdt + 16 * i + 12, 0);
575 cx_write(ch->cmds_start + 0, 8);
577 cx_write(ch->cmds_start + 0, risc);
579 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
580 cx_write(ch->cmds_start + 8, cdt);
581 cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
582 cx_write(ch->cmds_start + 16, ch->ctrl_start);
586 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
588 cx_write(ch->cmds_start + 20, 64 >> 2);
591 for (i = 24; i < 80; i += 4)
592 cx_write(ch->cmds_start + i, 0);
595 cx_write(ch->ptr1_reg, ch->fifo_start);
596 cx_write(ch->ptr2_reg, cdt);
597 cx_write(ch->cnt2_reg, (lines * 16) >> 3);
598 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
602 EXPORT_SYMBOL(cx25821_sram_channel_setup_audio);
604 void cx25821_sram_channel_dump(struct cx25821_dev *dev, struct sram_channel *ch)
606 static char *name[] = {
623 unsigned int i, j, n;
625 pr_warn("%s: %s - dma channel status dump\n", dev->name, ch->name);
626 for (i = 0; i < ARRAY_SIZE(name); i++)
627 pr_warn("cmds + 0x%2x: %-15s: 0x%08x\n",
628 i * 4, name[i], cx_read(ch->cmds_start + 4 * i));
631 for (i = 0; i < 4;) {
632 risc = cx_read(ch->cmds_start + 4 * (i + 14));
633 pr_warn("cmds + 0x%2x: risc%d: ", j + i * 4, i);
634 i += cx25821_risc_decode(risc);
637 for (i = 0; i < (64 >> 2); i += n) {
638 risc = cx_read(ch->ctrl_start + 4 * i);
639 /* No consideration for bits 63-32 */
641 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
642 i * 4, ch->ctrl_start + 4 * i, i);
643 n = cx25821_risc_decode(risc);
644 for (j = 1; j < n; j++) {
645 risc = cx_read(ch->ctrl_start + 4 * (i + j));
646 pr_warn("ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n",
647 4 * (i + j), i + j, risc, j);
651 pr_warn(" : fifo: 0x%08x -> 0x%x\n",
652 ch->fifo_start, ch->fifo_start + ch->fifo_size);
653 pr_warn(" : ctrl: 0x%08x -> 0x%x\n",
654 ch->ctrl_start, ch->ctrl_start + 6 * 16);
655 pr_warn(" : ptr1_reg: 0x%08x\n",
656 cx_read(ch->ptr1_reg));
657 pr_warn(" : ptr2_reg: 0x%08x\n",
658 cx_read(ch->ptr2_reg));
659 pr_warn(" : cnt1_reg: 0x%08x\n",
660 cx_read(ch->cnt1_reg));
661 pr_warn(" : cnt2_reg: 0x%08x\n",
662 cx_read(ch->cnt2_reg));
664 EXPORT_SYMBOL(cx25821_sram_channel_dump);
666 void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
667 struct sram_channel *ch)
669 static const char * const name[] = {
686 u32 risc, value, tmp;
687 unsigned int i, j, n;
689 pr_info("\n%s: %s - dma Audio channel status dump\n",
690 dev->name, ch->name);
692 for (i = 0; i < ARRAY_SIZE(name); i++)
693 pr_info("%s: cmds + 0x%2x: %-15s: 0x%08x\n",
694 dev->name, i * 4, name[i],
695 cx_read(ch->cmds_start + 4 * i));
698 for (i = 0; i < 4;) {
699 risc = cx_read(ch->cmds_start + 4 * (i + 14));
700 pr_warn("cmds + 0x%2x: risc%d: ", j + i * 4, i);
701 i += cx25821_risc_decode(risc);
704 for (i = 0; i < (64 >> 2); i += n) {
705 risc = cx_read(ch->ctrl_start + 4 * i);
706 /* No consideration for bits 63-32 */
708 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
709 i * 4, ch->ctrl_start + 4 * i, i);
710 n = cx25821_risc_decode(risc);
712 for (j = 1; j < n; j++) {
713 risc = cx_read(ch->ctrl_start + 4 * (i + j));
714 pr_warn("ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n",
715 4 * (i + j), i + j, risc, j);
719 pr_warn(" : fifo: 0x%08x -> 0x%x\n",
720 ch->fifo_start, ch->fifo_start + ch->fifo_size);
721 pr_warn(" : ctrl: 0x%08x -> 0x%x\n",
722 ch->ctrl_start, ch->ctrl_start + 6 * 16);
723 pr_warn(" : ptr1_reg: 0x%08x\n",
724 cx_read(ch->ptr1_reg));
725 pr_warn(" : ptr2_reg: 0x%08x\n",
726 cx_read(ch->ptr2_reg));
727 pr_warn(" : cnt1_reg: 0x%08x\n",
728 cx_read(ch->cnt1_reg));
729 pr_warn(" : cnt2_reg: 0x%08x\n",
730 cx_read(ch->cnt2_reg));
732 for (i = 0; i < 4; i++) {
733 risc = cx_read(ch->cmds_start + 56 + (i * 4));
734 pr_warn("instruction %d = 0x%x\n", i, risc);
737 /* read data from the first cdt buffer */
738 risc = cx_read(AUD_A_CDT);
739 pr_warn("\nread cdt loc=0x%x\n", risc);
740 for (i = 0; i < 8; i++) {
741 n = cx_read(risc + i * 4);
746 value = cx_read(CLK_RST);
747 CX25821_INFO(" CLK_RST = 0x%x\n\n", value);
749 value = cx_read(PLL_A_POST_STAT_BIST);
750 CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x\n\n", value);
751 value = cx_read(PLL_A_INT_FRAC);
752 CX25821_INFO(" PLL_A_INT_FRAC = 0x%x\n\n", value);
754 value = cx_read(PLL_B_POST_STAT_BIST);
755 CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x\n\n", value);
756 value = cx_read(PLL_B_INT_FRAC);
757 CX25821_INFO(" PLL_B_INT_FRAC = 0x%x\n\n", value);
759 value = cx_read(PLL_C_POST_STAT_BIST);
760 CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x\n\n", value);
761 value = cx_read(PLL_C_INT_FRAC);
762 CX25821_INFO(" PLL_C_INT_FRAC = 0x%x\n\n", value);
764 value = cx_read(PLL_D_POST_STAT_BIST);
765 CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x\n\n", value);
766 value = cx_read(PLL_D_INT_FRAC);
767 CX25821_INFO(" PLL_D_INT_FRAC = 0x%x\n\n", value);
769 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
770 CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x\n\n", value);
772 EXPORT_SYMBOL(cx25821_sram_channel_dump_audio);
774 static void cx25821_shutdown(struct cx25821_dev *dev)
778 /* disable RISC controller */
779 cx_write(DEV_CNTRL2, 0);
781 /* Disable Video A/B activity */
782 for (i = 0; i < VID_CHANNEL_NUM; i++) {
783 cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
784 cx_write(dev->channels[i].sram_channels->int_msk, 0);
787 for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
788 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
789 cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
790 cx_write(dev->channels[i].sram_channels->int_msk, 0);
793 /* Disable Audio activity */
794 cx_write(AUD_INT_DMA_CTL, 0);
796 /* Disable Serial port */
797 cx_write(UART_CTL, 0);
799 /* Disable Interrupts */
800 cx_write(PCI_INT_MSK, 0);
801 cx_write(AUD_A_INT_MSK, 0);
804 void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel_select,
807 if (channel_select <= 7 && channel_select >= 0) {
808 cx_write(dev->channels[channel_select].
809 sram_channels->pix_frmt, format);
810 dev->channels[channel_select].pixel_formats = format;
814 static void cx25821_set_vip_mode(struct cx25821_dev *dev,
815 struct sram_channel *ch)
817 cx_write(ch->pix_frmt, PIXEL_FRMT_422);
818 cx_write(ch->vip_ctl, PIXEL_ENGINE_VIP1);
821 static void cx25821_initialize(struct cx25821_dev *dev)
825 dprintk(1, "%s()\n", __func__);
827 cx25821_shutdown(dev);
828 cx_write(PCI_INT_STAT, 0xffffffff);
830 for (i = 0; i < VID_CHANNEL_NUM; i++)
831 cx_write(dev->channels[i].sram_channels->int_stat, 0xffffffff);
833 cx_write(AUD_A_INT_STAT, 0xffffffff);
834 cx_write(AUD_B_INT_STAT, 0xffffffff);
835 cx_write(AUD_C_INT_STAT, 0xffffffff);
836 cx_write(AUD_D_INT_STAT, 0xffffffff);
837 cx_write(AUD_E_INT_STAT, 0xffffffff);
839 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
840 cx_write(PAD_CTRL, 0x12); /* for I2C */
841 cx25821_registers_init(dev); /* init Pecos registers */
844 for (i = 0; i < VID_CHANNEL_NUM; i++) {
845 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
846 cx25821_sram_channel_setup(dev, dev->channels[i].sram_channels,
848 dev->channels[i].pixel_formats = PIXEL_FRMT_422;
849 dev->channels[i].use_cif_resolution = FALSE;
852 /* Probably only affect Downstream */
853 for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
854 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
855 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
858 cx25821_sram_channel_setup_audio(dev,
859 dev->channels[SRAM_CH08].sram_channels,
862 cx25821_gpio_init(dev);
865 static int cx25821_get_resources(struct cx25821_dev *dev)
867 if (request_mem_region
868 (pci_resource_start(dev->pci, 0), pci_resource_len(dev->pci, 0),
872 pr_err("%s: can't get MMIO memory @ 0x%llx\n",
873 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
878 static void cx25821_dev_checkrevision(struct cx25821_dev *dev)
880 dev->hwrevision = cx_read(RDR_CFG2) & 0xff;
882 pr_info("%s(): Hardware revision = 0x%02x\n",
883 __func__, dev->hwrevision);
886 static void cx25821_iounmap(struct cx25821_dev *dev)
891 /* Releasing IO memory */
892 if (dev->lmmio != NULL) {
893 CX25821_INFO("Releasing lmmio.\n");
899 static int cx25821_dev_setup(struct cx25821_dev *dev)
903 pr_info("\n***********************************\n");
904 pr_info("cx25821 set up\n");
905 pr_info("***********************************\n\n");
907 mutex_init(&dev->lock);
909 atomic_inc(&dev->refcount);
911 dev->nr = ++cx25821_devcount;
912 sprintf(dev->name, "cx25821[%d]", dev->nr);
914 mutex_lock(&devlist);
915 list_add_tail(&dev->devlist, &cx25821_devlist);
916 mutex_unlock(&devlist);
918 strcpy(cx25821_boards[UNKNOWN_BOARD].name, "unknown");
919 strcpy(cx25821_boards[CX25821_BOARD].name, "cx25821");
921 if (dev->pci->device != 0x8210) {
922 pr_info("%s(): Exiting. Incorrect Hardware device = 0x%02x\n",
923 __func__, dev->pci->device);
926 pr_info("Athena Hardware device = 0x%02x\n", dev->pci->device);
929 /* Apply a sensible clock frequency for the PCIe bridge */
930 dev->clk_freq = 28000000;
931 for (i = 0; i < MAX_VID_CHANNEL_NUM; i++)
932 dev->channels[i].sram_channels = &cx25821_sram_channels[i];
935 CX25821_INFO("dev->nr > 1!");
938 dev->board = 1; /* card[dev->nr]; */
939 dev->_max_num_decoders = MAX_DECODERS;
941 dev->pci_bus = dev->pci->bus->number;
942 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
943 dev->pci_irqmask = 0x001f00;
945 /* External Master 1 Bus */
946 dev->i2c_bus[0].nr = 0;
947 dev->i2c_bus[0].dev = dev;
948 dev->i2c_bus[0].reg_stat = I2C1_STAT;
949 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
950 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
951 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
952 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
953 dev->i2c_bus[0].i2c_period = (0x07 << 24); /* 1.95MHz */
955 if (cx25821_get_resources(dev) < 0) {
956 pr_err("%s: No more PCIe resources for subsystem: %04x:%04x\n",
957 dev->name, dev->pci->subsystem_vendor,
958 dev->pci->subsystem_device);
965 dev->base_io_addr = pci_resource_start(dev->pci, 0);
966 io_size = pci_resource_len(dev->pci, 0);
968 if (!dev->base_io_addr) {
969 CX25821_ERR("No PCI Memory resources, exiting!\n");
973 dev->lmmio = ioremap(dev->base_io_addr, pci_resource_len(dev->pci, 0));
977 ("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n");
978 cx25821_iounmap(dev);
982 dev->bmmio = (u8 __iomem *) dev->lmmio;
984 pr_info("%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
985 dev->name, dev->pci->subsystem_vendor,
986 dev->pci->subsystem_device, cx25821_boards[dev->board].name,
987 dev->board, card[dev->nr] == dev->board ?
988 "insmod option" : "autodetected");
991 cx25821_initialize(dev);
993 cx25821_i2c_register(&dev->i2c_bus[0]);
994 /* cx25821_i2c_register(&dev->i2c_bus[1]);
995 * cx25821_i2c_register(&dev->i2c_bus[2]); */
997 CX25821_INFO("i2c register! bus->i2c_rc = %d\n",
998 dev->i2c_bus[0].i2c_rc);
1000 cx25821_card_setup(dev);
1002 if (medusa_video_init(dev) < 0)
1003 CX25821_ERR("%s(): Failed to initialize medusa!\n", __func__);
1005 cx25821_video_register(dev);
1007 /* register IOCTL device */
1009 cx25821_vdev_init(dev, dev->pci, &cx25821_videoioctl_template,
1012 if (video_register_device
1013 (dev->ioctl_dev, VFL_TYPE_GRABBER, VIDEO_IOCTL_CH) < 0) {
1014 cx25821_videoioctl_unregister(dev);
1015 pr_err("%s(): Failed to register video adapter for IOCTL, so unregistering videoioctl device\n",
1019 cx25821_dev_checkrevision(dev);
1020 CX25821_INFO("setup done!\n");
1025 void cx25821_start_upstream_video_ch1(struct cx25821_dev *dev,
1026 struct upstream_user_struct *up_data)
1028 dev->_isNTSC = !strcmp(dev->vid_stdname, "NTSC") ? 1 : 0;
1030 dev->tvnorm = !dev->_isNTSC ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
1031 medusa_set_videostandard(dev);
1033 cx25821_vidupstream_init_ch1(dev, dev->channel_select,
1037 void cx25821_start_upstream_video_ch2(struct cx25821_dev *dev,
1038 struct upstream_user_struct *up_data)
1040 dev->_isNTSC_ch2 = !strcmp(dev->vid_stdname_ch2, "NTSC") ? 1 : 0;
1042 dev->tvnorm = !dev->_isNTSC_ch2 ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
1043 medusa_set_videostandard(dev);
1045 cx25821_vidupstream_init_ch2(dev, dev->channel_select_ch2,
1046 dev->pixel_format_ch2);
1049 void cx25821_start_upstream_audio(struct cx25821_dev *dev,
1050 struct upstream_user_struct *up_data)
1052 cx25821_audio_upstream_init(dev, AUDIO_UPSTREAM_SRAM_CHANNEL_B);
1055 void cx25821_dev_unregister(struct cx25821_dev *dev)
1059 if (!dev->base_io_addr)
1062 cx25821_free_mem_upstream_ch1(dev);
1063 cx25821_free_mem_upstream_ch2(dev);
1064 cx25821_free_mem_upstream_audio(dev);
1066 release_mem_region(dev->base_io_addr, pci_resource_len(dev->pci, 0));
1068 if (!atomic_dec_and_test(&dev->refcount))
1071 for (i = 0; i < VID_CHANNEL_NUM; i++)
1072 cx25821_video_unregister(dev, i);
1074 for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
1075 i <= AUDIO_UPSTREAM_SRAM_CHANNEL_B; i++) {
1076 cx25821_video_unregister(dev, i);
1079 cx25821_videoioctl_unregister(dev);
1081 cx25821_i2c_unregister(&dev->i2c_bus[0]);
1082 cx25821_iounmap(dev);
1084 EXPORT_SYMBOL(cx25821_dev_unregister);
1086 static __le32 *cx25821_risc_field(__le32 * rp, struct scatterlist *sglist,
1087 unsigned int offset, u32 sync_line,
1088 unsigned int bpl, unsigned int padding,
1091 struct scatterlist *sg;
1092 unsigned int line, todo;
1094 /* sync instruction */
1095 if (sync_line != NO_SYNC_LINE)
1096 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1100 for (line = 0; line < lines; line++) {
1101 while (offset && offset >= sg_dma_len(sg)) {
1102 offset -= sg_dma_len(sg);
1105 if (bpl <= sg_dma_len(sg) - offset) {
1106 /* fits into current chunk */
1108 cpu_to_le32(RISC_WRITE | RISC_SOL | RISC_EOL | bpl);
1109 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1110 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1113 /* scanline needs to be split */
1116 cpu_to_le32(RISC_WRITE | RISC_SOL |
1117 (sg_dma_len(sg) - offset));
1118 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1119 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1120 todo -= (sg_dma_len(sg) - offset);
1123 while (todo > sg_dma_len(sg)) {
1125 cpu_to_le32(RISC_WRITE | sg_dma_len(sg));
1126 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1127 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1128 todo -= sg_dma_len(sg);
1131 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1132 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1133 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1143 int cx25821_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
1144 struct scatterlist *sglist, unsigned int top_offset,
1145 unsigned int bottom_offset, unsigned int bpl,
1146 unsigned int padding, unsigned int lines)
1154 if (UNSET != top_offset)
1156 if (UNSET != bottom_offset)
1159 /* estimate risc mem: worst case is one write per page border +
1160 one write per scan line + syncs + jump (all 2 dwords). Padding
1161 can cause next bpl to start close to a page border. First DMA
1162 region may be smaller than PAGE_SIZE */
1163 /* write and jump need and extra dword */
1165 fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
1167 rc = btcx_riscmem_alloc(pci, risc, instructions * 12);
1172 /* write risc instructions */
1175 if (UNSET != top_offset) {
1176 rp = cx25821_risc_field(rp, sglist, top_offset, 0, bpl, padding,
1180 if (UNSET != bottom_offset) {
1181 rp = cx25821_risc_field(rp, sglist, bottom_offset, 0x200, bpl,
1185 /* save pointer to jmp instruction address */
1187 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1192 static __le32 *cx25821_risc_field_audio(__le32 * rp, struct scatterlist *sglist,
1193 unsigned int offset, u32 sync_line,
1194 unsigned int bpl, unsigned int padding,
1195 unsigned int lines, unsigned int lpi)
1197 struct scatterlist *sg;
1198 unsigned int line, todo, sol;
1200 /* sync instruction */
1201 if (sync_line != NO_SYNC_LINE)
1202 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1206 for (line = 0; line < lines; line++) {
1207 while (offset && offset >= sg_dma_len(sg)) {
1208 offset -= sg_dma_len(sg);
1212 if (lpi && line > 0 && !(line % lpi))
1213 sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
1217 if (bpl <= sg_dma_len(sg) - offset) {
1218 /* fits into current chunk */
1220 cpu_to_le32(RISC_WRITE | sol | RISC_EOL | bpl);
1221 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1222 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1225 /* scanline needs to be split */
1227 *(rp++) = cpu_to_le32(RISC_WRITE | sol |
1228 (sg_dma_len(sg) - offset));
1229 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1230 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1231 todo -= (sg_dma_len(sg) - offset);
1234 while (todo > sg_dma_len(sg)) {
1235 *(rp++) = cpu_to_le32(RISC_WRITE |
1237 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1238 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1239 todo -= sg_dma_len(sg);
1242 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1243 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1244 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1253 int cx25821_risc_databuffer_audio(struct pci_dev *pci,
1254 struct btcx_riscmem *risc,
1255 struct scatterlist *sglist,
1257 unsigned int lines, unsigned int lpi)
1263 /* estimate risc mem: worst case is one write per page border +
1264 one write per scan line + syncs + jump (all 2 dwords). Here
1265 there is no padding and no sync. First DMA region may be smaller
1267 /* Jump and write need an extra dword */
1268 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
1271 rc = btcx_riscmem_alloc(pci, risc, instructions * 12);
1275 /* write risc instructions */
1277 rp = cx25821_risc_field_audio(rp, sglist, 0, NO_SYNC_LINE, bpl, 0,
1280 /* save pointer to jmp instruction address */
1282 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1285 EXPORT_SYMBOL(cx25821_risc_databuffer_audio);
1287 int cx25821_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1288 u32 reg, u32 mask, u32 value)
1293 rc = btcx_riscmem_alloc(pci, risc, 4 * 16);
1298 /* write risc instructions */
1301 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ1);
1302 *(rp++) = cpu_to_le32(reg);
1303 *(rp++) = cpu_to_le32(value);
1304 *(rp++) = cpu_to_le32(mask);
1305 *(rp++) = cpu_to_le32(RISC_JUMP);
1306 *(rp++) = cpu_to_le32(risc->dma);
1307 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1311 void cx25821_free_buffer(struct videobuf_queue *q, struct cx25821_buffer *buf)
1313 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1315 BUG_ON(in_interrupt());
1316 videobuf_waiton(q, &buf->vb, 0, 0);
1317 videobuf_dma_unmap(q->dev, dma);
1318 videobuf_dma_free(dma);
1319 btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
1320 buf->vb.state = VIDEOBUF_NEEDS_INIT;
1323 static irqreturn_t cx25821_irq(int irq, void *dev_id)
1325 struct cx25821_dev *dev = dev_id;
1326 u32 pci_status, pci_mask;
1329 u32 mask[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
1331 pci_status = cx_read(PCI_INT_STAT);
1332 pci_mask = cx_read(PCI_INT_MSK);
1334 if (pci_status == 0)
1337 for (i = 0; i < VID_CHANNEL_NUM; i++) {
1338 if (pci_status & mask[i]) {
1339 vid_status = cx_read(dev->channels[i].
1340 sram_channels->int_stat);
1344 cx25821_video_irq(dev, i, vid_status);
1346 cx_write(PCI_INT_STAT, mask[i]);
1351 return IRQ_RETVAL(handled);
1354 void cx25821_print_irqbits(char *name, char *tag, char **strings,
1355 int len, u32 bits, u32 mask)
1359 printk(KERN_DEBUG pr_fmt("%s: %s [0x%x]"), name, tag, bits);
1361 for (i = 0; i < len; i++) {
1362 if (!(bits & (1 << i)))
1365 pr_cont(" %s", strings[i]);
1368 if (!(mask & (1 << i)))
1374 EXPORT_SYMBOL(cx25821_print_irqbits);
1376 struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci)
1378 struct cx25821_dev *dev = pci_get_drvdata(pci);
1381 EXPORT_SYMBOL(cx25821_dev_get);
1383 static int __devinit cx25821_initdev(struct pci_dev *pci_dev,
1384 const struct pci_device_id *pci_id)
1386 struct cx25821_dev *dev;
1389 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1393 err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
1399 if (pci_enable_device(pci_dev)) {
1402 pr_info("pci enable failed!\n");
1404 goto fail_unregister_device;
1407 pr_info("Athena pci enable !\n");
1409 err = cx25821_dev_setup(dev);
1412 goto fail_unregister_device;
1414 goto fail_unregister_pci;
1417 /* print pci info */
1418 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1419 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1420 pr_info("%s/0: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
1421 dev->name, pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1422 dev->pci_lat, (unsigned long long)dev->base_io_addr);
1424 pci_set_master(pci_dev);
1425 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1426 pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1432 request_irq(pci_dev->irq, cx25821_irq, IRQF_SHARED | IRQF_DISABLED,
1436 pr_err("%s: can't get IRQ %d\n", dev->name, pci_dev->irq);
1443 pr_info("cx25821_initdev() can't get IRQ !\n");
1444 cx25821_dev_unregister(dev);
1446 fail_unregister_pci:
1447 pci_disable_device(pci_dev);
1448 fail_unregister_device:
1449 v4l2_device_unregister(&dev->v4l2_dev);
1456 static void __devexit cx25821_finidev(struct pci_dev *pci_dev)
1458 struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
1459 struct cx25821_dev *dev = get_cx25821(v4l2_dev);
1461 cx25821_shutdown(dev);
1462 pci_disable_device(pci_dev);
1464 /* unregister stuff */
1466 free_irq(pci_dev->irq, dev);
1468 mutex_lock(&devlist);
1469 list_del(&dev->devlist);
1470 mutex_unlock(&devlist);
1472 cx25821_dev_unregister(dev);
1473 v4l2_device_unregister(v4l2_dev);
1477 static struct pci_device_id cx25821_pci_tbl[] = {
1479 /* CX25821 Athena */
1482 .subvendor = 0x14f1,
1483 .subdevice = 0x0920,
1486 /* --- end of list --- */
1490 MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl);
1492 static struct pci_driver cx25821_pci_driver = {
1494 .id_table = cx25821_pci_tbl,
1495 .probe = cx25821_initdev,
1496 .remove = __devexit_p(cx25821_finidev),
1502 static int __init cx25821_init(void)
1504 INIT_LIST_HEAD(&cx25821_devlist);
1505 pr_info("driver version %d.%d.%d loaded\n",
1506 (CX25821_VERSION_CODE >> 16) & 0xff,
1507 (CX25821_VERSION_CODE >> 8) & 0xff,
1508 CX25821_VERSION_CODE & 0xff);
1509 return pci_register_driver(&cx25821_pci_driver);
1512 static void __exit cx25821_fini(void)
1514 pci_unregister_driver(&cx25821_pci_driver);
1517 EXPORT_SYMBOL(cx25821_set_gpiopin_direction);
1519 module_init(cx25821_init);
1520 module_exit(cx25821_fini);