drivers/staging/cx25821/cx25821-core.c

   1 /*
   2  *  Driver for the Conexant CX25821 PCIe bridge
   3  *
   4  *  Copyright (C) 2009 Conexant Systems Inc.
   5  *  Authors  <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
   6  *  Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *
  17  *  GNU General Public License for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License
  20  *  along with this program; if not, write to the Free Software
  21  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #include <linux/i2c.h>
  25 #include <linux/slab.h>
  26 #include "cx25821.h"
  27 #include "cx25821-sram.h"
  28 #include "cx25821-video.h"
  29
  30 MODULE_DESCRIPTION("Driver for Athena cards");
  31 MODULE_AUTHOR("Shu Lin - Hiep Huynh");
  32 MODULE_LICENSE("GPL");
  33
  34 struct list_head cx25821_devlist;
  35 EXPORT_SYMBOL(cx25821_devlist);
  36
  37 static unsigned int debug;
  38 module_param(debug, int, 0644);
  39 MODULE_PARM_DESC(debug, "enable debug messages");
  40
  41 static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
  42 module_param_array(card, int, NULL, 0444);
  43 MODULE_PARM_DESC(card, "card type");
  44
  45 static unsigned int cx25821_devcount;
  46
  47 static DEFINE_MUTEX(devlist);
  48 LIST_HEAD(cx25821_devlist);
  49
  50 struct sram_channel cx25821_sram_channels[] = {
  51         [SRAM_CH00] = {
  52                        .i = SRAM_CH00,
  53                        .name = "VID A",
  54                        .cmds_start = VID_A_DOWN_CMDS,
  55                        .ctrl_start = VID_A_IQ,
  56                        .cdt = VID_A_CDT,
  57                        .fifo_start = VID_A_DOWN_CLUSTER_1,
  58                        .fifo_size = (VID_CLUSTER_SIZE << 2),
  59                        .ptr1_reg = DMA1_PTR1,
  60                        .ptr2_reg = DMA1_PTR2,
  61                        .cnt1_reg = DMA1_CNT1,
  62                        .cnt2_reg = DMA1_CNT2,
  63                        .int_msk = VID_A_INT_MSK,
  64                        .int_stat = VID_A_INT_STAT,
  65                        .int_mstat = VID_A_INT_MSTAT,
  66                        .dma_ctl = VID_DST_A_DMA_CTL,
  67                        .gpcnt_ctl = VID_DST_A_GPCNT_CTL,
  68                        .gpcnt = VID_DST_A_GPCNT,
  69                        .vip_ctl = VID_DST_A_VIP_CTL,
  70                        .pix_frmt = VID_DST_A_PIX_FRMT,
  71                        },
  72
  73         [SRAM_CH01] = {
  74                        .i = SRAM_CH01,
  75                        .name = "VID B",
  76                        .cmds_start = VID_B_DOWN_CMDS,
  77                        .ctrl_start = VID_B_IQ,
  78                        .cdt = VID_B_CDT,
  79                        .fifo_start = VID_B_DOWN_CLUSTER_1,
  80                        .fifo_size = (VID_CLUSTER_SIZE << 2),
  81                        .ptr1_reg = DMA2_PTR1,
  82                        .ptr2_reg = DMA2_PTR2,
  83                        .cnt1_reg = DMA2_CNT1,
  84                        .cnt2_reg = DMA2_CNT2,
  85                        .int_msk = VID_B_INT_MSK,
  86                        .int_stat = VID_B_INT_STAT,
  87                        .int_mstat = VID_B_INT_MSTAT,
  88                        .dma_ctl = VID_DST_B_DMA_CTL,
  89                        .gpcnt_ctl = VID_DST_B_GPCNT_CTL,
  90                        .gpcnt = VID_DST_B_GPCNT,
  91                        .vip_ctl = VID_DST_B_VIP_CTL,
  92                        .pix_frmt = VID_DST_B_PIX_FRMT,
  93                        },
  94
  95         [SRAM_CH02] = {
  96                        .i = SRAM_CH02,
  97                        .name = "VID C",
  98                        .cmds_start = VID_C_DOWN_CMDS,
  99                        .ctrl_start = VID_C_IQ,
 100                        .cdt = VID_C_CDT,
 101                        .fifo_start = VID_C_DOWN_CLUSTER_1,
 102                        .fifo_size = (VID_CLUSTER_SIZE << 2),
 103                        .ptr1_reg = DMA3_PTR1,
 104                        .ptr2_reg = DMA3_PTR2,
 105                        .cnt1_reg = DMA3_CNT1,
 106                        .cnt2_reg = DMA3_CNT2,
 107                        .int_msk = VID_C_INT_MSK,
 108                        .int_stat = VID_C_INT_STAT,
 109                        .int_mstat = VID_C_INT_MSTAT,
 110                        .dma_ctl = VID_DST_C_DMA_CTL,
 111                        .gpcnt_ctl = VID_DST_C_GPCNT_CTL,
 112                        .gpcnt = VID_DST_C_GPCNT,
 113                        .vip_ctl = VID_DST_C_VIP_CTL,
 114                        .pix_frmt = VID_DST_C_PIX_FRMT,
 115                        },
 116
 117         [SRAM_CH03] = {
 118                        .i = SRAM_CH03,
 119                        .name = "VID D",
 120                        .cmds_start = VID_D_DOWN_CMDS,
 121                        .ctrl_start = VID_D_IQ,
 122                        .cdt = VID_D_CDT,
 123                        .fifo_start = VID_D_DOWN_CLUSTER_1,
 124                        .fifo_size = (VID_CLUSTER_SIZE << 2),
 125                        .ptr1_reg = DMA4_PTR1,
 126                        .ptr2_reg = DMA4_PTR2,
 127                        .cnt1_reg = DMA4_CNT1,
 128                        .cnt2_reg = DMA4_CNT2,
 129                        .int_msk = VID_D_INT_MSK,
 130                        .int_stat = VID_D_INT_STAT,
 131                        .int_mstat = VID_D_INT_MSTAT,
 132                        .dma_ctl = VID_DST_D_DMA_CTL,
 133                        .gpcnt_ctl = VID_DST_D_GPCNT_CTL,
 134                        .gpcnt = VID_DST_D_GPCNT,
 135                        .vip_ctl = VID_DST_D_VIP_CTL,
 136                        .pix_frmt = VID_DST_D_PIX_FRMT,
 137                        },
 138
 139         [SRAM_CH04] = {
 140                        .i = SRAM_CH04,
 141                        .name = "VID E",
 142                        .cmds_start = VID_E_DOWN_CMDS,
 143                        .ctrl_start = VID_E_IQ,
 144                        .cdt = VID_E_CDT,
 145                        .fifo_start = VID_E_DOWN_CLUSTER_1,
 146                        .fifo_size = (VID_CLUSTER_SIZE << 2),
 147                        .ptr1_reg = DMA5_PTR1,
 148                        .ptr2_reg = DMA5_PTR2,
 149                        .cnt1_reg = DMA5_CNT1,
 150                        .cnt2_reg = DMA5_CNT2,
 151                        .int_msk = VID_E_INT_MSK,
 152                        .int_stat = VID_E_INT_STAT,
 153                        .int_mstat = VID_E_INT_MSTAT,
 154                        .dma_ctl = VID_DST_E_DMA_CTL,
 155                        .gpcnt_ctl = VID_DST_E_GPCNT_CTL,
 156                        .gpcnt = VID_DST_E_GPCNT,
 157                        .vip_ctl = VID_DST_E_VIP_CTL,
 158                        .pix_frmt = VID_DST_E_PIX_FRMT,
 159                        },
 160
 161         [SRAM_CH05] = {
 162                        .i = SRAM_CH05,
 163                        .name = "VID F",
 164                        .cmds_start = VID_F_DOWN_CMDS,
 165                        .ctrl_start = VID_F_IQ,
 166                        .cdt = VID_F_CDT,
 167                        .fifo_start = VID_F_DOWN_CLUSTER_1,
 168                        .fifo_size = (VID_CLUSTER_SIZE << 2),
 169                        .ptr1_reg = DMA6_PTR1,
 170                        .ptr2_reg = DMA6_PTR2,
 171                        .cnt1_reg = DMA6_CNT1,
 172                        .cnt2_reg = DMA6_CNT2,
 173                        .int_msk = VID_F_INT_MSK,
 174                        .int_stat = VID_F_INT_STAT,
 175                        .int_mstat = VID_F_INT_MSTAT,
 176                        .dma_ctl = VID_DST_F_DMA_CTL,
 177                        .gpcnt_ctl = VID_DST_F_GPCNT_CTL,
 178                        .gpcnt = VID_DST_F_GPCNT,
 179                        .vip_ctl = VID_DST_F_VIP_CTL,
 180                        .pix_frmt = VID_DST_F_PIX_FRMT,
 181                        },
 182
 183         [SRAM_CH06] = {
 184                        .i = SRAM_CH06,
 185                        .name = "VID G",
 186                        .cmds_start = VID_G_DOWN_CMDS,
 187                        .ctrl_start = VID_G_IQ,
 188                        .cdt = VID_G_CDT,
 189                        .fifo_start = VID_G_DOWN_CLUSTER_1,
 190                        .fifo_size = (VID_CLUSTER_SIZE << 2),
 191                        .ptr1_reg = DMA7_PTR1,
 192                        .ptr2_reg = DMA7_PTR2,
 193                        .cnt1_reg = DMA7_CNT1,
 194                        .cnt2_reg = DMA7_CNT2,
 195                        .int_msk = VID_G_INT_MSK,
 196                        .int_stat = VID_G_INT_STAT,
 197                        .int_mstat = VID_G_INT_MSTAT,
 198                        .dma_ctl = VID_DST_G_DMA_CTL,
 199                        .gpcnt_ctl = VID_DST_G_GPCNT_CTL,
 200                        .gpcnt = VID_DST_G_GPCNT,
 201                        .vip_ctl = VID_DST_G_VIP_CTL,
 202                        .pix_frmt = VID_DST_G_PIX_FRMT,
 203                        },
 204
 205         [SRAM_CH07] = {
 206                        .i = SRAM_CH07,
 207                        .name = "VID H",
 208                        .cmds_start = VID_H_DOWN_CMDS,
 209                        .ctrl_start = VID_H_IQ,
 210                        .cdt = VID_H_CDT,
 211                        .fifo_start = VID_H_DOWN_CLUSTER_1,
 212                        .fifo_size = (VID_CLUSTER_SIZE << 2),
 213                        .ptr1_reg = DMA8_PTR1,
 214                        .ptr2_reg = DMA8_PTR2,
 215                        .cnt1_reg = DMA8_CNT1,
 216                        .cnt2_reg = DMA8_CNT2,
 217                        .int_msk = VID_H_INT_MSK,
 218                        .int_stat = VID_H_INT_STAT,
 219                        .int_mstat = VID_H_INT_MSTAT,
 220                        .dma_ctl = VID_DST_H_DMA_CTL,
 221                        .gpcnt_ctl = VID_DST_H_GPCNT_CTL,
 222                        .gpcnt = VID_DST_H_GPCNT,
 223                        .vip_ctl = VID_DST_H_VIP_CTL,
 224                        .pix_frmt = VID_DST_H_PIX_FRMT,
 225                        },
 226
 227         [SRAM_CH08] = {
 228                        .name = "audio from",
 229                        .cmds_start = AUD_A_DOWN_CMDS,
 230                        .ctrl_start = AUD_A_IQ,
 231                        .cdt = AUD_A_CDT,
 232                        .fifo_start = AUD_A_DOWN_CLUSTER_1,
 233                        .fifo_size = AUDIO_CLUSTER_SIZE * 3,
 234                        .ptr1_reg = DMA17_PTR1,
 235                        .ptr2_reg = DMA17_PTR2,
 236                        .cnt1_reg = DMA17_CNT1,
 237                        .cnt2_reg = DMA17_CNT2,
 238                        },
 239
 240         [SRAM_CH09] = {
 241                        .i = SRAM_CH09,
 242                        .name = "VID Upstream I",
 243                        .cmds_start = VID_I_UP_CMDS,
 244                        .ctrl_start = VID_I_IQ,
 245                        .cdt = VID_I_CDT,
 246                        .fifo_start = VID_I_UP_CLUSTER_1,
 247                        .fifo_size = (VID_CLUSTER_SIZE << 2),
 248                        .ptr1_reg = DMA15_PTR1,
 249                        .ptr2_reg = DMA15_PTR2,
 250                        .cnt1_reg = DMA15_CNT1,
 251                        .cnt2_reg = DMA15_CNT2,
 252                        .int_msk = VID_I_INT_MSK,
 253                        .int_stat = VID_I_INT_STAT,
 254                        .int_mstat = VID_I_INT_MSTAT,
 255                        .dma_ctl = VID_SRC_I_DMA_CTL,
 256                        .gpcnt_ctl = VID_SRC_I_GPCNT_CTL,
 257                        .gpcnt = VID_SRC_I_GPCNT,
 258
 259                        .vid_fmt_ctl = VID_SRC_I_FMT_CTL,
 260                        .vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1,
 261                        .vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2,
 262                        .vid_cdt_size = VID_SRC_I_CDT_SZ,
 263                        .irq_bit = 8,
 264                        },
 265
 266         [SRAM_CH10] = {
 267                        .i = SRAM_CH10,
 268                        .name = "VID Upstream J",
 269                        .cmds_start = VID_J_UP_CMDS,
 270                        .ctrl_start = VID_J_IQ,
 271                        .cdt = VID_J_CDT,
 272                        .fifo_start = VID_J_UP_CLUSTER_1,
 273                        .fifo_size = (VID_CLUSTER_SIZE << 2),
 274                        .ptr1_reg = DMA16_PTR1,
 275                        .ptr2_reg = DMA16_PTR2,
 276                        .cnt1_reg = DMA16_CNT1,
 277                        .cnt2_reg = DMA16_CNT2,
 278                        .int_msk = VID_J_INT_MSK,
 279                        .int_stat = VID_J_INT_STAT,
 280                        .int_mstat = VID_J_INT_MSTAT,
 281                        .dma_ctl = VID_SRC_J_DMA_CTL,
 282                        .gpcnt_ctl = VID_SRC_J_GPCNT_CTL,
 283                        .gpcnt = VID_SRC_J_GPCNT,
 284
 285                        .vid_fmt_ctl = VID_SRC_J_FMT_CTL,
 286                        .vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1,
 287                        .vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2,
 288                        .vid_cdt_size = VID_SRC_J_CDT_SZ,
 289                        .irq_bit = 9,
 290                        },
 291
 292         [SRAM_CH11] = {
 293                        .i = SRAM_CH11,
 294                        .name = "Audio Upstream Channel B",
 295                        .cmds_start = AUD_B_UP_CMDS,
 296                        .ctrl_start = AUD_B_IQ,
 297                        .cdt = AUD_B_CDT,
 298                        .fifo_start = AUD_B_UP_CLUSTER_1,
 299                        .fifo_size = (AUDIO_CLUSTER_SIZE * 3),
 300                        .ptr1_reg = DMA22_PTR1,
 301                        .ptr2_reg = DMA22_PTR2,
 302                        .cnt1_reg = DMA22_CNT1,
 303                        .cnt2_reg = DMA22_CNT2,
 304                        .int_msk = AUD_B_INT_MSK,
 305                        .int_stat = AUD_B_INT_STAT,
 306                        .int_mstat = AUD_B_INT_MSTAT,
 307                        .dma_ctl = AUD_INT_DMA_CTL,
 308                        .gpcnt_ctl = AUD_B_GPCNT_CTL,
 309                        .gpcnt = AUD_B_GPCNT,
 310                        .aud_length = AUD_B_LNGTH,
 311                        .aud_cfg = AUD_B_CFG,
 312                        .fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN,
 313                        .fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN,
 314                        .irq_bit = 11,
 315                        },
 316 };
 317 EXPORT_SYMBOL(cx25821_sram_channels);
 318
 319 struct sram_channel *channel0 = &cx25821_sram_channels[SRAM_CH00];
 320 struct sram_channel *channel1 = &cx25821_sram_channels[SRAM_CH01];
 321 struct sram_channel *channel2 = &cx25821_sram_channels[SRAM_CH02];
 322 struct sram_channel *channel3 = &cx25821_sram_channels[SRAM_CH03];
 323 struct sram_channel *channel4 = &cx25821_sram_channels[SRAM_CH04];
 324 struct sram_channel *channel5 = &cx25821_sram_channels[SRAM_CH05];
 325 struct sram_channel *channel6 = &cx25821_sram_channels[SRAM_CH06];
 326 struct sram_channel *channel7 = &cx25821_sram_channels[SRAM_CH07];
 327 struct sram_channel *channel9 = &cx25821_sram_channels[SRAM_CH09];
 328 struct sram_channel *channel10 = &cx25821_sram_channels[SRAM_CH10];
 329 struct sram_channel *channel11 = &cx25821_sram_channels[SRAM_CH11];
 330
 331 struct cx25821_dmaqueue mpegq;
 332
 333 static int cx25821_risc_decode(u32 risc)
 334 {
 335         static char *instr[16] = {
 336                 [RISC_SYNC >> 28] = "sync",
 337                 [RISC_WRITE >> 28] = "write",
 338                 [RISC_WRITEC >> 28] = "writec",
 339                 [RISC_READ >> 28] = "read",
 340                 [RISC_READC >> 28] = "readc",
 341                 [RISC_JUMP >> 28] = "jump",
 342                 [RISC_SKIP >> 28] = "skip",
 343                 [RISC_WRITERM >> 28] = "writerm",
 344                 [RISC_WRITECM >> 28] = "writecm",
 345                 [RISC_WRITECR >> 28] = "writecr",
 346         };
 347         static int incr[16] = {
 348                 [RISC_WRITE >> 28] = 3,
 349                 [RISC_JUMP >> 28] = 3,
 350                 [RISC_SKIP >> 28] = 1,
 351                 [RISC_SYNC >> 28] = 1,
 352                 [RISC_WRITERM >> 28] = 3,
 353                 [RISC_WRITECM >> 28] = 3,
 354                 [RISC_WRITECR >> 28] = 4,
 355         };
 356         static char *bits[] = {
 357                 "12", "13", "14", "resync",
 358                 "cnt0", "cnt1", "18", "19",
 359                 "20", "21", "22", "23",
 360                 "irq1", "irq2", "eol", "sol",
 361         };
 362         int i;
 363
 364         printk("0x%08x [ %s", risc,
 365                instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
 366         for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) {
 367                 if (risc & (1 << (i + 12)))
 368                         printk(" %s", bits[i]);
 369         }
 370         printk(" count=%d ]\n", risc & 0xfff);
 371         return incr[risc >> 28] ? incr[risc >> 28] : 1;
 372 }
 373
 374 static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap)
 375 {
 376         struct cx25821_i2c *bus = i2c_adap->algo_data;
 377         struct cx25821_dev *dev = bus->dev;
 378         return cx_read(bus->reg_stat) & 0x01;
 379 }
 380
 381 void cx_i2c_read_print(struct cx25821_dev *dev, u32 reg, const char *reg_string)
 382 {
 383         int tmp = 0;
 384         u32 value = 0;
 385
 386         value = cx25821_i2c_read(&dev->i2c_bus[0], reg, &tmp);
 387 }
 388
 389 static void cx25821_registers_init(struct cx25821_dev *dev)
 390 {
 391         u32 tmp;
 392
 393         /* enable RUN_RISC in Pecos */
 394         cx_write(DEV_CNTRL2, 0x20);
 395
 396         /* Set the master PCI interrupt masks to enable video, audio, MBIF,
 397          * and GPIO interrupts
 398          * I2C interrupt masking is handled by the I2C objects themselves. */
 399         cx_write(PCI_INT_MSK, 0x2001FFFF);
 400
 401         tmp = cx_read(RDR_TLCTL0);
 402         tmp &= ~FLD_CFG_RCB_CK_EN;      /* Clear the RCB_CK_EN bit */
 403         cx_write(RDR_TLCTL0, tmp);
 404
 405         /* PLL-A setting for the Audio Master Clock */
 406         cx_write(PLL_A_INT_FRAC, 0x9807A58B);
 407
 408         /* PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1 */
 409         cx_write(PLL_A_POST_STAT_BIST, 0x8000019C);
 410
 411         /* clear reset bit [31] */
 412         tmp = cx_read(PLL_A_INT_FRAC);
 413         cx_write(PLL_A_INT_FRAC, tmp & 0x7FFFFFFF);
 414
 415         /* PLL-B setting for Mobilygen Host Bus Interface */
 416         cx_write(PLL_B_INT_FRAC, 0x9883A86F);
 417
 418         /* PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0 */
 419         cx_write(PLL_B_POST_STAT_BIST, 0x8000018D);
 420
 421         /* clear reset bit [31] */
 422         tmp = cx_read(PLL_B_INT_FRAC);
 423         cx_write(PLL_B_INT_FRAC, tmp & 0x7FFFFFFF);
 424
 425         /* PLL-C setting for video upstream channel */
 426         cx_write(PLL_C_INT_FRAC, 0x96A0EA3F);
 427
 428         /* PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0 */
 429         cx_write(PLL_C_POST_STAT_BIST, 0x80000103);
 430
 431         /* clear reset bit [31] */
 432         tmp = cx_read(PLL_C_INT_FRAC);
 433         cx_write(PLL_C_INT_FRAC, tmp & 0x7FFFFFFF);
 434
 435         /* PLL-D setting for audio upstream channel */
 436         cx_write(PLL_D_INT_FRAC, 0x98757F5B);
 437
 438         /* PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0 */
 439         cx_write(PLL_D_POST_STAT_BIST, 0x80000113);
 440
 441         /* clear reset bit [31] */
 442         tmp = cx_read(PLL_D_INT_FRAC);
 443         cx_write(PLL_D_INT_FRAC, tmp & 0x7FFFFFFF);
 444
 445         /* This selects the PLL C clock source for the video upstream channel
 446          * I and J */
 447         tmp = cx_read(VID_CH_CLK_SEL);
 448         cx_write(VID_CH_CLK_SEL, (tmp & 0x00FFFFFF) | 0x24000000);
 449
 450         /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
 451          * channel A-C
 452          * select 656/VIP DST for downstream Channel A - C */
 453         tmp = cx_read(VID_CH_MODE_SEL);
 454         /* cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); */
 455         cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
 456
 457         /* enables 656 port I and J as output */
 458         tmp = cx_read(CLK_RST);
 459         /* use external ALT_PLL_REF pin as its reference clock instead */
 460         tmp |= FLD_USE_ALT_PLL_REF;
 461         cx_write(CLK_RST, tmp & ~(FLD_VID_I_CLK_NOE | FLD_VID_J_CLK_NOE));
 462
 463         mdelay(100);
 464 }
 465
 466 int cx25821_sram_channel_setup(struct cx25821_dev *dev,
 467                                struct sram_channel *ch,
 468                                unsigned int bpl, u32 risc)
 469 {
 470         unsigned int i, lines;
 471         u32 cdt;
 472
 473         if (ch->cmds_start == 0) {
 474                 cx_write(ch->ptr1_reg, 0);
 475                 cx_write(ch->ptr2_reg, 0);
 476                 cx_write(ch->cnt2_reg, 0);
 477                 cx_write(ch->cnt1_reg, 0);
 478                 return 0;
 479         }
 480
 481         bpl = (bpl + 7) & ~7;   /* alignment */
 482         cdt = ch->cdt;
 483         lines = ch->fifo_size / bpl;
 484
 485         if (lines > 4)
 486                 lines = 4;
 487
 488         BUG_ON(lines < 2);
 489
 490         cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
 491         cx_write(8 + 4, 8);
 492         cx_write(8 + 8, 0);
 493
 494         /* write CDT */
 495         for (i = 0; i < lines; i++) {
 496                 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
 497                 cx_write(cdt + 16 * i + 4, 0);
 498                 cx_write(cdt + 16 * i + 8, 0);
 499                 cx_write(cdt + 16 * i + 12, 0);
 500         }
 501
 502         /* init the first cdt buffer */
 503         for (i = 0; i < 128; i++)
 504                 cx_write(ch->fifo_start + 4 * i, i);
 505
 506         /* write CMDS */
 507         if (ch->jumponly)
 508                 cx_write(ch->cmds_start + 0, 8);
 509         else
 510                 cx_write(ch->cmds_start + 0, risc);
 511
 512         cx_write(ch->cmds_start + 4, 0);        /* 64 bits 63-32 */
 513         cx_write(ch->cmds_start + 8, cdt);
 514         cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
 515         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 516
 517         if (ch->jumponly)
 518                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
 519         else
 520                 cx_write(ch->cmds_start + 20, 64 >> 2);
 521
 522         for (i = 24; i < 80; i += 4)
 523                 cx_write(ch->cmds_start + i, 0);
 524
 525         /* fill registers */
 526         cx_write(ch->ptr1_reg, ch->fifo_start);
 527         cx_write(ch->ptr2_reg, cdt);
 528         cx_write(ch->cnt2_reg, (lines * 16) >> 3);
 529         cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
 530
 531         return 0;
 532 }
 533 EXPORT_SYMBOL(cx25821_sram_channel_setup);
 534
 535 int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
 536                                      struct sram_channel *ch,
 537                                      unsigned int bpl, u32 risc)
 538 {
 539         unsigned int i, lines;
 540         u32 cdt;
 541
 542         if (ch->cmds_start == 0) {
 543                 cx_write(ch->ptr1_reg, 0);
 544                 cx_write(ch->ptr2_reg, 0);
 545                 cx_write(ch->cnt2_reg, 0);
 546                 cx_write(ch->cnt1_reg, 0);
 547                 return 0;
 548         }
 549
 550         bpl = (bpl + 7) & ~7;   /* alignment */
 551         cdt = ch->cdt;
 552         lines = ch->fifo_size / bpl;
 553
 554         if (lines > 3)
 555                 lines = 3;      /* for AUDIO */
 556
 557         BUG_ON(lines < 2);
 558
 559         cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
 560         cx_write(8 + 4, 8);
 561         cx_write(8 + 8, 0);
 562
 563         /* write CDT */
 564         for (i = 0; i < lines; i++) {
 565                 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
 566                 cx_write(cdt + 16 * i + 4, 0);
 567                 cx_write(cdt + 16 * i + 8, 0);
 568                 cx_write(cdt + 16 * i + 12, 0);
 569         }
 570
 571         /* write CMDS */
 572         if (ch->jumponly)
 573                 cx_write(ch->cmds_start + 0, 8);
 574         else
 575                 cx_write(ch->cmds_start + 0, risc);
 576
 577         cx_write(ch->cmds_start + 4, 0);        /* 64 bits 63-32 */
 578         cx_write(ch->cmds_start + 8, cdt);
 579         cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
 580         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 581
 582         /* IQ size */
 583         if (ch->jumponly)
 584                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
 585         else
 586                 cx_write(ch->cmds_start + 20, 64 >> 2);
 587
 588         /* zero out */
 589         for (i = 24; i < 80; i += 4)
 590                 cx_write(ch->cmds_start + i, 0);
 591
 592         /* fill registers */
 593         cx_write(ch->ptr1_reg, ch->fifo_start);
 594         cx_write(ch->ptr2_reg, cdt);
 595         cx_write(ch->cnt2_reg, (lines * 16) >> 3);
 596         cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
 597
 598         return 0;
 599 }
 600 EXPORT_SYMBOL(cx25821_sram_channel_setup_audio);
 601
 602 void cx25821_sram_channel_dump(struct cx25821_dev *dev, struct sram_channel *ch)
 603 {
 604         static char *name[] = {
 605                 "init risc lo",
 606                 "init risc hi",
 607                 "cdt base",
 608                 "cdt size",
 609                 "iq base",
 610                 "iq size",
 611                 "risc pc lo",
 612                 "risc pc hi",
 613                 "iq wr ptr",
 614                 "iq rd ptr",
 615                 "cdt current",
 616                 "pci target lo",
 617                 "pci target hi",
 618                 "line / byte",
 619         };
 620         u32 risc;
 621         unsigned int i, j, n;
 622
 623         printk(KERN_WARNING "%s: %s - dma channel status dump\n", dev->name,
 624                ch->name);
 625         for (i = 0; i < ARRAY_SIZE(name); i++)
 626                 printk(KERN_WARNING "cmds + 0x%2x:   %-15s: 0x%08x\n", i * 4,
 627                        name[i], cx_read(ch->cmds_start + 4 * i));
 628
 629         j = i * 4;
 630         for (i = 0; i < 4;) {
 631                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
 632                 printk(KERN_WARNING "cmds + 0x%2x:   risc%d: ", j + i * 4, i);
 633                 i += cx25821_risc_decode(risc);
 634         }
 635
 636         for (i = 0; i < (64 >> 2); i += n) {
 637                 risc = cx_read(ch->ctrl_start + 4 * i);
 638                 /* No consideration for bits 63-32 */
 639
 640                 printk(KERN_WARNING "ctrl + 0x%2x (0x%08x): iq %x: ", i * 4,
 641                        ch->ctrl_start + 4 * i, i);
 642                 n = cx25821_risc_decode(risc);
 643                 for (j = 1; j < n; j++) {
 644                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
 645                         printk(KERN_WARNING
 646                                "ctrl + 0x%2x :   iq %x: 0x%08x [ arg #%d ]\n",
 647                                4 * (i + j), i + j, risc, j);
 648                 }
 649         }
 650
 651         printk(KERN_WARNING "        :   fifo: 0x%08x -> 0x%x\n",
 652                ch->fifo_start, ch->fifo_start + ch->fifo_size);
 653         printk(KERN_WARNING "        :   ctrl: 0x%08x -> 0x%x\n",
 654                ch->ctrl_start, ch->ctrl_start + 6 * 16);
 655         printk(KERN_WARNING "        :   ptr1_reg: 0x%08x\n",
 656                cx_read(ch->ptr1_reg));
 657         printk(KERN_WARNING "        :   ptr2_reg: 0x%08x\n",
 658                cx_read(ch->ptr2_reg));
 659         printk(KERN_WARNING "        :   cnt1_reg: 0x%08x\n",
 660                cx_read(ch->cnt1_reg));
 661         printk(KERN_WARNING "        :   cnt2_reg: 0x%08x\n",
 662                cx_read(ch->cnt2_reg));
 663 }
 664 EXPORT_SYMBOL(cx25821_sram_channel_dump);
 665
 666 void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
 667                                      struct sram_channel *ch)
 668 {
 669         static char *name[] = {
 670                 "init risc lo",
 671                 "init risc hi",
 672                 "cdt base",
 673                 "cdt size",
 674                 "iq base",
 675                 "iq size",
 676                 "risc pc lo",
 677                 "risc pc hi",
 678                 "iq wr ptr",
 679                 "iq rd ptr",
 680                 "cdt current",
 681                 "pci target lo",
 682                 "pci target hi",
 683                 "line / byte",
 684         };
 685
 686         u32 risc, value, tmp;
 687         unsigned int i, j, n;
 688
 689         printk(KERN_INFO "\n%s: %s - dma Audio channel status dump\n",
 690                dev->name, ch->name);
 691
 692         for (i = 0; i < ARRAY_SIZE(name); i++)
 693                 printk(KERN_INFO "%s: cmds + 0x%2x:   %-15s: 0x%08x\n",
 694                        dev->name, i * 4, name[i],
 695                        cx_read(ch->cmds_start + 4 * i));
 696
 697         j = i * 4;
 698         for (i = 0; i < 4;) {
 699                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
 700                 printk(KERN_WARNING "cmds + 0x%2x:   risc%d: ", j + i * 4, i);
 701                 i += cx25821_risc_decode(risc);
 702         }
 703
 704         for (i = 0; i < (64 >> 2); i += n) {
 705                 risc = cx_read(ch->ctrl_start + 4 * i);
 706                 /* No consideration for bits 63-32 */
 707
 708                 printk(KERN_WARNING "ctrl + 0x%2x (0x%08x): iq %x: ", i * 4,
 709                        ch->ctrl_start + 4 * i, i);
 710                 n = cx25821_risc_decode(risc);
 711
 712                 for (j = 1; j < n; j++) {
 713                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
 714                         printk(KERN_WARNING
 715                                "ctrl + 0x%2x :   iq %x: 0x%08x [ arg #%d ]\n",
 716                                4 * (i + j), i + j, risc, j);
 717                 }
 718         }
 719
 720         printk(KERN_WARNING "        :   fifo: 0x%08x -> 0x%x\n",
 721                ch->fifo_start, ch->fifo_start + ch->fifo_size);
 722         printk(KERN_WARNING "        :   ctrl: 0x%08x -> 0x%x\n",
 723                ch->ctrl_start, ch->ctrl_start + 6 * 16);
 724         printk(KERN_WARNING "        :   ptr1_reg: 0x%08x\n",
 725                cx_read(ch->ptr1_reg));
 726         printk(KERN_WARNING "        :   ptr2_reg: 0x%08x\n",
 727                cx_read(ch->ptr2_reg));
 728         printk(KERN_WARNING "        :   cnt1_reg: 0x%08x\n",
 729                cx_read(ch->cnt1_reg));
 730         printk(KERN_WARNING "        :   cnt2_reg: 0x%08x\n",
 731                cx_read(ch->cnt2_reg));
 732
 733         for (i = 0; i < 4; i++) {
 734                 risc = cx_read(ch->cmds_start + 56 + (i * 4));
 735                 printk(KERN_WARNING "instruction %d = 0x%x\n", i, risc);
 736         }
 737
 738         /* read data from the first cdt buffer */
 739         risc = cx_read(AUD_A_CDT);
 740         printk(KERN_WARNING "\nread cdt loc=0x%x\n", risc);
 741         for (i = 0; i < 8; i++) {
 742                 n = cx_read(risc + i * 4);
 743                 printk(KERN_WARNING "0x%x ", n);
 744         }
 745         printk(KERN_WARNING "\n\n");
 746
 747         value = cx_read(CLK_RST);
 748         CX25821_INFO(" CLK_RST = 0x%x\n\n", value);
 749
 750         value = cx_read(PLL_A_POST_STAT_BIST);
 751         CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x\n\n", value);
 752         value = cx_read(PLL_A_INT_FRAC);
 753         CX25821_INFO(" PLL_A_INT_FRAC = 0x%x\n\n", value);
 754
 755         value = cx_read(PLL_B_POST_STAT_BIST);
 756         CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x\n\n", value);
 757         value = cx_read(PLL_B_INT_FRAC);
 758         CX25821_INFO(" PLL_B_INT_FRAC = 0x%x\n\n", value);
 759
 760         value = cx_read(PLL_C_POST_STAT_BIST);
 761         CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x\n\n", value);
 762         value = cx_read(PLL_C_INT_FRAC);
 763         CX25821_INFO(" PLL_C_INT_FRAC = 0x%x\n\n", value);
 764
 765         value = cx_read(PLL_D_POST_STAT_BIST);
 766         CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x\n\n", value);
 767         value = cx_read(PLL_D_INT_FRAC);
 768         CX25821_INFO(" PLL_D_INT_FRAC = 0x%x\n\n", value);
 769
 770         value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
 771         CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x\n\n", value);
 772 }
 773 EXPORT_SYMBOL(cx25821_sram_channel_dump_audio);
 774
 775 static void cx25821_shutdown(struct cx25821_dev *dev)
 776 {
 777         int i;
 778
 779         /* disable RISC controller */
 780         cx_write(DEV_CNTRL2, 0);
 781
 782         /* Disable Video A/B activity */
 783         for (i = 0; i < VID_CHANNEL_NUM; i++) {
 784                 cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
 785                 cx_write(dev->channels[i].sram_channels->int_msk, 0);
 786         }
 787
 788         for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
 789                 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
 790                 cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
 791                 cx_write(dev->channels[i].sram_channels->int_msk, 0);
 792         }
 793
 794         /* Disable Audio activity */
 795         cx_write(AUD_INT_DMA_CTL, 0);
 796
 797         /* Disable Serial port */
 798         cx_write(UART_CTL, 0);
 799
 800         /* Disable Interrupts */
 801         cx_write(PCI_INT_MSK, 0);
 802         cx_write(AUD_A_INT_MSK, 0);
 803 }
 804
 805 void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel_select,
 806                               u32 format)
 807 {
 808         if (channel_select <= 7 && channel_select >= 0) {
 809                 cx_write(dev->channels[channel_select].
 810                         sram_channels->pix_frmt, format);
 811                 dev->channels[channel_select].pixel_formats = format;
 812         }
 813 }
 814
 815 static void cx25821_set_vip_mode(struct cx25821_dev *dev,
 816                                  struct sram_channel *ch)
 817 {
 818         cx_write(ch->pix_frmt, PIXEL_FRMT_422);
 819         cx_write(ch->vip_ctl, PIXEL_ENGINE_VIP1);
 820 }
 821
 822 static void cx25821_initialize(struct cx25821_dev *dev)
 823 {
 824         int i;
 825
 826         dprintk(1, "%s()\n", __func__);
 827
 828         cx25821_shutdown(dev);
 829         cx_write(PCI_INT_STAT, 0xffffffff);
 830
 831         for (i = 0; i < VID_CHANNEL_NUM; i++)
 832                 cx_write(dev->channels[i].sram_channels->int_stat, 0xffffffff);
 833
 834         cx_write(AUD_A_INT_STAT, 0xffffffff);
 835         cx_write(AUD_B_INT_STAT, 0xffffffff);
 836         cx_write(AUD_C_INT_STAT, 0xffffffff);
 837         cx_write(AUD_D_INT_STAT, 0xffffffff);
 838         cx_write(AUD_E_INT_STAT, 0xffffffff);
 839
 840         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
 841         cx_write(PAD_CTRL, 0x12);       /* for I2C */
 842         cx25821_registers_init(dev);    /* init Pecos registers */
 843         mdelay(100);
 844
 845         for (i = 0; i < VID_CHANNEL_NUM; i++) {
 846                 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
 847                 cx25821_sram_channel_setup(dev, dev->channels[i].sram_channels,
 848                                                 1440, 0);
 849                 dev->channels[i].pixel_formats = PIXEL_FRMT_422;
 850                 dev->channels[i].use_cif_resolution = FALSE;
 851         }
 852
 853         /* Probably only affect Downstream */
 854         for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
 855                 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
 856                 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
 857         }
 858
 859         cx25821_sram_channel_setup_audio(dev,
 860                                 dev->channels[SRAM_CH08].sram_channels,
 861                                 128, 0);
 862
 863         cx25821_gpio_init(dev);
 864 }
 865
 866 static int cx25821_get_resources(struct cx25821_dev *dev)
 867 {
 868         if (request_mem_region
 869             (pci_resource_start(dev->pci, 0), pci_resource_len(dev->pci, 0),
 870              dev->name))
 871                 return 0;
 872
 873         printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
 874                dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
 875
 876         return -EBUSY;
 877 }
 878
 879 static void cx25821_dev_checkrevision(struct cx25821_dev *dev)
 880 {
 881         dev->hwrevision = cx_read(RDR_CFG2) & 0xff;
 882
 883         printk(KERN_INFO "%s() Hardware revision = 0x%02x\n", __func__,
 884                dev->hwrevision);
 885 }
 886
 887 static void cx25821_iounmap(struct cx25821_dev *dev)
 888 {
 889         if (dev == NULL)
 890                 return;
 891
 892         /* Releasing IO memory */
 893         if (dev->lmmio != NULL) {
 894                 CX25821_INFO("Releasing lmmio.\n");
 895                 iounmap(dev->lmmio);
 896                 dev->lmmio = NULL;
 897         }
 898 }
 899
 900 static int cx25821_dev_setup(struct cx25821_dev *dev)
 901 {
 902         int io_size = 0, i;
 903
 904         printk(KERN_INFO "\n***********************************\n");
 905         printk(KERN_INFO "cx25821 set up\n");
 906         printk(KERN_INFO "***********************************\n\n");
 907
 908         mutex_init(&dev->lock);
 909
 910         atomic_inc(&dev->refcount);
 911
 912         dev->nr = ++cx25821_devcount;
 913         sprintf(dev->name, "cx25821[%d]", dev->nr);
 914
 915         mutex_lock(&devlist);
 916         list_add_tail(&dev->devlist, &cx25821_devlist);
 917         mutex_unlock(&devlist);
 918
 919         strcpy(cx25821_boards[UNKNOWN_BOARD].name, "unknown");
 920         strcpy(cx25821_boards[CX25821_BOARD].name, "cx25821");
 921
 922         if (dev->pci->device != 0x8210) {
 923                 printk(KERN_INFO
 924                        "%s() Exiting. Incorrect Hardware device = 0x%02x\n",
 925                        __func__, dev->pci->device);
 926                 return -1;
 927         } else {
 928                 printk(KERN_INFO "Athena Hardware device = 0x%02x\n",
 929                        dev->pci->device);
 930         }
 931
 932         /* Apply a sensible clock frequency for the PCIe bridge */
 933         dev->clk_freq = 28000000;
 934         for (i = 0; i < MAX_VID_CHANNEL_NUM; i++)
 935                 dev->channels[i].sram_channels = &cx25821_sram_channels[i];
 936
 937         if (dev->nr > 1)
 938                 CX25821_INFO("dev->nr > 1!");
 939
 940         /* board config */
 941         dev->board = 1;         /* card[dev->nr]; */
 942         dev->_max_num_decoders = MAX_DECODERS;
 943
 944         dev->pci_bus = dev->pci->bus->number;
 945         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
 946         dev->pci_irqmask = 0x001f00;
 947
 948         /* External Master 1 Bus */
 949         dev->i2c_bus[0].nr = 0;
 950         dev->i2c_bus[0].dev = dev;
 951         dev->i2c_bus[0].reg_stat = I2C1_STAT;
 952         dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
 953         dev->i2c_bus[0].reg_addr = I2C1_ADDR;
 954         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
 955         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
 956         dev->i2c_bus[0].i2c_period = (0x07 << 24);      /* 1.95MHz */
 957
 958         if (cx25821_get_resources(dev) < 0) {
 959                 printk(KERN_ERR "%s No more PCIe resources for "
 960                        "subsystem: %04x:%04x\n",
 961                        dev->name, dev->pci->subsystem_vendor,
 962                        dev->pci->subsystem_device);
 963
 964                 cx25821_devcount--;
 965                 return -EBUSY;
 966         }
 967
 968         /* PCIe stuff */
 969         dev->base_io_addr = pci_resource_start(dev->pci, 0);
 970         io_size = pci_resource_len(dev->pci, 0);
 971
 972         if (!dev->base_io_addr) {
 973                 CX25821_ERR("No PCI Memory resources, exiting!\n");
 974                 return -ENODEV;
 975         }
 976
 977         dev->lmmio = ioremap(dev->base_io_addr, pci_resource_len(dev->pci, 0));
 978
 979         if (!dev->lmmio) {
 980                 CX25821_ERR
 981                     ("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n");
 982                 cx25821_iounmap(dev);
 983                 return -ENOMEM;
 984         }
 985
 986         dev->bmmio = (u8 __iomem *) dev->lmmio;
 987
 988         printk(KERN_INFO "%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
 989                dev->name, dev->pci->subsystem_vendor,
 990                dev->pci->subsystem_device, cx25821_boards[dev->board].name,
 991                dev->board, card[dev->nr] == dev->board ?
 992                "insmod option" : "autodetected");
 993
 994         /* init hardware */
 995         cx25821_initialize(dev);
 996
 997         cx25821_i2c_register(&dev->i2c_bus[0]);
 998 /*  cx25821_i2c_register(&dev->i2c_bus[1]);
 999  *  cx25821_i2c_register(&dev->i2c_bus[2]); */
1000
1001         CX25821_INFO("i2c register! bus->i2c_rc = %d\n",
1002                      dev->i2c_bus[0].i2c_rc);
1003
1004         cx25821_card_setup(dev);
1005
1006         if (medusa_video_init(dev) < 0)
1007                 CX25821_ERR("%s() Failed to initialize medusa!\n"
1008                 , __func__);
1009
1010         cx25821_video_register(dev);
1011
1012         /* register IOCTL device */
1013         dev->ioctl_dev =
1014            cx25821_vdev_init(dev, dev->pci, &cx25821_videoioctl_template,
1015                               "video");
1016
1017         if (video_register_device
1018             (dev->ioctl_dev, VFL_TYPE_GRABBER, VIDEO_IOCTL_CH) < 0) {
1019                 cx25821_videoioctl_unregister(dev);
1020                 printk(KERN_ERR
1021                    "%s() Failed to register video adapter for IOCTL, so \
1022                    unregistering videoioctl device.\n", __func__);
1023         }
1024
1025         cx25821_dev_checkrevision(dev);
1026         CX25821_INFO("cx25821 setup done!\n");
1027
1028         return 0;
1029 }
1030
1031 void cx25821_start_upstream_video_ch1(struct cx25821_dev *dev,
1032                                       struct upstream_user_struct *up_data)
1033 {
1034         dev->_isNTSC = !strcmp(dev->vid_stdname, "NTSC") ? 1 : 0;
1035
1036         dev->tvnorm = !dev->_isNTSC ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
1037         medusa_set_videostandard(dev);
1038
1039         cx25821_vidupstream_init_ch1(dev, dev->channel_select,
1040                                      dev->pixel_format);
1041 }
1042
1043 void cx25821_start_upstream_video_ch2(struct cx25821_dev *dev,
1044                                       struct upstream_user_struct *up_data)
1045 {
1046         dev->_isNTSC_ch2 = !strcmp(dev->vid_stdname_ch2, "NTSC") ? 1 : 0;
1047
1048         dev->tvnorm = !dev->_isNTSC_ch2 ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
1049         medusa_set_videostandard(dev);
1050
1051         cx25821_vidupstream_init_ch2(dev, dev->channel_select_ch2,
1052                                      dev->pixel_format_ch2);
1053 }
1054
1055 void cx25821_start_upstream_audio(struct cx25821_dev *dev,
1056                                   struct upstream_user_struct *up_data)
1057 {
1058         cx25821_audio_upstream_init(dev, AUDIO_UPSTREAM_SRAM_CHANNEL_B);
1059 }
1060
1061 void cx25821_dev_unregister(struct cx25821_dev *dev)
1062 {
1063         int i;
1064
1065         if (!dev->base_io_addr)
1066                 return;
1067
1068         cx25821_free_mem_upstream_ch1(dev);
1069         cx25821_free_mem_upstream_ch2(dev);
1070         cx25821_free_mem_upstream_audio(dev);
1071
1072         release_mem_region(dev->base_io_addr, pci_resource_len(dev->pci, 0));
1073
1074         if (!atomic_dec_and_test(&dev->refcount))
1075                 return;
1076
1077         for (i = 0; i < VID_CHANNEL_NUM; i++)
1078                 cx25821_video_unregister(dev, i);
1079
1080         for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
1081              i <= AUDIO_UPSTREAM_SRAM_CHANNEL_B; i++) {
1082                 cx25821_video_unregister(dev, i);
1083         }
1084
1085         cx25821_videoioctl_unregister(dev);
1086
1087         cx25821_i2c_unregister(&dev->i2c_bus[0]);
1088         cx25821_iounmap(dev);
1089 }
1090 EXPORT_SYMBOL(cx25821_dev_unregister);
1091
1092 static __le32 *cx25821_risc_field(__le32 * rp, struct scatterlist *sglist,
1093                                   unsigned int offset, u32 sync_line,
1094                                   unsigned int bpl, unsigned int padding,
1095                                   unsigned int lines)
1096 {
1097         struct scatterlist *sg;
1098         unsigned int line, todo;
1099
1100         /* sync instruction */
1101         if (sync_line != NO_SYNC_LINE)
1102                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1103
1104         /* scan lines */
1105         sg = sglist;
1106         for (line = 0; line < lines; line++) {
1107                 while (offset && offset >= sg_dma_len(sg)) {
1108                         offset -= sg_dma_len(sg);
1109                         sg++;
1110                 }
1111                 if (bpl <= sg_dma_len(sg) - offset) {
1112                         /* fits into current chunk */
1113                         *(rp++) =
1114                             cpu_to_le32(RISC_WRITE | RISC_SOL | RISC_EOL | bpl);
1115                         *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1116                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1117                         offset += bpl;
1118                 } else {
1119                         /* scanline needs to be split */
1120                         todo = bpl;
1121                         *(rp++) =
1122                             cpu_to_le32(RISC_WRITE | RISC_SOL |
1123                                         (sg_dma_len(sg) - offset));
1124                         *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1125                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1126                         todo -= (sg_dma_len(sg) - offset);
1127                         offset = 0;
1128                         sg++;
1129                         while (todo > sg_dma_len(sg)) {
1130                                 *(rp++) =
1131                                     cpu_to_le32(RISC_WRITE | sg_dma_len(sg));
1132                                 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1133                                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1134                                 todo -= sg_dma_len(sg);
1135                                 sg++;
1136                         }
1137                         *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1138                         *(rp++) = cpu_to_le32(sg_dma_address(sg));
1139                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1140                         offset += todo;
1141                 }
1142
1143                 offset += padding;
1144         }
1145
1146         return rp;
1147 }
1148
1149 int cx25821_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
1150                         struct scatterlist *sglist, unsigned int top_offset,
1151                         unsigned int bottom_offset, unsigned int bpl,
1152                         unsigned int padding, unsigned int lines)
1153 {
1154         u32 instructions;
1155         u32 fields;
1156         __le32 *rp;
1157         int rc;
1158
1159         fields = 0;
1160         if (UNSET != top_offset)
1161                 fields++;
1162         if (UNSET != bottom_offset)
1163                 fields++;
1164
1165         /* estimate risc mem: worst case is one write per page border +
1166            one write per scan line + syncs + jump (all 2 dwords).  Padding
1167            can cause next bpl to start close to a page border.  First DMA
1168            region may be smaller than PAGE_SIZE */
1169         /* write and jump need and extra dword */
1170         instructions =
1171             fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
1172         instructions += 2;
1173         rc = btcx_riscmem_alloc(pci, risc, instructions * 12);
1174
1175         if (rc < 0)
1176                 return rc;
1177
1178         /* write risc instructions */
1179         rp = risc->cpu;
1180
1181         if (UNSET != top_offset) {
1182                 rp = cx25821_risc_field(rp, sglist, top_offset, 0, bpl, padding,
1183                                         lines);
1184         }
1185
1186         if (UNSET != bottom_offset) {
1187                 rp = cx25821_risc_field(rp, sglist, bottom_offset, 0x200, bpl,
1188                                         padding, lines);
1189         }
1190
1191         /* save pointer to jmp instruction address */
1192         risc->jmp = rp;
1193         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1194
1195         return 0;
1196 }
1197
1198 static __le32 *cx25821_risc_field_audio(__le32 * rp, struct scatterlist *sglist,
1199                                         unsigned int offset, u32 sync_line,
1200                                         unsigned int bpl, unsigned int padding,
1201                                         unsigned int lines, unsigned int lpi)
1202 {
1203         struct scatterlist *sg;
1204         unsigned int line, todo, sol;
1205
1206         /* sync instruction */
1207         if (sync_line != NO_SYNC_LINE)
1208                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1209
1210         /* scan lines */
1211         sg = sglist;
1212         for (line = 0; line < lines; line++) {
1213                 while (offset && offset >= sg_dma_len(sg)) {
1214                         offset -= sg_dma_len(sg);
1215                         sg++;
1216                 }
1217
1218                 if (lpi && line > 0 && !(line % lpi))
1219                         sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
1220                 else
1221                         sol = RISC_SOL;
1222
1223                 if (bpl <= sg_dma_len(sg) - offset) {
1224                         /* fits into current chunk */
1225                         *(rp++) =
1226                             cpu_to_le32(RISC_WRITE | sol | RISC_EOL | bpl);
1227                         *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1228                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1229                         offset += bpl;
1230                 } else {
1231                         /* scanline needs to be split */
1232                         todo = bpl;
1233                         *(rp++) = cpu_to_le32(RISC_WRITE | sol |
1234                                               (sg_dma_len(sg) - offset));
1235                         *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1236                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1237                         todo -= (sg_dma_len(sg) - offset);
1238                         offset = 0;
1239                         sg++;
1240                         while (todo > sg_dma_len(sg)) {
1241                                 *(rp++) = cpu_to_le32(RISC_WRITE |
1242                                                       sg_dma_len(sg));
1243                                 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1244                                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1245                                 todo -= sg_dma_len(sg);
1246                                 sg++;
1247                         }
1248                         *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1249                         *(rp++) = cpu_to_le32(sg_dma_address(sg));
1250                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1251                         offset += todo;
1252                 }
1253                 offset += padding;
1254         }
1255
1256         return rp;
1257 }
1258
1259 int cx25821_risc_databuffer_audio(struct pci_dev *pci,
1260                                   struct btcx_riscmem *risc,
1261                                   struct scatterlist *sglist,
1262                                   unsigned int bpl,
1263                                   unsigned int lines, unsigned int lpi)
1264 {
1265         u32 instructions;
1266         __le32 *rp;
1267         int rc;
1268
1269         /* estimate risc mem: worst case is one write per page border +
1270            one write per scan line + syncs + jump (all 2 dwords).  Here
1271            there is no padding and no sync.  First DMA region may be smaller
1272            than PAGE_SIZE */
1273         /* Jump and write need an extra dword */
1274         instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
1275         instructions += 1;
1276
1277         rc = btcx_riscmem_alloc(pci, risc, instructions * 12);
1278         if (rc < 0)
1279                 return rc;
1280
1281         /* write risc instructions */
1282         rp = risc->cpu;
1283         rp = cx25821_risc_field_audio(rp, sglist, 0, NO_SYNC_LINE, bpl, 0,
1284                                       lines, lpi);
1285
1286         /* save pointer to jmp instruction address */
1287         risc->jmp = rp;
1288         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1289         return 0;
1290 }
1291 EXPORT_SYMBOL(cx25821_risc_databuffer_audio);
1292
1293 int cx25821_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1294                          u32 reg, u32 mask, u32 value)
1295 {
1296         __le32 *rp;
1297         int rc;
1298
1299         rc = btcx_riscmem_alloc(pci, risc, 4 * 16);
1300
1301         if (rc < 0)
1302                 return rc;
1303
1304         /* write risc instructions */
1305         rp = risc->cpu;
1306
1307         *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ1);
1308         *(rp++) = cpu_to_le32(reg);
1309         *(rp++) = cpu_to_le32(value);
1310         *(rp++) = cpu_to_le32(mask);
1311         *(rp++) = cpu_to_le32(RISC_JUMP);
1312         *(rp++) = cpu_to_le32(risc->dma);
1313         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1314         return 0;
1315 }
1316
1317 void cx25821_free_buffer(struct videobuf_queue *q, struct cx25821_buffer *buf)
1318 {
1319         struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1320
1321         BUG_ON(in_interrupt());
1322         videobuf_waiton(q, &buf->vb, 0, 0);
1323         videobuf_dma_unmap(q->dev, dma);
1324         videobuf_dma_free(dma);
1325         btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
1326         buf->vb.state = VIDEOBUF_NEEDS_INIT;
1327 }
1328
1329 static irqreturn_t cx25821_irq(int irq, void *dev_id)
1330 {
1331         struct cx25821_dev *dev = dev_id;
1332         u32 pci_status, pci_mask;
1333         u32 vid_status;
1334         int i, handled = 0;
1335         u32 mask[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
1336
1337         pci_status = cx_read(PCI_INT_STAT);
1338         pci_mask = cx_read(PCI_INT_MSK);
1339
1340         if (pci_status == 0)
1341                 goto out;
1342
1343         for (i = 0; i < VID_CHANNEL_NUM; i++) {
1344                 if (pci_status & mask[i]) {
1345                         vid_status = cx_read(dev->channels[i].
1346                                 sram_channels->int_stat);
1347
1348                         if (vid_status)
1349                                 handled +=
1350                                 cx25821_video_irq(dev, i, vid_status);
1351
1352                         cx_write(PCI_INT_STAT, mask[i]);
1353                 }
1354         }
1355
1356 out:
1357         return IRQ_RETVAL(handled);
1358 }
1359
1360 void cx25821_print_irqbits(char *name, char *tag, char **strings,
1361                            int len, u32 bits, u32 mask)
1362 {
1363         unsigned int i;
1364
1365         printk(KERN_DEBUG "%s: %s [0x%x]", name, tag, bits);
1366
1367         for (i = 0; i < len; i++) {
1368                 if (!(bits & (1 << i)))
1369                         continue;
1370                 if (strings[i])
1371                         printk(" %s", strings[i]);
1372                 else
1373                         printk(" %d", i);
1374                 if (!(mask & (1 << i)))
1375                         continue;
1376                 printk("*");
1377         }
1378         printk("\n");
1379 }
1380 EXPORT_SYMBOL(cx25821_print_irqbits);
1381
1382 struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci)
1383 {
1384         struct cx25821_dev *dev = pci_get_drvdata(pci);
1385         return dev;
1386 }
1387 EXPORT_SYMBOL(cx25821_dev_get);
1388
1389 static int __devinit cx25821_initdev(struct pci_dev *pci_dev,
1390                                      const struct pci_device_id *pci_id)
1391 {
1392         struct cx25821_dev *dev;
1393         int err = 0;
1394
1395         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1396         if (NULL == dev)
1397                 return -ENOMEM;
1398
1399         err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
1400         if (err < 0)
1401                 goto fail_free;
1402
1403         /* pci init */
1404         dev->pci = pci_dev;
1405         if (pci_enable_device(pci_dev)) {
1406                 err = -EIO;
1407
1408                 printk(KERN_INFO "pci enable failed! ");
1409
1410                 goto fail_unregister_device;
1411         }
1412
1413         printk(KERN_INFO "cx25821 Athena pci enable !\n");
1414
1415         err = cx25821_dev_setup(dev);
1416         if (err) {
1417                 if (err == -EBUSY)
1418                         goto fail_unregister_device;
1419                 else
1420                         goto fail_unregister_pci;
1421         }
1422
1423         /* print pci info */
1424         pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1425         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1426         printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1427                "latency: %d, mmio: 0x%llx\n", dev->name,
1428                pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1429                dev->pci_lat, (unsigned long long)dev->base_io_addr);
1430
1431         pci_set_master(pci_dev);
1432         if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1433                 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1434                 err = -EIO;
1435                 goto fail_irq;
1436         }
1437
1438         err =
1439             request_irq(pci_dev->irq, cx25821_irq, IRQF_SHARED | IRQF_DISABLED,
1440                         dev->name, dev);
1441
1442         if (err < 0) {
1443                 printk(KERN_ERR "%s: can't get IRQ %d\n", dev->name,
1444                        pci_dev->irq);
1445                 goto fail_irq;
1446         }
1447
1448         return 0;
1449
1450 fail_irq:
1451         printk(KERN_INFO "cx25821 cx25821_initdev() can't get IRQ !\n");
1452         cx25821_dev_unregister(dev);
1453
1454 fail_unregister_pci:
1455         pci_disable_device(pci_dev);
1456 fail_unregister_device:
1457         v4l2_device_unregister(&dev->v4l2_dev);
1458
1459 fail_free:
1460         kfree(dev);
1461         return err;
1462 }
1463
1464 static void __devexit cx25821_finidev(struct pci_dev *pci_dev)
1465 {
1466         struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
1467         struct cx25821_dev *dev = get_cx25821(v4l2_dev);
1468
1469         cx25821_shutdown(dev);
1470         pci_disable_device(pci_dev);
1471
1472         /* unregister stuff */
1473         if (pci_dev->irq)
1474                 free_irq(pci_dev->irq, dev);
1475
1476         mutex_lock(&devlist);
1477         list_del(&dev->devlist);
1478         mutex_unlock(&devlist);
1479
1480         cx25821_dev_unregister(dev);
1481         v4l2_device_unregister(v4l2_dev);
1482         kfree(dev);
1483 }
1484
1485 static struct pci_device_id cx25821_pci_tbl[] = {
1486         {
1487          /* CX25821 Athena */
1488          .vendor = 0x14f1,
1489          .device = 0x8210,
1490          .subvendor = 0x14f1,
1491          .subdevice = 0x0920,
1492          },
1493         {
1494          /* --- end of list --- */
1495          }
1496 };
1497
1498 MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl);
1499
1500 static struct pci_driver cx25821_pci_driver = {
1501         .name = "cx25821",
1502         .id_table = cx25821_pci_tbl,
1503         .probe = cx25821_initdev,
1504         .remove = __devexit_p(cx25821_finidev),
1505         /* TODO */
1506         .suspend = NULL,
1507         .resume = NULL,
1508 };
1509
1510 static int __init cx25821_init(void)
1511 {
1512         INIT_LIST_HEAD(&cx25821_devlist);
1513         printk(KERN_INFO "cx25821 driver version %d.%d.%d loaded\n",
1514                (CX25821_VERSION_CODE >> 16) & 0xff,
1515                (CX25821_VERSION_CODE >> 8) & 0xff, CX25821_VERSION_CODE & 0xff);
1516         return pci_register_driver(&cx25821_pci_driver);
1517 }
1518
1519 static void __exit cx25821_fini(void)
1520 {
1521         pci_unregister_driver(&cx25821_pci_driver);
1522 }
1523
1524 EXPORT_SYMBOL(cx25821_set_gpiopin_direction);
1525
1526 module_init(cx25821_init);
1527 module_exit(cx25821_fini);