drivers/staging/comedi/drivers/ni_pcimio.c

   1 /*
   2     comedi/drivers/ni_pcimio.c
   3     Hardware driver for NI PCI-MIO E series cards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21 */
  22 /*
  23 Driver: ni_pcimio
  24 Description: National Instruments PCI-MIO-E series and M series (all boards)
  25 Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
  26   Herman Bruyninckx, Terry Barnaby
  27 Status: works
  28 Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
  29   PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
  30   PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
  31   PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
  32   PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224, PCI-6225, PXI-6225,
  33   PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PCI-6254, PCI-6259, PCIe-6259,
  34   PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
  35   PCI-6711, PXI-6711, PCI-6713, PXI-6713,
  36   PXI-6071E, PCI-6070E, PXI-6070E,
  37   PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
  38   PCI-6143, PXI-6143
  39 Updated: Wed, 03 Dec 2008 10:51:47 +0000
  40
  41 These boards are almost identical to the AT-MIO E series, except that
  42 they use the PCI bus instead of ISA (i.e., AT).  See the notes for
  43 the ni_atmio.o driver for additional information about these boards.
  44
  45 Autocalibration is supported on many of the devices, using the
  46 comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
  47 M-Series boards do analog input and analog output calibration entirely
  48 in software. The software calibration corrects
  49 the analog input for offset, gain and
  50 nonlinearity.  The analog outputs are corrected for offset and gain.
  51 See the comedilib documentation on comedi_get_softcal_converter() for
  52 more information.
  53
  54 By default, the driver uses DMA to transfer analog input data to
  55 memory.  When DMA is enabled, not all triggering features are
  56 supported.
  57
  58 Digital I/O may not work on 673x.
  59
  60 Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
  61 With this board all of the convertors perform one simultaineous sample during
  62 a scan interval. The period for a scan is used for the convert time in a
  63 Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
  64
  65 The RTSI trigger bus is supported on these cards on
  66 subdevice 10. See the comedilib documentation for details.
  67
  68 Information (number of channels, bits, etc.) for some devices may be
  69 incorrect.  Please check this and submit a bug if there are problems
  70 for your device.
  71
  72 SCXI is probably broken for m-series boards.
  73
  74 Bugs:
  75  - When DMA is enabled, COMEDI_EV_CONVERT does
  76    not work correctly.
  77
  78 */
  79 /*
  80         The PCI-MIO E series driver was originally written by
  81         Tomasz Motylewski <...>, and ported to comedi by ds.
  82
  83         References:
  84
  85            341079b.pdf  PCI E Series Register-Level Programmer Manual
  86            340934b.pdf  DAQ-STC reference manual
  87
  88            322080b.pdf  6711/6713/6715 User Manual
  89
  90            320945c.pdf  PCI E Series User Manual
  91            322138a.pdf  PCI-6052E and DAQPad-6052E User Manual
  92
  93         ISSUES:
  94
  95         need to deal with external reference for DAC, and other DAC
  96         properties in board properties
  97
  98         deal with at-mio-16de-10 revision D to N changes, etc.
  99
 100         need to add other CALDAC type
 101
 102         need to slow down DAC loading.  I don't trust NI's claim that
 103         two writes to the PCI bus slows IO enough.  I would prefer to
 104         use udelay().  Timing specs: (clock)
 105                 AD8522          30ns
 106                 DAC8043         120ns
 107                 DAC8800         60ns
 108                 MB88341         ?
 109
 110 */
 111
 112 #include "../comedidev.h"
 113
 114 #include <asm/byteorder.h>
 115 #include <linux/delay.h>
 116
 117 #include "ni_stc.h"
 118 #include "mite.h"
 119
 120 /* #define PCI_DEBUG */
 121
 122 #define PCIDMA
 123
 124 #define PCIMIO 1
 125 #undef ATMIO
 126
 127 #define MAX_N_CALDACS (16+16+2)
 128
 129 #define DRV_NAME "ni_pcimio"
 130
 131 /* The following two tables must be in the same order */
 132 static DEFINE_PCI_DEVICE_TABLE(ni_pci_table) = {
 133         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x0162)},
 134         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1170)},
 135         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1180)},
 136         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1190)},
 137         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11b0)},
 138         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11c0)},
 139         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11d0)},
 140         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1270)},
 141         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1330)},
 142         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1340)},
 143         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1350)},
 144         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x14e0)},
 145         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x14f0)},
 146         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1580)},
 147         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x15b0)},
 148         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1880)},
 149         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1870)},
 150         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x18b0)},
 151         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x18c0)},
 152         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2410)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2420)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2430)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2890)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x28c0)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a60)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a70)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a80)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2ab0)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b80)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b90)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2c80)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2ca0)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70aa)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70ab)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70ac)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70af)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b0)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b4)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b6)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b7)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b8)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bc)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bd)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bf)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70c0)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70f2)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x710d)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x716c)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x716d)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x717f)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x71bc)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x717d)},
 185         {0}
 186 };
 187
 188 MODULE_DEVICE_TABLE(pci, ni_pci_table);
 189
 190 /* These are not all the possible ao ranges for 628x boards.
 191  They can do OFFSET +- REFERENCE where OFFSET can be
 192  0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
 193  be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>.  That's
 194  63 different possibilities.  An AO channel
 195  can not act as it's own OFFSET or REFERENCE.
 196 */
 197 static const struct comedi_lrange range_ni_M_628x_ao = { 8, {
 198                                                              RANGE(-10, 10),
 199                                                              RANGE(-5, 5),
 200                                                              RANGE(-2, 2),
 201                                                              RANGE(-1, 1),
 202                                                              RANGE(-5, 15),
 203                                                              RANGE(0, 10),
 204                                                              RANGE(3, 7),
 205                                                              RANGE(4, 6),
 206                                                              RANGE_ext(-1, 1)
 207                                                              }
 208 };
 209
 210 static const struct comedi_lrange range_ni_M_625x_ao = { 3, {
 211                                                              RANGE(-10, 10),
 212                                                              RANGE(-5, 5),
 213                                                              RANGE_ext(-1, 1)
 214                                                              }
 215 };
 216
 217 static const struct comedi_lrange range_ni_M_622x_ao = { 1, {
 218                                                              RANGE(-10, 10),
 219                                                              }
 220 };
 221
 222 static const struct ni_board_struct ni_boards[] = {
 223         {
 224          .device_id = 0x0162,   /*  NI also says 0x1620.  typo? */
 225          .name = "pci-mio-16xe-50",
 226          .n_adchan = 16,
 227          .adbits = 16,
 228          .ai_fifo_depth = 2048,
 229          .alwaysdither = 1,
 230          .gainlkup = ai_gain_8,
 231          .ai_speed = 50000,
 232          .n_aochan = 2,
 233          .aobits = 12,
 234          .ao_fifo_depth = 0,
 235          .ao_range_table = &range_bipolar10,
 236          .ao_unipolar = 0,
 237          .ao_speed = 50000,
 238          .num_p0_dio_channels = 8,
 239          .caldac = {dac8800, dac8043},
 240          .has_8255 = 0,
 241          },
 242         {
 243          .device_id = 0x1170,
 244          .name = "pci-mio-16xe-10",     /*  aka pci-6030E */
 245          .n_adchan = 16,
 246          .adbits = 16,
 247          .ai_fifo_depth = 512,
 248          .alwaysdither = 1,
 249          .gainlkup = ai_gain_14,
 250          .ai_speed = 10000,
 251          .n_aochan = 2,
 252          .aobits = 16,
 253          .ao_fifo_depth = 2048,
 254          .ao_range_table = &range_ni_E_ao_ext,
 255          .ao_unipolar = 1,
 256          .ao_speed = 10000,
 257          .num_p0_dio_channels = 8,
 258          .caldac = {dac8800, dac8043, ad8522},
 259          .has_8255 = 0,
 260          },
 261         {
 262          .device_id = 0x28c0,
 263          .name = "pci-6014",
 264          .n_adchan = 16,
 265          .adbits = 16,
 266          .ai_fifo_depth = 512,
 267          .alwaysdither = 1,
 268          .gainlkup = ai_gain_4,
 269          .ai_speed = 5000,
 270          .n_aochan = 2,
 271          .aobits = 16,
 272          .ao_fifo_depth = 0,
 273          .ao_range_table = &range_bipolar10,
 274          .ao_unipolar = 0,
 275          .ao_speed = 100000,
 276          .num_p0_dio_channels = 8,
 277          .caldac = {ad8804_debug},
 278          .has_8255 = 0,
 279          },
 280         {
 281          .device_id = 0x11d0,
 282          .name = "pxi-6030e",
 283          .n_adchan = 16,
 284          .adbits = 16,
 285          .ai_fifo_depth = 512,
 286          .alwaysdither = 1,
 287          .gainlkup = ai_gain_14,
 288          .ai_speed = 10000,
 289          .n_aochan = 2,
 290          .aobits = 16,
 291          .ao_fifo_depth = 2048,
 292          .ao_range_table = &range_ni_E_ao_ext,
 293          .ao_unipolar = 1,
 294          .ao_speed = 10000,
 295          .num_p0_dio_channels = 8,
 296          .caldac = {dac8800, dac8043, ad8522},
 297          .has_8255 = 0,
 298          },
 299         {
 300          .device_id = 0x1180,
 301          .name = "pci-mio-16e-1",       /* aka pci-6070e */
 302          .n_adchan = 16,
 303          .adbits = 12,
 304          .ai_fifo_depth = 512,
 305          .alwaysdither = 0,
 306          .gainlkup = ai_gain_16,
 307          .ai_speed = 800,
 308          .n_aochan = 2,
 309          .aobits = 12,
 310          .ao_fifo_depth = 2048,
 311          .ao_range_table = &range_ni_E_ao_ext,
 312          .ao_unipolar = 1,
 313          .ao_speed = 1000,
 314          .num_p0_dio_channels = 8,
 315          .caldac = {mb88341},
 316          .has_8255 = 0,
 317          },
 318         {
 319          .device_id = 0x1190,
 320          .name = "pci-mio-16e-4",       /* aka pci-6040e */
 321          .n_adchan = 16,
 322          .adbits = 12,
 323          .ai_fifo_depth = 512,
 324          .alwaysdither = 0,
 325          .gainlkup = ai_gain_16,
 326          /*      .Note = there have been reported problems with full speed
 327           * on this board */
 328          .ai_speed = 2000,
 329          .n_aochan = 2,
 330          .aobits = 12,
 331          .ao_fifo_depth = 512,
 332          .ao_range_table = &range_ni_E_ao_ext,
 333          .ao_unipolar = 1,
 334          .ao_speed = 1000,
 335          .num_p0_dio_channels = 8,
 336          .caldac = {ad8804_debug},      /*  doc says mb88341 */
 337          .has_8255 = 0,
 338          },
 339         {
 340          .device_id = 0x11c0,
 341          .name = "pxi-6040e",
 342          .n_adchan = 16,
 343          .adbits = 12,
 344          .ai_fifo_depth = 512,
 345          .alwaysdither = 0,
 346          .gainlkup = ai_gain_16,
 347          .ai_speed = 2000,
 348          .n_aochan = 2,
 349          .aobits = 12,
 350          .ao_fifo_depth = 512,
 351          .ao_range_table = &range_ni_E_ao_ext,
 352          .ao_unipolar = 1,
 353          .ao_speed = 1000,
 354          .num_p0_dio_channels = 8,
 355          .caldac = {mb88341},
 356          .has_8255 = 0,
 357          },
 358
 359         {
 360          .device_id = 0x1330,
 361          .name = "pci-6031e",
 362          .n_adchan = 64,
 363          .adbits = 16,
 364          .ai_fifo_depth = 512,
 365          .alwaysdither = 1,
 366          .gainlkup = ai_gain_14,
 367          .ai_speed = 10000,
 368          .n_aochan = 2,
 369          .aobits = 16,
 370          .ao_fifo_depth = 2048,
 371          .ao_range_table = &range_ni_E_ao_ext,
 372          .ao_unipolar = 1,
 373          .ao_speed = 10000,
 374          .num_p0_dio_channels = 8,
 375          .caldac = {dac8800, dac8043, ad8522},
 376          .has_8255 = 0,
 377          },
 378         {
 379          .device_id = 0x1270,
 380          .name = "pci-6032e",
 381          .n_adchan = 16,
 382          .adbits = 16,
 383          .ai_fifo_depth = 512,
 384          .alwaysdither = 1,
 385          .gainlkup = ai_gain_14,
 386          .ai_speed = 10000,
 387          .n_aochan = 0,
 388          .aobits = 0,
 389          .ao_fifo_depth = 0,
 390          .ao_unipolar = 0,
 391          .num_p0_dio_channels = 8,
 392          .caldac = {dac8800, dac8043, ad8522},
 393          .has_8255 = 0,
 394          },
 395         {
 396          .device_id = 0x1340,
 397          .name = "pci-6033e",
 398          .n_adchan = 64,
 399          .adbits = 16,
 400          .ai_fifo_depth = 512,
 401          .alwaysdither = 1,
 402          .gainlkup = ai_gain_14,
 403          .ai_speed = 10000,
 404          .n_aochan = 0,
 405          .aobits = 0,
 406          .ao_fifo_depth = 0,
 407          .ao_unipolar = 0,
 408          .num_p0_dio_channels = 8,
 409          .caldac = {dac8800, dac8043, ad8522},
 410          .has_8255 = 0,
 411          },
 412         {
 413          .device_id = 0x1350,
 414          .name = "pci-6071e",
 415          .n_adchan = 64,
 416          .adbits = 12,
 417          .ai_fifo_depth = 512,
 418          .alwaysdither = 1,
 419          .gainlkup = ai_gain_16,
 420          .ai_speed = 800,
 421          .n_aochan = 2,
 422          .aobits = 12,
 423          .ao_fifo_depth = 2048,
 424          .ao_range_table = &range_ni_E_ao_ext,
 425          .ao_unipolar = 1,
 426          .ao_speed = 1000,
 427          .num_p0_dio_channels = 8,
 428          .caldac = {ad8804_debug},
 429          .has_8255 = 0,
 430          },
 431         {
 432          .device_id = 0x2a60,
 433          .name = "pci-6023e",
 434          .n_adchan = 16,
 435          .adbits = 12,
 436          .ai_fifo_depth = 512,
 437          .alwaysdither = 0,
 438          .gainlkup = ai_gain_4,
 439          .ai_speed = 5000,
 440          .n_aochan = 0,
 441          .aobits = 0,
 442          .ao_unipolar = 0,
 443          .num_p0_dio_channels = 8,
 444          .caldac = {ad8804_debug},      /* manual is wrong */
 445          .has_8255 = 0,
 446          },
 447         {
 448          .device_id = 0x2a70,
 449          .name = "pci-6024e",
 450          .n_adchan = 16,
 451          .adbits = 12,
 452          .ai_fifo_depth = 512,
 453          .alwaysdither = 0,
 454          .gainlkup = ai_gain_4,
 455          .ai_speed = 5000,
 456          .n_aochan = 2,
 457          .aobits = 12,
 458          .ao_fifo_depth = 0,
 459          .ao_range_table = &range_bipolar10,
 460          .ao_unipolar = 0,
 461          .ao_speed = 100000,
 462          .num_p0_dio_channels = 8,
 463          .caldac = {ad8804_debug},      /* manual is wrong */
 464          .has_8255 = 0,
 465          },
 466         {
 467          .device_id = 0x2a80,
 468          .name = "pci-6025e",
 469          .n_adchan = 16,
 470          .adbits = 12,
 471          .ai_fifo_depth = 512,
 472          .alwaysdither = 0,
 473          .gainlkup = ai_gain_4,
 474          .ai_speed = 5000,
 475          .n_aochan = 2,
 476          .aobits = 12,
 477          .ao_fifo_depth = 0,
 478          .ao_range_table = &range_bipolar10,
 479          .ao_unipolar = 0,
 480          .ao_speed = 100000,
 481          .num_p0_dio_channels = 8,
 482          .caldac = {ad8804_debug},      /* manual is wrong */
 483          .has_8255 = 1,
 484          },
 485         {
 486          .device_id = 0x2ab0,
 487          .name = "pxi-6025e",
 488          .n_adchan = 16,
 489          .adbits = 12,
 490          .ai_fifo_depth = 512,
 491          .alwaysdither = 0,
 492          .gainlkup = ai_gain_4,
 493          .ai_speed = 5000,
 494          .n_aochan = 2,
 495          .aobits = 12,
 496          .ao_fifo_depth = 0,
 497          .ao_range_table = &range_ni_E_ao_ext,
 498          .ao_unipolar = 1,
 499          .ao_speed = 100000,
 500          .num_p0_dio_channels = 8,
 501          .caldac = {ad8804_debug},      /* manual is wrong */
 502          .has_8255 = 1,
 503          },
 504
 505         {
 506          .device_id = 0x2ca0,
 507          .name = "pci-6034e",
 508          .n_adchan = 16,
 509          .adbits = 16,
 510          .ai_fifo_depth = 512,
 511          .alwaysdither = 1,
 512          .gainlkup = ai_gain_4,
 513          .ai_speed = 5000,
 514          .n_aochan = 0,
 515          .aobits = 0,
 516          .ao_fifo_depth = 0,
 517          .ao_unipolar = 0,
 518          .num_p0_dio_channels = 8,
 519          .caldac = {ad8804_debug},
 520          .has_8255 = 0,
 521          },
 522         {
 523          .device_id = 0x2c80,
 524          .name = "pci-6035e",
 525          .n_adchan = 16,
 526          .adbits = 16,
 527          .ai_fifo_depth = 512,
 528          .alwaysdither = 1,
 529          .gainlkup = ai_gain_4,
 530          .ai_speed = 5000,
 531          .n_aochan = 2,
 532          .aobits = 12,
 533          .ao_fifo_depth = 0,
 534          .ao_range_table = &range_bipolar10,
 535          .ao_unipolar = 0,
 536          .ao_speed = 100000,
 537          .num_p0_dio_channels = 8,
 538          .caldac = {ad8804_debug},
 539          .has_8255 = 0,
 540          },
 541         {
 542          .device_id = 0x18b0,
 543          .name = "pci-6052e",
 544          .n_adchan = 16,
 545          .adbits = 16,
 546          .ai_fifo_depth = 512,
 547          .alwaysdither = 1,
 548          .gainlkup = ai_gain_16,
 549          .ai_speed = 3000,
 550          .n_aochan = 2,
 551          .aobits = 16,
 552          .ao_unipolar = 1,
 553          .ao_fifo_depth = 2048,
 554          .ao_range_table = &range_ni_E_ao_ext,
 555          .ao_speed = 3000,
 556          .num_p0_dio_channels = 8,
 557          .caldac = {ad8804_debug, ad8804_debug, ad8522},        /* manual is wrong */
 558          },
 559         {.device_id = 0x14e0,
 560          .name = "pci-6110",
 561          .n_adchan = 4,
 562          .adbits = 12,
 563          .ai_fifo_depth = 8192,
 564          .alwaysdither = 0,
 565          .gainlkup = ai_gain_611x,
 566          .ai_speed = 200,
 567          .n_aochan = 2,
 568          .aobits = 16,
 569          .reg_type = ni_reg_611x,
 570          .ao_range_table = &range_bipolar10,
 571          .ao_unipolar = 0,
 572          .ao_fifo_depth = 2048,
 573          .ao_speed = 250,
 574          .num_p0_dio_channels = 8,
 575          .caldac = {ad8804, ad8804},
 576          },
 577         {
 578          .device_id = 0x14f0,
 579          .name = "pci-6111",
 580          .n_adchan = 2,
 581          .adbits = 12,
 582          .ai_fifo_depth = 8192,
 583          .alwaysdither = 0,
 584          .gainlkup = ai_gain_611x,
 585          .ai_speed = 200,
 586          .n_aochan = 2,
 587          .aobits = 16,
 588          .reg_type = ni_reg_611x,
 589          .ao_range_table = &range_bipolar10,
 590          .ao_unipolar = 0,
 591          .ao_fifo_depth = 2048,
 592          .ao_speed = 250,
 593          .num_p0_dio_channels = 8,
 594          .caldac = {ad8804, ad8804},
 595          },
 596 #if 0
 597         /* The 6115 boards probably need their own driver */
 598         {
 599          .device_id = 0x2ed0,
 600          .name = "pci-6115",
 601          .n_adchan = 4,
 602          .adbits = 12,
 603          .ai_fifo_depth = 8192,
 604          .alwaysdither = 0,
 605          .gainlkup = ai_gain_611x,
 606          .ai_speed = 100,
 607          .n_aochan = 2,
 608          .aobits = 16,
 609          .ao_671x = 1,
 610          .ao_unipolar = 0,
 611          .ao_fifo_depth = 2048,
 612          .ao_speed = 250,
 613          .num_p0_dio_channels = 8,
 614          .reg_611x = 1,
 615          .caldac = {ad8804_debug, ad8804_debug, ad8804_debug},  /* XXX */
 616          },
 617 #endif
 618 #if 0
 619         {
 620          .device_id = 0x0000,
 621          .name = "pxi-6115",
 622          .n_adchan = 4,
 623          .adbits = 12,
 624          .ai_fifo_depth = 8192,
 625          .alwaysdither = 0,
 626          .gainlkup = ai_gain_611x,
 627          .ai_speed = 100,
 628          .n_aochan = 2,
 629          .aobits = 16,
 630          .ao_671x = 1,
 631          .ao_unipolar = 0,
 632          .ao_fifo_depth = 2048,
 633          .ao_speed = 250,
 634          .reg_611x = 1,
 635          .num_p0_dio_channels = 8,
 636          caldac = {ad8804_debug, ad8804_debug, ad8804_debug},   /* XXX */
 637          },
 638 #endif
 639         {
 640          .device_id = 0x1880,
 641          .name = "pci-6711",
 642          .n_adchan = 0,         /* no analog input */
 643          .n_aochan = 4,
 644          .aobits = 12,
 645          .ao_unipolar = 0,
 646          .ao_fifo_depth = 16384,
 647          /* data sheet says 8192, but fifo really holds 16384 samples */
 648          .ao_range_table = &range_bipolar10,
 649          .ao_speed = 1000,
 650          .num_p0_dio_channels = 8,
 651          .reg_type = ni_reg_6711,
 652          .caldac = {ad8804_debug},
 653          },
 654         {
 655          .device_id = 0x2b90,
 656          .name = "pxi-6711",
 657          .n_adchan = 0,         /* no analog input */
 658          .n_aochan = 4,
 659          .aobits = 12,
 660          .ao_unipolar = 0,
 661          .ao_fifo_depth = 16384,
 662          .ao_range_table = &range_bipolar10,
 663          .ao_speed = 1000,
 664          .num_p0_dio_channels = 8,
 665          .reg_type = ni_reg_6711,
 666          .caldac = {ad8804_debug},
 667          },
 668         {
 669          .device_id = 0x1870,
 670          .name = "pci-6713",
 671          .n_adchan = 0,         /* no analog input */
 672          .n_aochan = 8,
 673          .aobits = 12,
 674          .ao_unipolar = 0,
 675          .ao_fifo_depth = 16384,
 676          .ao_range_table = &range_bipolar10,
 677          .ao_speed = 1000,
 678          .num_p0_dio_channels = 8,
 679          .reg_type = ni_reg_6713,
 680          .caldac = {ad8804_debug, ad8804_debug},
 681          },
 682         {
 683          .device_id = 0x2b80,
 684          .name = "pxi-6713",
 685          .n_adchan = 0,         /* no analog input */
 686          .n_aochan = 8,
 687          .aobits = 12,
 688          .ao_unipolar = 0,
 689          .ao_fifo_depth = 16384,
 690          .ao_range_table = &range_bipolar10,
 691          .ao_speed = 1000,
 692          .num_p0_dio_channels = 8,
 693          .reg_type = ni_reg_6713,
 694          .caldac = {ad8804_debug, ad8804_debug},
 695          },
 696         {
 697          .device_id = 0x2430,
 698          .name = "pci-6731",
 699          .n_adchan = 0,         /* no analog input */
 700          .n_aochan = 4,
 701          .aobits = 16,
 702          .ao_unipolar = 0,
 703          .ao_fifo_depth = 8192,
 704          .ao_range_table = &range_bipolar10,
 705          .ao_speed = 1000,
 706          .num_p0_dio_channels = 8,
 707          .reg_type = ni_reg_6711,
 708          .caldac = {ad8804_debug},
 709          },
 710 #if 0                           /* need device ids */
 711         {
 712          .device_id = 0x0,
 713          .name = "pxi-6731",
 714          .n_adchan = 0,         /* no analog input */
 715          .n_aochan = 4,
 716          .aobits = 16,
 717          .ao_unipolar = 0,
 718          .ao_fifo_depth = 8192,
 719          .ao_range_table = &range_bipolar10,
 720          .num_p0_dio_channels = 8,
 721          .reg_type = ni_reg_6711,
 722          .caldac = {ad8804_debug},
 723          },
 724 #endif
 725         {
 726          .device_id = 0x2410,
 727          .name = "pci-6733",
 728          .n_adchan = 0,         /* no analog input */
 729          .n_aochan = 8,
 730          .aobits = 16,
 731          .ao_unipolar = 0,
 732          .ao_fifo_depth = 16384,
 733          .ao_range_table = &range_bipolar10,
 734          .ao_speed = 1000,
 735          .num_p0_dio_channels = 8,
 736          .reg_type = ni_reg_6713,
 737          .caldac = {ad8804_debug, ad8804_debug},
 738          },
 739         {
 740          .device_id = 0x2420,
 741          .name = "pxi-6733",
 742          .n_adchan = 0,         /* no analog input */
 743          .n_aochan = 8,
 744          .aobits = 16,
 745          .ao_unipolar = 0,
 746          .ao_fifo_depth = 16384,
 747          .ao_range_table = &range_bipolar10,
 748          .ao_speed = 1000,
 749          .num_p0_dio_channels = 8,
 750          .reg_type = ni_reg_6713,
 751          .caldac = {ad8804_debug, ad8804_debug},
 752          },
 753         {
 754          .device_id = 0x15b0,
 755          .name = "pxi-6071e",
 756          .n_adchan = 64,
 757          .adbits = 12,
 758          .ai_fifo_depth = 512,
 759          .alwaysdither = 1,
 760          .gainlkup = ai_gain_16,
 761          .ai_speed = 800,
 762          .n_aochan = 2,
 763          .aobits = 12,
 764          .ao_fifo_depth = 2048,
 765          .ao_range_table = &range_ni_E_ao_ext,
 766          .ao_unipolar = 1,
 767          .ao_speed = 1000,
 768          .num_p0_dio_channels = 8,
 769          .caldac = {ad8804_debug},
 770          .has_8255 = 0,
 771          },
 772         {
 773          .device_id = 0x11b0,
 774          .name = "pxi-6070e",
 775          .n_adchan = 16,
 776          .adbits = 12,
 777          .ai_fifo_depth = 512,
 778          .alwaysdither = 1,
 779          .gainlkup = ai_gain_16,
 780          .ai_speed = 800,
 781          .n_aochan = 2,
 782          .aobits = 12,
 783          .ao_fifo_depth = 2048,
 784          .ao_range_table = &range_ni_E_ao_ext,
 785          .ao_unipolar = 1,
 786          .ao_speed = 1000,
 787          .num_p0_dio_channels = 8,
 788          .caldac = {ad8804_debug},
 789          .has_8255 = 0,
 790          },
 791         {
 792          .device_id = 0x18c0,
 793          .name = "pxi-6052e",
 794          .n_adchan = 16,
 795          .adbits = 16,
 796          .ai_fifo_depth = 512,
 797          .alwaysdither = 1,
 798          .gainlkup = ai_gain_16,
 799          .ai_speed = 3000,
 800          .n_aochan = 2,
 801          .aobits = 16,
 802          .ao_unipolar = 1,
 803          .ao_fifo_depth = 2048,
 804          .ao_range_table = &range_ni_E_ao_ext,
 805          .ao_speed = 3000,
 806          .num_p0_dio_channels = 8,
 807          .caldac = {mb88341, mb88341, ad8522},
 808          },
 809         {
 810          .device_id = 0x1580,
 811          .name = "pxi-6031e",
 812          .n_adchan = 64,
 813          .adbits = 16,
 814          .ai_fifo_depth = 512,
 815          .alwaysdither = 1,
 816          .gainlkup = ai_gain_14,
 817          .ai_speed = 10000,
 818          .n_aochan = 2,
 819          .aobits = 16,
 820          .ao_fifo_depth = 2048,
 821          .ao_range_table = &range_ni_E_ao_ext,
 822          .ao_unipolar = 1,
 823          .ao_speed = 10000,
 824          .num_p0_dio_channels = 8,
 825          .caldac = {dac8800, dac8043, ad8522},
 826          },
 827         {
 828          .device_id = 0x2890,
 829          .name = "pci-6036e",
 830          .n_adchan = 16,
 831          .adbits = 16,
 832          .ai_fifo_depth = 512,
 833          .alwaysdither = 1,
 834          .gainlkup = ai_gain_4,
 835          .ai_speed = 5000,
 836          .n_aochan = 2,
 837          .aobits = 16,
 838          .ao_fifo_depth = 0,
 839          .ao_range_table = &range_bipolar10,
 840          .ao_unipolar = 0,
 841          .ao_speed = 100000,
 842          .num_p0_dio_channels = 8,
 843          .caldac = {ad8804_debug},
 844          .has_8255 = 0,
 845          },
 846         {
 847          .device_id = 0x70b0,
 848          .name = "pci-6220",
 849          .n_adchan = 16,
 850          .adbits = 16,
 851          .ai_fifo_depth = 512,
 852          /*      .FIXME = guess */
 853          .gainlkup = ai_gain_622x,
 854          .ai_speed = 4000,
 855          .n_aochan = 0,
 856          .aobits = 0,
 857          .ao_fifo_depth = 0,
 858          .num_p0_dio_channels = 8,
 859          .reg_type = ni_reg_622x,
 860          .ao_unipolar = 0,
 861          .caldac = {caldac_none},
 862          .has_8255 = 0,
 863          },
 864         {
 865          .device_id = 0x70af,
 866          .name = "pci-6221",
 867          .n_adchan = 16,
 868          .adbits = 16,
 869          .ai_fifo_depth = 4095,
 870          .gainlkup = ai_gain_622x,
 871          .ai_speed = 4000,
 872          .n_aochan = 2,
 873          .aobits = 16,
 874          .ao_fifo_depth = 8191,
 875          .ao_range_table = &range_ni_M_622x_ao,
 876          .reg_type = ni_reg_622x,
 877          .ao_unipolar = 0,
 878          .ao_speed = 1200,
 879          .num_p0_dio_channels = 8,
 880          .caldac = {caldac_none},
 881          .has_8255 = 0,
 882          },
 883         {
 884          .device_id = 0x71bc,
 885          .name = "pci-6221_37pin",
 886          .n_adchan = 16,
 887          .adbits = 16,
 888          .ai_fifo_depth = 4095,
 889          .gainlkup = ai_gain_622x,
 890          .ai_speed = 4000,
 891          .n_aochan = 2,
 892          .aobits = 16,
 893          .ao_fifo_depth = 8191,
 894          .ao_range_table = &range_ni_M_622x_ao,
 895          .reg_type = ni_reg_622x,
 896          .ao_unipolar = 0,
 897          .ao_speed = 1200,
 898          .num_p0_dio_channels = 8,
 899          .caldac = {caldac_none},
 900          .has_8255 = 0,
 901          },
 902         {
 903          .device_id = 0x70f2,
 904          .name = "pci-6224",
 905          .n_adchan = 32,
 906          .adbits = 16,
 907          .ai_fifo_depth = 4095,
 908          .gainlkup = ai_gain_622x,
 909          .ai_speed = 4000,
 910          .n_aochan = 0,
 911          .aobits = 0,
 912          .ao_fifo_depth = 0,
 913          .reg_type = ni_reg_622x,
 914          .ao_unipolar = 0,
 915          .num_p0_dio_channels = 32,
 916          .caldac = {caldac_none},
 917          .has_8255 = 0,
 918          },
 919         {
 920          .device_id = 0x70f3,
 921          .name = "pxi-6224",
 922          .n_adchan = 32,
 923          .adbits = 16,
 924          .ai_fifo_depth = 4095,
 925          .gainlkup = ai_gain_622x,
 926          .ai_speed = 4000,
 927          .n_aochan = 0,
 928          .aobits = 0,
 929          .ao_fifo_depth = 0,
 930          .reg_type = ni_reg_622x,
 931          .ao_unipolar = 0,
 932          .num_p0_dio_channels = 32,
 933          .caldac = {caldac_none},
 934          .has_8255 = 0,
 935          },
 936         {
 937          .device_id = 0x716c,
 938          .name = "pci-6225",
 939          .n_adchan = 80,
 940          .adbits = 16,
 941          .ai_fifo_depth = 4095,
 942          .gainlkup = ai_gain_622x,
 943          .ai_speed = 4000,
 944          .n_aochan = 2,
 945          .aobits = 16,
 946          .ao_fifo_depth = 8191,
 947          .ao_range_table = &range_ni_M_622x_ao,
 948          .reg_type = ni_reg_622x,
 949          .ao_unipolar = 0,
 950          .ao_speed = 1200,
 951          .num_p0_dio_channels = 32,
 952          .caldac = {caldac_none},
 953          .has_8255 = 0,
 954          },
 955         {
 956          .device_id = 0x716d,
 957          .name = "pxi-6225",
 958          .n_adchan = 80,
 959          .adbits = 16,
 960          .ai_fifo_depth = 4095,
 961          .gainlkup = ai_gain_622x,
 962          .ai_speed = 4000,
 963          .n_aochan = 2,
 964          .aobits = 16,
 965          .ao_fifo_depth = 8191,
 966          .ao_range_table = &range_ni_M_622x_ao,
 967          .reg_type = ni_reg_622x,
 968          .ao_unipolar = 0,
 969          .ao_speed = 1200,
 970          .num_p0_dio_channels = 32,
 971          .caldac = {caldac_none},
 972          .has_8255 = 0,
 973         },
 974         {
 975          .device_id = 0x70aa,
 976          .name = "pci-6229",
 977          .n_adchan = 32,
 978          .adbits = 16,
 979          .ai_fifo_depth = 4095,
 980          .gainlkup = ai_gain_622x,
 981          .ai_speed = 4000,
 982          .n_aochan = 4,
 983          .aobits = 16,
 984          .ao_fifo_depth = 8191,
 985          .ao_range_table = &range_ni_M_622x_ao,
 986          .reg_type = ni_reg_622x,
 987          .ao_unipolar = 0,
 988          .ao_speed = 1200,
 989          .num_p0_dio_channels = 32,
 990          .caldac = {caldac_none},
 991          .has_8255 = 0,
 992          },
 993         {
 994          .device_id = 0x70b4,
 995          .name = "pci-6250",
 996          .n_adchan = 16,
 997          .adbits = 16,
 998          .ai_fifo_depth = 4095,
 999          .gainlkup = ai_gain_628x,
1000          .ai_speed = 800,
1001          .n_aochan = 0,
1002          .aobits = 0,
1003          .ao_fifo_depth = 0,
1004          .reg_type = ni_reg_625x,
1005          .ao_unipolar = 0,
1006          .num_p0_dio_channels = 8,
1007          .caldac = {caldac_none},
1008          .has_8255 = 0,
1009          },
1010         {
1011          .device_id = 0x70b8,
1012          .name = "pci-6251",
1013          .n_adchan = 16,
1014          .adbits = 16,
1015          .ai_fifo_depth = 4095,
1016          .gainlkup = ai_gain_628x,
1017          .ai_speed = 800,
1018          .n_aochan = 2,
1019          .aobits = 16,
1020          .ao_fifo_depth = 8191,
1021          .ao_range_table = &range_ni_M_625x_ao,
1022          .reg_type = ni_reg_625x,
1023          .ao_unipolar = 0,
1024          .ao_speed = 357,
1025          .num_p0_dio_channels = 8,
1026          .caldac = {caldac_none},
1027          .has_8255 = 0,
1028          },
1029         {
1030          .device_id = 0x717d,
1031          .name = "pcie-6251",
1032          .n_adchan = 16,
1033          .adbits = 16,
1034          .ai_fifo_depth = 4095,
1035          .gainlkup = ai_gain_628x,
1036          .ai_speed = 800,
1037          .n_aochan = 2,
1038          .aobits = 16,
1039          .ao_fifo_depth = 8191,
1040          .ao_range_table = &range_ni_M_625x_ao,
1041          .reg_type = ni_reg_625x,
1042          .ao_unipolar = 0,
1043          .ao_speed = 357,
1044          .num_p0_dio_channels = 8,
1045          .caldac = {caldac_none},
1046          .has_8255 = 0,
1047          },
1048         {
1049          .device_id = 0x70b7,
1050          .name = "pci-6254",
1051          .n_adchan = 32,
1052          .adbits = 16,
1053          .ai_fifo_depth = 4095,
1054          .gainlkup = ai_gain_628x,
1055          .ai_speed = 800,
1056          .n_aochan = 0,
1057          .aobits = 0,
1058          .ao_fifo_depth = 0,
1059          .reg_type = ni_reg_625x,
1060          .ao_unipolar = 0,
1061          .num_p0_dio_channels = 32,
1062          .caldac = {caldac_none},
1063          .has_8255 = 0,
1064          },
1065         {
1066          .device_id = 0x70ab,
1067          .name = "pci-6259",
1068          .n_adchan = 32,
1069          .adbits = 16,
1070          .ai_fifo_depth = 4095,
1071          .gainlkup = ai_gain_628x,
1072          .ai_speed = 800,
1073          .n_aochan = 4,
1074          .aobits = 16,
1075          .ao_fifo_depth = 8191,
1076          .ao_range_table = &range_ni_M_625x_ao,
1077          .reg_type = ni_reg_625x,
1078          .ao_unipolar = 0,
1079          .ao_speed = 357,
1080          .num_p0_dio_channels = 32,
1081          .caldac = {caldac_none},
1082          .has_8255 = 0,
1083          },
1084         {
1085          .device_id = 0x717f,
1086          .name = "pcie-6259",
1087          .n_adchan = 32,
1088          .adbits = 16,
1089          .ai_fifo_depth = 4095,
1090          .gainlkup = ai_gain_628x,
1091          .ai_speed = 800,
1092          .n_aochan = 4,
1093          .aobits = 16,
1094          .ao_fifo_depth = 8191,
1095          .ao_range_table = &range_ni_M_625x_ao,
1096          .reg_type = ni_reg_625x,
1097          .ao_unipolar = 0,
1098          .ao_speed = 357,
1099          .num_p0_dio_channels = 32,
1100          .caldac = {caldac_none},
1101          .has_8255 = 0,
1102          },
1103         {
1104          .device_id = 0x70b6,
1105          .name = "pci-6280",
1106          .n_adchan = 16,
1107          .adbits = 18,
1108          .ai_fifo_depth = 2047,
1109          .gainlkup = ai_gain_628x,
1110          .ai_speed = 1600,
1111          .n_aochan = 0,
1112          .aobits = 0,
1113          .ao_fifo_depth = 8191,
1114          .reg_type = ni_reg_628x,
1115          .ao_unipolar = 0,
1116          .num_p0_dio_channels = 8,
1117          .caldac = {caldac_none},
1118          .has_8255 = 0,
1119          },
1120         {
1121          .device_id = 0x70bd,
1122          .name = "pci-6281",
1123          .n_adchan = 16,
1124          .adbits = 18,
1125          .ai_fifo_depth = 2047,
1126          .gainlkup = ai_gain_628x,
1127          .ai_speed = 1600,
1128          .n_aochan = 2,
1129          .aobits = 16,
1130          .ao_fifo_depth = 8191,
1131          .ao_range_table = &range_ni_M_628x_ao,
1132          .reg_type = ni_reg_628x,
1133          .ao_unipolar = 1,
1134          .ao_speed = 357,
1135          .num_p0_dio_channels = 8,
1136          .caldac = {caldac_none},
1137          .has_8255 = 0,
1138          },
1139         {
1140          .device_id = 0x70bf,
1141          .name = "pxi-6281",
1142          .n_adchan = 16,
1143          .adbits = 18,
1144          .ai_fifo_depth = 2047,
1145          .gainlkup = ai_gain_628x,
1146          .ai_speed = 1600,
1147          .n_aochan = 2,
1148          .aobits = 16,
1149          .ao_fifo_depth = 8191,
1150          .ao_range_table = &range_ni_M_628x_ao,
1151          .reg_type = ni_reg_628x,
1152          .ao_unipolar = 1,
1153          .ao_speed = 357,
1154          .num_p0_dio_channels = 8,
1155          .caldac = {caldac_none},
1156          .has_8255 = 0,
1157          },
1158         {
1159          .device_id = 0x70bc,
1160          .name = "pci-6284",
1161          .n_adchan = 32,
1162          .adbits = 18,
1163          .ai_fifo_depth = 2047,
1164          .gainlkup = ai_gain_628x,
1165          .ai_speed = 1600,
1166          .n_aochan = 0,
1167          .aobits = 0,
1168          .ao_fifo_depth = 0,
1169          .reg_type = ni_reg_628x,
1170          .ao_unipolar = 0,
1171          .num_p0_dio_channels = 32,
1172          .caldac = {caldac_none},
1173          .has_8255 = 0,
1174          },
1175         {
1176          .device_id = 0x70ac,
1177          .name = "pci-6289",
1178          .n_adchan = 32,
1179          .adbits = 18,
1180          .ai_fifo_depth = 2047,
1181          .gainlkup = ai_gain_628x,
1182          .ai_speed = 1600,
1183          .n_aochan = 4,
1184          .aobits = 16,
1185          .ao_fifo_depth = 8191,
1186          .ao_range_table = &range_ni_M_628x_ao,
1187          .reg_type = ni_reg_628x,
1188          .ao_unipolar = 1,
1189          .ao_speed = 357,
1190          .num_p0_dio_channels = 32,
1191          .caldac = {caldac_none},
1192          .has_8255 = 0,
1193          },
1194         {
1195          .device_id = 0x70C0,
1196          .name = "pci-6143",
1197          .n_adchan = 8,
1198          .adbits = 16,
1199          .ai_fifo_depth = 1024,
1200          .alwaysdither = 0,
1201          .gainlkup = ai_gain_6143,
1202          .ai_speed = 4000,
1203          .n_aochan = 0,
1204          .aobits = 0,
1205          .reg_type = ni_reg_6143,
1206          .ao_unipolar = 0,
1207          .ao_fifo_depth = 0,
1208          .num_p0_dio_channels = 8,
1209          .caldac = {ad8804_debug, ad8804_debug},
1210          },
1211         {
1212          .device_id = 0x710D,
1213          .name = "pxi-6143",
1214          .n_adchan = 8,
1215          .adbits = 16,
1216          .ai_fifo_depth = 1024,
1217          .alwaysdither = 0,
1218          .gainlkup = ai_gain_6143,
1219          .ai_speed = 4000,
1220          .n_aochan = 0,
1221          .aobits = 0,
1222          .reg_type = ni_reg_6143,
1223          .ao_unipolar = 0,
1224          .ao_fifo_depth = 0,
1225          .num_p0_dio_channels = 8,
1226          .caldac = {ad8804_debug, ad8804_debug},
1227          },
1228 };
1229
1230 #define n_pcimio_boards ARRAY_SIZE(ni_boards)
1231
1232 static int pcimio_attach(struct comedi_device *dev,
1233                          struct comedi_devconfig *it);
1234 static int pcimio_detach(struct comedi_device *dev);
1235 static struct comedi_driver driver_pcimio = {
1236         .driver_name = DRV_NAME,
1237         .module = THIS_MODULE,
1238         .attach = pcimio_attach,
1239         .detach = pcimio_detach,
1240 };
1241
1242 COMEDI_PCI_INITCLEANUP(driver_pcimio, ni_pci_table)
1243
1244 struct ni_private {
1245 NI_PRIVATE_COMMON};
1246 #define devpriv ((struct ni_private *)dev->private)
1247
1248 /* How we access registers */
1249
1250 #define ni_writel(a, b) (writel((a), devpriv->mite->daq_io_addr + (b)))
1251 #define ni_readl(a)     (readl(devpriv->mite->daq_io_addr + (a)))
1252 #define ni_writew(a, b) (writew((a), devpriv->mite->daq_io_addr + (b)))
1253 #define ni_readw(a)     (readw(devpriv->mite->daq_io_addr + (a)))
1254 #define ni_writeb(a, b) (writeb((a), devpriv->mite->daq_io_addr + (b)))
1255 #define ni_readb(a)     (readb(devpriv->mite->daq_io_addr + (a)))
1256
1257 /* How we access STC registers */
1258
1259 /* We automatically take advantage of STC registers that can be
1260  * read/written directly in the I/O space of the board.  Most
1261  * PCIMIO devices map the low 8 STC registers to iobase+addr*2.
1262  * The 611x devices map the write registers to iobase+addr*2, and
1263  * the read registers to iobase+(addr-1)*2. */
1264 /* However, the 611x boards still aren't working, so I'm disabling
1265  * non-windowed STC access temporarily */
1266
1267 static void e_series_win_out(struct comedi_device *dev, uint16_t data, int reg)
1268 {
1269         unsigned long flags;
1270
1271         spin_lock_irqsave(&devpriv->window_lock, flags);
1272         ni_writew(reg, Window_Address);
1273         ni_writew(data, Window_Data);
1274         spin_unlock_irqrestore(&devpriv->window_lock, flags);
1275 }
1276
1277 static uint16_t e_series_win_in(struct comedi_device *dev, int reg)
1278 {
1279         unsigned long flags;
1280         uint16_t ret;
1281
1282         spin_lock_irqsave(&devpriv->window_lock, flags);
1283         ni_writew(reg, Window_Address);
1284         ret = ni_readw(Window_Data);
1285         spin_unlock_irqrestore(&devpriv->window_lock, flags);
1286
1287         return ret;
1288 }
1289
1290 static void m_series_stc_writew(struct comedi_device *dev, uint16_t data,
1291                                 int reg)
1292 {
1293         unsigned offset;
1294         switch (reg) {
1295         case ADC_FIFO_Clear:
1296                 offset = M_Offset_AI_FIFO_Clear;
1297                 break;
1298         case AI_Command_1_Register:
1299                 offset = M_Offset_AI_Command_1;
1300                 break;
1301         case AI_Command_2_Register:
1302                 offset = M_Offset_AI_Command_2;
1303                 break;
1304         case AI_Mode_1_Register:
1305                 offset = M_Offset_AI_Mode_1;
1306                 break;
1307         case AI_Mode_2_Register:
1308                 offset = M_Offset_AI_Mode_2;
1309                 break;
1310         case AI_Mode_3_Register:
1311                 offset = M_Offset_AI_Mode_3;
1312                 break;
1313         case AI_Output_Control_Register:
1314                 offset = M_Offset_AI_Output_Control;
1315                 break;
1316         case AI_Personal_Register:
1317                 offset = M_Offset_AI_Personal;
1318                 break;
1319         case AI_SI2_Load_A_Register:
1320                 /*  this is actually a 32 bit register on m series boards */
1321                 ni_writel(data, M_Offset_AI_SI2_Load_A);
1322                 return;
1323                 break;
1324         case AI_SI2_Load_B_Register:
1325                 /*  this is actually a 32 bit register on m series boards */
1326                 ni_writel(data, M_Offset_AI_SI2_Load_B);
1327                 return;
1328                 break;
1329         case AI_START_STOP_Select_Register:
1330                 offset = M_Offset_AI_START_STOP_Select;
1331                 break;
1332         case AI_Trigger_Select_Register:
1333                 offset = M_Offset_AI_Trigger_Select;
1334                 break;
1335         case Analog_Trigger_Etc_Register:
1336                 offset = M_Offset_Analog_Trigger_Etc;
1337                 break;
1338         case AO_Command_1_Register:
1339                 offset = M_Offset_AO_Command_1;
1340                 break;
1341         case AO_Command_2_Register:
1342                 offset = M_Offset_AO_Command_2;
1343                 break;
1344         case AO_Mode_1_Register:
1345                 offset = M_Offset_AO_Mode_1;
1346                 break;
1347         case AO_Mode_2_Register:
1348                 offset = M_Offset_AO_Mode_2;
1349                 break;
1350         case AO_Mode_3_Register:
1351                 offset = M_Offset_AO_Mode_3;
1352                 break;
1353         case AO_Output_Control_Register:
1354                 offset = M_Offset_AO_Output_Control;
1355                 break;
1356         case AO_Personal_Register:
1357                 offset = M_Offset_AO_Personal;
1358                 break;
1359         case AO_Start_Select_Register:
1360                 offset = M_Offset_AO_Start_Select;
1361                 break;
1362         case AO_Trigger_Select_Register:
1363                 offset = M_Offset_AO_Trigger_Select;
1364                 break;
1365         case Clock_and_FOUT_Register:
1366                 offset = M_Offset_Clock_and_FOUT;
1367                 break;
1368         case Configuration_Memory_Clear:
1369                 offset = M_Offset_Configuration_Memory_Clear;
1370                 break;
1371         case DAC_FIFO_Clear:
1372                 offset = M_Offset_AO_FIFO_Clear;
1373                 break;
1374         case DIO_Control_Register:
1375                 printk
1376                     ("%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n",
1377                      __func__, reg);
1378                 return;
1379                 break;
1380         case G_Autoincrement_Register(0):
1381                 offset = M_Offset_G0_Autoincrement;
1382                 break;
1383         case G_Autoincrement_Register(1):
1384                 offset = M_Offset_G1_Autoincrement;
1385                 break;
1386         case G_Command_Register(0):
1387                 offset = M_Offset_G0_Command;
1388                 break;
1389         case G_Command_Register(1):
1390                 offset = M_Offset_G1_Command;
1391                 break;
1392         case G_Input_Select_Register(0):
1393                 offset = M_Offset_G0_Input_Select;
1394                 break;
1395         case G_Input_Select_Register(1):
1396                 offset = M_Offset_G1_Input_Select;
1397                 break;
1398         case G_Mode_Register(0):
1399                 offset = M_Offset_G0_Mode;
1400                 break;
1401         case G_Mode_Register(1):
1402                 offset = M_Offset_G1_Mode;
1403                 break;
1404         case Interrupt_A_Ack_Register:
1405                 offset = M_Offset_Interrupt_A_Ack;
1406                 break;
1407         case Interrupt_A_Enable_Register:
1408                 offset = M_Offset_Interrupt_A_Enable;
1409                 break;
1410         case Interrupt_B_Ack_Register:
1411                 offset = M_Offset_Interrupt_B_Ack;
1412                 break;
1413         case Interrupt_B_Enable_Register:
1414                 offset = M_Offset_Interrupt_B_Enable;
1415                 break;
1416         case Interrupt_Control_Register:
1417                 offset = M_Offset_Interrupt_Control;
1418                 break;
1419         case IO_Bidirection_Pin_Register:
1420                 offset = M_Offset_IO_Bidirection_Pin;
1421                 break;
1422         case Joint_Reset_Register:
1423                 offset = M_Offset_Joint_Reset;
1424                 break;
1425         case RTSI_Trig_A_Output_Register:
1426                 offset = M_Offset_RTSI_Trig_A_Output;
1427                 break;
1428         case RTSI_Trig_B_Output_Register:
1429                 offset = M_Offset_RTSI_Trig_B_Output;
1430                 break;
1431         case RTSI_Trig_Direction_Register:
1432                 offset = M_Offset_RTSI_Trig_Direction;
1433                 break;
1434                 /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit)
1435                    and M_Offset_SCXI_Serial_Data_Out (8 bit) */
1436         default:
1437                 printk("%s: bug! unhandled register=0x%x in switch.\n",
1438                        __func__, reg);
1439                 BUG();
1440                 return;
1441                 break;
1442         }
1443         ni_writew(data, offset);
1444 }
1445
1446 static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
1447 {
1448         unsigned offset;
1449         switch (reg) {
1450         case AI_Status_1_Register:
1451                 offset = M_Offset_AI_Status_1;
1452                 break;
1453         case AO_Status_1_Register:
1454                 offset = M_Offset_AO_Status_1;
1455                 break;
1456         case AO_Status_2_Register:
1457                 offset = M_Offset_AO_Status_2;
1458                 break;
1459         case DIO_Serial_Input_Register:
1460                 return ni_readb(M_Offset_SCXI_Serial_Data_In);
1461                 break;
1462         case Joint_Status_1_Register:
1463                 offset = M_Offset_Joint_Status_1;
1464                 break;
1465         case Joint_Status_2_Register:
1466                 offset = M_Offset_Joint_Status_2;
1467                 break;
1468         case G_Status_Register:
1469                 offset = M_Offset_G01_Status;
1470                 break;
1471         default:
1472                 printk("%s: bug! unhandled register=0x%x in switch.\n",
1473                        __func__, reg);
1474                 BUG();
1475                 return 0;
1476                 break;
1477         }
1478         return ni_readw(offset);
1479 }
1480
1481 static void m_series_stc_writel(struct comedi_device *dev, uint32_t data,
1482                                 int reg)
1483 {
1484         unsigned offset;
1485         switch (reg) {
1486         case AI_SC_Load_A_Registers:
1487                 offset = M_Offset_AI_SC_Load_A;
1488                 break;
1489         case AI_SI_Load_A_Registers:
1490                 offset = M_Offset_AI_SI_Load_A;
1491                 break;
1492         case AO_BC_Load_A_Register:
1493                 offset = M_Offset_AO_BC_Load_A;
1494                 break;
1495         case AO_UC_Load_A_Register:
1496                 offset = M_Offset_AO_UC_Load_A;
1497                 break;
1498         case AO_UI_Load_A_Register:
1499                 offset = M_Offset_AO_UI_Load_A;
1500                 break;
1501         case G_Load_A_Register(0):
1502                 offset = M_Offset_G0_Load_A;
1503                 break;
1504         case G_Load_A_Register(1):
1505                 offset = M_Offset_G1_Load_A;
1506                 break;
1507         case G_Load_B_Register(0):
1508                 offset = M_Offset_G0_Load_B;
1509                 break;
1510         case G_Load_B_Register(1):
1511                 offset = M_Offset_G1_Load_B;
1512                 break;
1513         default:
1514                 printk("%s: bug! unhandled register=0x%x in switch.\n",
1515                        __func__, reg);
1516                 BUG();
1517                 return;
1518                 break;
1519         }
1520         ni_writel(data, offset);
1521 }
1522
1523 static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
1524 {
1525         unsigned offset;
1526         switch (reg) {
1527         case G_HW_Save_Register(0):
1528                 offset = M_Offset_G0_HW_Save;
1529                 break;
1530         case G_HW_Save_Register(1):
1531                 offset = M_Offset_G1_HW_Save;
1532                 break;
1533         case G_Save_Register(0):
1534                 offset = M_Offset_G0_Save;
1535                 break;
1536         case G_Save_Register(1):
1537                 offset = M_Offset_G1_Save;
1538                 break;
1539         default:
1540                 printk("%s: bug! unhandled register=0x%x in switch.\n",
1541                        __func__, reg);
1542                 BUG();
1543                 return 0;
1544                 break;
1545         }
1546         return ni_readl(offset);
1547 }
1548
1549 #define interrupt_pin(a)        0
1550 #define IRQ_POLARITY 1
1551
1552 #define NI_E_IRQ_FLAGS          IRQF_SHARED
1553
1554 #include "ni_mio_common.c"
1555
1556 static int pcimio_find_device(struct comedi_device *dev, int bus, int slot);
1557 static int pcimio_ai_change(struct comedi_device *dev,
1558                             struct comedi_subdevice *s, unsigned long new_size);
1559 static int pcimio_ao_change(struct comedi_device *dev,
1560                             struct comedi_subdevice *s, unsigned long new_size);
1561 static int pcimio_gpct0_change(struct comedi_device *dev,
1562                                struct comedi_subdevice *s,
1563                                unsigned long new_size);
1564 static int pcimio_gpct1_change(struct comedi_device *dev,
1565                                struct comedi_subdevice *s,
1566                                unsigned long new_size);
1567 static int pcimio_dio_change(struct comedi_device *dev,
1568                              struct comedi_subdevice *s,
1569                              unsigned long new_size);
1570
1571 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1572 {
1573         static const int Start_Cal_EEPROM = 0x400;
1574         static const unsigned window_size = 10;
1575         static const int serial_number_eeprom_offset = 0x4;
1576         static const int serial_number_eeprom_length = 0x4;
1577         unsigned old_iodwbsr_bits;
1578         unsigned old_iodwbsr1_bits;
1579         unsigned old_iodwcr1_bits;
1580         int i;
1581
1582         old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR);
1583         old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1584         old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1585         writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1586         writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr),
1587                devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1588         writel(0x1 | old_iodwcr1_bits,
1589                devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1590         writel(0xf, devpriv->mite->mite_io_addr + 0x30);
1591
1592         BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1593         for (i = 0; i < serial_number_eeprom_length; ++i) {
1594                 char *byte_ptr = (char *)&devpriv->serial_number + i;
1595                 *byte_ptr = ni_readb(serial_number_eeprom_offset + i);
1596         }
1597         devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1598
1599         for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i) {
1600                 devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i);
1601         }
1602
1603         writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1604         writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1605         writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1606         writel(0x0, devpriv->mite->mite_io_addr + 0x30);
1607 }
1608
1609 static void init_6143(struct comedi_device *dev)
1610 {
1611         /*  Disable interrupts */
1612         devpriv->stc_writew(dev, 0, Interrupt_Control_Register);
1613
1614         /*  Initialise 6143 AI specific bits */
1615         ni_writeb(0x00, Magic_6143);    /*  Set G0,G1 DMA mode to E series version */
1616         ni_writeb(0x80, PipelineDelay_6143);    /*  Set EOCMode, ADCMode and pipelinedelay */
1617         ni_writeb(0x00, EOC_Set_6143);  /*  Set EOC Delay */
1618
1619         ni_writel(boardtype.ai_fifo_depth / 2, AIFIFO_Flag_6143);       /*  Set the FIFO half full level */
1620
1621         /*  Strobe Relay disable bit */
1622         devpriv->ai_calib_source_enabled = 0;
1623         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff,
1624                   Calibration_Channel_6143);
1625         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1626 }
1627
1628 /* cleans up allocated resources */
1629 static int pcimio_detach(struct comedi_device *dev)
1630 {
1631         mio_common_detach(dev);
1632         if (dev->irq) {
1633                 free_irq(dev->irq, dev);
1634         }
1635         if (dev->private) {
1636                 mite_free_ring(devpriv->ai_mite_ring);
1637                 mite_free_ring(devpriv->ao_mite_ring);
1638                 mite_free_ring(devpriv->cdo_mite_ring);
1639                 mite_free_ring(devpriv->gpct_mite_ring[0]);
1640                 mite_free_ring(devpriv->gpct_mite_ring[1]);
1641                 if (devpriv->mite)
1642                         mite_unsetup(devpriv->mite);
1643         }
1644
1645         return 0;
1646 }
1647
1648 static int pcimio_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1649 {
1650         int ret;
1651
1652         printk("comedi%d: ni_pcimio:", dev->minor);
1653
1654         ret = ni_alloc_private(dev);
1655         if (ret < 0)
1656                 return ret;
1657
1658         ret = pcimio_find_device(dev, it->options[0], it->options[1]);
1659         if (ret < 0)
1660                 return ret;
1661
1662         printk(" %s", boardtype.name);
1663         dev->board_name = boardtype.name;
1664
1665         if (boardtype.reg_type & ni_reg_m_series_mask) {
1666                 devpriv->stc_writew = &m_series_stc_writew;
1667                 devpriv->stc_readw = &m_series_stc_readw;
1668                 devpriv->stc_writel = &m_series_stc_writel;
1669                 devpriv->stc_readl = &m_series_stc_readl;
1670         } else {
1671                 devpriv->stc_writew = &e_series_win_out;
1672                 devpriv->stc_readw = &e_series_win_in;
1673                 devpriv->stc_writel = &win_out2;
1674                 devpriv->stc_readl = &win_in2;
1675         }
1676
1677         ret = mite_setup(devpriv->mite);
1678         if (ret < 0) {
1679                 printk(" error setting up mite\n");
1680                 return ret;
1681         }
1682         comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev);
1683         devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1684         if (devpriv->ai_mite_ring == NULL)
1685                 return -ENOMEM;
1686         devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1687         if (devpriv->ao_mite_ring == NULL)
1688                 return -ENOMEM;
1689         devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1690         if (devpriv->cdo_mite_ring == NULL)
1691                 return -ENOMEM;
1692         devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1693         if (devpriv->gpct_mite_ring[0] == NULL)
1694                 return -ENOMEM;
1695         devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1696         if (devpriv->gpct_mite_ring[1] == NULL)
1697                 return -ENOMEM;
1698
1699         if (boardtype.reg_type & ni_reg_m_series_mask)
1700                 m_series_init_eeprom_buffer(dev);
1701         if (boardtype.reg_type == ni_reg_6143)
1702                 init_6143(dev);
1703
1704         dev->irq = mite_irq(devpriv->mite);
1705
1706         if (dev->irq == 0) {
1707                 printk(" unknown irq (bad)\n");
1708         } else {
1709                 printk(" ( irq = %u )", dev->irq);
1710                 ret = request_irq(dev->irq, ni_E_interrupt, NI_E_IRQ_FLAGS,
1711                                   DRV_NAME, dev);
1712                 if (ret < 0) {
1713                         printk(" irq not available\n");
1714                         dev->irq = 0;
1715                 }
1716         }
1717
1718         ret = ni_E_init(dev, it);
1719         if (ret < 0)
1720                 return ret;
1721
1722         dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1723         dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1724         dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1725         dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1726         dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1727
1728         return ret;
1729 }
1730
1731 static int pcimio_find_device(struct comedi_device *dev, int bus, int slot)
1732 {
1733         struct mite_struct *mite;
1734         int i;
1735
1736         for (mite = mite_devices; mite; mite = mite->next) {
1737                 if (mite->used)
1738                         continue;
1739                 if (bus || slot) {
1740                         if (bus != mite->pcidev->bus->number ||
1741                             slot != PCI_SLOT(mite->pcidev->devfn))
1742                                 continue;
1743                 }
1744
1745                 for (i = 0; i < n_pcimio_boards; i++) {
1746                         if (mite_device_id(mite) == ni_boards[i].device_id) {
1747                                 dev->board_ptr = ni_boards + i;
1748                                 devpriv->mite = mite;
1749
1750                                 return 0;
1751                         }
1752                 }
1753         }
1754         printk("no device found\n");
1755         mite_list_devices();
1756         return -EIO;
1757 }
1758
1759 static int pcimio_ai_change(struct comedi_device *dev,
1760                             struct comedi_subdevice *s, unsigned long new_size)
1761 {
1762         int ret;
1763
1764         ret = mite_buf_change(devpriv->ai_mite_ring, s->async);
1765         if (ret < 0)
1766                 return ret;
1767
1768         return 0;
1769 }
1770
1771 static int pcimio_ao_change(struct comedi_device *dev,
1772                             struct comedi_subdevice *s, unsigned long new_size)
1773 {
1774         int ret;
1775
1776         ret = mite_buf_change(devpriv->ao_mite_ring, s->async);
1777         if (ret < 0)
1778                 return ret;
1779
1780         return 0;
1781 }
1782
1783 static int pcimio_gpct0_change(struct comedi_device *dev,
1784                                struct comedi_subdevice *s,
1785                                unsigned long new_size)
1786 {
1787         int ret;
1788
1789         ret = mite_buf_change(devpriv->gpct_mite_ring[0], s->async);
1790         if (ret < 0)
1791                 return ret;
1792
1793         return 0;
1794 }
1795
1796 static int pcimio_gpct1_change(struct comedi_device *dev,
1797                                struct comedi_subdevice *s,
1798                                unsigned long new_size)
1799 {
1800         int ret;
1801
1802         ret = mite_buf_change(devpriv->gpct_mite_ring[1], s->async);
1803         if (ret < 0)
1804                 return ret;
1805
1806         return 0;
1807 }
1808
1809 static int pcimio_dio_change(struct comedi_device *dev,
1810                              struct comedi_subdevice *s, unsigned long new_size)
1811 {
1812         int ret;
1813
1814         ret = mite_buf_change(devpriv->cdo_mite_ring, s->async);
1815         if (ret < 0)
1816                 return ret;
1817
1818         return 0;
1819 }