drivers/staging/comedi/drivers/ni_660x.c

   1 /*
   2   comedi/drivers/ni_660x.c
   3   Hardware driver for NI 660x devices
   4
   5   This program is free software; you can redistribute it and/or modify
   6   it under the terms of the GNU General Public License as published by
   7   the Free Software Foundation; either version 2 of the License, or
   8   (at your option) any later version.
   9
  10   This program is distributed in the hope that it will be useful,
  11   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13   GNU General Public License for more details.
  14
  15   You should have received a copy of the GNU General Public License
  16   along with this program; if not, write to the Free Software
  17   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18 */
  19
  20 /*
  21 Driver: ni_660x
  22 Description: National Instruments 660x counter/timer boards
  23 Devices:
  24 [National Instruments] PCI-6601 (ni_660x), PCI-6602, PXI-6602,
  25         PXI-6608
  26 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
  27         Herman.Bruyninckx@mech.kuleuven.ac.be,
  28         Wim.Meeussen@mech.kuleuven.ac.be,
  29         Klaas.Gadeyne@mech.kuleuven.ac.be,
  30         Frank Mori Hess <fmhess@users.sourceforge.net>
  31 Updated: Thu Oct 18 12:56:06 EDT 2007
  32 Status: experimental
  33
  34 Encoders work.  PulseGeneration (both single pulse and pulse train)
  35 works. Buffered commands work for input but not output.
  36
  37 References:
  38 DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
  39 DAQ 6601/6602 User Manual (NI 322137B-01)
  40
  41 */
  42
  43 #include <linux/interrupt.h>
  44 #include "../comedidev.h"
  45 #include "mite.h"
  46 #include "ni_tio.h"
  47
  48 enum ni_660x_constants {
  49         min_counter_pfi_chan = 8,
  50         max_dio_pfi_chan = 31,
  51         counters_per_chip = 4
  52 };
  53
  54 #define NUM_PFI_CHANNELS 40
  55 /* really there are only up to 3 dma channels, but the register layout allows
  56 for 4 */
  57 #define MAX_DMA_CHANNEL 4
  58
  59 /* See Register-Level Programmer Manual page 3.1 */
  60 enum NI_660x_Register {
  61         G0InterruptAcknowledge,
  62         G0StatusRegister,
  63         G1InterruptAcknowledge,
  64         G1StatusRegister,
  65         G01StatusRegister,
  66         G0CommandRegister,
  67         STCDIOParallelInput,
  68         G1CommandRegister,
  69         G0HWSaveRegister,
  70         G1HWSaveRegister,
  71         STCDIOOutput,
  72         STCDIOControl,
  73         G0SWSaveRegister,
  74         G1SWSaveRegister,
  75         G0ModeRegister,
  76         G01JointStatus1Register,
  77         G1ModeRegister,
  78         STCDIOSerialInput,
  79         G0LoadARegister,
  80         G01JointStatus2Register,
  81         G0LoadBRegister,
  82         G1LoadARegister,
  83         G1LoadBRegister,
  84         G0InputSelectRegister,
  85         G1InputSelectRegister,
  86         G0AutoincrementRegister,
  87         G1AutoincrementRegister,
  88         G01JointResetRegister,
  89         G0InterruptEnable,
  90         G1InterruptEnable,
  91         G0CountingModeRegister,
  92         G1CountingModeRegister,
  93         G0SecondGateRegister,
  94         G1SecondGateRegister,
  95         G0DMAConfigRegister,
  96         G0DMAStatusRegister,
  97         G1DMAConfigRegister,
  98         G1DMAStatusRegister,
  99         G2InterruptAcknowledge,
 100         G2StatusRegister,
 101         G3InterruptAcknowledge,
 102         G3StatusRegister,
 103         G23StatusRegister,
 104         G2CommandRegister,
 105         G3CommandRegister,
 106         G2HWSaveRegister,
 107         G3HWSaveRegister,
 108         G2SWSaveRegister,
 109         G3SWSaveRegister,
 110         G2ModeRegister,
 111         G23JointStatus1Register,
 112         G3ModeRegister,
 113         G2LoadARegister,
 114         G23JointStatus2Register,
 115         G2LoadBRegister,
 116         G3LoadARegister,
 117         G3LoadBRegister,
 118         G2InputSelectRegister,
 119         G3InputSelectRegister,
 120         G2AutoincrementRegister,
 121         G3AutoincrementRegister,
 122         G23JointResetRegister,
 123         G2InterruptEnable,
 124         G3InterruptEnable,
 125         G2CountingModeRegister,
 126         G3CountingModeRegister,
 127         G3SecondGateRegister,
 128         G2SecondGateRegister,
 129         G2DMAConfigRegister,
 130         G2DMAStatusRegister,
 131         G3DMAConfigRegister,
 132         G3DMAStatusRegister,
 133         DIO32Input,
 134         DIO32Output,
 135         ClockConfigRegister,
 136         GlobalInterruptStatusRegister,
 137         DMAConfigRegister,
 138         GlobalInterruptConfigRegister,
 139         IOConfigReg0_1,
 140         IOConfigReg2_3,
 141         IOConfigReg4_5,
 142         IOConfigReg6_7,
 143         IOConfigReg8_9,
 144         IOConfigReg10_11,
 145         IOConfigReg12_13,
 146         IOConfigReg14_15,
 147         IOConfigReg16_17,
 148         IOConfigReg18_19,
 149         IOConfigReg20_21,
 150         IOConfigReg22_23,
 151         IOConfigReg24_25,
 152         IOConfigReg26_27,
 153         IOConfigReg28_29,
 154         IOConfigReg30_31,
 155         IOConfigReg32_33,
 156         IOConfigReg34_35,
 157         IOConfigReg36_37,
 158         IOConfigReg38_39,
 159         NumRegisters,
 160 };
 161
 162 static inline unsigned IOConfigReg(unsigned pfi_channel)
 163 {
 164         unsigned reg = IOConfigReg0_1 + pfi_channel / 2;
 165         BUG_ON(reg > IOConfigReg38_39);
 166         return reg;
 167 }
 168
 169 enum ni_660x_register_width {
 170         DATA_1B,
 171         DATA_2B,
 172         DATA_4B
 173 };
 174
 175 enum ni_660x_register_direction {
 176         NI_660x_READ,
 177         NI_660x_WRITE,
 178         NI_660x_READ_WRITE
 179 };
 180
 181 enum ni_660x_pfi_output_select {
 182         pfi_output_select_high_Z = 0,
 183         pfi_output_select_counter = 1,
 184         pfi_output_select_do = 2,
 185         num_pfi_output_selects
 186 };
 187
 188 enum ni_660x_subdevices {
 189         NI_660X_DIO_SUBDEV = 1,
 190         NI_660X_GPCT_SUBDEV_0 = 2
 191 };
 192 static inline unsigned NI_660X_GPCT_SUBDEV(unsigned index)
 193 {
 194         return NI_660X_GPCT_SUBDEV_0 + index;
 195 }
 196
 197 struct NI_660xRegisterData {
 198
 199         const char *name;       /*  Register Name */
 200         int offset;             /*  Offset from base address from GPCT chip */
 201         enum ni_660x_register_direction direction;
 202         enum ni_660x_register_width size; /* 1 byte, 2 bytes, or 4 bytes */
 203 };
 204
 205 static const struct NI_660xRegisterData registerData[NumRegisters] = {
 206         {"G0 Interrupt Acknowledge", 0x004, NI_660x_WRITE, DATA_2B},
 207         {"G0 Status Register", 0x004, NI_660x_READ, DATA_2B},
 208         {"G1 Interrupt Acknowledge", 0x006, NI_660x_WRITE, DATA_2B},
 209         {"G1 Status Register", 0x006, NI_660x_READ, DATA_2B},
 210         {"G01 Status Register ", 0x008, NI_660x_READ, DATA_2B},
 211         {"G0 Command Register", 0x00C, NI_660x_WRITE, DATA_2B},
 212         {"STC DIO Parallel Input", 0x00E, NI_660x_READ, DATA_2B},
 213         {"G1 Command Register", 0x00E, NI_660x_WRITE, DATA_2B},
 214         {"G0 HW Save Register", 0x010, NI_660x_READ, DATA_4B},
 215         {"G1 HW Save Register", 0x014, NI_660x_READ, DATA_4B},
 216         {"STC DIO Output", 0x014, NI_660x_WRITE, DATA_2B},
 217         {"STC DIO Control", 0x016, NI_660x_WRITE, DATA_2B},
 218         {"G0 SW Save Register", 0x018, NI_660x_READ, DATA_4B},
 219         {"G1 SW Save Register", 0x01C, NI_660x_READ, DATA_4B},
 220         {"G0 Mode Register", 0x034, NI_660x_WRITE, DATA_2B},
 221         {"G01 Joint Status 1 Register", 0x036, NI_660x_READ, DATA_2B},
 222         {"G1 Mode Register", 0x036, NI_660x_WRITE, DATA_2B},
 223         {"STC DIO Serial Input", 0x038, NI_660x_READ, DATA_2B},
 224         {"G0 Load A Register", 0x038, NI_660x_WRITE, DATA_4B},
 225         {"G01 Joint Status 2 Register", 0x03A, NI_660x_READ, DATA_2B},
 226         {"G0 Load B Register", 0x03C, NI_660x_WRITE, DATA_4B},
 227         {"G1 Load A Register", 0x040, NI_660x_WRITE, DATA_4B},
 228         {"G1 Load B Register", 0x044, NI_660x_WRITE, DATA_4B},
 229         {"G0 Input Select Register", 0x048, NI_660x_WRITE, DATA_2B},
 230         {"G1 Input Select Register", 0x04A, NI_660x_WRITE, DATA_2B},
 231         {"G0 Autoincrement Register", 0x088, NI_660x_WRITE, DATA_2B},
 232         {"G1 Autoincrement Register", 0x08A, NI_660x_WRITE, DATA_2B},
 233         {"G01 Joint Reset Register", 0x090, NI_660x_WRITE, DATA_2B},
 234         {"G0 Interrupt Enable", 0x092, NI_660x_WRITE, DATA_2B},
 235         {"G1 Interrupt Enable", 0x096, NI_660x_WRITE, DATA_2B},
 236         {"G0 Counting Mode Register", 0x0B0, NI_660x_WRITE, DATA_2B},
 237         {"G1 Counting Mode Register", 0x0B2, NI_660x_WRITE, DATA_2B},
 238         {"G0 Second Gate Register", 0x0B4, NI_660x_WRITE, DATA_2B},
 239         {"G1 Second Gate Register", 0x0B6, NI_660x_WRITE, DATA_2B},
 240         {"G0 DMA Config Register", 0x0B8, NI_660x_WRITE, DATA_2B},
 241         {"G0 DMA Status Register", 0x0B8, NI_660x_READ, DATA_2B},
 242         {"G1 DMA Config Register", 0x0BA, NI_660x_WRITE, DATA_2B},
 243         {"G1 DMA Status Register", 0x0BA, NI_660x_READ, DATA_2B},
 244         {"G2 Interrupt Acknowledge", 0x104, NI_660x_WRITE, DATA_2B},
 245         {"G2 Status Register", 0x104, NI_660x_READ, DATA_2B},
 246         {"G3 Interrupt Acknowledge", 0x106, NI_660x_WRITE, DATA_2B},
 247         {"G3 Status Register", 0x106, NI_660x_READ, DATA_2B},
 248         {"G23 Status Register", 0x108, NI_660x_READ, DATA_2B},
 249         {"G2 Command Register", 0x10C, NI_660x_WRITE, DATA_2B},
 250         {"G3 Command Register", 0x10E, NI_660x_WRITE, DATA_2B},
 251         {"G2 HW Save Register", 0x110, NI_660x_READ, DATA_4B},
 252         {"G3 HW Save Register", 0x114, NI_660x_READ, DATA_4B},
 253         {"G2 SW Save Register", 0x118, NI_660x_READ, DATA_4B},
 254         {"G3 SW Save Register", 0x11C, NI_660x_READ, DATA_4B},
 255         {"G2 Mode Register", 0x134, NI_660x_WRITE, DATA_2B},
 256         {"G23 Joint Status 1 Register", 0x136, NI_660x_READ, DATA_2B},
 257         {"G3 Mode Register", 0x136, NI_660x_WRITE, DATA_2B},
 258         {"G2 Load A Register", 0x138, NI_660x_WRITE, DATA_4B},
 259         {"G23 Joint Status 2 Register", 0x13A, NI_660x_READ, DATA_2B},
 260         {"G2 Load B Register", 0x13C, NI_660x_WRITE, DATA_4B},
 261         {"G3 Load A Register", 0x140, NI_660x_WRITE, DATA_4B},
 262         {"G3 Load B Register", 0x144, NI_660x_WRITE, DATA_4B},
 263         {"G2 Input Select Register", 0x148, NI_660x_WRITE, DATA_2B},
 264         {"G3 Input Select Register", 0x14A, NI_660x_WRITE, DATA_2B},
 265         {"G2 Autoincrement Register", 0x188, NI_660x_WRITE, DATA_2B},
 266         {"G3 Autoincrement Register", 0x18A, NI_660x_WRITE, DATA_2B},
 267         {"G23 Joint Reset Register", 0x190, NI_660x_WRITE, DATA_2B},
 268         {"G2 Interrupt Enable", 0x192, NI_660x_WRITE, DATA_2B},
 269         {"G3 Interrupt Enable", 0x196, NI_660x_WRITE, DATA_2B},
 270         {"G2 Counting Mode Register", 0x1B0, NI_660x_WRITE, DATA_2B},
 271         {"G3 Counting Mode Register", 0x1B2, NI_660x_WRITE, DATA_2B},
 272         {"G3 Second Gate Register", 0x1B6, NI_660x_WRITE, DATA_2B},
 273         {"G2 Second Gate Register", 0x1B4, NI_660x_WRITE, DATA_2B},
 274         {"G2 DMA Config Register", 0x1B8, NI_660x_WRITE, DATA_2B},
 275         {"G2 DMA Status Register", 0x1B8, NI_660x_READ, DATA_2B},
 276         {"G3 DMA Config Register", 0x1BA, NI_660x_WRITE, DATA_2B},
 277         {"G3 DMA Status Register", 0x1BA, NI_660x_READ, DATA_2B},
 278         {"32 bit Digital Input", 0x414, NI_660x_READ, DATA_4B},
 279         {"32 bit Digital Output", 0x510, NI_660x_WRITE, DATA_4B},
 280         {"Clock Config Register", 0x73C, NI_660x_WRITE, DATA_4B},
 281         {"Global Interrupt Status Register", 0x754, NI_660x_READ, DATA_4B},
 282         {"DMA Configuration Register", 0x76C, NI_660x_WRITE, DATA_4B},
 283         {"Global Interrupt Config Register", 0x770, NI_660x_WRITE, DATA_4B},
 284         {"IO Config Register 0-1", 0x77C, NI_660x_READ_WRITE, DATA_2B},
 285         {"IO Config Register 2-3", 0x77E, NI_660x_READ_WRITE, DATA_2B},
 286         {"IO Config Register 4-5", 0x780, NI_660x_READ_WRITE, DATA_2B},
 287         {"IO Config Register 6-7", 0x782, NI_660x_READ_WRITE, DATA_2B},
 288         {"IO Config Register 8-9", 0x784, NI_660x_READ_WRITE, DATA_2B},
 289         {"IO Config Register 10-11", 0x786, NI_660x_READ_WRITE, DATA_2B},
 290         {"IO Config Register 12-13", 0x788, NI_660x_READ_WRITE, DATA_2B},
 291         {"IO Config Register 14-15", 0x78A, NI_660x_READ_WRITE, DATA_2B},
 292         {"IO Config Register 16-17", 0x78C, NI_660x_READ_WRITE, DATA_2B},
 293         {"IO Config Register 18-19", 0x78E, NI_660x_READ_WRITE, DATA_2B},
 294         {"IO Config Register 20-21", 0x790, NI_660x_READ_WRITE, DATA_2B},
 295         {"IO Config Register 22-23", 0x792, NI_660x_READ_WRITE, DATA_2B},
 296         {"IO Config Register 24-25", 0x794, NI_660x_READ_WRITE, DATA_2B},
 297         {"IO Config Register 26-27", 0x796, NI_660x_READ_WRITE, DATA_2B},
 298         {"IO Config Register 28-29", 0x798, NI_660x_READ_WRITE, DATA_2B},
 299         {"IO Config Register 30-31", 0x79A, NI_660x_READ_WRITE, DATA_2B},
 300         {"IO Config Register 32-33", 0x79C, NI_660x_READ_WRITE, DATA_2B},
 301         {"IO Config Register 34-35", 0x79E, NI_660x_READ_WRITE, DATA_2B},
 302         {"IO Config Register 36-37", 0x7A0, NI_660x_READ_WRITE, DATA_2B},
 303         {"IO Config Register 38-39", 0x7A2, NI_660x_READ_WRITE, DATA_2B}
 304 };
 305
 306 /* kind of ENABLE for the second counter */
 307 enum clock_config_register_bits {
 308         CounterSwap = 0x1 << 21
 309 };
 310
 311 /* ioconfigreg */
 312 static inline unsigned ioconfig_bitshift(unsigned pfi_channel)
 313 {
 314         if (pfi_channel % 2)
 315                 return 0;
 316         else
 317                 return 8;
 318 }
 319
 320 static inline unsigned pfi_output_select_mask(unsigned pfi_channel)
 321 {
 322         return 0x3 << ioconfig_bitshift(pfi_channel);
 323 }
 324
 325 static inline unsigned pfi_output_select_bits(unsigned pfi_channel,
 326                                               unsigned output_select)
 327 {
 328         return (output_select & 0x3) << ioconfig_bitshift(pfi_channel);
 329 }
 330
 331 static inline unsigned pfi_input_select_mask(unsigned pfi_channel)
 332 {
 333         return 0x7 << (4 + ioconfig_bitshift(pfi_channel));
 334 }
 335
 336 static inline unsigned pfi_input_select_bits(unsigned pfi_channel,
 337                                              unsigned input_select)
 338 {
 339         return (input_select & 0x7) << (4 + ioconfig_bitshift(pfi_channel));
 340 }
 341
 342 /* dma configuration register bits */
 343 static inline unsigned dma_select_mask(unsigned dma_channel)
 344 {
 345         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
 346         return 0x1f << (8 * dma_channel);
 347 }
 348
 349 enum dma_selection {
 350         dma_selection_none = 0x1f,
 351 };
 352 static inline unsigned dma_selection_counter(unsigned counter_index)
 353 {
 354         BUG_ON(counter_index >= counters_per_chip);
 355         return counter_index;
 356 }
 357
 358 static inline unsigned dma_select_bits(unsigned dma_channel, unsigned selection)
 359 {
 360         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
 361         return (selection << (8 * dma_channel)) & dma_select_mask(dma_channel);
 362 }
 363
 364 static inline unsigned dma_reset_bit(unsigned dma_channel)
 365 {
 366         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
 367         return 0x80 << (8 * dma_channel);
 368 }
 369
 370 enum global_interrupt_status_register_bits {
 371         Counter_0_Int_Bit = 0x100,
 372         Counter_1_Int_Bit = 0x200,
 373         Counter_2_Int_Bit = 0x400,
 374         Counter_3_Int_Bit = 0x800,
 375         Cascade_Int_Bit = 0x20000000,
 376         Global_Int_Bit = 0x80000000
 377 };
 378
 379 enum global_interrupt_config_register_bits {
 380         Cascade_Int_Enable_Bit = 0x20000000,
 381         Global_Int_Polarity_Bit = 0x40000000,
 382         Global_Int_Enable_Bit = 0x80000000
 383 };
 384
 385 /* Offset of the GPCT chips from the base-adress of the card */
 386 /* First chip is at base-address + 0x00, etc. */
 387 static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 };
 388
 389 /* Board description*/
 390 struct ni_660x_board {
 391         unsigned short dev_id;  /* `lspci` will show you this */
 392         const char *name;
 393         unsigned n_chips;       /* total number of TIO chips */
 394 };
 395
 396 static const struct ni_660x_board ni_660x_boards[] = {
 397         {
 398          .dev_id = 0x2c60,
 399          .name = "PCI-6601",
 400          .n_chips = 1,
 401          },
 402         {
 403          .dev_id = 0x1310,
 404          .name = "PCI-6602",
 405          .n_chips = 2,
 406          },
 407         {
 408          .dev_id = 0x1360,
 409          .name = "PXI-6602",
 410          .n_chips = 2,
 411          },
 412         {
 413          .dev_id = 0x2cc0,
 414          .name = "PXI-6608",
 415          .n_chips = 2,
 416          },
 417 };
 418
 419 #define NI_660X_MAX_NUM_CHIPS 2
 420 #define NI_660X_MAX_NUM_COUNTERS (NI_660X_MAX_NUM_CHIPS * counters_per_chip)
 421
 422 static DEFINE_PCI_DEVICE_TABLE(ni_660x_pci_table) = {
 423         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2c60)},
 424         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1310)},
 425         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1360)},
 426         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2cc0)},
 427         {0}
 428 };
 429
 430 MODULE_DEVICE_TABLE(pci, ni_660x_pci_table);
 431
 432 struct ni_660x_private {
 433         struct mite_struct *mite;
 434         struct ni_gpct_device *counter_dev;
 435         uint64_t pfi_direction_bits;
 436         struct mite_dma_descriptor_ring
 437         *mite_rings[NI_660X_MAX_NUM_CHIPS][counters_per_chip];
 438         spinlock_t mite_channel_lock;
 439         /* interrupt_lock prevents races between interrupt and comedi_poll */
 440         spinlock_t interrupt_lock;
 441         unsigned dma_configuration_soft_copies[NI_660X_MAX_NUM_CHIPS];
 442         spinlock_t soft_reg_copy_lock;
 443         unsigned short pfi_output_selects[NUM_PFI_CHANNELS];
 444 };
 445
 446 static inline struct ni_660x_private *private(struct comedi_device *dev)
 447 {
 448         return dev->private;
 449 }
 450
 451 /* initialized in ni_660x_find_device() */
 452 static inline const struct ni_660x_board *board(struct comedi_device *dev)
 453 {
 454         return dev->board_ptr;
 455 }
 456
 457 #define n_ni_660x_boards ARRAY_SIZE(ni_660x_boards)
 458
 459 static int ni_660x_attach(struct comedi_device *dev,
 460                           struct comedi_devconfig *it);
 461 static int ni_660x_detach(struct comedi_device *dev);
 462 static void init_tio_chip(struct comedi_device *dev, int chipset);
 463 static void ni_660x_select_pfi_output(struct comedi_device *dev,
 464                                       unsigned pfi_channel,
 465                                       unsigned output_select);
 466
 467 static struct comedi_driver driver_ni_660x = {
 468         .driver_name = "ni_660x",
 469         .module = THIS_MODULE,
 470         .attach = ni_660x_attach,
 471         .detach = ni_660x_detach,
 472 };
 473
 474 COMEDI_PCI_INITCLEANUP(driver_ni_660x, ni_660x_pci_table);
 475
 476 static int ni_660x_find_device(struct comedi_device *dev, int bus, int slot);
 477 static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan,
 478                                    unsigned source);
 479
 480 /* Possible instructions for a GPCT */
 481 static int ni_660x_GPCT_rinsn(struct comedi_device *dev,
 482                               struct comedi_subdevice *s,
 483                               struct comedi_insn *insn, unsigned int *data);
 484 static int ni_660x_GPCT_insn_config(struct comedi_device *dev,
 485                                     struct comedi_subdevice *s,
 486                                     struct comedi_insn *insn,
 487                                     unsigned int *data);
 488 static int ni_660x_GPCT_winsn(struct comedi_device *dev,
 489                               struct comedi_subdevice *s,
 490                               struct comedi_insn *insn, unsigned int *data);
 491
 492 /* Possible instructions for Digital IO */
 493 static int ni_660x_dio_insn_config(struct comedi_device *dev,
 494                                    struct comedi_subdevice *s,
 495                                    struct comedi_insn *insn,
 496                                    unsigned int *data);
 497 static int ni_660x_dio_insn_bits(struct comedi_device *dev,
 498                                  struct comedi_subdevice *s,
 499                                  struct comedi_insn *insn, unsigned int *data);
 500
 501 static inline unsigned ni_660x_num_counters(struct comedi_device *dev)
 502 {
 503         return board(dev)->n_chips * counters_per_chip;
 504 }
 505
 506 static enum NI_660x_Register ni_gpct_to_660x_register(enum ni_gpct_register reg)
 507 {
 508         enum NI_660x_Register ni_660x_register;
 509         switch (reg) {
 510         case NITIO_G0_Autoincrement_Reg:
 511                 ni_660x_register = G0AutoincrementRegister;
 512                 break;
 513         case NITIO_G1_Autoincrement_Reg:
 514                 ni_660x_register = G1AutoincrementRegister;
 515                 break;
 516         case NITIO_G2_Autoincrement_Reg:
 517                 ni_660x_register = G2AutoincrementRegister;
 518                 break;
 519         case NITIO_G3_Autoincrement_Reg:
 520                 ni_660x_register = G3AutoincrementRegister;
 521                 break;
 522         case NITIO_G0_Command_Reg:
 523                 ni_660x_register = G0CommandRegister;
 524                 break;
 525         case NITIO_G1_Command_Reg:
 526                 ni_660x_register = G1CommandRegister;
 527                 break;
 528         case NITIO_G2_Command_Reg:
 529                 ni_660x_register = G2CommandRegister;
 530                 break;
 531         case NITIO_G3_Command_Reg:
 532                 ni_660x_register = G3CommandRegister;
 533                 break;
 534         case NITIO_G0_HW_Save_Reg:
 535                 ni_660x_register = G0HWSaveRegister;
 536                 break;
 537         case NITIO_G1_HW_Save_Reg:
 538                 ni_660x_register = G1HWSaveRegister;
 539                 break;
 540         case NITIO_G2_HW_Save_Reg:
 541                 ni_660x_register = G2HWSaveRegister;
 542                 break;
 543         case NITIO_G3_HW_Save_Reg:
 544                 ni_660x_register = G3HWSaveRegister;
 545                 break;
 546         case NITIO_G0_SW_Save_Reg:
 547                 ni_660x_register = G0SWSaveRegister;
 548                 break;
 549         case NITIO_G1_SW_Save_Reg:
 550                 ni_660x_register = G1SWSaveRegister;
 551                 break;
 552         case NITIO_G2_SW_Save_Reg:
 553                 ni_660x_register = G2SWSaveRegister;
 554                 break;
 555         case NITIO_G3_SW_Save_Reg:
 556                 ni_660x_register = G3SWSaveRegister;
 557                 break;
 558         case NITIO_G0_Mode_Reg:
 559                 ni_660x_register = G0ModeRegister;
 560                 break;
 561         case NITIO_G1_Mode_Reg:
 562                 ni_660x_register = G1ModeRegister;
 563                 break;
 564         case NITIO_G2_Mode_Reg:
 565                 ni_660x_register = G2ModeRegister;
 566                 break;
 567         case NITIO_G3_Mode_Reg:
 568                 ni_660x_register = G3ModeRegister;
 569                 break;
 570         case NITIO_G0_LoadA_Reg:
 571                 ni_660x_register = G0LoadARegister;
 572                 break;
 573         case NITIO_G1_LoadA_Reg:
 574                 ni_660x_register = G1LoadARegister;
 575                 break;
 576         case NITIO_G2_LoadA_Reg:
 577                 ni_660x_register = G2LoadARegister;
 578                 break;
 579         case NITIO_G3_LoadA_Reg:
 580                 ni_660x_register = G3LoadARegister;
 581                 break;
 582         case NITIO_G0_LoadB_Reg:
 583                 ni_660x_register = G0LoadBRegister;
 584                 break;
 585         case NITIO_G1_LoadB_Reg:
 586                 ni_660x_register = G1LoadBRegister;
 587                 break;
 588         case NITIO_G2_LoadB_Reg:
 589                 ni_660x_register = G2LoadBRegister;
 590                 break;
 591         case NITIO_G3_LoadB_Reg:
 592                 ni_660x_register = G3LoadBRegister;
 593                 break;
 594         case NITIO_G0_Input_Select_Reg:
 595                 ni_660x_register = G0InputSelectRegister;
 596                 break;
 597         case NITIO_G1_Input_Select_Reg:
 598                 ni_660x_register = G1InputSelectRegister;
 599                 break;
 600         case NITIO_G2_Input_Select_Reg:
 601                 ni_660x_register = G2InputSelectRegister;
 602                 break;
 603         case NITIO_G3_Input_Select_Reg:
 604                 ni_660x_register = G3InputSelectRegister;
 605                 break;
 606         case NITIO_G01_Status_Reg:
 607                 ni_660x_register = G01StatusRegister;
 608                 break;
 609         case NITIO_G23_Status_Reg:
 610                 ni_660x_register = G23StatusRegister;
 611                 break;
 612         case NITIO_G01_Joint_Reset_Reg:
 613                 ni_660x_register = G01JointResetRegister;
 614                 break;
 615         case NITIO_G23_Joint_Reset_Reg:
 616                 ni_660x_register = G23JointResetRegister;
 617                 break;
 618         case NITIO_G01_Joint_Status1_Reg:
 619                 ni_660x_register = G01JointStatus1Register;
 620                 break;
 621         case NITIO_G23_Joint_Status1_Reg:
 622                 ni_660x_register = G23JointStatus1Register;
 623                 break;
 624         case NITIO_G01_Joint_Status2_Reg:
 625                 ni_660x_register = G01JointStatus2Register;
 626                 break;
 627         case NITIO_G23_Joint_Status2_Reg:
 628                 ni_660x_register = G23JointStatus2Register;
 629                 break;
 630         case NITIO_G0_Counting_Mode_Reg:
 631                 ni_660x_register = G0CountingModeRegister;
 632                 break;
 633         case NITIO_G1_Counting_Mode_Reg:
 634                 ni_660x_register = G1CountingModeRegister;
 635                 break;
 636         case NITIO_G2_Counting_Mode_Reg:
 637                 ni_660x_register = G2CountingModeRegister;
 638                 break;
 639         case NITIO_G3_Counting_Mode_Reg:
 640                 ni_660x_register = G3CountingModeRegister;
 641                 break;
 642         case NITIO_G0_Second_Gate_Reg:
 643                 ni_660x_register = G0SecondGateRegister;
 644                 break;
 645         case NITIO_G1_Second_Gate_Reg:
 646                 ni_660x_register = G1SecondGateRegister;
 647                 break;
 648         case NITIO_G2_Second_Gate_Reg:
 649                 ni_660x_register = G2SecondGateRegister;
 650                 break;
 651         case NITIO_G3_Second_Gate_Reg:
 652                 ni_660x_register = G3SecondGateRegister;
 653                 break;
 654         case NITIO_G0_DMA_Config_Reg:
 655                 ni_660x_register = G0DMAConfigRegister;
 656                 break;
 657         case NITIO_G0_DMA_Status_Reg:
 658                 ni_660x_register = G0DMAStatusRegister;
 659                 break;
 660         case NITIO_G1_DMA_Config_Reg:
 661                 ni_660x_register = G1DMAConfigRegister;
 662                 break;
 663         case NITIO_G1_DMA_Status_Reg:
 664                 ni_660x_register = G1DMAStatusRegister;
 665                 break;
 666         case NITIO_G2_DMA_Config_Reg:
 667                 ni_660x_register = G2DMAConfigRegister;
 668                 break;
 669         case NITIO_G2_DMA_Status_Reg:
 670                 ni_660x_register = G2DMAStatusRegister;
 671                 break;
 672         case NITIO_G3_DMA_Config_Reg:
 673                 ni_660x_register = G3DMAConfigRegister;
 674                 break;
 675         case NITIO_G3_DMA_Status_Reg:
 676                 ni_660x_register = G3DMAStatusRegister;
 677                 break;
 678         case NITIO_G0_Interrupt_Acknowledge_Reg:
 679                 ni_660x_register = G0InterruptAcknowledge;
 680                 break;
 681         case NITIO_G1_Interrupt_Acknowledge_Reg:
 682                 ni_660x_register = G1InterruptAcknowledge;
 683                 break;
 684         case NITIO_G2_Interrupt_Acknowledge_Reg:
 685                 ni_660x_register = G2InterruptAcknowledge;
 686                 break;
 687         case NITIO_G3_Interrupt_Acknowledge_Reg:
 688                 ni_660x_register = G3InterruptAcknowledge;
 689                 break;
 690         case NITIO_G0_Status_Reg:
 691                 ni_660x_register = G0StatusRegister;
 692                 break;
 693         case NITIO_G1_Status_Reg:
 694                 ni_660x_register = G1StatusRegister;
 695                 break;
 696         case NITIO_G2_Status_Reg:
 697                 ni_660x_register = G2StatusRegister;
 698                 break;
 699         case NITIO_G3_Status_Reg:
 700                 ni_660x_register = G3StatusRegister;
 701                 break;
 702         case NITIO_G0_Interrupt_Enable_Reg:
 703                 ni_660x_register = G0InterruptEnable;
 704                 break;
 705         case NITIO_G1_Interrupt_Enable_Reg:
 706                 ni_660x_register = G1InterruptEnable;
 707                 break;
 708         case NITIO_G2_Interrupt_Enable_Reg:
 709                 ni_660x_register = G2InterruptEnable;
 710                 break;
 711         case NITIO_G3_Interrupt_Enable_Reg:
 712                 ni_660x_register = G3InterruptEnable;
 713                 break;
 714         default:
 715                 printk(KERN_WARNING "%s: unhandled register 0x%x in switch.\n",
 716                        __func__, reg);
 717                 BUG();
 718                 return 0;
 719                 break;
 720         }
 721         return ni_660x_register;
 722 }
 723
 724 static inline void ni_660x_write_register(struct comedi_device *dev,
 725                                           unsigned chip_index, unsigned bits,
 726                                           enum NI_660x_Register reg)
 727 {
 728         void *const write_address =
 729             private(dev)->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
 730             registerData[reg].offset;
 731
 732         switch (registerData[reg].size) {
 733         case DATA_2B:
 734                 writew(bits, write_address);
 735                 break;
 736         case DATA_4B:
 737                 writel(bits, write_address);
 738                 break;
 739         default:
 740                 printk(KERN_WARNING "%s: %s: bug! unhandled case (reg=0x%x) in switch.\n",
 741                        __FILE__, __func__, reg);
 742                 BUG();
 743                 break;
 744         }
 745 }
 746
 747 static inline unsigned ni_660x_read_register(struct comedi_device *dev,
 748                                              unsigned chip_index,
 749                                              enum NI_660x_Register reg)
 750 {
 751         void *const read_address =
 752             private(dev)->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
 753             registerData[reg].offset;
 754
 755         switch (registerData[reg].size) {
 756         case DATA_2B:
 757                 return readw(read_address);
 758                 break;
 759         case DATA_4B:
 760                 return readl(read_address);
 761                 break;
 762         default:
 763                 printk(KERN_WARNING "%s: %s: bug! unhandled case (reg=0x%x) in switch.\n",
 764                        __FILE__, __func__, reg);
 765                 BUG();
 766                 break;
 767         }
 768         return 0;
 769 }
 770
 771 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
 772                                    enum ni_gpct_register reg)
 773 {
 774         struct comedi_device *dev = counter->counter_dev->dev;
 775         enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
 776         ni_660x_write_register(dev, counter->chip_index, bits,
 777                                ni_660x_register);
 778 }
 779
 780 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
 781                                       enum ni_gpct_register reg)
 782 {
 783         struct comedi_device *dev = counter->counter_dev->dev;
 784         enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
 785         return ni_660x_read_register(dev, counter->chip_index,
 786                                      ni_660x_register);
 787 }
 788
 789 static inline struct mite_dma_descriptor_ring *mite_ring(struct ni_660x_private
 790                                                          *priv,
 791                                                          struct ni_gpct
 792                                                          *counter)
 793 {
 794         return priv->mite_rings[counter->chip_index][counter->counter_index];
 795 }
 796
 797 static inline void ni_660x_set_dma_channel(struct comedi_device *dev,
 798                                            unsigned mite_channel,
 799                                            struct ni_gpct *counter)
 800 {
 801         unsigned long flags;
 802         spin_lock_irqsave(&private(dev)->soft_reg_copy_lock, flags);
 803         private(dev)->dma_configuration_soft_copies[counter->chip_index] &=
 804             ~dma_select_mask(mite_channel);
 805         private(dev)->dma_configuration_soft_copies[counter->chip_index] |=
 806             dma_select_bits(mite_channel,
 807                             dma_selection_counter(counter->counter_index));
 808         ni_660x_write_register(dev, counter->chip_index,
 809                                private(dev)->
 810                                dma_configuration_soft_copies
 811                                [counter->chip_index] |
 812                                dma_reset_bit(mite_channel), DMAConfigRegister);
 813         mmiowb();
 814         spin_unlock_irqrestore(&private(dev)->soft_reg_copy_lock, flags);
 815 }
 816
 817 static inline void ni_660x_unset_dma_channel(struct comedi_device *dev,
 818                                              unsigned mite_channel,
 819                                              struct ni_gpct *counter)
 820 {
 821         unsigned long flags;
 822         spin_lock_irqsave(&private(dev)->soft_reg_copy_lock, flags);
 823         private(dev)->dma_configuration_soft_copies[counter->chip_index] &=
 824             ~dma_select_mask(mite_channel);
 825         private(dev)->dma_configuration_soft_copies[counter->chip_index] |=
 826             dma_select_bits(mite_channel, dma_selection_none);
 827         ni_660x_write_register(dev, counter->chip_index,
 828                                private(dev)->
 829                                dma_configuration_soft_copies
 830                                [counter->chip_index], DMAConfigRegister);
 831         mmiowb();
 832         spin_unlock_irqrestore(&private(dev)->soft_reg_copy_lock, flags);
 833 }
 834
 835 static int ni_660x_request_mite_channel(struct comedi_device *dev,
 836                                         struct ni_gpct *counter,
 837                                         enum comedi_io_direction direction)
 838 {
 839         unsigned long flags;
 840         struct mite_channel *mite_chan;
 841
 842         spin_lock_irqsave(&private(dev)->mite_channel_lock, flags);
 843         BUG_ON(counter->mite_chan);
 844         mite_chan =
 845             mite_request_channel(private(dev)->mite, mite_ring(private(dev),
 846                                                                counter));
 847         if (mite_chan == NULL) {
 848                 spin_unlock_irqrestore(&private(dev)->mite_channel_lock, flags);
 849                 comedi_error(dev,
 850                              "failed to reserve mite dma channel for counter.");
 851                 return -EBUSY;
 852         }
 853         mite_chan->dir = direction;
 854         ni_tio_set_mite_channel(counter, mite_chan);
 855         ni_660x_set_dma_channel(dev, mite_chan->channel, counter);
 856         spin_unlock_irqrestore(&private(dev)->mite_channel_lock, flags);
 857         return 0;
 858 }
 859
 860 void ni_660x_release_mite_channel(struct comedi_device *dev,
 861                                   struct ni_gpct *counter)
 862 {
 863         unsigned long flags;
 864
 865         spin_lock_irqsave(&private(dev)->mite_channel_lock, flags);
 866         if (counter->mite_chan) {
 867                 struct mite_channel *mite_chan = counter->mite_chan;
 868
 869                 ni_660x_unset_dma_channel(dev, mite_chan->channel, counter);
 870                 ni_tio_set_mite_channel(counter, NULL);
 871                 mite_release_channel(mite_chan);
 872         }
 873         spin_unlock_irqrestore(&private(dev)->mite_channel_lock, flags);
 874 }
 875
 876 static int ni_660x_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
 877 {
 878         int retval;
 879
 880         struct ni_gpct *counter = subdev_to_counter(s);
 881 /* const struct comedi_cmd *cmd = &s->async->cmd; */
 882
 883         retval = ni_660x_request_mite_channel(dev, counter, COMEDI_INPUT);
 884         if (retval) {
 885                 comedi_error(dev,
 886                              "no dma channel available for use by counter");
 887                 return retval;
 888         }
 889         ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
 890         retval = ni_tio_cmd(counter, s->async);
 891
 892         return retval;
 893 }
 894
 895 static int ni_660x_cmdtest(struct comedi_device *dev,
 896                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
 897 {
 898         struct ni_gpct *counter = subdev_to_counter(s);
 899
 900         return ni_tio_cmdtest(counter, cmd);
 901 }
 902
 903 static int ni_660x_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
 904 {
 905         struct ni_gpct *counter = subdev_to_counter(s);
 906         int retval;
 907
 908         retval = ni_tio_cancel(counter);
 909         ni_660x_release_mite_channel(dev, counter);
 910         return retval;
 911 }
 912
 913 static void set_tio_counterswap(struct comedi_device *dev, int chipset)
 914 {
 915         /* See P. 3.5 of the Register-Level Programming manual.  The
 916            CounterSwap bit has to be set on the second chip, otherwise
 917            it will try to use the same pins as the first chip.
 918          */
 919         if (chipset)
 920                 ni_660x_write_register(dev, chipset, CounterSwap,
 921                                        ClockConfigRegister);
 922         else
 923                 ni_660x_write_register(dev, chipset, 0, ClockConfigRegister);
 924 }
 925
 926 static void ni_660x_handle_gpct_interrupt(struct comedi_device *dev,
 927                                           struct comedi_subdevice *s)
 928 {
 929         ni_tio_handle_interrupt(subdev_to_counter(s), s);
 930         if (s->async->events) {
 931                 if (s->async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR |
 932                                         COMEDI_CB_OVERFLOW)) {
 933                         ni_660x_cancel(dev, s);
 934                 }
 935                 comedi_event(dev, s);
 936         }
 937 }
 938
 939 static irqreturn_t ni_660x_interrupt(int irq, void *d)
 940 {
 941         struct comedi_device *dev = d;
 942         struct comedi_subdevice *s;
 943         unsigned i;
 944         unsigned long flags;
 945
 946         if (dev->attached == 0)
 947                 return IRQ_NONE;
 948         /* lock to avoid race with comedi_poll */
 949         spin_lock_irqsave(&private(dev)->interrupt_lock, flags);
 950         smp_mb();
 951         for (i = 0; i < ni_660x_num_counters(dev); ++i) {
 952                 s = dev->subdevices + NI_660X_GPCT_SUBDEV(i);
 953                 ni_660x_handle_gpct_interrupt(dev, s);
 954         }
 955         spin_unlock_irqrestore(&private(dev)->interrupt_lock, flags);
 956         return IRQ_HANDLED;
 957 }
 958
 959 static int ni_660x_input_poll(struct comedi_device *dev,
 960                               struct comedi_subdevice *s)
 961 {
 962         unsigned long flags;
 963         /* lock to avoid race with comedi_poll */
 964         spin_lock_irqsave(&private(dev)->interrupt_lock, flags);
 965         mite_sync_input_dma(subdev_to_counter(s)->mite_chan, s->async);
 966         spin_unlock_irqrestore(&private(dev)->interrupt_lock, flags);
 967         return comedi_buf_read_n_available(s->async);
 968 }
 969
 970 static int ni_660x_buf_change(struct comedi_device *dev,
 971                               struct comedi_subdevice *s,
 972                               unsigned long new_size)
 973 {
 974         int ret;
 975
 976         ret = mite_buf_change(mite_ring(private(dev), subdev_to_counter(s)),
 977                               s->async);
 978         if (ret < 0)
 979                 return ret;
 980
 981         return 0;
 982 }
 983
 984 static int ni_660x_allocate_private(struct comedi_device *dev)
 985 {
 986         int retval;
 987         unsigned i;
 988
 989         retval = alloc_private(dev, sizeof(struct ni_660x_private));
 990         if (retval < 0)
 991                 return retval;
 992
 993         spin_lock_init(&private(dev)->mite_channel_lock);
 994         spin_lock_init(&private(dev)->interrupt_lock);
 995         spin_lock_init(&private(dev)->soft_reg_copy_lock);
 996         for (i = 0; i < NUM_PFI_CHANNELS; ++i)
 997                 private(dev)->pfi_output_selects[i] = pfi_output_select_counter;
 998
 999         return 0;
1000 }
1001
1002 static int ni_660x_alloc_mite_rings(struct comedi_device *dev)
1003 {
1004         unsigned i;
1005         unsigned j;
1006
1007         for (i = 0; i < board(dev)->n_chips; ++i) {
1008                 for (j = 0; j < counters_per_chip; ++j) {
1009                         private(dev)->mite_rings[i][j] =
1010                             mite_alloc_ring(private(dev)->mite);
1011                         if (private(dev)->mite_rings[i][j] == NULL)
1012                                 return -ENOMEM;
1013                 }
1014         }
1015         return 0;
1016 }
1017
1018 static void ni_660x_free_mite_rings(struct comedi_device *dev)
1019 {
1020         unsigned i;
1021         unsigned j;
1022
1023         for (i = 0; i < board(dev)->n_chips; ++i) {
1024                 for (j = 0; j < counters_per_chip; ++j)
1025                         mite_free_ring(private(dev)->mite_rings[i][j]);
1026         }
1027 }
1028
1029 static int ni_660x_attach(struct comedi_device *dev,
1030                           struct comedi_devconfig *it)
1031 {
1032         struct comedi_subdevice *s;
1033         int ret;
1034         unsigned i;
1035         unsigned global_interrupt_config_bits;
1036
1037         printk(KERN_INFO "comedi%d: ni_660x: ", dev->minor);
1038
1039         ret = ni_660x_allocate_private(dev);
1040         if (ret < 0)
1041                 return ret;
1042         ret = ni_660x_find_device(dev, it->options[0], it->options[1]);
1043         if (ret < 0)
1044                 return ret;
1045
1046         dev->board_name = board(dev)->name;
1047
1048         ret = mite_setup2(private(dev)->mite, 1);
1049         if (ret < 0) {
1050                 printk(KERN_WARNING "error setting up mite\n");
1051                 return ret;
1052         }
1053         comedi_set_hw_dev(dev, &private(dev)->mite->pcidev->dev);
1054         ret = ni_660x_alloc_mite_rings(dev);
1055         if (ret < 0)
1056                 return ret;
1057
1058         printk(KERN_INFO " %s ", dev->board_name);
1059
1060         dev->n_subdevices = 2 + NI_660X_MAX_NUM_COUNTERS;
1061
1062         if (alloc_subdevices(dev, dev->n_subdevices) < 0)
1063                 return -ENOMEM;
1064
1065         s = dev->subdevices + 0;
1066         /* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */
1067         s->type = COMEDI_SUBD_UNUSED;
1068
1069         s = dev->subdevices + NI_660X_DIO_SUBDEV;
1070         /* DIGITAL I/O SUBDEVICE */
1071         s->type = COMEDI_SUBD_DIO;
1072         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1073         s->n_chan = NUM_PFI_CHANNELS;
1074         s->maxdata = 1;
1075         s->range_table = &range_digital;
1076         s->insn_bits = ni_660x_dio_insn_bits;
1077         s->insn_config = ni_660x_dio_insn_config;
1078         s->io_bits = 0;         /* all bits default to input */
1079         /*  we use the ioconfig registers to control dio direction, so zero
1080         output enables in stc dio control reg */
1081         ni_660x_write_register(dev, 0, 0, STCDIOControl);
1082
1083         private(dev)->counter_dev = ni_gpct_device_construct(dev,
1084                                                      &ni_gpct_write_register,
1085                                                      &ni_gpct_read_register,
1086                                                      ni_gpct_variant_660x,
1087                                                      ni_660x_num_counters
1088                                                      (dev));
1089         if (private(dev)->counter_dev == NULL)
1090                 return -ENOMEM;
1091         for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) {
1092                 s = dev->subdevices + NI_660X_GPCT_SUBDEV(i);
1093                 if (i < ni_660x_num_counters(dev)) {
1094                         s->type = COMEDI_SUBD_COUNTER;
1095                         s->subdev_flags =
1096                             SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL |
1097                             SDF_CMD_READ /* | SDF_CMD_WRITE */ ;
1098                         s->n_chan = 3;
1099                         s->maxdata = 0xffffffff;
1100                         s->insn_read = ni_660x_GPCT_rinsn;
1101                         s->insn_write = ni_660x_GPCT_winsn;
1102                         s->insn_config = ni_660x_GPCT_insn_config;
1103                         s->do_cmd = &ni_660x_cmd;
1104                         s->len_chanlist = 1;
1105                         s->do_cmdtest = &ni_660x_cmdtest;
1106                         s->cancel = &ni_660x_cancel;
1107                         s->poll = &ni_660x_input_poll;
1108                         s->async_dma_dir = DMA_BIDIRECTIONAL;
1109                         s->buf_change = &ni_660x_buf_change;
1110                         s->private = &private(dev)->counter_dev->counters[i];
1111
1112                         private(dev)->counter_dev->counters[i].chip_index =
1113                             i / counters_per_chip;
1114                         private(dev)->counter_dev->counters[i].counter_index =
1115                             i % counters_per_chip;
1116                 } else {
1117                         s->type = COMEDI_SUBD_UNUSED;
1118                 }
1119         }
1120         for (i = 0; i < board(dev)->n_chips; ++i)
1121                 init_tio_chip(dev, i);
1122
1123         for (i = 0; i < ni_660x_num_counters(dev); ++i)
1124                 ni_tio_init_counter(&private(dev)->counter_dev->counters[i]);
1125
1126         for (i = 0; i < NUM_PFI_CHANNELS; ++i) {
1127                 if (i < min_counter_pfi_chan)
1128                         ni_660x_set_pfi_routing(dev, i, pfi_output_select_do);
1129                 else
1130                         ni_660x_set_pfi_routing(dev, i,
1131                                                 pfi_output_select_counter);
1132                 ni_660x_select_pfi_output(dev, i, pfi_output_select_high_Z);
1133         }
1134         /* to be safe, set counterswap bits on tio chips after all the counter
1135            outputs have been set to high impedance mode */
1136         for (i = 0; i < board(dev)->n_chips; ++i)
1137                 set_tio_counterswap(dev, i);
1138
1139         ret = request_irq(mite_irq(private(dev)->mite), ni_660x_interrupt,
1140                           IRQF_SHARED, "ni_660x", dev);
1141         if (ret < 0) {
1142                 printk(KERN_WARNING " irq not available\n");
1143                 return ret;
1144         }
1145         dev->irq = mite_irq(private(dev)->mite);
1146         global_interrupt_config_bits = Global_Int_Enable_Bit;
1147         if (board(dev)->n_chips > 1)
1148                 global_interrupt_config_bits |= Cascade_Int_Enable_Bit;
1149         ni_660x_write_register(dev, 0, global_interrupt_config_bits,
1150                                GlobalInterruptConfigRegister);
1151         printk(KERN_INFO "attached\n");
1152         return 0;
1153 }
1154
1155 static int ni_660x_detach(struct comedi_device *dev)
1156 {
1157         printk(KERN_INFO "comedi%d: ni_660x: remove\n", dev->minor);
1158
1159         /* Free irq */
1160         if (dev->irq)
1161                 free_irq(dev->irq, dev);
1162
1163         if (dev->private) {
1164                 if (private(dev)->counter_dev)
1165                         ni_gpct_device_destroy(private(dev)->counter_dev);
1166                 if (private(dev)->mite) {
1167                         ni_660x_free_mite_rings(dev);
1168                         mite_unsetup(private(dev)->mite);
1169                 }
1170         }
1171         return 0;
1172 }
1173
1174 static int
1175 ni_660x_GPCT_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1176                    struct comedi_insn *insn, unsigned int *data)
1177 {
1178         return ni_tio_rinsn(subdev_to_counter(s), insn, data);
1179 }
1180
1181 static void init_tio_chip(struct comedi_device *dev, int chipset)
1182 {
1183         unsigned i;
1184
1185         /*  init dma configuration register */
1186         private(dev)->dma_configuration_soft_copies[chipset] = 0;
1187         for (i = 0; i < MAX_DMA_CHANNEL; ++i) {
1188                 private(dev)->dma_configuration_soft_copies[chipset] |=
1189                     dma_select_bits(i, dma_selection_none) & dma_select_mask(i);
1190         }
1191         ni_660x_write_register(dev, chipset,
1192                                private(dev)->
1193                                dma_configuration_soft_copies[chipset],
1194                                DMAConfigRegister);
1195         for (i = 0; i < NUM_PFI_CHANNELS; ++i)
1196                 ni_660x_write_register(dev, chipset, 0, IOConfigReg(i));
1197 }
1198
1199 static int
1200 ni_660x_GPCT_insn_config(struct comedi_device *dev, struct comedi_subdevice *s,
1201                          struct comedi_insn *insn, unsigned int *data)
1202 {
1203         return ni_tio_insn_config(subdev_to_counter(s), insn, data);
1204 }
1205
1206 static int ni_660x_GPCT_winsn(struct comedi_device *dev,
1207                               struct comedi_subdevice *s,
1208                               struct comedi_insn *insn, unsigned int *data)
1209 {
1210         return ni_tio_winsn(subdev_to_counter(s), insn, data);
1211 }
1212
1213 static int ni_660x_find_device(struct comedi_device *dev, int bus, int slot)
1214 {
1215         struct mite_struct *mite;
1216         int i;
1217
1218         for (mite = mite_devices; mite; mite = mite->next) {
1219                 if (mite->used)
1220                         continue;
1221                 if (bus || slot) {
1222                         if (bus != mite->pcidev->bus->number ||
1223                             slot != PCI_SLOT(mite->pcidev->devfn))
1224                                 continue;
1225                 }
1226
1227                 for (i = 0; i < n_ni_660x_boards; i++) {
1228                         if (mite_device_id(mite) == ni_660x_boards[i].dev_id) {
1229                                 dev->board_ptr = ni_660x_boards + i;
1230                                 private(dev)->mite = mite;
1231                                 return 0;
1232                         }
1233                 }
1234         }
1235         printk(KERN_WARNING "no device found\n");
1236         mite_list_devices();
1237         return -EIO;
1238 }
1239
1240 static int ni_660x_dio_insn_bits(struct comedi_device *dev,
1241                                  struct comedi_subdevice *s,
1242                                  struct comedi_insn *insn, unsigned int *data)
1243 {
1244         unsigned base_bitfield_channel = CR_CHAN(insn->chanspec);
1245
1246         /*  Check if we have to write some bits */
1247         if (data[0]) {
1248                 s->state &= ~(data[0] << base_bitfield_channel);
1249                 s->state |= (data[0] & data[1]) << base_bitfield_channel;
1250                 /* Write out the new digital output lines */
1251                 ni_660x_write_register(dev, 0, s->state, DIO32Output);
1252         }
1253         /* on return, data[1] contains the value of the digital
1254          * input and output lines. */
1255         data[1] =
1256             (ni_660x_read_register(dev, 0,
1257                                    DIO32Input) >> base_bitfield_channel);
1258         return 2;
1259 }
1260
1261 static void ni_660x_select_pfi_output(struct comedi_device *dev,
1262                                       unsigned pfi_channel,
1263                                       unsigned output_select)
1264 {
1265         static const unsigned counter_4_7_first_pfi = 8;
1266         static const unsigned counter_4_7_last_pfi = 23;
1267         unsigned active_chipset = 0;
1268         unsigned idle_chipset = 0;
1269         unsigned active_bits;
1270         unsigned idle_bits;
1271
1272         if (board(dev)->n_chips > 1) {
1273                 if (output_select == pfi_output_select_counter &&
1274                     pfi_channel >= counter_4_7_first_pfi &&
1275                     pfi_channel <= counter_4_7_last_pfi) {
1276                         active_chipset = 1;
1277                         idle_chipset = 0;
1278                 } else {
1279                         active_chipset = 0;
1280                         idle_chipset = 1;
1281                 }
1282         }
1283
1284         if (idle_chipset != active_chipset) {
1285                 idle_bits =
1286                     ni_660x_read_register(dev, idle_chipset,
1287                                           IOConfigReg(pfi_channel));
1288                 idle_bits &= ~pfi_output_select_mask(pfi_channel);
1289                 idle_bits |=
1290                     pfi_output_select_bits(pfi_channel,
1291                                            pfi_output_select_high_Z);
1292                 ni_660x_write_register(dev, idle_chipset, idle_bits,
1293                                        IOConfigReg(pfi_channel));
1294         }
1295
1296         active_bits =
1297             ni_660x_read_register(dev, active_chipset,
1298                                   IOConfigReg(pfi_channel));
1299         active_bits &= ~pfi_output_select_mask(pfi_channel);
1300         active_bits |= pfi_output_select_bits(pfi_channel, output_select);
1301         ni_660x_write_register(dev, active_chipset, active_bits,
1302                                IOConfigReg(pfi_channel));
1303 }
1304
1305 static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan,
1306                                    unsigned source)
1307 {
1308         if (source > num_pfi_output_selects)
1309                 return -EINVAL;
1310         if (source == pfi_output_select_high_Z)
1311                 return -EINVAL;
1312         if (chan < min_counter_pfi_chan) {
1313                 if (source == pfi_output_select_counter)
1314                         return -EINVAL;
1315         } else if (chan > max_dio_pfi_chan) {
1316                 if (source == pfi_output_select_do)
1317                         return -EINVAL;
1318         }
1319         BUG_ON(chan >= NUM_PFI_CHANNELS);
1320
1321         private(dev)->pfi_output_selects[chan] = source;
1322         if (private(dev)->pfi_direction_bits & (((uint64_t) 1) << chan))
1323                 ni_660x_select_pfi_output(dev, chan,
1324                                           private(dev)->
1325                                           pfi_output_selects[chan]);
1326         return 0;
1327 }
1328
1329 static unsigned ni_660x_get_pfi_routing(struct comedi_device *dev,
1330                                         unsigned chan)
1331 {
1332         BUG_ON(chan >= NUM_PFI_CHANNELS);
1333         return private(dev)->pfi_output_selects[chan];
1334 }
1335
1336 static void ni660x_config_filter(struct comedi_device *dev,
1337                                  unsigned pfi_channel,
1338                                  enum ni_gpct_filter_select filter)
1339 {
1340         unsigned bits = ni_660x_read_register(dev, 0, IOConfigReg(pfi_channel));
1341         bits &= ~pfi_input_select_mask(pfi_channel);
1342         bits |= pfi_input_select_bits(pfi_channel, filter);
1343         ni_660x_write_register(dev, 0, bits, IOConfigReg(pfi_channel));
1344 }
1345
1346 static int ni_660x_dio_insn_config(struct comedi_device *dev,
1347                                    struct comedi_subdevice *s,
1348                                    struct comedi_insn *insn, unsigned int *data)
1349 {
1350         int chan = CR_CHAN(insn->chanspec);
1351
1352         /* The input or output configuration of each digital line is
1353          * configured by a special insn_config instruction.  chanspec
1354          * contains the channel to be changed, and data[0] contains the
1355          * value COMEDI_INPUT or COMEDI_OUTPUT. */
1356
1357         switch (data[0]) {
1358         case INSN_CONFIG_DIO_OUTPUT:
1359                 private(dev)->pfi_direction_bits |= ((uint64_t) 1) << chan;
1360                 ni_660x_select_pfi_output(dev, chan,
1361                                           private(dev)->
1362                                           pfi_output_selects[chan]);
1363                 break;
1364         case INSN_CONFIG_DIO_INPUT:
1365                 private(dev)->pfi_direction_bits &= ~(((uint64_t) 1) << chan);
1366                 ni_660x_select_pfi_output(dev, chan, pfi_output_select_high_Z);
1367                 break;
1368         case INSN_CONFIG_DIO_QUERY:
1369                 data[1] =
1370                     (private(dev)->pfi_direction_bits &
1371                      (((uint64_t) 1) << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
1372                 return 0;
1373         case INSN_CONFIG_SET_ROUTING:
1374                 return ni_660x_set_pfi_routing(dev, chan, data[1]);
1375                 break;
1376         case INSN_CONFIG_GET_ROUTING:
1377                 data[1] = ni_660x_get_pfi_routing(dev, chan);
1378                 break;
1379         case INSN_CONFIG_FILTER:
1380                 ni660x_config_filter(dev, chan, data[1]);
1381                 break;
1382         default:
1383                 return -EINVAL;
1384                 break;
1385         };
1386         return 0;
1387 }