drivers/staging/comedi/drivers/mite.c

   1 /*
   2     comedi/drivers/mite.c
   3     Hardware driver for NI Mite PCI interface chip
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21
  22 */
  23
  24 /*
  25         The PCI-MIO E series driver was originally written by
  26         Tomasz Motylewski <...>, and ported to comedi by ds.
  27
  28         References for specifications:
  29
  30            321747b.pdf  Register Level Programmer Manual (obsolete)
  31            321747c.pdf  Register Level Programmer Manual (new)
  32            DAQ-STC reference manual
  33
  34         Other possibly relevant info:
  35
  36            320517c.pdf  User manual (obsolete)
  37            320517f.pdf  User manual (new)
  38            320889a.pdf  delete
  39            320906c.pdf  maximum signal ratings
  40            321066a.pdf  about 16x
  41            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  42            321808a.pdf  about at-mio-16e-10 rev P
  43            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  44            321838a.pdf  about at-mio-16de-10 rev N
  45
  46         ISSUES:
  47
  48 */
  49
  50 /* #define USE_KMALLOC */
  51
  52 #include "mite.h"
  53
  54 #include "comedi_fc.h"
  55 #include "comedi_pci.h"
  56 #include "../comedidev.h"
  57
  58 #include <asm/system.h>
  59
  60 #define PCI_MITE_SIZE           4096
  61 #define PCI_DAQ_SIZE            4096
  62 #define PCI_DAQ_SIZE_660X       8192
  63
  64 MODULE_LICENSE("GPL");
  65
  66 struct mite_struct *mite_devices;
  67 EXPORT_SYMBOL(mite_devices);
  68
  69 #define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
  70
  71 void mite_init(void)
  72 {
  73         struct pci_dev *pcidev;
  74         struct mite_struct *mite;
  75
  76         for (pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, NULL);
  77              pcidev != NULL;
  78              pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pcidev)) {
  79                 if (pcidev->vendor == PCI_VENDOR_ID_NI) {
  80                         unsigned i;
  81
  82                         mite = kzalloc(sizeof(*mite), GFP_KERNEL);
  83                         if (!mite) {
  84                                 printk(KERN_ERR "mite: allocation failed\n");
  85                                 pci_dev_put(pcidev);
  86                                 return;
  87                         }
  88                         spin_lock_init(&mite->lock);
  89                         mite->pcidev = pci_dev_get(pcidev);
  90                         for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
  91                                 mite->channels[i].mite = mite;
  92                                 mite->channels[i].channel = i;
  93                                 mite->channels[i].done = 1;
  94                         }
  95                         mite->next = mite_devices;
  96                         mite_devices = mite;
  97                 }
  98         }
  99 }
 100
 101 static void dump_chip_signature(u32 csigr_bits)
 102 {
 103         printk(KERN_INFO "mite: version = %i, type = %i, mite mode = %i,"
 104                "interface mode = %i\n",
 105                mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
 106                mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
 107         printk(KERN_INFO "mite: num channels = %i, write post fifo depth = %i,"
 108                "wins = %i, iowins = %i\n",
 109                mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
 110                mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
 111 }
 112
 113 unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
 114 {
 115         unsigned fcr_bits = readl(mite->mite_io_addr + MITE_FCR(channel));
 116         unsigned empty_count = (fcr_bits >> 16) & 0xff;
 117         unsigned full_count = fcr_bits & 0xff;
 118         return empty_count + full_count;
 119 }
 120
 121 int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
 122 {
 123         unsigned long length;
 124         resource_size_t addr;
 125         int i;
 126         u32 csigr_bits;
 127         unsigned unknown_dma_burst_bits;
 128
 129         if (comedi_pci_enable(mite->pcidev, "mite")) {
 130                 printk(KERN_ERR "error enabling mite and requesting io regions\n");
 131                 return -EIO;
 132         }
 133         pci_set_master(mite->pcidev);
 134
 135         addr = pci_resource_start(mite->pcidev, 0);
 136         mite->mite_phys_addr = addr;
 137         mite->mite_io_addr = ioremap(addr, PCI_MITE_SIZE);
 138         if (!mite->mite_io_addr) {
 139                 printk(KERN_ERR "Failed to remap mite io memory address\n");
 140                 return -ENOMEM;
 141         }
 142         printk(KERN_INFO "MITE:0x%08llx mapped to %p ",
 143                (unsigned long long)mite->mite_phys_addr, mite->mite_io_addr);
 144
 145         addr = pci_resource_start(mite->pcidev, 1);
 146         mite->daq_phys_addr = addr;
 147         length = pci_resource_len(mite->pcidev, 1);
 148         /*
 149          * In case of a 660x board, DAQ size is 8k instead of 4k
 150          * (see as shown by lspci output)
 151          */
 152         mite->daq_io_addr = ioremap(mite->daq_phys_addr, length);
 153         if (!mite->daq_io_addr) {
 154                 printk(KERN_ERR "Failed to remap daq io memory address\n");
 155                 return -ENOMEM;
 156         }
 157         printk(KERN_INFO "DAQ:0x%08llx mapped to %p\n",
 158                (unsigned long long)mite->daq_phys_addr, mite->daq_io_addr);
 159
 160         if (use_iodwbsr_1) {
 161                 writel(0, mite->mite_io_addr + MITE_IODWBSR);
 162                 printk(KERN_INFO "mite: using I/O Window Base Size register 1\n");
 163                 writel(mite->daq_phys_addr | WENAB |
 164                        MITE_IODWBSR_1_WSIZE_bits(length),
 165                        mite->mite_io_addr + MITE_IODWBSR_1);
 166                 writel(0, mite->mite_io_addr + MITE_IODWCR_1);
 167         } else {
 168                 writel(mite->daq_phys_addr | WENAB,
 169                        mite->mite_io_addr + MITE_IODWBSR);
 170         }
 171         /*
 172          * make sure dma bursts work. I got this from running a bus analyzer
 173          * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
 174          * of 0x61f and bursts worked. 6281 powered up with register value of
 175          * 0x1f and bursts didn't work. The NI windows driver reads the
 176          * register, then does a bitwise-or of 0x600 with it and writes it back.
 177          */
 178         unknown_dma_burst_bits =
 179             readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
 180         unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
 181         writel(unknown_dma_burst_bits,
 182                mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
 183
 184         csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
 185         mite->num_channels = mite_csigr_dmac(csigr_bits);
 186         if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
 187                 printk(KERN_WARNING "mite: bug? chip claims to have %i dma "
 188                        "channels. Setting to %i.\n",
 189                        mite->num_channels, MAX_MITE_DMA_CHANNELS);
 190                 mite->num_channels = MAX_MITE_DMA_CHANNELS;
 191         }
 192         dump_chip_signature(csigr_bits);
 193         for (i = 0; i < mite->num_channels; i++) {
 194                 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i));
 195                 /* disable interrupts */
 196                 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
 197                        CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
 198                        CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
 199                        mite->mite_io_addr + MITE_CHCR(i));
 200         }
 201         mite->fifo_size = mite_fifo_size(mite, 0);
 202         printk(KERN_INFO "mite: fifo size is %i.\n", mite->fifo_size);
 203         mite->used = 1;
 204
 205         return 0;
 206 }
 207 EXPORT_SYMBOL(mite_setup2);
 208
 209 int mite_setup(struct mite_struct *mite)
 210 {
 211         return mite_setup2(mite, 0);
 212 }
 213 EXPORT_SYMBOL(mite_setup);
 214
 215 void mite_cleanup(void)
 216 {
 217         struct mite_struct *mite, *next;
 218
 219         for (mite = mite_devices; mite; mite = next) {
 220                 pci_dev_put(mite->pcidev);
 221                 next = mite->next;
 222                 kfree(mite);
 223         }
 224 }
 225
 226 void mite_unsetup(struct mite_struct *mite)
 227 {
 228         /* unsigned long offset, start, length; */
 229
 230         if (!mite)
 231                 return;
 232
 233         if (mite->mite_io_addr) {
 234                 iounmap(mite->mite_io_addr);
 235                 mite->mite_io_addr = NULL;
 236         }
 237         if (mite->daq_io_addr) {
 238                 iounmap(mite->daq_io_addr);
 239                 mite->daq_io_addr = NULL;
 240         }
 241         if (mite->mite_phys_addr) {
 242                 comedi_pci_disable(mite->pcidev);
 243                 mite->mite_phys_addr = 0;
 244         }
 245
 246         mite->used = 0;
 247 }
 248 EXPORT_SYMBOL(mite_unsetup);
 249
 250 void mite_list_devices(void)
 251 {
 252         struct mite_struct *mite, *next;
 253
 254         printk(KERN_INFO "Available NI device IDs:");
 255         if (mite_devices)
 256                 for (mite = mite_devices; mite; mite = next) {
 257                         next = mite->next;
 258                         printk(KERN_INFO " 0x%04x", mite_device_id(mite));
 259                         if (mite->used)
 260                                 printk(KERN_INFO "(used)");
 261                 }
 262         printk(KERN_INFO "\n");
 263 }
 264 EXPORT_SYMBOL(mite_list_devices);
 265
 266 struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
 267                                                    struct
 268                                                    mite_dma_descriptor_ring
 269                                                    *ring, unsigned min_channel,
 270                                                    unsigned max_channel)
 271 {
 272         int i;
 273         unsigned long flags;
 274         struct mite_channel *channel = NULL;
 275
 276         /* spin lock so mite_release_channel can be called safely
 277          * from interrupts
 278          */
 279         spin_lock_irqsave(&mite->lock, flags);
 280         for (i = min_channel; i <= max_channel; ++i) {
 281                 if (mite->channel_allocated[i] == 0) {
 282                         mite->channel_allocated[i] = 1;
 283                         channel = &mite->channels[i];
 284                         channel->ring = ring;
 285                         break;
 286                 }
 287         }
 288         spin_unlock_irqrestore(&mite->lock, flags);
 289         return channel;
 290 }
 291 EXPORT_SYMBOL(mite_request_channel_in_range);
 292
 293 void mite_release_channel(struct mite_channel *mite_chan)
 294 {
 295         struct mite_struct *mite = mite_chan->mite;
 296         unsigned long flags;
 297
 298         /*  spin lock to prevent races with mite_request_channel */
 299         spin_lock_irqsave(&mite->lock, flags);
 300         if (mite->channel_allocated[mite_chan->channel]) {
 301                 mite_dma_disarm(mite_chan);
 302                 mite_dma_reset(mite_chan);
 303         /*
 304          * disable all channel's interrupts (do it after disarm/reset so
 305          * MITE_CHCR reg isn't changed while dma is still active!)
 306          */
 307                 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
 308                        CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
 309                        CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
 310                        CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
 311                        mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
 312                 mite->channel_allocated[mite_chan->channel] = 0;
 313                 mite_chan->ring = NULL;
 314                 mmiowb();
 315         }
 316         spin_unlock_irqrestore(&mite->lock, flags);
 317 }
 318 EXPORT_SYMBOL(mite_release_channel);
 319
 320 void mite_dma_arm(struct mite_channel *mite_chan)
 321 {
 322         struct mite_struct *mite = mite_chan->mite;
 323         int chor;
 324         unsigned long flags;
 325
 326         MDPRINTK("mite_dma_arm ch%i\n", channel);
 327         /*
 328          * memory barrier is intended to insure any twiddling with the buffer
 329          * is done before writing to the mite to arm dma transfer
 330          */
 331         smp_mb();
 332         /* arm */
 333         chor = CHOR_START;
 334         spin_lock_irqsave(&mite->lock, flags);
 335         mite_chan->done = 0;
 336         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 337         mmiowb();
 338         spin_unlock_irqrestore(&mite->lock, flags);
 339 /*       mite_dma_tcr(mite, channel); */
 340 }
 341 EXPORT_SYMBOL(mite_dma_arm);
 342
 343 /**************************************/
 344
 345 int mite_buf_change(struct mite_dma_descriptor_ring *ring,
 346                     struct comedi_async *async)
 347 {
 348         unsigned int n_links;
 349         int i;
 350
 351         if (ring->descriptors) {
 352                 dma_free_coherent(ring->hw_dev,
 353                                   ring->n_links *
 354                                   sizeof(struct mite_dma_descriptor),
 355                                   ring->descriptors,
 356                                   ring->descriptors_dma_addr);
 357         }
 358         ring->descriptors = NULL;
 359         ring->descriptors_dma_addr = 0;
 360         ring->n_links = 0;
 361
 362         if (async->prealloc_bufsz == 0)
 363                 return 0;
 364
 365         n_links = async->prealloc_bufsz >> PAGE_SHIFT;
 366
 367         MDPRINTK("ring->hw_dev=%p, n_links=0x%04x\n", ring->hw_dev, n_links);
 368
 369         ring->descriptors =
 370             dma_alloc_coherent(ring->hw_dev,
 371                                n_links * sizeof(struct mite_dma_descriptor),
 372                                &ring->descriptors_dma_addr, GFP_KERNEL);
 373         if (!ring->descriptors) {
 374                 printk(KERN_ERR "mite: ring buffer allocation failed\n");
 375                 return -ENOMEM;
 376         }
 377         ring->n_links = n_links;
 378
 379         for (i = 0; i < n_links; i++) {
 380                 ring->descriptors[i].count = cpu_to_le32(PAGE_SIZE);
 381                 ring->descriptors[i].addr =
 382                     cpu_to_le32(async->buf_page_list[i].dma_addr);
 383                 ring->descriptors[i].next =
 384                     cpu_to_le32(ring->descriptors_dma_addr + (i +
 385                                                               1) *
 386                                 sizeof(struct mite_dma_descriptor));
 387         }
 388         ring->descriptors[n_links - 1].next =
 389             cpu_to_le32(ring->descriptors_dma_addr);
 390         /*
 391          * barrier is meant to insure that all the writes to the dma descriptors
 392          * have completed before the dma controller is commanded to read them
 393          */
 394         smp_wmb();
 395         return 0;
 396 }
 397 EXPORT_SYMBOL(mite_buf_change);
 398
 399 void mite_prep_dma(struct mite_channel *mite_chan,
 400                    unsigned int num_device_bits, unsigned int num_memory_bits)
 401 {
 402         unsigned int chor, chcr, mcr, dcr, lkcr;
 403         struct mite_struct *mite = mite_chan->mite;
 404
 405         MDPRINTK("mite_prep_dma ch%i\n", mite_chan->channel);
 406
 407         /* reset DMA and FIFO */
 408         chor = CHOR_DMARESET | CHOR_FRESET;
 409         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 410
 411         /* short link chaining mode */
 412         chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
 413             CHCR_BURSTEN;
 414         /*
 415          * Link Complete Interrupt: interrupt every time a link
 416          * in MITE_RING is completed. This can generate a lot of
 417          * extra interrupts, but right now we update the values
 418          * of buf_int_ptr and buf_int_count at each interrupt. A
 419          * better method is to poll the MITE before each user
 420          * "read()" to calculate the number of bytes available.
 421          */
 422         chcr |= CHCR_SET_LC_IE;
 423         if (num_memory_bits == 32 && num_device_bits == 16) {
 424                 /*
 425                  * Doing a combined 32 and 16 bit byteswap gets the 16 bit
 426                  * samples into the fifo in the right order. Tested doing 32 bit
 427                  * memory to 16 bit device transfers to the analog out of a
 428                  * pxi-6281, which has mite version = 1, type = 4. This also
 429                  * works for dma reads from the counters on e-series boards.
 430                  */
 431                 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
 432         }
 433         if (mite_chan->dir == COMEDI_INPUT)
 434                 chcr |= CHCR_DEV_TO_MEM;
 435
 436         writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel));
 437
 438         /* to/from memory */
 439         mcr = CR_RL(64) | CR_ASEQUP;
 440         switch (num_memory_bits) {
 441         case 8:
 442                 mcr |= CR_PSIZE8;
 443                 break;
 444         case 16:
 445                 mcr |= CR_PSIZE16;
 446                 break;
 447         case 32:
 448                 mcr |= CR_PSIZE32;
 449                 break;
 450         default:
 451                 printk(KERN_WARNING "mite: bug! invalid mem bit width for dma "
 452                        "transfer\n");
 453                 break;
 454         }
 455         writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
 456
 457         /* from/to device */
 458         dcr = CR_RL(64) | CR_ASEQUP;
 459         dcr |= CR_PORTIO | CR_AMDEVICE | CR_REQSDRQ(mite_chan->channel);
 460         switch (num_device_bits) {
 461         case 8:
 462                 dcr |= CR_PSIZE8;
 463                 break;
 464         case 16:
 465                 dcr |= CR_PSIZE16;
 466                 break;
 467         case 32:
 468                 dcr |= CR_PSIZE32;
 469                 break;
 470         default:
 471                 printk(KERN_WARNING "mite: bug! invalid dev bit width for dma "
 472                        "transfer\n");
 473                 break;
 474         }
 475         writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
 476
 477         /* reset the DAR */
 478         writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel));
 479
 480         /* the link is 32bits */
 481         lkcr = CR_RL(64) | CR_ASEQUP | CR_PSIZE32;
 482         writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel));
 483
 484         /* starting address for link chaining */
 485         writel(mite_chan->ring->descriptors_dma_addr,
 486                mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
 487
 488         MDPRINTK("exit mite_prep_dma\n");
 489 }
 490 EXPORT_SYMBOL(mite_prep_dma);
 491
 492 u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
 493 {
 494         struct mite_struct *mite = mite_chan->mite;
 495         return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
 496 }
 497
 498 u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
 499 {
 500         struct mite_struct *mite = mite_chan->mite;
 501         return readl(mite->mite_io_addr +
 502                      MITE_FCR(mite_chan->channel)) & 0x000000FF;
 503 }
 504 EXPORT_SYMBOL(mite_bytes_in_transit);
 505
 506 /* returns lower bound for number of bytes transferred from device to memory */
 507 u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
 508 {
 509         u32 device_byte_count;
 510
 511         device_byte_count = mite_device_bytes_transferred(mite_chan);
 512         return device_byte_count - mite_bytes_in_transit(mite_chan);
 513 }
 514 EXPORT_SYMBOL(mite_bytes_written_to_memory_lb);
 515
 516 /* returns upper bound for number of bytes transferred from device to memory */
 517 u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
 518 {
 519         u32 in_transit_count;
 520
 521         in_transit_count = mite_bytes_in_transit(mite_chan);
 522         return mite_device_bytes_transferred(mite_chan) - in_transit_count;
 523 }
 524 EXPORT_SYMBOL(mite_bytes_written_to_memory_ub);
 525
 526 /* returns lower bound for number of bytes read from memory to device */
 527 u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
 528 {
 529         u32 device_byte_count;
 530
 531         device_byte_count = mite_device_bytes_transferred(mite_chan);
 532         return device_byte_count + mite_bytes_in_transit(mite_chan);
 533 }
 534 EXPORT_SYMBOL(mite_bytes_read_from_memory_lb);
 535
 536 /* returns upper bound for number of bytes read from memory to device */
 537 u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
 538 {
 539         u32 in_transit_count;
 540
 541         in_transit_count = mite_bytes_in_transit(mite_chan);
 542         return mite_device_bytes_transferred(mite_chan) + in_transit_count;
 543 }
 544 EXPORT_SYMBOL(mite_bytes_read_from_memory_ub);
 545
 546 unsigned mite_dma_tcr(struct mite_channel *mite_chan)
 547 {
 548         struct mite_struct *mite = mite_chan->mite;
 549         int tcr;
 550         int lkar;
 551
 552         lkar = readl(mite->mite_io_addr + MITE_LKAR(mite_chan->channel));
 553         tcr = readl(mite->mite_io_addr + MITE_TCR(mite_chan->channel));
 554         MDPRINTK("mite_dma_tcr ch%i, lkar=0x%08x tcr=%d\n", mite_chan->channel,
 555                  lkar, tcr);
 556
 557         return tcr;
 558 }
 559 EXPORT_SYMBOL(mite_dma_tcr);
 560
 561 void mite_dma_disarm(struct mite_channel *mite_chan)
 562 {
 563         struct mite_struct *mite = mite_chan->mite;
 564         unsigned chor;
 565
 566         /* disarm */
 567         chor = CHOR_ABORT;
 568         writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 569 }
 570 EXPORT_SYMBOL(mite_dma_disarm);
 571
 572 int mite_sync_input_dma(struct mite_channel *mite_chan,
 573                         struct comedi_async *async)
 574 {
 575         int count;
 576         unsigned int nbytes, old_alloc_count;
 577         const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice);
 578
 579         old_alloc_count = async->buf_write_alloc_count;
 580         /* write alloc as much as we can */
 581         comedi_buf_write_alloc(async, async->prealloc_bufsz);
 582
 583         nbytes = mite_bytes_written_to_memory_lb(mite_chan);
 584         if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
 585                   old_alloc_count) > 0) {
 586                 printk("mite: DMA overwrite of free area\n");
 587                 async->events |= COMEDI_CB_OVERFLOW;
 588                 return -1;
 589         }
 590
 591         count = nbytes - async->buf_write_count;
 592         /* it's possible count will be negative due to
 593          * conservative value returned by mite_bytes_written_to_memory_lb */
 594         if (count <= 0)
 595                 return 0;
 596
 597         comedi_buf_write_free(async, count);
 598
 599         async->scan_progress += count;
 600         if (async->scan_progress >= bytes_per_scan) {
 601                 async->scan_progress %= bytes_per_scan;
 602                 async->events |= COMEDI_CB_EOS;
 603         }
 604         async->events |= COMEDI_CB_BLOCK;
 605         return 0;
 606 }
 607 EXPORT_SYMBOL(mite_sync_input_dma);
 608
 609 int mite_sync_output_dma(struct mite_channel *mite_chan,
 610                          struct comedi_async *async)
 611 {
 612         int count;
 613         u32 nbytes_ub, nbytes_lb;
 614         unsigned int old_alloc_count;
 615         u32 stop_count =
 616             async->cmd.stop_arg * cfc_bytes_per_scan(async->subdevice);
 617
 618         old_alloc_count = async->buf_read_alloc_count;
 619         /*  read alloc as much as we can */
 620         comedi_buf_read_alloc(async, async->prealloc_bufsz);
 621         nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan);
 622         if (async->cmd.stop_src == TRIG_COUNT &&
 623             (int)(nbytes_lb - stop_count) > 0)
 624                 nbytes_lb = stop_count;
 625         nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan);
 626         if (async->cmd.stop_src == TRIG_COUNT &&
 627             (int)(nbytes_ub - stop_count) > 0)
 628                 nbytes_ub = stop_count;
 629         if ((int)(nbytes_ub - old_alloc_count) > 0) {
 630                 printk(KERN_ERR "mite: DMA underrun\n");
 631                 async->events |= COMEDI_CB_OVERFLOW;
 632                 return -1;
 633         }
 634         count = nbytes_lb - async->buf_read_count;
 635         if (count <= 0)
 636                 return 0;
 637
 638         if (count) {
 639                 comedi_buf_read_free(async, count);
 640                 async->events |= COMEDI_CB_BLOCK;
 641         }
 642         return 0;
 643 }
 644 EXPORT_SYMBOL(mite_sync_output_dma);
 645
 646 unsigned mite_get_status(struct mite_channel *mite_chan)
 647 {
 648         struct mite_struct *mite = mite_chan->mite;
 649         unsigned status;
 650         unsigned long flags;
 651
 652         spin_lock_irqsave(&mite->lock, flags);
 653         status = readl(mite->mite_io_addr + MITE_CHSR(mite_chan->channel));
 654         if (status & CHSR_DONE) {
 655                 mite_chan->done = 1;
 656                 writel(CHOR_CLRDONE,
 657                        mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
 658         }
 659         mmiowb();
 660         spin_unlock_irqrestore(&mite->lock, flags);
 661         return status;
 662 }
 663 EXPORT_SYMBOL(mite_get_status);
 664
 665 int mite_done(struct mite_channel *mite_chan)
 666 {
 667         struct mite_struct *mite = mite_chan->mite;
 668         unsigned long flags;
 669         int done;
 670
 671         mite_get_status(mite_chan);
 672         spin_lock_irqsave(&mite->lock, flags);
 673         done = mite_chan->done;
 674         spin_unlock_irqrestore(&mite->lock, flags);
 675         return done;
 676 }
 677 EXPORT_SYMBOL(mite_done);
 678
 679 #ifdef DEBUG_MITE
 680
 681 static void mite_decode(char **bit_str, unsigned int bits);
 682
 683 /* names of bits in mite registers */
 684
 685 static const char *const mite_CHOR_strings[] = {
 686         "start", "cont", "stop", "abort",
 687         "freset", "clrlc", "clrrb", "clrdone",
 688         "clr_lpause", "set_lpause", "clr_send_tc",
 689         "set_send_tc", "12", "13", "14",
 690         "15", "16", "17", "18",
 691         "19", "20", "21", "22",
 692         "23", "24", "25", "26",
 693         "27", "28", "29", "30",
 694         "dmareset",
 695 };
 696
 697 static const char *const mite_CHCR_strings[] = {
 698         "continue", "ringbuff", "2", "3",
 699         "4", "5", "6", "7",
 700         "8", "9", "10", "11",
 701         "12", "13", "bursten", "fifodis",
 702         "clr_cont_rb_ie", "set_cont_rb_ie", "clr_lc_ie", "set_lc_ie",
 703         "clr_drdy_ie", "set_drdy_ie", "clr_mrdy_ie", "set_mrdy_ie",
 704         "clr_done_ie", "set_done_ie", "clr_sar_ie", "set_sar_ie",
 705         "clr_linkp_ie", "set_linkp_ie", "clr_dma_ie", "set_dma_ie",
 706 };
 707
 708 static const char *const mite_MCR_strings[] = {
 709         "amdevice", "1", "2", "3",
 710         "4", "5", "portio", "portvxi",
 711         "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "11",
 712         "12", "13", "blocken", "berhand",
 713         "reqsintlim/reqs0", "reqs1", "reqs2", "rd32",
 714         "rd512", "rl1", "rl2", "rl8",
 715         "24", "25", "26", "27",
 716         "28", "29", "30", "stopen",
 717 };
 718
 719 static const char *const mite_DCR_strings[] = {
 720         "amdevice", "1", "2", "3",
 721         "4", "5", "portio", "portvxi",
 722         "psizebyte", "psizehalf (byte & half = word)", "aseqxp1", "aseqxp2",
 723         "aseqxp8", "13", "blocken", "berhand",
 724         "reqsintlim", "reqs1", "reqs2", "rd32",
 725         "rd512", "rl1", "rl2", "rl8",
 726         "23", "24", "25", "27",
 727         "28", "wsdevc", "wsdevs", "rwdevpack",
 728 };
 729
 730 static const char *const mite_LKCR_strings[] = {
 731         "amdevice", "1", "2", "3",
 732         "4", "5", "portio", "portvxi",
 733         "psizebyte", "psizehalf (byte & half = word)", "asequp", "aseqdown",
 734         "12", "13", "14", "berhand",
 735         "16", "17", "18", "rd32",
 736         "rd512", "rl1", "rl2", "rl8",
 737         "24", "25", "26", "27",
 738         "28", "29", "30", "chngend",
 739 };
 740
 741 static const char *const mite_CHSR_strings[] = {
 742         "d.err0", "d.err1", "m.err0", "m.err1",
 743         "l.err0", "l.err1", "drq0", "drq1",
 744         "end", "xferr", "operr0", "operr1",
 745         "stops", "habort", "sabort", "error",
 746         "16", "conts_rb", "18", "linkc",
 747         "20", "drdy", "22", "mrdy",
 748         "24", "done", "26", "sars",
 749         "28", "lpauses", "30", "int",
 750 };
 751
 752 void mite_dump_regs(struct mite_channel *mite_chan)
 753 {
 754         unsigned long mite_io_addr =
 755             (unsigned long)mite_chan->mite->mite_io_addr;
 756         unsigned long addr = 0;
 757         unsigned long temp = 0;
 758
 759         printk(KERN_DEBUG "mite_dump_regs ch%i\n", mite_chan->channel);
 760         printk(KERN_DEBUG "mite address is  =0x%08lx\n", mite_io_addr);
 761
 762         addr = mite_io_addr + MITE_CHOR(channel);
 763         printk(KERN_DEBUG "mite status[CHOR]at 0x%08lx =0x%08lx\n", addr,
 764                temp = readl(addr));
 765         mite_decode(mite_CHOR_strings, temp);
 766         addr = mite_io_addr + MITE_CHCR(channel);
 767         printk(KERN_DEBUG "mite status[CHCR]at 0x%08lx =0x%08lx\n", addr,
 768                temp = readl(addr));
 769         mite_decode(mite_CHCR_strings, temp);
 770         addr = mite_io_addr + MITE_TCR(channel);
 771         printk(KERN_DEBUG "mite status[TCR] at 0x%08lx =0x%08x\n", addr,
 772                readl(addr));
 773         addr = mite_io_addr + MITE_MCR(channel);
 774         printk(KERN_DEBUG "mite status[MCR] at 0x%08lx =0x%08lx\n", addr,
 775                temp = readl(addr));
 776         mite_decode(mite_MCR_strings, temp);
 777
 778         addr = mite_io_addr + MITE_MAR(channel);
 779         printk(KERN_DEBUG "mite status[MAR] at 0x%08lx =0x%08x\n", addr,
 780                readl(addr));
 781         addr = mite_io_addr + MITE_DCR(channel);
 782         printk(KERN_DEBUG "mite status[DCR] at 0x%08lx =0x%08lx\n", addr,
 783                temp = readl(addr));
 784         mite_decode(mite_DCR_strings, temp);
 785         addr = mite_io_addr + MITE_DAR(channel);
 786         printk(KERN_DEBUG "mite status[DAR] at 0x%08lx =0x%08x\n", addr,
 787                readl(addr));
 788         addr = mite_io_addr + MITE_LKCR(channel);
 789         printk(KERN_DEBUG "mite status[LKCR]at 0x%08lx =0x%08lx\n", addr,
 790                temp = readl(addr));
 791         mite_decode(mite_LKCR_strings, temp);
 792         addr = mite_io_addr + MITE_LKAR(channel);
 793         printk(KERN_DEBUG "mite status[LKAR]at 0x%08lx =0x%08x\n", addr,
 794                readl(addr));
 795         addr = mite_io_addr + MITE_CHSR(channel);
 796         printk(KERN_DEBUG "mite status[CHSR]at 0x%08lx =0x%08lx\n", addr,
 797                temp = readl(addr));
 798         mite_decode(mite_CHSR_strings, temp);
 799         addr = mite_io_addr + MITE_FCR(channel);
 800         printk(KERN_DEBUG "mite status[FCR] at 0x%08lx =0x%08x\n\n", addr,
 801                readl(addr));
 802 }
 803 EXPORT_SYMBOL(mite_dump_regs);
 804
 805 static void mite_decode(char **bit_str, unsigned int bits)
 806 {
 807         int i;
 808
 809         for (i = 31; i >= 0; i--) {
 810                 if (bits & (1 << i))
 811                         printk(KERN_DEBUG " %s", bit_str[i]);
 812         }
 813         printk(KERN_DEBUG "\n");
 814 }
 815 EXPORT_SYMBOL(mite_decode);
 816 #endif
 817
 818 #ifdef MODULE
 819 int __init init_module(void)
 820 {
 821         mite_init();
 822         mite_list_devices();
 823
 824         return 0;
 825 }
 826
 827 void __exit cleanup_module(void)
 828 {
 829         mite_cleanup();
 830 }
 831 #endif