2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/kernel.h>
18 #include <linux/string.h>
28 #include <pcie_core.h>
39 #include <sbsdpcmdev.h>
44 /* this file now contains only definitions for sb functions, only necessary
45 *for devices using Sonics backplanes (bcm4329)
48 /* if an amba SDIO device is supported, please further restrict the inclusion
52 #include "siutils_priv.h"
55 /* local prototypes */
56 static si_info_t *si_doattach(si_info_t *sii, uint devid, osl_t *osh,
57 void *regs, uint bustype, void *sdh, char **vars,
59 static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid,
61 static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,
62 u32 savewin, uint *origidx, void *regs);
63 static void si_nvram_process(si_info_t *sii, char *pvars);
65 /* dev path concatenation util */
66 static char *si_devpathvar(si_t *sih, char *var, int len, const char *name);
67 static bool _si_clkctl_cc(si_info_t *sii, uint mode);
68 static bool si_ispcie(si_info_t *sii);
69 static uint socram_banksize(si_info_t *sii, sbsocramregs_t *r,
72 /* global variable to indicate reservation/release of gpio's */
73 static u32 si_gpioreservation;
76 * Allocate a si handle.
77 * devid - pci device id (used to determine chip#)
78 * osh - opaque OS handle
79 * regs - virtual address of initial core registers
80 * bustype - pci/sb/sdio/etc
81 * vars - pointer to a pointer area for "environment" variables
82 * varsz - pointer to int to return the size of the vars
84 si_t *si_attach(uint devid, osl_t *osh, void *regs, uint bustype, void *sdh,
85 char **vars, uint *varsz)
90 sii = kmalloc(sizeof(si_info_t), GFP_ATOMIC);
92 SI_ERROR(("si_attach: malloc failed!\n"));
96 if (si_doattach(sii, devid, osh, regs, bustype, sdh, vars, varsz) ==
101 sii->vars = vars ? *vars : NULL;
102 sii->varsz = varsz ? *varsz : 0;
107 /* global kernel resource */
108 static si_info_t ksii;
110 static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid,
115 /* kludge to enable the clock on the 4306 which lacks a slowclock */
116 if (BUSTYPE(bustype) == PCI_BUS && !si_ispcie(sii))
117 si_clkctl_xtal(&sii->pub, XTAL | PLL, ON);
121 if (BUSTYPE(bustype) == SDIO_BUS) {
125 /* Try forcing SDIO core to do ALPAvail request only */
126 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
127 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
132 /* If register supported, wait for ALPAvail and then force ALP */
134 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
135 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
136 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
138 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
139 SBSDIO_FUNC1_CHIPCLKCSR,
141 !SBSDIO_ALPAV(clkval)),
142 PMU_MAX_TRANSITION_DLY);
143 if (!SBSDIO_ALPAV(clkval)) {
144 SI_ERROR(("timeout on ALPAV wait, clkval 0x%02x\n", clkval));
148 SBSDIO_FORCE_HW_CLKREQ_OFF |
150 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
151 SBSDIO_FUNC1_CHIPCLKCSR,
157 /* Also, disable the extra SDIO pull-ups */
158 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0,
161 #endif /* defined(BCMSDIO) */
166 static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,
167 u32 savewin, uint *origidx, void *regs)
171 uint pciidx, pcieidx, pcirev, pcierev;
173 cc = si_setcoreidx(&sii->pub, SI_CC_IDX);
176 /* get chipcommon rev */
177 sii->pub.ccrev = (int)si_corerev(&sii->pub);
179 /* get chipcommon chipstatus */
180 if (sii->pub.ccrev >= 11)
181 sii->pub.chipst = R_REG(sii->osh, &cc->chipstatus);
183 /* get chipcommon capabilites */
184 sii->pub.cccaps = R_REG(sii->osh, &cc->capabilities);
185 /* get chipcommon extended capabilities */
188 if (sii->pub.ccrev >= 35)
189 sii->pub.cccaps_ext = R_REG(sii->osh, &cc->capabilities_ext);
191 /* get pmu rev and caps */
192 if (sii->pub.cccaps & CC_CAP_PMU) {
193 sii->pub.pmucaps = R_REG(sii->osh, &cc->pmucapabilities);
194 sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
198 SI_MSG(("Chipc: rev %d, caps 0x%x, chipst 0x%x pmurev %d, pmucaps 0x%x\n",
199 sii->pub.ccrev, sii->pub.cccaps, sii->pub.chipst, sii->pub.pmurev,
203 /* figure out bus/orignal core idx */
204 sii->pub.buscoretype = NODEV_CORE_ID;
205 sii->pub.buscorerev = NOREV;
206 sii->pub.buscoreidx = BADIDX;
209 pcirev = pcierev = NOREV;
210 pciidx = pcieidx = BADIDX;
212 for (i = 0; i < sii->numcores; i++) {
215 si_setcoreidx(&sii->pub, i);
216 cid = si_coreid(&sii->pub);
217 crev = si_corerev(&sii->pub);
219 /* Display cores found */
220 SI_VMSG(("CORE[%d]: id 0x%x rev %d base 0x%x regs 0x%p\n",
221 i, cid, crev, sii->coresba[i], sii->regs[i]));
223 if (BUSTYPE(bustype) == PCI_BUS) {
224 if (cid == PCI_CORE_ID) {
228 } else if (cid == PCIE_CORE_ID) {
235 else if (((BUSTYPE(bustype) == SDIO_BUS) ||
236 (BUSTYPE(bustype) == SPI_BUS)) &&
237 ((cid == PCMCIA_CORE_ID) || (cid == SDIOD_CORE_ID))) {
238 sii->pub.buscorerev = crev;
239 sii->pub.buscoretype = cid;
240 sii->pub.buscoreidx = i;
244 /* find the core idx before entering this func. */
245 if ((savewin && (savewin == sii->coresba[i])) ||
246 (regs == sii->regs[i]))
251 SI_MSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx,
252 sii->pub.buscoretype, sii->pub.buscorerev));
254 /* Make sure any on-chip ARM is off (in case strapping is wrong),
255 * or downloaded code was
258 if ((BUSTYPE(bustype) == SDIO_BUS) || (BUSTYPE(bustype) == SPI_BUS)) {
259 if (si_setcore(&sii->pub, ARM7S_CORE_ID, 0) ||
260 si_setcore(&sii->pub, ARMCM3_CORE_ID, 0))
261 si_core_disable(&sii->pub, 0);
271 sii->pub.buscoretype = PCI_CORE_ID;
272 sii->pub.buscorerev = pcirev;
273 sii->pub.buscoreidx = pciidx;
275 sii->pub.buscoretype = PCIE_CORE_ID;
276 sii->pub.buscorerev = pcierev;
277 sii->pub.buscoreidx = pcieidx;
280 SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx,
281 sii->pub.buscoretype, sii->pub.buscorerev));
283 /* fixup necessary chip/core configurations */
284 if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
287 sii->pch = (void *)pcicore_init(
289 (void *)PCIEREGS(sii));
290 if (sii->pch == NULL)
294 if (si_pci_fixcfg(&sii->pub)) {
295 SI_ERROR(("si_doattach: sb_pci_fixcfg failed\n"));
300 /* return to the original core */
301 si_setcoreidx(&sii->pub, *origidx);
306 static __used void si_nvram_process(si_info_t *sii, char *pvars)
310 /* get boardtype and boardrev */
311 switch (BUSTYPE(sii->pub.bustype)) {
313 /* do a pci config read to get subsystem id and subvendor id */
314 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_SVID, sizeof(u32));
315 /* Let nvram variables override subsystem Vend/ID */
316 sii->pub.boardvendor = (u16)si_getdevpathintvar(&sii->pub,
318 if (sii->pub.boardvendor == 0)
319 sii->pub.boardvendor = w & 0xffff;
321 SI_ERROR(("Overriding boardvendor: 0x%x instead of 0x%x\n", sii->pub.boardvendor, w & 0xffff));
322 sii->pub.boardtype = (u16)si_getdevpathintvar(&sii->pub,
324 if (sii->pub.boardtype == 0)
325 sii->pub.boardtype = (w >> 16) & 0xffff;
327 SI_ERROR(("Overriding boardtype: 0x%x instead of 0x%x\n", sii->pub.boardtype, (w >> 16) & 0xffff));
333 sii->pub.boardvendor = getintvar(pvars, "manfid");
334 sii->pub.boardtype = getintvar(pvars, "prodid");
339 sii->pub.boardvendor = VENDOR_BROADCOM;
340 sii->pub.boardtype = SPI_BOARD;
346 sii->pub.boardvendor = VENDOR_BROADCOM;
347 sii->pub.boardtype = getintvar(pvars, "prodid");
348 if (pvars == NULL || (sii->pub.boardtype == 0)) {
349 sii->pub.boardtype = getintvar(NULL, "boardtype");
350 if (sii->pub.boardtype == 0)
351 sii->pub.boardtype = 0xffff;
356 if (sii->pub.boardtype == 0) {
357 SI_ERROR(("si_doattach: unknown board type\n"));
358 ASSERT(sii->pub.boardtype);
361 sii->pub.boardflags = getintvar(pvars, "boardflags");
364 /* this is will make Sonics calls directly, since Sonics is no longer supported in the Si abstraction */
365 /* this has been customized for the bcm 4329 ONLY */
367 static si_info_t *si_doattach(si_info_t *sii, uint devid, osl_t *osh,
368 void *regs, uint bustype, void *sdh,
369 char **vars, uint *varsz)
371 struct si_pub *sih = &sii->pub;
377 ASSERT(GOODREGS(regs));
379 bzero((unsigned char *) sii, sizeof(si_info_t));
383 sih->buscoreidx = BADIDX;
389 /* find Chipcommon address */
390 cc = (chipcregs_t *) sii->curmap;
391 sih->bustype = bustype;
393 if (bustype != BUSTYPE(bustype)) {
394 SI_ERROR(("si_doattach: bus type %d does not match configured bus type %d\n", bustype, BUSTYPE(bustype)));
398 /* bus/core/clk setup for register access */
399 if (!si_buscore_prep(sii, bustype, devid, sdh)) {
400 SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n",
405 /* ChipID recognition.
406 * We assume we can read chipid at offset 0 from the regs arg.
407 * If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon),
408 * some way of recognizing them needs to be added here.
410 w = R_REG(osh, &cc->chipid);
411 sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
412 /* Might as wll fill in chip id rev & pkg */
413 sih->chip = w & CID_ID_MASK;
414 sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;
415 sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;
417 if ((CHIPID(sih->chip) == BCM4329_CHIP_ID) &&
418 (sih->chippkg != BCM4329_289PIN_PKG_ID))
419 sih->chippkg = BCM4329_182PIN_PKG_ID;
421 sih->issim = IS_SIM(sih->chippkg);
424 /* SI_MSG(("Found chip type SB (0x%08x)\n", w)); */
425 sb_scan(&sii->pub, regs, devid);
427 /* no cores found, bail out */
428 if (sii->numcores == 0) {
429 SI_ERROR(("si_doattach: could not find any cores\n"));
432 /* bus/core/clk setup */
434 if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) {
435 SI_ERROR(("si_doattach: si_buscore_setup failed\n"));
442 /* Init nvram from flash if it exists */
443 nvram_init((void *)&(sii->pub));
445 /* Init nvram from sprom/otp if they exist */
447 (&sii->pub, BUSTYPE(bustype), regs, sii->osh, vars, varsz)) {
448 SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n"));
451 pvars = vars ? *vars : NULL;
452 si_nvram_process(sii, pvars);
455 /* === NVRAM, clock is ready === */
458 if (sii->pub.ccrev >= 20) {
460 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
461 W_REG(osh, &cc->gpiopullup, 0);
462 W_REG(osh, &cc->gpiopulldown, 0);
463 sb_setcoreidx(sih, origidx);
469 /* PMU specific initializations */
470 if (PMUCTL_ENAB(sih)) {
472 si_pmu_init(sih, sii->osh);
473 si_pmu_chip_init(sih, sii->osh);
474 xtalfreq = getintvar(pvars, "xtalfreq");
475 /* If xtalfreq var not available, try to measure it */
477 xtalfreq = si_pmu_measure_alpclk(sih, sii->osh);
478 si_pmu_pll_init(sih, sii->osh, xtalfreq);
479 si_pmu_res_init(sih, sii->osh);
480 si_pmu_swreg_init(sih, sii->osh);
483 /* setup the GPIO based LED powersave register */
484 w = getintvar(pvars, "leddc");
486 w = DEFAULT_GPIOTIMERVAL;
487 sb_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w);
490 /* clear any previous epidiag-induced target abort */
491 sb_taclear(sih, false);
502 static si_info_t *si_doattach(si_info_t *sii, uint devid, osl_t *osh,
503 void *regs, uint bustype, void *sdh,
504 char **vars, uint *varsz)
506 struct si_pub *sih = &sii->pub;
512 ASSERT(GOODREGS(regs));
514 bzero((unsigned char *) sii, sizeof(si_info_t));
518 sih->buscoreidx = BADIDX;
524 /* check to see if we are a si core mimic'ing a pci core */
525 if ((bustype == PCI_BUS) &&
526 (OSL_PCI_READ_CONFIG(sii->osh, PCI_SPROM_CONTROL, sizeof(u32)) ==
528 SI_ERROR(("%s: incoming bus is PCI but it's a lie, switching to SI " "devid:0x%x\n", __func__, devid));
532 /* find Chipcommon address */
533 if (bustype == PCI_BUS) {
535 OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(u32));
536 if (!GOODCOREADDR(savewin, SI_ENUM_BASE))
537 savewin = SI_ENUM_BASE;
538 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, SI_ENUM_BASE);
539 cc = (chipcregs_t *) regs;
541 cc = (chipcregs_t *) REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
544 sih->bustype = bustype;
545 if (bustype != BUSTYPE(bustype)) {
546 SI_ERROR(("si_doattach: bus type %d does not match configured bus type %d\n", bustype, BUSTYPE(bustype)));
550 /* bus/core/clk setup for register access */
551 if (!si_buscore_prep(sii, bustype, devid, sdh)) {
552 SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n",
557 /* ChipID recognition.
558 * We assume we can read chipid at offset 0 from the regs arg.
559 * If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon),
560 * some way of recognizing them needs to be added here.
562 w = R_REG(osh, &cc->chipid);
563 sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
564 /* Might as wll fill in chip id rev & pkg */
565 sih->chip = w & CID_ID_MASK;
566 sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;
567 sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;
569 sih->issim = IS_SIM(sih->chippkg);
572 if (CHIPTYPE(sii->pub.socitype) == SOCI_AI) {
573 SI_MSG(("Found chip type AI (0x%08x)\n", w));
574 /* pass chipc address instead of original core base */
575 ai_scan(&sii->pub, (void *)cc, devid);
577 SI_ERROR(("Found chip of unknown type (0x%08x)\n", w));
580 /* no cores found, bail out */
581 if (sii->numcores == 0) {
582 SI_ERROR(("si_doattach: could not find any cores\n"));
585 /* bus/core/clk setup */
587 if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) {
588 SI_ERROR(("si_doattach: si_buscore_setup failed\n"));
592 /* assume current core is CC */
593 if ((sii->pub.ccrev == 0x25)
595 ((CHIPID(sih->chip) == BCM43236_CHIP_ID
596 || CHIPID(sih->chip) == BCM43235_CHIP_ID
597 || CHIPID(sih->chip) == BCM43238_CHIP_ID)
598 && (CHIPREV(sii->pub.chiprev) <= 2))) {
600 if ((cc->chipstatus & CST43236_BP_CLK) != 0) {
602 clkdiv = R_REG(osh, &cc->clkdiv);
603 /* otp_clk_div is even number, 120/14 < 9mhz */
604 clkdiv = (clkdiv & ~CLKD_OTP) | (14 << CLKD_OTP_SHIFT);
605 W_REG(osh, &cc->clkdiv, clkdiv);
606 SI_ERROR(("%s: set clkdiv to %x\n", __func__, clkdiv));
611 /* Init nvram from flash if it exists */
612 nvram_init((void *)&(sii->pub));
614 /* Init nvram from sprom/otp if they exist */
616 (&sii->pub, BUSTYPE(bustype), regs, sii->osh, vars, varsz)) {
617 SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n"));
620 pvars = vars ? *vars : NULL;
621 si_nvram_process(sii, pvars);
623 /* === NVRAM, clock is ready === */
624 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
625 W_REG(osh, &cc->gpiopullup, 0);
626 W_REG(osh, &cc->gpiopulldown, 0);
627 si_setcoreidx(sih, origidx);
629 /* PMU specific initializations */
630 if (PMUCTL_ENAB(sih)) {
632 si_pmu_init(sih, sii->osh);
633 si_pmu_chip_init(sih, sii->osh);
634 xtalfreq = getintvar(pvars, "xtalfreq");
635 /* If xtalfreq var not available, try to measure it */
637 xtalfreq = si_pmu_measure_alpclk(sih, sii->osh);
638 si_pmu_pll_init(sih, sii->osh, xtalfreq);
639 si_pmu_res_init(sih, sii->osh);
640 si_pmu_swreg_init(sih, sii->osh);
643 /* setup the GPIO based LED powersave register */
644 w = getintvar(pvars, "leddc");
646 w = DEFAULT_GPIOTIMERVAL;
647 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w);
650 ASSERT(sii->pch != NULL);
651 pcicore_attach(sii->pch, pvars, SI_DOATTACH);
654 if ((CHIPID(sih->chip) == BCM43224_CHIP_ID) ||
655 (CHIPID(sih->chip) == BCM43421_CHIP_ID)) {
656 /* enable 12 mA drive strenth for 43224 and set chipControl register bit 15 */
657 if (CHIPREV(sih->chiprev) == 0) {
658 SI_MSG(("Applying 43224A0 WARs\n"));
659 si_corereg(sih, SI_CC_IDX,
660 offsetof(chipcregs_t, chipcontrol),
661 CCTRL43224_GPIO_TOGGLE,
662 CCTRL43224_GPIO_TOGGLE);
663 si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
664 CCTRL_43224A0_12MA_LED_DRIVE);
666 if (CHIPREV(sih->chiprev) >= 1) {
667 SI_MSG(("Applying 43224B0+ WARs\n"));
668 si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE,
669 CCTRL_43224B0_12MA_LED_DRIVE);
673 if (CHIPID(sih->chip) == BCM4313_CHIP_ID) {
674 /* enable 12 mA drive strenth for 4313 and set chipControl register bit 1 */
675 SI_MSG(("Applying 4313 WARs\n"));
676 si_pmu_chipcontrol(sih, 0, CCTRL_4313_12MA_LED_DRIVE,
677 CCTRL_4313_12MA_LED_DRIVE);
680 if (CHIPID(sih->chip) == BCM4331_CHIP_ID) {
681 /* Enable Ext PA lines depending on chip package option */
682 si_chipcontrl_epa4331(sih, true);
687 if (BUSTYPE(sih->bustype) == PCI_BUS) {
689 pcicore_deinit(sii->pch);
697 /* may be called with core in reset */
698 void si_detach(si_t *sih)
703 struct si_pub *si_local = NULL;
704 bcopy(&sih, &si_local, sizeof(si_t **));
711 if (BUSTYPE(sih->bustype) == SI_BUS)
712 for (idx = 0; idx < SI_MAXCORES; idx++)
713 if (sii->regs[idx]) {
714 REG_UNMAP(sii->regs[idx]);
715 sii->regs[idx] = NULL;
719 nvram_exit((void *)si_local); /* free up nvram buffers */
721 if (BUSTYPE(sih->bustype) == PCI_BUS) {
723 pcicore_deinit(sii->pch);
727 #if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SI_BUS)
729 #endif /* !BCMBUSTYPE || (BCMBUSTYPE == SI_BUS) */
733 void *si_osh(si_t *sih)
741 /* register driver interrupt disabling and restoring callback functions */
743 si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
744 void *intrsenabled_fn, void *intr_arg)
749 sii->intr_arg = intr_arg;
750 sii->intrsoff_fn = (si_intrsoff_t) intrsoff_fn;
751 sii->intrsrestore_fn = (si_intrsrestore_t) intrsrestore_fn;
752 sii->intrsenabled_fn = (si_intrsenabled_t) intrsenabled_fn;
753 /* save current core id. when this function called, the current core
754 * must be the core which provides driver functions(il, et, wl, etc.)
756 sii->dev_coreid = sii->coreid[sii->curidx];
759 void si_deregister_intr_callback(si_t *sih)
764 sii->intrsoff_fn = NULL;
767 uint si_flag(si_t *sih)
769 if (CHIPTYPE(sih->socitype) == SOCI_AI)
777 void si_setint(si_t *sih, int siflag)
779 if (CHIPTYPE(sih->socitype) == SOCI_AI)
780 ai_setint(sih, siflag);
786 uint si_coreid(si_t *sih)
791 return sii->coreid[sii->curidx];
795 uint si_coreidx(si_t *sih)
803 bool si_backplane64(si_t *sih)
805 return (sih->cccaps & CC_CAP_BKPLN64) != 0;
809 uint si_corerev(si_t *sih)
811 if (CHIPTYPE(sih->socitype) == SOCI_AI)
812 return ai_corerev(sih);
820 /* return index of coreid or BADIDX if not found */
821 uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit)
831 for (i = 0; i < sii->numcores; i++)
832 if (sii->coreid[i] == coreid) {
833 if (found == coreunit)
842 * This function changes logical "focus" to the indicated core;
843 * must be called with interrupts off.
844 * Moreover, callers should keep interrupts off during switching out of and back to d11 core
846 void *si_setcore(si_t *sih, uint coreid, uint coreunit)
850 idx = si_findcoreidx(sih, coreid, coreunit);
854 if (CHIPTYPE(sih->socitype) == SOCI_AI)
855 return ai_setcoreidx(sih, idx);
858 return sb_setcoreidx(sih, idx);
867 void *si_setcoreidx(si_t *sih, uint coreidx)
869 if (CHIPTYPE(sih->socitype) == SOCI_AI)
870 return ai_setcoreidx(sih, coreidx);
878 /* Turn off interrupt as required by sb_setcore, before switch core */
879 void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val)
887 /* Overloading the origidx variable to remember the coreid,
888 * this works because the core ids cannot be confused with
892 if (coreid == CC_CORE_ID)
893 return (void *)CCREGS_FAST(sii);
894 else if (coreid == sih->buscoretype)
895 return (void *)PCIEREGS(sii);
897 INTR_OFF(sii, *intr_val);
898 *origidx = sii->curidx;
899 cc = si_setcore(sih, coreid, 0);
905 /* restore coreidx and restore interrupt */
906 void si_restore_core(si_t *sih, uint coreid, uint intr_val)
912 && ((coreid == CC_CORE_ID) || (coreid == sih->buscoretype)))
915 si_setcoreidx(sih, coreid);
916 INTR_RESTORE(sii, intr_val);
919 u32 si_core_cflags(si_t *sih, u32 mask, u32 val)
921 if (CHIPTYPE(sih->socitype) == SOCI_AI)
922 return ai_core_cflags(sih, mask, val);
929 u32 si_core_sflags(si_t *sih, u32 mask, u32 val)
931 if (CHIPTYPE(sih->socitype) == SOCI_AI)
932 return ai_core_sflags(sih, mask, val);
939 bool si_iscoreup(si_t *sih)
941 if (CHIPTYPE(sih->socitype) == SOCI_AI)
942 return ai_iscoreup(sih);
945 return sb_iscoreup(sih);
953 void si_write_wrapperreg(si_t *sih, u32 offset, u32 val)
955 /* only for 4319, no requirement for SOCI_SB */
956 if (CHIPTYPE(sih->socitype) == SOCI_AI) {
957 ai_write_wrap_reg(sih, offset, val);
961 uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
964 if (CHIPTYPE(sih->socitype) == SOCI_AI)
965 return ai_corereg(sih, coreidx, regoff, mask, val);
968 return sb_corereg(sih, coreidx, regoff, mask, val);
976 void si_core_disable(si_t *sih, u32 bits)
979 if (CHIPTYPE(sih->socitype) == SOCI_AI)
980 ai_core_disable(sih, bits);
983 sb_core_disable(sih, bits);
987 void si_core_reset(si_t *sih, u32 bits, u32 resetbits)
989 if (CHIPTYPE(sih->socitype) == SOCI_AI)
990 ai_core_reset(sih, bits, resetbits);
993 sb_core_reset(sih, bits, resetbits);
997 u32 si_alp_clock(si_t *sih)
999 if (PMUCTL_ENAB(sih))
1000 return si_pmu_alp_clock(sih, si_osh(sih));
1005 u32 si_ilp_clock(si_t *sih)
1007 if (PMUCTL_ENAB(sih))
1008 return si_pmu_ilp_clock(sih, si_osh(sih));
1013 /* set chip watchdog reset timer to fire in 'ticks' */
1016 si_watchdog(si_t *sih, uint ticks)
1018 if (PMUCTL_ENAB(sih)) {
1020 if ((sih->chip == BCM4319_CHIP_ID) && (sih->chiprev == 0) &&
1022 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t,
1023 clk_ctl_st), ~0, 0x2);
1024 si_setcore(sih, USB20D_CORE_ID, 0);
1025 si_core_disable(sih, 1);
1026 si_setcore(sih, CC_CORE_ID, 0);
1031 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmuwatchdog),
1035 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, watchdog),
1040 void si_watchdog(si_t *sih, uint ticks)
1044 if (PMUCTL_ENAB(sih)) {
1046 if ((CHIPID(sih->chip) == BCM4319_CHIP_ID) &&
1047 (CHIPREV(sih->chiprev) == 0) && (ticks != 0)) {
1048 si_corereg(sih, SI_CC_IDX,
1049 offsetof(chipcregs_t, clk_ctl_st), ~0, 0x2);
1050 si_setcore(sih, USB20D_CORE_ID, 0);
1051 si_core_disable(sih, 1);
1052 si_setcore(sih, CC_CORE_ID, 0);
1055 nb = (sih->ccrev < 26) ? 16 : ((sih->ccrev >= 37) ? 32 : 24);
1056 /* The mips compiler uses the sllv instruction,
1057 * so we specially handle the 32-bit case.
1062 maxt = ((1 << nb) - 1);
1066 else if (ticks > maxt)
1069 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmuwatchdog),
1072 /* make sure we come up in fast clock mode; or if clearing, clear clock */
1073 si_clkctl_cc(sih, ticks ? CLK_FAST : CLK_DYNAMIC);
1074 maxt = (1 << 28) - 1;
1078 si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, watchdog), ~0,
1084 /* return the slow clock source - LPO, XTAL, or PCI */
1085 static uint si_slowclk_src(si_info_t *sii)
1089 ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
1091 if (sii->pub.ccrev < 6) {
1092 if ((BUSTYPE(sii->pub.bustype) == PCI_BUS) &&
1093 (OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(u32))
1094 & PCI_CFG_GPIO_SCS))
1098 } else if (sii->pub.ccrev < 10) {
1099 cc = (chipcregs_t *) si_setcoreidx(&sii->pub, sii->curidx);
1100 return R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK;
1101 } else /* Insta-clock */
1105 /* return the ILP (slowclock) min or max frequency */
1106 static uint si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
1111 ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
1113 /* shouldn't be here unless we've established the chip has dynamic clk control */
1114 ASSERT(R_REG(sii->osh, &cc->capabilities) & CC_CAP_PWR_CTL);
1116 slowclk = si_slowclk_src(sii);
1117 if (sii->pub.ccrev < 6) {
1118 if (slowclk == SCC_SS_PCI)
1119 return max_freq ? (PCIMAXFREQ / 64)
1120 : (PCIMINFREQ / 64);
1122 return max_freq ? (XTALMAXFREQ / 32)
1123 : (XTALMINFREQ / 32);
1124 } else if (sii->pub.ccrev < 10) {
1126 (((R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >>
1128 if (slowclk == SCC_SS_LPO)
1129 return max_freq ? LPOMAXFREQ : LPOMINFREQ;
1130 else if (slowclk == SCC_SS_XTAL)
1131 return max_freq ? (XTALMAXFREQ / div)
1132 : (XTALMINFREQ / div);
1133 else if (slowclk == SCC_SS_PCI)
1134 return max_freq ? (PCIMAXFREQ / div)
1135 : (PCIMINFREQ / div);
1139 /* Chipc rev 10 is InstaClock */
1140 div = R_REG(sii->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;
1141 div = 4 * (div + 1);
1142 return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
1147 static void si_clkctl_setdelay(si_info_t *sii, void *chipcregs)
1149 chipcregs_t *cc = (chipcregs_t *) chipcregs;
1150 uint slowmaxfreq, pll_delay, slowclk;
1151 uint pll_on_delay, fref_sel_delay;
1153 pll_delay = PLL_DELAY;
1155 /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
1156 * since the xtal will also be powered down by dynamic clk control logic.
1159 slowclk = si_slowclk_src(sii);
1160 if (slowclk != SCC_SS_XTAL)
1161 pll_delay += XTAL_ON_DELAY;
1163 /* Starting with 4318 it is ILP that is used for the delays */
1165 si_slowclk_freq(sii, (sii->pub.ccrev >= 10) ? false : true, cc);
1167 pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
1168 fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
1170 W_REG(sii->osh, &cc->pll_on_delay, pll_on_delay);
1171 W_REG(sii->osh, &cc->fref_sel_delay, fref_sel_delay);
1174 /* initialize power control delay registers */
1175 void si_clkctl_init(si_t *sih)
1182 if (!CCCTL_ENAB(sih))
1186 fast = SI_FAST(sii);
1188 origidx = sii->curidx;
1189 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
1193 cc = (chipcregs_t *) CCREGS_FAST(sii);
1199 /* set all Instaclk chip ILP to 1 MHz */
1200 if (sih->ccrev >= 10)
1201 SET_REG(sii->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
1202 (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
1204 si_clkctl_setdelay(sii, (void *)cc);
1207 si_setcoreidx(sih, origidx);
1210 /* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
1211 u16 si_clkctl_fast_pwrup_delay(si_t *sih)
1222 if (PMUCTL_ENAB(sih)) {
1223 INTR_OFF(sii, intr_val);
1224 fpdelay = si_pmu_fast_pwrup_delay(sih, sii->osh);
1225 INTR_RESTORE(sii, intr_val);
1229 if (!CCCTL_ENAB(sih))
1232 fast = SI_FAST(sii);
1235 origidx = sii->curidx;
1236 INTR_OFF(sii, intr_val);
1237 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
1241 cc = (chipcregs_t *) CCREGS_FAST(sii);
1247 slowminfreq = si_slowclk_freq(sii, false, cc);
1248 fpdelay = (((R_REG(sii->osh, &cc->pll_on_delay) + 2) * 1000000) +
1249 (slowminfreq - 1)) / slowminfreq;
1253 si_setcoreidx(sih, origidx);
1254 INTR_RESTORE(sii, intr_val);
1259 /* turn primary xtal and/or pll off/on */
1260 int si_clkctl_xtal(si_t *sih, uint what, bool on)
1267 switch (BUSTYPE(sih->bustype)) {
1272 #endif /* BCMSDIO */
1275 /* pcie core doesn't have any mapping to control the xtal pu */
1279 in = OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_IN, sizeof(u32));
1281 OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUT, sizeof(u32));
1283 OSL_PCI_READ_CONFIG(sii->osh, PCI_GPIO_OUTEN,
1287 * Avoid glitching the clock if GPRS is already using it.
1288 * We can't actually read the state of the PLLPD so we infer it
1289 * by the value of XTAL_PU which *is* readable via gpioin.
1291 if (on && (in & PCI_CFG_GPIO_XTAL))
1295 outen |= PCI_CFG_GPIO_XTAL;
1297 outen |= PCI_CFG_GPIO_PLL;
1300 /* turn primary xtal on */
1302 out |= PCI_CFG_GPIO_XTAL;
1304 out |= PCI_CFG_GPIO_PLL;
1305 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT,
1307 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN,
1308 sizeof(u32), outen);
1309 udelay(XTAL_ON_DELAY);
1314 out &= ~PCI_CFG_GPIO_PLL;
1315 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT,
1321 out &= ~PCI_CFG_GPIO_XTAL;
1323 out |= PCI_CFG_GPIO_PLL;
1324 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUT,
1326 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_GPIO_OUTEN,
1327 sizeof(u32), outen);
1338 * clock control policy function throught chipcommon
1340 * set dynamic clk control mode (forceslow, forcefast, dynamic)
1341 * returns true if we are forcing fast clock
1342 * this is a wrapper over the next internal function
1343 * to allow flexible policy settings for outside caller
1345 bool si_clkctl_cc(si_t *sih, uint mode)
1351 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1355 if (PCI_FORCEHT(sii))
1356 return mode == CLK_FAST;
1358 return _si_clkctl_cc(sii, mode);
1361 /* clk control mechanism through chipcommon, no policy checking */
1362 static bool _si_clkctl_cc(si_info_t *sii, uint mode)
1368 bool fast = SI_FAST(sii);
1370 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1371 if (sii->pub.ccrev < 6)
1374 /* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */
1375 ASSERT(sii->pub.ccrev != 10);
1378 INTR_OFF(sii, intr_val);
1379 origidx = sii->curidx;
1381 if ((BUSTYPE(sii->pub.bustype) == SI_BUS) &&
1382 si_setcore(&sii->pub, MIPS33_CORE_ID, 0) &&
1383 (si_corerev(&sii->pub) <= 7) && (sii->pub.ccrev >= 10))
1386 cc = (chipcregs_t *) si_setcore(&sii->pub, CC_CORE_ID, 0);
1388 cc = (chipcregs_t *) CCREGS_FAST(sii);
1394 if (!CCCTL_ENAB(&sii->pub) && (sii->pub.ccrev < 20))
1398 case CLK_FAST: /* FORCEHT, fast (pll) clock */
1399 if (sii->pub.ccrev < 10) {
1400 /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
1401 si_clkctl_xtal(&sii->pub, XTAL, ON);
1402 SET_REG(sii->osh, &cc->slow_clk_ctl,
1403 (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
1404 } else if (sii->pub.ccrev < 20) {
1405 OR_REG(sii->osh, &cc->system_clk_ctl, SYCC_HR);
1407 OR_REG(sii->osh, &cc->clk_ctl_st, CCS_FORCEHT);
1410 /* wait for the PLL */
1411 if (PMUCTL_ENAB(&sii->pub)) {
1412 u32 htavail = CCS_HTAVAIL;
1413 SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail)
1414 == 0), PMU_MAX_TRANSITION_DLY);
1415 ASSERT(R_REG(sii->osh, &cc->clk_ctl_st) & htavail);
1421 case CLK_DYNAMIC: /* enable dynamic clock control */
1422 if (sii->pub.ccrev < 10) {
1423 scc = R_REG(sii->osh, &cc->slow_clk_ctl);
1424 scc &= ~(SCC_FS | SCC_IP | SCC_XC);
1425 if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
1427 W_REG(sii->osh, &cc->slow_clk_ctl, scc);
1429 /* for dynamic control, we have to release our xtal_pu "force on" */
1431 si_clkctl_xtal(&sii->pub, XTAL, OFF);
1432 } else if (sii->pub.ccrev < 20) {
1434 AND_REG(sii->osh, &cc->system_clk_ctl, ~SYCC_HR);
1436 AND_REG(sii->osh, &cc->clk_ctl_st, ~CCS_FORCEHT);
1446 si_setcoreidx(&sii->pub, origidx);
1447 INTR_RESTORE(sii, intr_val);
1449 return mode == CLK_FAST;
1452 /* Build device path. Support SI, PCI, and JTAG for now. */
1453 int si_devpath(si_t *sih, char *path, int size)
1457 ASSERT(path != NULL);
1458 ASSERT(size >= SI_DEVPATH_BUFSZ);
1460 if (!path || size <= 0)
1463 switch (BUSTYPE(sih->bustype)) {
1466 slen = snprintf(path, (size_t) size, "sb/%u/", si_coreidx(sih));
1469 ASSERT((SI_INFO(sih))->osh != NULL);
1470 slen = snprintf(path, (size_t) size, "pci/%u/%u/",
1471 OSL_PCI_BUS((SI_INFO(sih))->osh),
1472 OSL_PCI_SLOT((SI_INFO(sih))->osh));
1477 SI_ERROR(("si_devpath: device 0 assumed\n"));
1478 slen = snprintf(path, (size_t) size, "sd/%u/", si_coreidx(sih));
1487 if (slen < 0 || slen >= size) {
1495 /* Get a variable, but only if it has a devpath prefix */
1496 char *si_getdevpathvar(si_t *sih, const char *name)
1498 char varname[SI_DEVPATH_BUFSZ + 32];
1500 si_devpathvar(sih, varname, sizeof(varname), name);
1502 return getvar(NULL, varname);
1505 /* Get a variable, but only if it has a devpath prefix */
1506 int si_getdevpathintvar(si_t *sih, const char *name)
1508 #if defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS)
1509 return getintvar(NULL, name);
1511 char varname[SI_DEVPATH_BUFSZ + 32];
1513 si_devpathvar(sih, varname, sizeof(varname), name);
1515 return getintvar(NULL, varname);
1519 char *si_getnvramflvar(si_t *sih, const char *name)
1521 return getvar(NULL, name);
1524 /* Concatenate the dev path with a varname into the given 'var' buffer
1525 * and return the 'var' pointer.
1526 * Nothing is done to the arguments if len == 0 or var is NULL, var is still returned.
1527 * On overflow, the first char will be set to '\0'.
1529 static char *si_devpathvar(si_t *sih, char *var, int len, const char *name)
1533 if (!var || len <= 0)
1536 if (si_devpath(sih, var, len) == 0) {
1537 path_len = strlen(var);
1539 if (strlen(name) + 1 > (uint) (len - path_len))
1542 strncpy(var + path_len, name, len - path_len - 1);
1548 /* return true if PCIE capability exists in the pci config space */
1549 static __used bool si_ispcie(si_info_t *sii)
1553 if (BUSTYPE(sii->pub.bustype) != PCI_BUS)
1557 pcicore_find_pci_capability(sii->osh, PCI_CAP_PCIECAP_ID, NULL,
1566 /* initialize the sdio core */
1567 void si_sdio_init(si_t *sih)
1569 si_info_t *sii = SI_INFO(sih);
1571 if (((sih->buscoretype == PCMCIA_CORE_ID) && (sih->buscorerev >= 8)) ||
1572 (sih->buscoretype == SDIOD_CORE_ID)) {
1574 sdpcmd_regs_t *sdpregs;
1576 /* get the current core index */
1578 ASSERT(idx == si_findcoreidx(sih, D11_CORE_ID, 0));
1580 /* switch to sdio core */
1581 sdpregs = (sdpcmd_regs_t *) si_setcore(sih, PCMCIA_CORE_ID, 0);
1584 (sdpcmd_regs_t *) si_setcore(sih, SDIOD_CORE_ID, 0);
1587 SI_MSG(("si_sdio_init: For PCMCIA/SDIO Corerev %d, enable ints from core %d " "through SD core %d (%p)\n", sih->buscorerev, idx, sii->curidx, sdpregs));
1589 /* enable backplane error and core interrupts */
1590 W_REG(sii->osh, &sdpregs->hostintmask, I_SBINT);
1591 W_REG(sii->osh, &sdpregs->sbintmask,
1592 (I_SB_SERR | I_SB_RESPERR | (1 << idx)));
1594 /* switch back to previous core */
1595 si_setcoreidx(sih, idx);
1598 /* enable interrupts */
1599 bcmsdh_intr_enable(sii->sdh);
1602 #endif /* BCMSDIO */
1604 bool si_pci_war16165(si_t *sih)
1610 return PCI(sii) && (sih->buscorerev <= 10);
1613 void si_pci_up(si_t *sih)
1619 /* if not pci bus, we're done */
1620 if (BUSTYPE(sih->bustype) != PCI_BUS)
1623 if (PCI_FORCEHT(sii))
1624 _si_clkctl_cc(sii, CLK_FAST);
1627 pcicore_up(sii->pch, SI_PCIUP);
1631 /* Unconfigure and/or apply various WARs when system is going to sleep mode */
1632 void si_pci_sleep(si_t *sih)
1638 pcicore_sleep(sii->pch);
1641 /* Unconfigure and/or apply various WARs when going down */
1642 void si_pci_down(si_t *sih)
1648 /* if not pci bus, we're done */
1649 if (BUSTYPE(sih->bustype) != PCI_BUS)
1652 /* release FORCEHT since chip is going to "down" state */
1653 if (PCI_FORCEHT(sii))
1654 _si_clkctl_cc(sii, CLK_DYNAMIC);
1656 pcicore_down(sii->pch, SI_PCIDOWN);
1660 * Configure the pci core for pci client (NIC) action
1661 * coremask is the bitvec of cores by index to be enabled.
1663 void si_pci_setup(si_t *sih, uint coremask)
1666 struct sbpciregs *pciregs = NULL;
1672 if (BUSTYPE(sii->pub.bustype) != PCI_BUS)
1675 ASSERT(PCI(sii) || PCIE(sii));
1676 ASSERT(sii->pub.buscoreidx != BADIDX);
1679 /* get current core index */
1682 /* we interrupt on this backplane flag number */
1683 siflag = si_flag(sih);
1685 /* switch over to pci core */
1686 pciregs = (struct sbpciregs *)si_setcoreidx(sih, sii->pub.buscoreidx);
1690 * Enable sb->pci interrupts. Assume
1691 * PCI rev 2.3 support was added in pci core rev 6 and things changed..
1693 if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) {
1694 /* pci config write to set this core bit in PCIIntMask */
1695 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_INT_MASK, sizeof(u32));
1696 w |= (coremask << PCI_SBIM_SHIFT);
1697 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_INT_MASK, sizeof(u32), w);
1699 /* set sbintvec bit for our flag number */
1700 si_setint(sih, siflag);
1704 OR_REG(sii->osh, &pciregs->sbtopci2,
1705 (SBTOPCI_PREF | SBTOPCI_BURST));
1706 if (sii->pub.buscorerev >= 11) {
1707 OR_REG(sii->osh, &pciregs->sbtopci2,
1708 SBTOPCI_RC_READMULTI);
1709 w = R_REG(sii->osh, &pciregs->clkrun);
1710 W_REG(sii->osh, &pciregs->clkrun,
1711 (w | PCI_CLKRUN_DSBL));
1712 w = R_REG(sii->osh, &pciregs->clkrun);
1715 /* switch back to previous core */
1716 si_setcoreidx(sih, idx);
1721 * Fixup SROMless PCI device's configuration.
1722 * The current core may be changed upon return.
1724 int si_pci_fixcfg(si_t *sih)
1726 uint origidx, pciidx;
1727 struct sbpciregs *pciregs = NULL;
1728 sbpcieregs_t *pcieregs = NULL;
1730 u16 val16, *reg16 = NULL;
1732 si_info_t *sii = SI_INFO(sih);
1734 ASSERT(BUSTYPE(sii->pub.bustype) == PCI_BUS);
1736 /* Fixup PI in SROM shadow area to enable the correct PCI core access */
1737 /* save the current index */
1738 origidx = si_coreidx(&sii->pub);
1740 /* check 'pi' is correct and fix it if not */
1741 if (sii->pub.buscoretype == PCIE_CORE_ID) {
1743 (sbpcieregs_t *) si_setcore(&sii->pub, PCIE_CORE_ID, 0);
1745 ASSERT(pcieregs != NULL);
1746 reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
1747 } else if (sii->pub.buscoretype == PCI_CORE_ID) {
1748 pciregs = (struct sbpciregs *)si_setcore(&sii->pub, PCI_CORE_ID, 0);
1750 ASSERT(pciregs != NULL);
1751 reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
1753 pciidx = si_coreidx(&sii->pub);
1754 val16 = R_REG(sii->osh, reg16);
1755 if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (u16) pciidx) {
1757 (u16) (pciidx << SRSH_PI_SHIFT) | (val16 &
1759 W_REG(sii->osh, reg16, val16);
1762 /* restore the original index */
1763 si_setcoreidx(&sii->pub, origidx);
1765 pcicore_hwup(sii->pch);
1769 /* mask&set gpiocontrol bits */
1770 u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val, u8 priority)
1776 /* gpios could be shared on router platforms
1777 * ignore reservation if it's high priority (e.g., test apps)
1779 if ((priority != GPIO_HI_PRIORITY) &&
1780 (BUSTYPE(sih->bustype) == SI_BUS) && (val || mask)) {
1781 mask = priority ? (si_gpioreservation & mask) :
1782 ((si_gpioreservation | mask) & ~(si_gpioreservation));
1786 regoff = offsetof(chipcregs_t, gpiocontrol);
1787 return si_corereg(sih, SI_CC_IDX, regoff, mask, val);
1790 /* Return the size of the specified SOCRAM bank */
1792 socram_banksize(si_info_t *sii, sbsocramregs_t *regs, u8 index,
1795 uint banksize, bankinfo;
1796 uint bankidx = index | (mem_type << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
1798 ASSERT(mem_type <= SOCRAM_MEMTYPE_DEVRAM);
1800 W_REG(sii->osh, ®s->bankidx, bankidx);
1801 bankinfo = R_REG(sii->osh, ®s->bankinfo);
1803 SOCRAM_BANKINFO_SZBASE * ((bankinfo & SOCRAM_BANKINFO_SZMASK) + 1);
1807 /* Return the RAM size of the SOCRAM core */
1808 u32 si_socram_size(si_t *sih)
1814 sbsocramregs_t *regs;
1822 /* Block ints and save current core */
1823 INTR_OFF(sii, intr_val);
1824 origidx = si_coreidx(sih);
1826 /* Switch to SOCRAM core */
1827 regs = si_setcore(sih, SOCRAM_CORE_ID, 0);
1831 /* Get info for determining size */
1832 wasup = si_iscoreup(sih);
1834 si_core_reset(sih, 0, 0);
1835 corerev = si_corerev(sih);
1836 coreinfo = R_REG(sii->osh, ®s->coreinfo);
1838 /* Calculate size from coreinfo based on rev */
1840 memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK));
1841 else if (corerev < 3) {
1842 memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK));
1843 memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
1844 } else if ((corerev <= 7) || (corerev == 12)) {
1845 uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
1846 uint bsz = (coreinfo & SRCI_SRBSZ_MASK);
1847 uint lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT;
1850 memsize = nb * (1 << (bsz + SR_BSZ_BASE));
1852 memsize += (1 << ((lss - 1) + SR_BSZ_BASE));
1855 uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
1856 for (i = 0; i < nb; i++)
1858 socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM);
1861 /* Return to previous state and core */
1863 si_core_disable(sih, 0);
1864 si_setcoreidx(sih, origidx);
1867 INTR_RESTORE(sii, intr_val);
1872 void si_chipcontrl_epa4331(si_t *sih, bool on)
1880 origidx = si_coreidx(sih);
1882 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
1884 val = R_REG(sii->osh, &cc->chipcontrol);
1887 if (sih->chippkg == 9 || sih->chippkg == 0xb) {
1888 /* Ext PA Controls for 4331 12x9 Package */
1889 W_REG(sii->osh, &cc->chipcontrol, val |
1890 (CCTRL4331_EXTPA_EN |
1891 CCTRL4331_EXTPA_ON_GPIO2_5));
1893 /* Ext PA Controls for 4331 12x12 Package */
1894 W_REG(sii->osh, &cc->chipcontrol,
1895 val | (CCTRL4331_EXTPA_EN));
1898 val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
1899 W_REG(sii->osh, &cc->chipcontrol, val);
1902 si_setcoreidx(sih, origidx);
1905 /* Enable BT-COEX & Ex-PA for 4313 */
1906 void si_epa_4313war(si_t *sih)
1913 origidx = si_coreidx(sih);
1915 cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
1918 W_REG(sii->osh, &cc->gpiocontrol,
1919 R_REG(sii->osh, &cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK);
1921 si_setcoreidx(sih, origidx);
1924 /* check if the device is removed */
1925 bool si_deviceremoved(si_t *sih)
1932 switch (BUSTYPE(sih->bustype)) {
1934 ASSERT(sii->osh != NULL);
1935 w = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_VID, sizeof(u32));
1936 if ((w & 0xFFFF) != VENDOR_BROADCOM)
1943 bool si_is_sprom_available(si_t *sih)
1945 if (sih->ccrev >= 31) {
1951 if ((sih->cccaps & CC_CAP_SROM) == 0)
1955 origidx = sii->curidx;
1956 cc = si_setcoreidx(sih, SI_CC_IDX);
1957 sromctrl = R_REG(sii->osh, &cc->sromcontrol);
1958 si_setcoreidx(sih, origidx);
1959 return sromctrl & SRC_PRESENT;
1962 switch (CHIPID(sih->chip)) {
1963 case BCM4329_CHIP_ID:
1964 return (sih->chipst & CST4329_SPROM_SEL) != 0;
1965 case BCM4319_CHIP_ID:
1966 return (sih->chipst & CST4319_SPROM_SEL) != 0;
1967 case BCM4336_CHIP_ID:
1968 return (sih->chipst & CST4336_SPROM_PRESENT) != 0;
1969 case BCM4330_CHIP_ID:
1970 return (sih->chipst & CST4330_SPROM_PRESENT) != 0;
1971 case BCM4313_CHIP_ID:
1972 return (sih->chipst & CST4313_SPROM_PRESENT) != 0;
1973 case BCM4331_CHIP_ID:
1974 return (sih->chipst & CST4331_SPROM_PRESENT) != 0;
1980 bool si_is_otp_disabled(si_t *sih)
1982 switch (CHIPID(sih->chip)) {
1983 case BCM4329_CHIP_ID:
1984 return (sih->chipst & CST4329_SPROM_OTP_SEL_MASK) ==
1986 case BCM4319_CHIP_ID:
1987 return (sih->chipst & CST4319_SPROM_OTP_SEL_MASK) ==
1989 case BCM4336_CHIP_ID:
1990 return (sih->chipst & CST4336_OTP_PRESENT) == 0;
1991 case BCM4330_CHIP_ID:
1992 return (sih->chipst & CST4330_OTP_PRESENT) == 0;
1993 case BCM4313_CHIP_ID:
1994 return (sih->chipst & CST4313_OTP_PRESENT) == 0;
1995 /* These chips always have their OTP on */
1996 case BCM43224_CHIP_ID:
1997 case BCM43225_CHIP_ID:
1998 case BCM43421_CHIP_ID:
1999 case BCM43235_CHIP_ID:
2000 case BCM43236_CHIP_ID:
2001 case BCM43238_CHIP_ID:
2002 case BCM4331_CHIP_ID:
2008 bool si_is_otp_powered(si_t *sih)
2010 if (PMUCTL_ENAB(sih))
2011 return si_pmu_is_otp_powered(sih, si_osh(sih));
2015 void si_otp_power(si_t *sih, bool on)
2017 if (PMUCTL_ENAB(sih))
2018 si_pmu_otp_power(sih, si_osh(sih), on);