drivers/staging/brcm80211/sys/wlc_rpc.h

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef _WLC_RPC_H_
  18 #define _WLC_RPC_H_
  19
  20 #include <wlc_types.h>
  21
  22 /* RPC IDs, reordering is OK. This needs to be in sync with RPC_ID_TABLE below */
  23 typedef enum {
  24         WLRPC_NULL_ID = 0,
  25         WLRPC_WLC_REG_READ_ID,
  26         WLRPC_WLC_REG_WRITE_ID,
  27         WLRPC_WLC_MHF_SET_ID,
  28         WLRPC_WLC_MHF_GET_ID,
  29         WLRPC_WLC_BMAC_UP_PREP_ID,
  30         WLRPC_WLC_BMAC_UP_FINISH_ID,
  31         WLRPC_WLC_BMAC_DOWN_PREP_ID,
  32         WLRPC_WLC_BMAC_DOWN_FINISH_ID,
  33         WLRPC_WLC_BMAC_WRITE_HW_BCNTEMPLATES_ID,
  34         WLRPC_WLC_BMAC_RESET_ID,
  35         WLRPC_WLC_DNGL_REBOOT_ID,
  36         WLRPC_WLC_BMAC_RPC_TXQ_WM_SET_ID,
  37         WLRPC_WLC_BMAC_RPC_TXQ_WM_GET_ID,
  38         WLRPC_WLC_BMAC_RPC_AGG_SET_ID,
  39         WLRPC_WLC_BMAC_RPC_MSGLEVEL_SET_ID,
  40         WLRPC_WLC_BMAC_RPC_AGG_LIMIT_SET_ID,
  41         WLRPC_WLC_BMAC_RPC_AGG_LIMIT_GET_ID,
  42         WLRPC_WLC_BMAC_INIT_ID,
  43         WLRPC_WLC_BMAC_SET_CWMIN_ID,
  44         WLRPC_WLC_BMAC_MUTE_ID,
  45         WLRPC_WLC_PHY_DOIOVAR_ID,
  46         WLRPC_WLC_PHY_HOLD_UPD_ID,
  47         WLRPC_WLC_PHY_MUTE_UPD_ID,
  48         WLRPC_WLC_PHY_CLEAR_TSSI_ID,
  49         WLRPC_WLC_PHY_ANT_RXDIV_GET_ID,
  50         WLRPC_WLC_PHY_ANT_RXDIV_SET_ID,
  51         WLRPC_WLC_PHY_PREAMBLE_SET_ID,
  52         WLRPC_WLC_PHY_FREQTRACK_END_ID,
  53         WLRPC_WLC_PHY_FREQTRACK_START_ID,
  54         WLRPC_WLC_PHY_IOCTL_ID,
  55         WLRPC_WLC_PHY_NOISE_SAMPLE_REQUEST_ID,
  56         WLRPC_WLC_PHY_CAL_PERICAL_ID,
  57         WLRPC_WLC_PHY_TXPOWER_GET_ID,
  58         WLRPC_WLC_PHY_TXPOWER_SET_ID,
  59         WLRPC_WLC_PHY_TXPOWER_SROMLIMIT_ID,
  60         WLRPC_WLC_PHY_RADAR_DETECT_ENABLE_ID,
  61         WLRPC_WLC_PHY_RADAR_DETECT_RUN_ID,
  62         WLRPC_WLC_PHY_TEST_ISON_ID,
  63         WLRPC_WLC_BMAC_COPYFROM_OBJMEM_ID,
  64         WLRPC_WLC_BMAC_COPYTO_OBJMEM_ID,
  65         WLRPC_WLC_ENABLE_MAC_ID,
  66         WLRPC_WLC_MCTRL_ID,
  67         WLRPC_WLC_CORERESET_ID,
  68         WLRPC_WLC_BMAC_READ_SHM_ID,
  69         WLRPC_WLC_BMAC_READ_TSF_ID,
  70         WLRPC_WLC_BMAC_SET_ADDRMATCH_ID,
  71         WLRPC_WLC_BMAC_SET_CWMAX_ID,
  72         WLRPC_WLC_BMAC_SET_RCMTA_ID,
  73         WLRPC_WLC_BMAC_SET_SHM_ID,
  74         WLRPC_WLC_SUSPEND_MAC_AND_WAIT_ID,
  75         WLRPC_WLC_BMAC_WRITE_SHM_ID,
  76         WLRPC_WLC_BMAC_WRITE_TEMPLATE_RAM_ID,
  77         WLRPC_WLC_TX_FIFO_SUSPEND_ID,
  78         WLRPC_WLC_TX_FIFO_RESUME_ID,
  79         WLRPC_WLC_TX_FIFO_SUSPENDED_ID,
  80         WLRPC_WLC_HW_ETHERADDR_ID,
  81         WLRPC_WLC_SET_HW_ETHERADDR_ID,
  82         WLRPC_WLC_BMAC_CHANSPEC_SET_ID,
  83         WLRPC_WLC_BMAC_TXANT_SET_ID,
  84         WLRPC_WLC_BMAC_ANTSEL_TYPE_SET_ID,
  85         WLRPC_WLC_BMAC_TXFIFO_ID,
  86         WLRPC_WLC_RADIO_READ_HWDISABLED_ID,
  87         WLRPC_WLC_RM_CCA_MEASURE_ID,
  88         WLRPC_WLC_SET_SHORTSLOT_ID,
  89         WLRPC_WLC_WAIT_FOR_WAKE_ID,
  90         WLRPC_WLC_PHY_TXPOWER_GET_CURRENT_ID,
  91         WLRPC_WLC_PHY_TXPOWER_HW_CTRL_GET_ID,
  92         WLRPC_WLC_PHY_TXPOWER_HW_CTRL_SET_ID,
  93         WLRPC_WLC_PHY_BSSINIT_ID,
  94         WLRPC_WLC_BAND_STF_SS_SET_ID,
  95         WLRPC_WLC_PHY_BAND_FIRST_CHANSPEC_ID,
  96         WLRPC_WLC_PHY_TXPOWER_LIMIT_SET_ID,
  97         WLRPC_WLC_PHY_BAND_CHANNELS_ID,
  98         WLRPC_WLC_BMAC_REVINFO_GET_ID,
  99         WLRPC_WLC_BMAC_STATE_GET_ID,
 100         WLRPC_WLC_BMAC_XMTFIFO_SZ_GET_ID,
 101         WLRPC_WLC_BMAC_XMTFIFO_SZ_SET_ID,
 102         WLRPC_WLC_BMAC_VALIDATE_CHIP_ACCESS_ID,
 103         WLRPC_WLC_RM_CCA_COMPLETE_ID,
 104         WLRPC_WLC_RECV_ID,
 105         WLRPC_WLC_DOTXSTATUS_ID,
 106         WLRPC_WLC_HIGH_DPC_ID,
 107         WLRPC_WLC_FATAL_ERROR_ID,
 108         WLRPC_WLC_PHY_SET_CHANNEL_14_WIDE_FILTER_ID,
 109         WLRPC_WLC_PHY_NOISE_AVG_ID,
 110         WLRPC_WLC_PHYCHAIN_INIT_ID,
 111         WLRPC_WLC_PHYCHAIN_SET_ID,
 112         WLRPC_WLC_PHYCHAIN_GET_ID,
 113         WLRPC_WLC_PHY_TKIP_RIFS_WAR_ID,
 114         WLRPC_WLC_BMAC_COPYFROM_VARS_ID,
 115         WLRPC_WLC_BMAC_RETRYLIMIT_UPD_ID,
 116         WLRPC_WLC_BMAC_BTC_MODE_SET_ID,
 117         WLRPC_WLC_BMAC_BTC_MODE_GET_ID,
 118         WLRPC_WLC_BMAC_BTC_WIRE_SET_ID,
 119         WLRPC_WLC_BMAC_BTC_WIRE_GET_ID,
 120         WLRPC_WLC_BMAC_SET_NORESET_ID,
 121         WLRPC_WLC_AMPDU_TXSTATUS_COMPLETE_ID,
 122         WLRPC_WLC_BMAC_FIFOERRORS_ID,
 123         WLRPC_WLC_PHY_TXPOWER_GET_TARGET_MIN_ID,
 124         WLRPC_WLC_PHY_TXPOWER_GET_TARGET_MAX_ID,
 125         WLRPC_WLC_NOISE_CB_ID,
 126         WLRPC_WLC_BMAC_LED_HW_DEINIT_ID,
 127         WLRPC_WLC_BMAC_LED_HW_MASK_INIT_ID,
 128         WLRPC_WLC_PLLREQ_ID,
 129         WLRPC_WLC_BMAC_TACLEAR_ID,
 130         WLRPC_WLC_BMAC_SET_CLK_ID,
 131         WLRPC_WLC_PHY_OFDM_RATESET_WAR_ID,
 132         WLRPC_WLC_PHY_BF_PREEMPT_ENABLE_ID,
 133         WLRPC_WLC_BMAC_DOIOVARS_ID,
 134         WLRPC_WLC_BMAC_DUMP_ID,
 135         WLRPC_WLC_CISWRITE_ID,
 136         WLRPC_WLC_CISDUMP_ID,
 137         WLRPC_WLC_UPDATE_PHY_MODE_ID,
 138         WLRPC_WLC_RESET_BMAC_DONE_ID,
 139         WLRPC_WLC_BMAC_LED_BLINK_EVENT_ID,
 140         WLRPC_WLC_BMAC_LED_SET_ID,
 141         WLRPC_WLC_BMAC_LED_BLINK_ID,
 142         WLRPC_WLC_BMAC_LED_ID,
 143         WLRPC_WLC_BMAC_RATE_SHM_OFFSET_ID,
 144         WLRPC_SI_ISCORE_UP_ID,
 145         WLRPC_WLC_BMAC_PS_SWITCH_ID,
 146         WLRPC_WLC_PHY_STF_SSMODE_GET_ID,
 147         WLRPC_WLC_BMAC_DEBUG_ID,
 148         WLRPC_WLC_EXTLOG_MSG_ID,
 149         WLRPC_WLC_EXTLOG_CFG_ID,
 150         WLRPC_BCM_ASSERT_LOG_ID,
 151         WLRPC_BCM_ASSERT_TYPE_ID,
 152         WLRPC_WLC_BMAC_SET_PHYCAL_CACHE_FLAG_ID,
 153         WLRPC_WLC_BMAC_GET_PHYCAL_CACHE_FLAG_ID,
 154         WLRPC_WLC_PHY_CAL_CACHE_INIT_ID,
 155         WLRPC_WLC_PHY_CAL_CACHE_DEINIT_ID,
 156         WLRPC_WLC_BMAC_HW_UP_ID,
 157         WLRPC_WLC_BMAC_SET_TXPWR_PERCENT_ID,
 158         WLRPC_WLC_PHYCHAIN_ACTIVE_GET_ID,
 159         WLRPC_WLC_BMAC_BLINK_SYNC_ID,
 160         WLRPC_WLC_BMAC_UCODE_DBGSEL_SET_ID,
 161         WLRPC_WLC_BMAC_UCODE_DBGSEL_GET_ID,
 162         WLRPC_WLC_PHY_RADAR_DETECT_MODE_SET_ID,
 163         WLRPC_WLC_PHY_ACIM_NOISEM_RESET_NPHY_ID,
 164         WLRPC_WLC_PHY_INTERFER_SET_NPHY_ID,
 165         WLRPC_WLC_BMAC_IFSCTL_EDCRS_SET_ID,
 166         WLRPC_WLC_PKTENGTX,
 167         WLRPC_WLC_BMAC_SET_DEAF,
 168         WLRPC_WLC_BMAC_CLEAR_DEAF,
 169         WLRPC_WLC_BMAC_BTC_FLAGS_SET_ID,
 170         WLRPC_WLC_BMAC_BTC_FLAGS_GET_ID,
 171         WLRPC_WLC_BMAC_SET_RCMTA_TYPE_ID,
 172         WLRPC_WLC_BMAC_BTC_FLAGS_UPD_ID,
 173         WLRPC_WLC_BMAC_BTC_STUCKWAR_ID,
 174         WLRPC_WLC_BMAC_CCA_STATS_READ_ID,
 175         WLRPC_WLC_BMAC_ANTSEL_SET_ID,
 176         WLRPC_WLC_BMAC_SET_UCODE_LOADED,
 177         WLRPC_WLC_PHY_LDPC_SET_ID,
 178
 179         WLRPC_LAST
 180 } wlc_rpc_id_t;
 181
 182 #if defined(BCMDBG) | 0
 183 struct name_entry {
 184         int id;
 185         char *name;
 186 };
 187
 188 #define NAME_ENTRY(x) {x, #x}
 189
 190 #define RPC_ID_TABLE { \
 191         NAME_ENTRY(WLRPC_WLC_REG_READ_ID),      \
 192         NAME_ENTRY(WLRPC_WLC_REG_WRITE_ID),     \
 193         NAME_ENTRY(WLRPC_WLC_MHF_SET_ID),       \
 194         NAME_ENTRY(WLRPC_WLC_MHF_GET_ID),       \
 195         NAME_ENTRY(WLRPC_WLC_BMAC_UP_PREP_ID),  \
 196         NAME_ENTRY(WLRPC_WLC_BMAC_UP_FINISH_ID),        \
 197         NAME_ENTRY(WLRPC_WLC_BMAC_DOWN_PREP_ID),        \
 198         NAME_ENTRY(WLRPC_WLC_BMAC_DOWN_FINISH_ID),      \
 199         NAME_ENTRY(WLRPC_WLC_BMAC_WRITE_HW_BCNTEMPLATES_ID),    \
 200         NAME_ENTRY(WLRPC_WLC_BMAC_RESET_ID),    \
 201         NAME_ENTRY(WLRPC_WLC_DNGL_REBOOT_ID),   \
 202         NAME_ENTRY(WLRPC_WLC_BMAC_RPC_TXQ_WM_SET_ID),   \
 203         NAME_ENTRY(WLRPC_WLC_BMAC_RPC_TXQ_WM_GET_ID),   \
 204         NAME_ENTRY(WLRPC_WLC_BMAC_RPC_AGG_SET_ID),      \
 205         NAME_ENTRY(WLRPC_WLC_BMAC_RPC_MSGLEVEL_SET_ID), \
 206         NAME_ENTRY(WLRPC_WLC_BMAC_RPC_AGG_LIMIT_SET_ID),        \
 207         NAME_ENTRY(WLRPC_WLC_BMAC_RPC_AGG_LIMIT_GET_ID),        \
 208         NAME_ENTRY(WLRPC_WLC_BMAC_INIT_ID),     \
 209         NAME_ENTRY(WLRPC_WLC_BMAC_SET_CWMIN_ID),        \
 210         NAME_ENTRY(WLRPC_WLC_BMAC_MUTE_ID),     \
 211         NAME_ENTRY(WLRPC_WLC_PHY_DOIOVAR_ID),   \
 212         NAME_ENTRY(WLRPC_WLC_PHY_HOLD_UPD_ID),  \
 213         NAME_ENTRY(WLRPC_WLC_PHY_MUTE_UPD_ID),  \
 214         NAME_ENTRY(WLRPC_WLC_PHY_CLEAR_TSSI_ID),        \
 215         NAME_ENTRY(WLRPC_WLC_PHY_ANT_RXDIV_GET_ID),     \
 216         NAME_ENTRY(WLRPC_WLC_PHY_ANT_RXDIV_SET_ID),     \
 217         NAME_ENTRY(WLRPC_WLC_PHY_PREAMBLE_SET_ID),      \
 218         NAME_ENTRY(WLRPC_WLC_PHY_FREQTRACK_END_ID),     \
 219         NAME_ENTRY(WLRPC_WLC_PHY_FREQTRACK_START_ID),   \
 220         NAME_ENTRY(WLRPC_WLC_PHY_IOCTL_ID),     \
 221         NAME_ENTRY(WLRPC_WLC_PHY_NOISE_SAMPLE_REQUEST_ID),      \
 222         NAME_ENTRY(WLRPC_WLC_PHY_CAL_PERICAL_ID),       \
 223         NAME_ENTRY(WLRPC_WLC_PHY_TXPOWER_GET_ID),       \
 224         NAME_ENTRY(WLRPC_WLC_PHY_TXPOWER_SET_ID),       \
 225         NAME_ENTRY(WLRPC_WLC_PHY_TXPOWER_SROMLIMIT_ID), \
 226         NAME_ENTRY(WLRPC_WLC_PHY_RADAR_DETECT_ENABLE_ID),       \
 227         NAME_ENTRY(WLRPC_WLC_PHY_RADAR_DETECT_RUN_ID),  \
 228         NAME_ENTRY(WLRPC_WLC_PHY_TEST_ISON_ID), \
 229         NAME_ENTRY(WLRPC_WLC_BMAC_COPYFROM_OBJMEM_ID),  \
 230         NAME_ENTRY(WLRPC_WLC_BMAC_COPYTO_OBJMEM_ID),    \
 231         NAME_ENTRY(WLRPC_WLC_ENABLE_MAC_ID),    \
 232         NAME_ENTRY(WLRPC_WLC_MCTRL_ID), \
 233         NAME_ENTRY(WLRPC_WLC_CORERESET_ID), \
 234         NAME_ENTRY(WLRPC_WLC_BMAC_READ_SHM_ID), \
 235         NAME_ENTRY(WLRPC_WLC_BMAC_READ_TSF_ID), \
 236         NAME_ENTRY(WLRPC_WLC_BMAC_SET_ADDRMATCH_ID),    \
 237         NAME_ENTRY(WLRPC_WLC_BMAC_SET_CWMAX_ID),        \
 238         NAME_ENTRY(WLRPC_WLC_BMAC_SET_RCMTA_ID),        \
 239         NAME_ENTRY(WLRPC_WLC_BMAC_SET_SHM_ID),  \
 240         NAME_ENTRY(WLRPC_WLC_SUSPEND_MAC_AND_WAIT_ID),  \
 241         NAME_ENTRY(WLRPC_WLC_BMAC_WRITE_SHM_ID),        \
 242         NAME_ENTRY(WLRPC_WLC_BMAC_WRITE_TEMPLATE_RAM_ID),       \
 243         NAME_ENTRY(WLRPC_WLC_TX_FIFO_SUSPEND_ID),       \
 244         NAME_ENTRY(WLRPC_WLC_TX_FIFO_RESUME_ID),        \
 245         NAME_ENTRY(WLRPC_WLC_TX_FIFO_SUSPENDED_ID),     \
 246         NAME_ENTRY(WLRPC_WLC_HW_ETHERADDR_ID),  \
 247         NAME_ENTRY(WLRPC_WLC_SET_HW_ETHERADDR_ID),      \
 248         NAME_ENTRY(WLRPC_WLC_BMAC_CHANSPEC_SET_ID),     \
 249         NAME_ENTRY(WLRPC_WLC_BMAC_TXANT_SET_ID),        \
 250         NAME_ENTRY(WLRPC_WLC_BMAC_ANTSEL_TYPE_SET_ID),  \
 251         NAME_ENTRY(WLRPC_WLC_BMAC_TXFIFO_ID),   \
 252         NAME_ENTRY(WLRPC_WLC_RADIO_READ_HWDISABLED_ID), \
 253         NAME_ENTRY(WLRPC_WLC_RM_CCA_MEASURE_ID),        \
 254         NAME_ENTRY(WLRPC_WLC_SET_SHORTSLOT_ID), \
 255         NAME_ENTRY(WLRPC_WLC_WAIT_FOR_WAKE_ID), \
 256         NAME_ENTRY(WLRPC_WLC_PHY_TXPOWER_GET_CURRENT_ID),       \
 257         NAME_ENTRY(WLRPC_WLC_PHY_TXPOWER_HW_CTRL_GET_ID),       \
 258         NAME_ENTRY(WLRPC_WLC_PHY_TXPOWER_HW_CTRL_SET_ID),       \
 259         NAME_ENTRY(WLRPC_WLC_PHY_BSSINIT_ID),   \
 260         NAME_ENTRY(WLRPC_WLC_BAND_STF_SS_SET_ID),       \
 261         NAME_ENTRY(WLRPC_WLC_PHY_BAND_FIRST_CHANSPEC_ID),       \
 262         NAME_ENTRY(WLRPC_WLC_PHY_TXPOWER_LIMIT_SET_ID), \
 263         NAME_ENTRY(WLRPC_WLC_PHY_BAND_CHANNELS_ID),     \
 264         NAME_ENTRY(WLRPC_WLC_BMAC_REVINFO_GET_ID),      \
 265         NAME_ENTRY(WLRPC_WLC_BMAC_STATE_GET_ID),        \
 266         NAME_ENTRY(WLRPC_WLC_BMAC_XMTFIFO_SZ_GET_ID),   \
 267         NAME_ENTRY(WLRPC_WLC_BMAC_XMTFIFO_SZ_SET_ID),   \
 268         NAME_ENTRY(WLRPC_WLC_BMAC_VALIDATE_CHIP_ACCESS_ID),     \
 269         NAME_ENTRY(WLRPC_WLC_RM_CCA_COMPLETE_ID),       \
 270         NAME_ENTRY(WLRPC_WLC_RECV_ID),  \
 271         NAME_ENTRY(WLRPC_WLC_DOTXSTATUS_ID),    \
 272         NAME_ENTRY(WLRPC_WLC_HIGH_DPC_ID),      \
 273         NAME_ENTRY(WLRPC_WLC_FATAL_ERROR_ID),   \
 274         NAME_ENTRY(WLRPC_WLC_PHY_SET_CHANNEL_14_WIDE_FILTER_ID), \
 275         NAME_ENTRY(WLRPC_WLC_PHY_NOISE_AVG_ID), \
 276         NAME_ENTRY(WLRPC_WLC_PHYCHAIN_INIT_ID), \
 277         NAME_ENTRY(WLRPC_WLC_PHYCHAIN_SET_ID), \
 278         NAME_ENTRY(WLRPC_WLC_PHYCHAIN_GET_ID), \
 279         NAME_ENTRY(WLRPC_WLC_PHY_TKIP_RIFS_WAR_ID), \
 280         NAME_ENTRY(WLRPC_WLC_BMAC_COPYFROM_VARS_ID), \
 281         NAME_ENTRY(WLRPC_WLC_BMAC_RETRYLIMIT_UPD_ID), \
 282         NAME_ENTRY(WLRPC_WLC_BMAC_BTC_MODE_SET_ID), \
 283         NAME_ENTRY(WLRPC_WLC_BMAC_BTC_MODE_GET_ID), \
 284         NAME_ENTRY(WLRPC_WLC_BMAC_BTC_WIRE_SET_ID), \
 285         NAME_ENTRY(WLRPC_WLC_BMAC_BTC_WIRE_GET_ID), \
 286         NAME_ENTRY(WLRPC_WLC_BMAC_SET_NORESET_ID), \
 287         NAME_ENTRY(WLRPC_WLC_AMPDU_TXSTATUS_COMPLETE_ID), \
 288         NAME_ENTRY(WLRPC_WLC_BMAC_FIFOERRORS_ID), \
 289         NAME_ENTRY(WLRPC_WLC_PHY_TXPOWER_GET_TARGET_MIN_ID), \
 290         NAME_ENTRY(WLRPC_WLC_PHY_TXPOWER_GET_TARGET_MAX_ID), \
 291         NAME_ENTRY(WLRPC_WLC_NOISE_CB_ID), \
 292         NAME_ENTRY(WLRPC_WLC_BMAC_LED_HW_DEINIT_ID), \
 293         NAME_ENTRY(WLRPC_WLC_BMAC_LED_HW_MASK_INIT_ID), \
 294         NAME_ENTRY(WLRPC_WLC_PLLREQ_ID), \
 295         NAME_ENTRY(WLRPC_WLC_BMAC_TACLEAR_ID), \
 296         NAME_ENTRY(WLRPC_WLC_BMAC_SET_CLK_ID), \
 297         NAME_ENTRY(WLRPC_WLC_PHY_OFDM_RATESET_WAR_ID), \
 298         NAME_ENTRY(WLRPC_WLC_PHY_BF_PREEMPT_ENABLE_ID), \
 299         NAME_ENTRY(WLRPC_WLC_BMAC_DOIOVARS_ID), \
 300         NAME_ENTRY(WLRPC_WLC_BMAC_DUMP_ID), \
 301         NAME_ENTRY(WLRPC_WLC_CISWRITE_ID), \
 302         NAME_ENTRY(WLRPC_WLC_CISDUMP_ID), \
 303         NAME_ENTRY(WLRPC_WLC_UPDATE_PHY_MODE_ID), \
 304         NAME_ENTRY(WLRPC_WLC_RESET_BMAC_DONE_ID), \
 305         NAME_ENTRY(WLRPC_WLC_BMAC_LED_BLINK_EVENT_ID), \
 306         NAME_ENTRY(WLRPC_WLC_BMAC_LED_SET_ID), \
 307         NAME_ENTRY(WLRPC_WLC_BMAC_LED_BLINK_ID), \
 308         NAME_ENTRY(WLRPC_WLC_BMAC_LED_ID), \
 309         NAME_ENTRY(WLRPC_WLC_BMAC_RATE_SHM_OFFSET_ID), \
 310         NAME_ENTRY(WLRPC_SI_ISCORE_UP_ID), \
 311         NAME_ENTRY(WLRPC_WLC_BMAC_PS_SWITCH_ID),        \
 312         NAME_ENTRY(WLRPC_WLC_PHY_STF_SSMODE_GET_ID), \
 313         NAME_ENTRY(WLRPC_WLC_BMAC_DEBUG_ID), \
 314         NAME_ENTRY(WLRPC_WLC_EXTLOG_MSG_ID), \
 315         NAME_ENTRY(WLRPC_WLC_EXTLOG_CFG_ID), \
 316         NAME_ENTRY(WLRPC_BCM_ASSERT_LOG_ID), \
 317         NAME_ENTRY(WLRPC_BCM_ASSERT_TYPE_ID), \
 318         NAME_ENTRY(WLRPC_WLC_BMAC_SET_PHYCAL_CACHE_FLAG_ID), \
 319         NAME_ENTRY(WLRPC_WLC_BMAC_GET_PHYCAL_CACHE_FLAG_ID), \
 320         NAME_ENTRY(WLRPC_WLC_PHY_CAL_CACHE_INIT_ID), \
 321         NAME_ENTRY(WLRPC_WLC_PHY_CAL_CACHE_DEINIT_ID), \
 322         NAME_ENTRY(WLRPC_WLC_BMAC_HW_UP_ID), \
 323         NAME_ENTRY(WLRPC_WLC_BMAC_SET_TXPWR_PERCENT_ID), \
 324         NAME_ENTRY(WLRPC_WLC_PHYCHAIN_ACTIVE_GET_ID), \
 325         NAME_ENTRY(WLRPC_WLC_BMAC_BLINK_SYNC_ID), \
 326         NAME_ENTRY(WLRPC_WLC_BMAC_UCODE_DBGSEL_SET_ID), \
 327         NAME_ENTRY(WLRPC_WLC_BMAC_UCODE_DBGSEL_GET_ID), \
 328         NAME_ENTRY(WLRPC_WLC_PHY_RADAR_DETECT_MODE_SET_ID), \
 329         NAME_ENTRY(WLRPC_WLC_PHY_ACIM_NOISEM_RESET_NPHY_ID), \
 330         NAME_ENTRY(WLRPC_WLC_PHY_INTERFER_SET_NPHY_ID), \
 331         NAME_ENTRY(WLRPC_WLC_BMAC_IFSCTL_EDCRS_SET_ID), \
 332         NAME_ENTRY(WLRPC_WLC_PKTENGTX), \
 333         NAME_ENTRY(WLRPC_WLC_BMAC_SET_DEAF), \
 334         NAME_ENTRY(WLRPC_WLC_BMAC_CLEAR_DEAF), \
 335         NAME_ENTRY(WLRPC_WLC_BMAC_BTC_FLAGS_SET_ID), \
 336         NAME_ENTRY(WLRPC_WLC_BMAC_BTC_FLAGS_GET_ID), \
 337         NAME_ENTRY(WLRPC_WLC_BMAC_SET_RCMTA_TYPE_ID), \
 338         NAME_ENTRY(WLRPC_WLC_BMAC_CCA_STATS_READ_ID), \
 339         NAME_ENTRY(WLRPC_WLC_BMAC_ANTSEL_SET_ID), \
 340         NAME_ENTRY(WLRPC_WLC_BMAC_SET_UCODE_LOADED), \
 341         NAME_ENTRY(WLRPC_WLC_PHY_LDPC_SET_ID),  \
 342         {0, NULL} \
 343         }
 344
 345 static __inline char *_wlc_rpc_id_lookup(const struct name_entry *tbl, int _id)
 346 {
 347         const struct name_entry *elt = tbl;
 348         static char __unknown[64];
 349         for (; elt->name != NULL; elt++) {
 350                 if (_id == elt->id)
 351                         break;
 352         }
 353         if (_id == elt->id)
 354                 strncpy(__unknown, elt->name, sizeof(__unknown));
 355         else
 356                 snprintf(__unknown, sizeof(__unknown), "ID:%d", _id);
 357         return __unknown;
 358 }
 359
 360 #define WLC_RPC_ID_LOOKUP(tbl, _id) (_wlc_rpc_id_lookup(tbl, _id))
 361
 362 #endif                          /* BCMDBG */
 363
 364 /* refer to txpwr_limits_t for each elements, mcs32 is the at the end for 1 byte */
 365 #define TXPOWER_XDR_SZ  (roundup(WLC_NUM_RATES_CCK, 4) + roundup(WLC_NUM_RATES_OFDM, 4) * 4 + \
 366         roundup(WLC_NUM_RATES_MCS_1_STREAM, 4) * 6 + roundup(WLC_NUM_RATES_MCS_2_STREAM, 4) * 2 + \
 367         roundup(1, 4))
 368
 369 #define wlc_rpc_txpwr_limits(b, txpwr, op, err) \
 370         do {                                                                                    \
 371                 (err) = bcm_xdr_##op##_u8_vec((b), (txpwr)->cck, WLC_NUM_RATES_CCK);            \
 372                 ASSERT(!(err));                                                                 \
 373                                                                                                 \
 374                 /* 20 MHz Legacy OFDM rates with SISO transmission */                           \
 375                 (err) = bcm_xdr_##op##_u8_vec((b), (txpwr)->ofdm, WLC_NUM_RATES_OFDM);  \
 376                 ASSERT(!(err));                                                                 \
 377                                                                                                 \
 378                 /* 20 MHz Legacy OFDM rates with CDD transmission */                            \
 379                 (err) = bcm_xdr_##op##_u8_vec((b), (txpwr)->ofdm_cdd, WLC_NUM_RATES_OFDM);   \
 380                 ASSERT(!(err));                                                                 \
 381                                                                                                 \
 382                 /* 40 MHz Legacy OFDM rates with SISO transmission */                           \
 383                 (err) = bcm_xdr_##op##_u8_vec((b), (txpwr)->ofdm_40_siso, WLC_NUM_RATES_OFDM); \
 384                 ASSERT(!(err));                                                                 \
 385                                                                                                 \
 386                 /* 40 MHz Legacy OFDM rates with CDD transmission */                            \
 387                 (err) = bcm_xdr_##op##_u8_vec((b), (txpwr)->ofdm_40_cdd, WLC_NUM_RATES_OFDM); \
 388                 ASSERT(!(err));                                                                 \
 389                                                                                                 \
 390                 /* 20MHz MCS rates SISO/CDD/STBC/SDM */                                                  \
 391                 (err) = bcm_xdr_##op##_u8_vec((b), (txpwr)->mcs_20_siso, WLC_NUM_RATES_MCS_1_STREAM); \
 392                 ASSERT(!(err));                                                                 \
 393                                                                                                 \
 394                 (err) = bcm_xdr_##op##_u8_vec((b), (txpwr)->mcs_20_cdd, WLC_NUM_RATES_MCS_1_STREAM); \
 395                 ASSERT(!(err));                                                                 \
 396                                                                                                 \
 397                 (err) = bcm_xdr_##op##_u8_vec((b), (txpwr)->mcs_20_stbc, WLC_NUM_RATES_MCS_1_STREAM); \
 398                 ASSERT(!(err));                                                                 \
 399                                                                                                 \
 400                 (err) = bcm_xdr_##op##_u8_vec((b), (txpwr)->mcs_20_mimo, WLC_NUM_RATES_MCS_2_STREAM); \
 401                 ASSERT(!(err));                                                                 \
 402                                                                                                 \
 403                 /* 40MHz MCS rates SISO/CDD/STBC/SDM */                                                  \
 404                 (err) = bcm_xdr_##op##_u8_vec((b), (txpwr)->mcs_40_siso, WLC_NUM_RATES_MCS_1_STREAM); \
 405                 ASSERT(!(err));                                                                 \
 406                                                                                                 \
 407                 (err) = bcm_xdr_##op##_u8_vec((b), (txpwr)->mcs_40_cdd, WLC_NUM_RATES_MCS_1_STREAM); \
 408                 ASSERT(!(err));                                                                 \
 409                                                                                                 \
 410                 (err) = bcm_xdr_##op##_u8_vec((b), (txpwr)->mcs_40_stbc, WLC_NUM_RATES_MCS_1_STREAM); \
 411                 ASSERT(!(err));                                                                 \
 412                                                                                                 \
 413                 (err) = bcm_xdr_##op##_u8_vec((b), (txpwr)->mcs_40_mimo, WLC_NUM_RATES_MCS_2_STREAM); \
 414                 ASSERT(!(err));                                                                 \
 415         } while (0)
 416
 417 typedef struct wlc_rpc_ctx {
 418         rpc_info_t *rpc;
 419         wlc_info_t *wlc;
 420         wlc_hw_info_t *wlc_hw;
 421 } wlc_rpc_ctx_t;
 422
 423 static inline rpc_buf_t *wlc_rpc_buf_alloc(rpc_info_t *rpc, bcm_xdr_buf_t *b,
 424                                            uint len, wlc_rpc_id_t rpc_id)
 425 {
 426         rpc_buf_t *rpc_buf;
 427
 428         rpc_buf = bcm_rpc_buf_alloc(rpc, len + sizeof(u32));
 429
 430         if (!rpc_buf)
 431                 return NULL;
 432
 433         bcm_xdr_buf_init(b, bcm_rpc_buf_data(bcm_rpc_tp_get(rpc), rpc_buf),
 434                          len + sizeof(u32));
 435
 436         bcm_xdr_pack_u32(b, rpc_id);
 437
 438         return rpc_buf;
 439 }
 440
 441 #if defined(BCMDBG)
 442 static __inline wlc_rpc_id_t
 443 wlc_rpc_id_get(struct rpc_info *rpc, rpc_buf_t *buf)
 444 {
 445         wlc_rpc_id_t rpc_id;
 446         bcm_xdr_buf_t b;
 447
 448         bcm_xdr_buf_init(&b, bcm_rpc_buf_data(bcm_rpc_tp_get(rpc), buf),
 449                          sizeof(u32));
 450
 451         bcm_xdr_unpack_u32(&b, (u32 *)((unsigned long) & rpc_id));
 452         return rpc_id;
 453 }
 454 #endif
 455
 456 static __inline int _wlc_rpc_call(struct rpc_info *rpc, rpc_buf_t *send)
 457 {
 458         int _err = 0;
 459 #if defined(BCMDBG)
 460         wlc_rpc_id_t rpc_id = wlc_rpc_id_get(rpc, send);
 461         /* const struct name_entry rpc_name_tbl[] = RPC_ID_TABLE; */
 462         static struct name_entry rpc_name_tbl[] = RPC_ID_TABLE;
 463         WL_TRACE(("%s: Called id %s\n", __func__,
 464                   WLC_RPC_ID_LOOKUP(rpc_name_tbl, rpc_id)));
 465 #endif
 466         _err = bcm_rpc_call(rpc, send);
 467         if (_err) {
 468 #if defined(BCMDBG)
 469                 WL_ERROR(("%s: Call id %s FAILED\n", __func__,
 470                           WLC_RPC_ID_LOOKUP(rpc_name_tbl, rpc_id)));
 471 #endif
 472                 _err = 0;
 473         }
 474         return _err;
 475 }
 476
 477 #define wlc_rpc_call(rpc, send) (_wlc_rpc_call(rpc, send))
 478
 479 #include <sbhnddma.h>
 480 #include <sbhndpio.h>
 481 #include <d11.h>
 482
 483 #ifdef WLC_LOW
 484 extern void wlc_rpc_bmac_dispatch(wlc_rpc_ctx_t *rpc_ctx, struct rpc_buf *buf);
 485 extern void wlc_rpc_bmac_dump_txfifohist(wlc_hw_info_t *wlc_hw,
 486                                          bool dump_clear);
 487 #else
 488 extern void wlc_rpc_high_dispatch(wlc_rpc_ctx_t *ctx, struct rpc_buf *buf);
 489 #endif
 490
 491 /* Packed structure for ease of transport across RPC bus along u32 boundary */
 492 typedef struct wlc_rpc_txstatus {
 493         u32 PAD_framelen;
 494         u32 status_frameid;
 495         u32 sequence_lasttxtime;
 496         u32 ackphyrxsh_phyerr;
 497 } wlc_rpc_txstatus_t;
 498
 499 static inline
 500     void txstatus2rpc_txstatus(tx_status_t *txstatus,
 501                                wlc_rpc_txstatus_t *rpc_txstatus)
 502 {
 503         rpc_txstatus->PAD_framelen = txstatus->framelen;
 504         rpc_txstatus->status_frameid =
 505             (txstatus->status << 16) | txstatus->frameid;
 506         rpc_txstatus->sequence_lasttxtime =
 507             (txstatus->sequence << 16) | txstatus->lasttxtime;
 508         rpc_txstatus->ackphyrxsh_phyerr =
 509             (txstatus->ackphyrxsh << 16) | txstatus->phyerr;
 510 }
 511
 512 static inline
 513     void rpc_txstatus2txstatus(wlc_rpc_txstatus_t *rpc_txstatus,
 514                                tx_status_t *txstatus)
 515 {
 516         txstatus->framelen = rpc_txstatus->PAD_framelen & 0xffff;
 517         txstatus->status = (rpc_txstatus->status_frameid >> 16) & 0xffff;
 518         txstatus->frameid = rpc_txstatus->status_frameid & 0xffff;
 519         txstatus->sequence = (rpc_txstatus->sequence_lasttxtime >> 16) & 0xffff;
 520         txstatus->lasttxtime = rpc_txstatus->sequence_lasttxtime & 0xffff;
 521         txstatus->ackphyrxsh = (rpc_txstatus->ackphyrxsh_phyerr >> 16) & 0xffff;
 522         txstatus->phyerr = rpc_txstatus->ackphyrxsh_phyerr & 0xffff;
 523 }
 524
 525 extern void wlc_bmac_dngl_reboot(rpc_info_t *rpc);
 526
 527 #endif                          /* WLC_RPC_H */