drivers/staging/brcm80211/sys/wlc_bmac.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17
  18 #include <linux/kernel.h>
  19 #include <wlc_cfg.h>
  20 #include <linux/module.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <bcmdefs.h>
  24 #include <osl.h>
  25 #include <proto/802.11.h>
  26 #include <bcmwifi.h>
  27 #include <bcmutils.h>
  28 #include <siutils.h>
  29 #include <bcmendian.h>
  30 #include <wlioctl.h>
  31 #include <sbconfig.h>
  32 #include <sbchipc.h>
  33 #include <pcicfg.h>
  34 #include <sbhndpio.h>
  35 #include <sbhnddma.h>
  36 #include <hnddma.h>
  37 #include <hndpmu.h>
  38 #include <d11.h>
  39 #include <wlc_rate.h>
  40 #include <wlc_pub.h>
  41 #include <wlc_channel.h>
  42 #include <bcmsrom.h>
  43 #include <wlc_key.h>
  44 #include <bcmdevs.h>
  45 /* BMAC_NOTE: a WLC_HIGH compile include of wlc.h adds in more structures and type
  46  * dependencies. Need to include these to files to allow a clean include of wlc.h
  47  * with WLC_HIGH defined.
  48  * At some point we may be able to skip the include of wlc.h and instead just
  49  * define a stub wlc_info and band struct to allow rpc calls to get the rpc handle.
  50  */
  51 #include <wlc_event.h>
  52 #include <wlc_mac80211.h>
  53 #include <wlc_bmac.h>
  54 #include <wlc_phy_shim.h>
  55 #include <wlc_phy_hal.h>
  56 #include <wl_export.h>
  57 #include "wl_ucode.h"
  58 #include "d11ucode_ext.h"
  59 #include <bcmotp.h>
  60
  61 /* BMAC_NOTE: With WLC_HIGH defined, some fns in this file make calls to high level
  62  * functions defined in the headers below. We should be eliminating those calls and
  63  * will be able to delete these include lines.
  64  */
  65 #include <wlc_antsel.h>
  66
  67 #include <pcie_core.h>
  68
  69 #include <wlc_alloc.h>
  70 #include <wl_dbg.h>
  71
  72 #define TIMER_INTERVAL_WATCHDOG_BMAC    1000    /* watchdog timer, in unit of ms */
  73
  74 #define SYNTHPU_DLY_APHY_US     3700    /* a phy synthpu_dly time in us */
  75 #define SYNTHPU_DLY_BPHY_US     1050    /* b/g phy synthpu_dly time in us, default */
  76 #define SYNTHPU_DLY_NPHY_US     2048    /* n phy REV3 synthpu_dly time in us, default */
  77 #define SYNTHPU_DLY_LPPHY_US    300     /* lpphy synthpu_dly time in us */
  78
  79 #define SYNTHPU_DLY_PHY_US_QT   100     /* QT synthpu_dly time in us */
  80
  81 #ifndef BMAC_DUP_TO_REMOVE
  82 #define WLC_RM_WAIT_TX_SUSPEND          4       /* Wait Tx Suspend */
  83
  84 #define ANTCNT                  10      /* vanilla M_MAX_ANTCNT value */
  85
  86 #endif                          /* BMAC_DUP_TO_REMOVE */
  87
  88 #define DMAREG(wlc_hw, direction, fifonum)      (D11REV_LT(wlc_hw->corerev, 11) ? \
  89         ((direction == DMA_TX) ? \
  90                 (void *)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].xmt) : \
  91                 (void *)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].rcv)) : \
  92         ((direction == DMA_TX) ? \
  93                 (void *)&(wlc_hw->regs->fifo.f64regs[fifonum].dmaxmt) : \
  94                 (void *)&(wlc_hw->regs->fifo.f64regs[fifonum].dmarcv)))
  95
  96 /*
  97  * The following table lists the buffer memory allocated to xmt fifos in HW.
  98  * the size is in units of 256bytes(one block), total size is HW dependent
  99  * ucode has default fifo partition, sw can overwrite if necessary
 100  *
 101  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
 102  * the twiki is updated before making changes.
 103  */
 104
 105 #define XMTFIFOTBL_STARTREV     20      /* Starting corerev for the fifo size table */
 106
 107 static u16 xmtfifo_sz[][NFIFO] = {
 108         {20, 192, 192, 21, 17, 5},      /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
 109         {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
 110         {20, 192, 192, 21, 17, 5},      /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
 111         {20, 192, 192, 21, 17, 5},      /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
 112         {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
 113 };
 114
 115 static void wlc_clkctl_clk(wlc_hw_info_t *wlc, uint mode);
 116 static void wlc_coreinit(struct wlc_info *wlc);
 117
 118 /* used by wlc_wakeucode_init() */
 119 static void wlc_write_inits(wlc_hw_info_t *wlc_hw, const d11init_t *inits);
 120 static void wlc_ucode_write(wlc_hw_info_t *wlc_hw, const u32 ucode[],
 121                             const uint nbytes);
 122 static void wlc_ucode_download(wlc_hw_info_t *wlc);
 123 static void wlc_ucode_txant_set(wlc_hw_info_t *wlc_hw);
 124
 125 /* used by wlc_dpc() */
 126 static bool wlc_bmac_dotxstatus(wlc_hw_info_t *wlc, tx_status_t *txs,
 127                                 u32 s2);
 128 static bool wlc_bmac_txstatus_corerev4(wlc_hw_info_t *wlc);
 129 static bool wlc_bmac_txstatus(wlc_hw_info_t *wlc, bool bound, bool *fatal);
 130 static bool wlc_bmac_recv(wlc_hw_info_t *wlc_hw, uint fifo, bool bound);
 131
 132 /* used by wlc_down() */
 133 static void wlc_flushqueues(struct wlc_info *wlc);
 134
 135 static void wlc_write_mhf(wlc_hw_info_t *wlc_hw, u16 *mhfs);
 136 static void wlc_mctrl_reset(wlc_hw_info_t *wlc_hw);
 137 static void wlc_corerev_fifofixup(wlc_hw_info_t *wlc_hw);
 138
 139 /* Low Level Prototypes */
 140 static u16 wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset,
 141                                    u32 sel);
 142 static void wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, u16 v,
 143                                   u32 sel);
 144 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
 145 static void wlc_bmac_detach_dmapio(wlc_hw_info_t *wlc_hw);
 146 static void wlc_ucode_bsinit(wlc_hw_info_t *wlc_hw);
 147 static bool wlc_validboardtype(wlc_hw_info_t *wlc);
 148 static bool wlc_isgoodchip(wlc_hw_info_t *wlc_hw);
 149 static char *wlc_get_macaddr(wlc_hw_info_t *wlc_hw);
 150 static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
 151 static void wlc_mctrl_write(wlc_hw_info_t *wlc_hw);
 152 static void wlc_ucode_mute_override_set(wlc_hw_info_t *wlc_hw);
 153 static void wlc_ucode_mute_override_clear(wlc_hw_info_t *wlc_hw);
 154 static u32 wlc_wlintrsoff(struct wlc_info *wlc);
 155 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
 156 static void wlc_gpio_init(struct wlc_info *wlc);
 157 static void wlc_write_hw_bcntemplate0(wlc_hw_info_t *wlc_hw, void *bcn,
 158                                       int len);
 159 static void wlc_write_hw_bcntemplate1(wlc_hw_info_t *wlc_hw, void *bcn,
 160                                       int len);
 161 static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
 162 static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
 163 static void wlc_bmac_setband(wlc_hw_info_t *wlc_hw, uint bandunit,
 164                              chanspec_t chanspec);
 165 static void wlc_bmac_update_slot_timing(wlc_hw_info_t *wlc_hw, bool shortslot);
 166 static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t *wlc_hw);
 167 static u16 wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t *wlc_hw,
 168                                              u8 rate);
 169
 170 /* === Low Level functions === */
 171
 172 void wlc_bmac_set_shortslot(wlc_hw_info_t *wlc_hw, bool shortslot)
 173 {
 174         wlc_hw->shortslot = shortslot;
 175
 176         if (BAND_2G(wlc_hw->band->bandtype) && wlc_hw->up) {
 177                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
 178                 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
 179                 wlc_enable_mac(wlc_hw->wlc);
 180         }
 181 }
 182
 183 /*
 184  * Update the slot timing for standard 11b/g (20us slots)
 185  * or shortslot 11g (9us slots)
 186  * The PSM needs to be suspended for this call.
 187  */
 188 static void wlc_bmac_update_slot_timing(wlc_hw_info_t *wlc_hw, bool shortslot)
 189 {
 190         struct osl_info *osh;
 191         d11regs_t *regs;
 192
 193         osh = wlc_hw->osh;
 194         regs = wlc_hw->regs;
 195
 196         if (shortslot) {
 197                 /* 11g short slot: 11a timing */
 198                 W_REG(osh, &regs->ifs_slot, 0x0207);    /* APHY_SLOT_TIME */
 199                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 200         } else {
 201                 /* 11g long slot: 11b timing */
 202                 W_REG(osh, &regs->ifs_slot, 0x0212);    /* BPHY_SLOT_TIME */
 203                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 204         }
 205 }
 206
 207 static void WLBANDINITFN(wlc_ucode_bsinit) (wlc_hw_info_t *wlc_hw)
 208 {
 209         /* init microcode host flags */
 210         wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 211
 212         /* do band-specific ucode IHR, SHM, and SCR inits */
 213         if (D11REV_IS(wlc_hw->corerev, 23)) {
 214                 if (WLCISNPHY(wlc_hw->band)) {
 215                         wlc_write_inits(wlc_hw, d11n0bsinitvals16);
 216                 } else {
 217                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
 218                                   __func__, wlc_hw->unit, wlc_hw->corerev));
 219                 }
 220         } else {
 221                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 222                         if (WLCISLCNPHY(wlc_hw->band)) {
 223                                 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
 224                         } else
 225                                 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n", __func__, wlc_hw->unit, wlc_hw->corerev));
 226                 } else {
 227                         WL_ERROR(("%s: wl%d: unsupported corerev %d\n",
 228                                   __func__, wlc_hw->unit, wlc_hw->corerev));
 229                 }
 230         }
 231 }
 232
 233 /* switch to new band but leave it inactive */
 234 static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
 235 {
 236         wlc_hw_info_t *wlc_hw = wlc->hw;
 237         u32 macintmask;
 238         u32 tmp;
 239
 240         WL_TRACE(("wl%d: wlc_setband_inact\n", wlc_hw->unit));
 241
 242         ASSERT(bandunit != wlc_hw->band->bandunit);
 243         ASSERT(si_iscoreup(wlc_hw->sih));
 244         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
 245                0);
 246
 247         /* disable interrupts */
 248         macintmask = wl_intrsoff(wlc->wl);
 249
 250         /* radio off */
 251         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 252
 253         ASSERT(wlc_hw->clk);
 254
 255         if (D11REV_LT(wlc_hw->corerev, 17))
 256                 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
 257
 258         wlc_bmac_core_phy_clk(wlc_hw, OFF);
 259
 260         wlc_setxband(wlc_hw, bandunit);
 261
 262         return macintmask;
 263 }
 264
 265 /* Process received frames */
 266 /*
 267  * Return true if more frames need to be processed. false otherwise.
 268  * Param 'bound' indicates max. # frames to process before break out.
 269  */
 270 static bool BCMFASTPATH
 271 wlc_bmac_recv(wlc_hw_info_t *wlc_hw, uint fifo, bool bound)
 272 {
 273         struct sk_buff *p;
 274         struct sk_buff *head = NULL;
 275         struct sk_buff *tail = NULL;
 276         uint n = 0;
 277         uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
 278         u32 tsf_h, tsf_l;
 279         wlc_d11rxhdr_t *wlc_rxhdr = NULL;
 280
 281         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
 282         /* gather received frames */
 283         while ((p = dma_rx(wlc_hw->di[fifo]))) {
 284
 285                 if (!tail)
 286                         head = tail = p;
 287                 else {
 288                         tail->prev = p;
 289                         tail = p;
 290                 }
 291
 292                 /* !give others some time to run! */
 293                 if (++n >= bound_limit)
 294                         break;
 295         }
 296
 297         /* get the TSF REG reading */
 298         wlc_bmac_read_tsf(wlc_hw, &tsf_l, &tsf_h);
 299
 300         /* post more rbufs */
 301         dma_rxfill(wlc_hw->di[fifo]);
 302
 303         /* process each frame */
 304         while ((p = head) != NULL) {
 305                 head = head->prev;
 306                 p->prev = NULL;
 307
 308                 /* record the tsf_l in wlc_rxd11hdr */
 309                 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
 310                 wlc_rxhdr->tsf_l = htol32(tsf_l);
 311
 312                 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
 313                 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
 314
 315                 wlc_recv(wlc_hw->wlc, p);
 316         }
 317
 318         return n >= bound_limit;
 319 }
 320
 321 /* second-level interrupt processing
 322  *   Return true if another dpc needs to be re-scheduled. false otherwise.
 323  *   Param 'bounded' indicates if applicable loops should be bounded.
 324  */
 325 bool BCMFASTPATH wlc_dpc(struct wlc_info *wlc, bool bounded)
 326 {
 327         u32 macintstatus;
 328         wlc_hw_info_t *wlc_hw = wlc->hw;
 329         d11regs_t *regs = wlc_hw->regs;
 330         bool fatal = false;
 331
 332         if (DEVICEREMOVED(wlc)) {
 333                 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
 334                 wl_down(wlc->wl);
 335                 return false;
 336         }
 337
 338         /* grab and clear the saved software intstatus bits */
 339         macintstatus = wlc->macintstatus;
 340         wlc->macintstatus = 0;
 341
 342         WL_TRACE(("wl%d: wlc_dpc: macintstatus 0x%x\n", wlc_hw->unit,
 343                   macintstatus));
 344
 345         if (macintstatus & MI_PRQ) {
 346                 /* Process probe request FIFO */
 347                 ASSERT(0 && "PRQ Interrupt in non-MBSS");
 348         }
 349
 350         /* BCN template is available */
 351         /* ZZZ: Use AP_ACTIVE ? */
 352         if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub) || wlc->aps_associated)
 353             && (macintstatus & MI_BCNTPL)) {
 354                 wlc_update_beacon(wlc);
 355         }
 356
 357         /* PMQ entry addition */
 358         if (macintstatus & MI_PMQ) {
 359         }
 360
 361         /* tx status */
 362         if (macintstatus & MI_TFS) {
 363                 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
 364                         wlc->macintstatus |= MI_TFS;
 365                 if (fatal) {
 366                         WL_ERROR(("MI_TFS: fatal\n"));
 367                         goto fatal;
 368                 }
 369         }
 370
 371         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
 372                 wlc_tbtt(wlc, regs);
 373
 374         /* ATIM window end */
 375         if (macintstatus & MI_ATIMWINEND) {
 376                 WL_TRACE(("wlc_isr: end of ATIM window\n"));
 377
 378                 OR_REG(wlc_hw->osh, &regs->maccommand, wlc->qvalid);
 379                 wlc->qvalid = 0;
 380         }
 381
 382         /* phy tx error */
 383         if (macintstatus & MI_PHYTXERR) {
 384                 WLCNTINCR(wlc->pub->_cnt->txphyerr);
 385         }
 386
 387         /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
 388         if (macintstatus & MI_DMAINT) {
 389                 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
 390                         wlc->macintstatus |= MI_DMAINT;
 391                 }
 392         }
 393
 394         /* TX FIFO suspend/flush completion */
 395         if (macintstatus & MI_TXSTOP) {
 396                 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
 397                         /*      WL_ERROR(("dpc: fifo_suspend_comlete\n")); */
 398                 }
 399         }
 400
 401         /* noise sample collected */
 402         if (macintstatus & MI_BG_NOISE) {
 403                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
 404         }
 405
 406         if (macintstatus & MI_GP0) {
 407                 WL_ERROR(("wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now));
 408
 409                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
 410                                         __func__, wlc_hw->sih->chip,
 411                                         wlc_hw->sih->chiprev);
 412
 413                 WLCNTINCR(wlc->pub->_cnt->psmwds);
 414
 415                 /* big hammer */
 416                 wl_init(wlc->wl);
 417         }
 418
 419         /* gptimer timeout */
 420         if (macintstatus & MI_TO) {
 421                 W_REG(wlc_hw->osh, &regs->gptimer, 0);
 422         }
 423
 424         if (macintstatus & MI_RFDISABLE) {
 425 #if defined(BCMDBG)
 426                 u32 rfd = R_REG(wlc_hw->osh, &regs->phydebug) & PDBG_RFD;
 427 #endif
 428
 429                 WL_ERROR(("wl%d: MAC Detected a change on the RF Disable Input 0x%x\n", wlc_hw->unit, rfd));
 430
 431                 WLCNTINCR(wlc->pub->_cnt->rfdisable);
 432         }
 433
 434         /* send any enq'd tx packets. Just makes sure to jump start tx */
 435         if (!pktq_empty(&wlc->active_queue->q))
 436                 wlc_send_q(wlc, wlc->active_queue);
 437
 438         ASSERT(wlc_ps_check(wlc));
 439
 440         /* make sure the bound indication and the implementation are in sync */
 441         ASSERT(bounded == true || wlc->macintstatus == 0);
 442
 443         /* it isn't done and needs to be resched if macintstatus is non-zero */
 444         return wlc->macintstatus != 0;
 445
 446  fatal:
 447         wl_init(wlc->wl);
 448         return wlc->macintstatus != 0;
 449 }
 450
 451 /* common low-level watchdog code */
 452 void wlc_bmac_watchdog(void *arg)
 453 {
 454         struct wlc_info *wlc = (struct wlc_info *) arg;
 455         wlc_hw_info_t *wlc_hw = wlc->hw;
 456
 457         WL_TRACE(("wl%d: wlc_bmac_watchdog\n", wlc_hw->unit));
 458
 459         if (!wlc_hw->up)
 460                 return;
 461
 462         /* increment second count */
 463         wlc_hw->now++;
 464
 465         /* Check for FIFO error interrupts */
 466         wlc_bmac_fifoerrors(wlc_hw);
 467
 468         /* make sure RX dma has buffers */
 469         dma_rxfill(wlc->hw->di[RX_FIFO]);
 470         if (D11REV_IS(wlc_hw->corerev, 4)) {
 471                 dma_rxfill(wlc->hw->di[RX_TXSTATUS_FIFO]);
 472         }
 473
 474         wlc_phy_watchdog(wlc_hw->band->pi);
 475 }
 476
 477 void
 478 wlc_bmac_set_chanspec(wlc_hw_info_t *wlc_hw, chanspec_t chanspec, bool mute,
 479                       struct txpwr_limits *txpwr)
 480 {
 481         uint bandunit;
 482
 483         WL_TRACE(("wl%d: wlc_bmac_set_chanspec 0x%x\n", wlc_hw->unit,
 484                   chanspec));
 485
 486         wlc_hw->chanspec = chanspec;
 487
 488         /* Switch bands if necessary */
 489         if (NBANDS_HW(wlc_hw) > 1) {
 490                 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
 491                 if (wlc_hw->band->bandunit != bandunit) {
 492                         /* wlc_bmac_setband disables other bandunit,
 493                          *  use light band switch if not up yet
 494                          */
 495                         if (wlc_hw->up) {
 496                                 wlc_phy_chanspec_radio_set(wlc_hw->
 497                                                            bandstate[bandunit]->
 498                                                            pi, chanspec);
 499                                 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
 500                         } else {
 501                                 wlc_setxband(wlc_hw, bandunit);
 502                         }
 503                 }
 504         }
 505
 506         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
 507
 508         if (!wlc_hw->up) {
 509                 if (wlc_hw->clk)
 510                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
 511                                                   chanspec);
 512                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
 513         } else {
 514                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
 515                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
 516
 517                 /* Update muting of the channel */
 518                 wlc_bmac_mute(wlc_hw, mute, 0);
 519         }
 520 }
 521
 522 int wlc_bmac_revinfo_get(wlc_hw_info_t *wlc_hw, wlc_bmac_revinfo_t *revinfo)
 523 {
 524         si_t *sih = wlc_hw->sih;
 525         uint idx;
 526
 527         revinfo->vendorid = wlc_hw->vendorid;
 528         revinfo->deviceid = wlc_hw->deviceid;
 529
 530         revinfo->boardrev = wlc_hw->boardrev;
 531         revinfo->corerev = wlc_hw->corerev;
 532         revinfo->sromrev = wlc_hw->sromrev;
 533         revinfo->chiprev = sih->chiprev;
 534         revinfo->chip = sih->chip;
 535         revinfo->chippkg = sih->chippkg;
 536         revinfo->boardtype = sih->boardtype;
 537         revinfo->boardvendor = sih->boardvendor;
 538         revinfo->bustype = sih->bustype;
 539         revinfo->buscoretype = sih->buscoretype;
 540         revinfo->buscorerev = sih->buscorerev;
 541         revinfo->issim = sih->issim;
 542
 543         revinfo->nbands = NBANDS_HW(wlc_hw);
 544
 545         for (idx = 0; idx < NBANDS_HW(wlc_hw); idx++) {
 546                 wlc_hwband_t *band = wlc_hw->bandstate[idx];
 547                 revinfo->band[idx].bandunit = band->bandunit;
 548                 revinfo->band[idx].bandtype = band->bandtype;
 549                 revinfo->band[idx].phytype = band->phytype;
 550                 revinfo->band[idx].phyrev = band->phyrev;
 551                 revinfo->band[idx].radioid = band->radioid;
 552                 revinfo->band[idx].radiorev = band->radiorev;
 553                 revinfo->band[idx].abgphy_encore = band->abgphy_encore;
 554                 revinfo->band[idx].anarev = 0;
 555
 556         }
 557         return 0;
 558 }
 559
 560 int wlc_bmac_state_get(wlc_hw_info_t *wlc_hw, wlc_bmac_state_t *state)
 561 {
 562         state->machwcap = wlc_hw->machwcap;
 563
 564         return 0;
 565 }
 566
 567 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
 568 {
 569         uint i;
 570         char name[8];
 571         /* ucode host flag 2 needed for pio mode, independent of band and fifo */
 572         u16 pio_mhf2 = 0;
 573         wlc_hw_info_t *wlc_hw = wlc->hw;
 574         uint unit = wlc_hw->unit;
 575         wlc_tunables_t *tune = wlc->pub->tunables;
 576
 577         /* name and offsets for dma_attach */
 578         snprintf(name, sizeof(name), "wl%d", unit);
 579
 580         if (wlc_hw->di[0] == 0) {       /* Init FIFOs */
 581                 uint addrwidth;
 582                 int dma_attach_err = 0;
 583                 struct osl_info *osh = wlc_hw->osh;
 584
 585                 /* Find out the DMA addressing capability and let OS know
 586                  * All the channels within one DMA core have 'common-minimum' same
 587                  * capability
 588                  */
 589                 addrwidth =
 590                     dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
 591
 592                 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
 593                         WL_ERROR(("wl%d: wlc_attach: alloc_dma_resources failed\n", unit));
 594                         return false;
 595                 }
 596
 597                 /*
 598                  * FIFO 0
 599                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
 600                  * RX: RX_FIFO (RX data packets)
 601                  */
 602                 ASSERT(TX_AC_BK_FIFO == 0);
 603                 ASSERT(RX_FIFO == 0);
 604                 wlc_hw->di[0] = dma_attach(osh, name, wlc_hw->sih,
 605                                            (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
 606                                             NULL), DMAREG(wlc_hw, DMA_RX, 0),
 607                                            (wme ? tune->ntxd : 0), tune->nrxd,
 608                                            tune->rxbufsz, -1, tune->nrxbufpost,
 609                                            WL_HWRXOFF, &wl_msg_level);
 610                 dma_attach_err |= (NULL == wlc_hw->di[0]);
 611
 612                 /*
 613                  * FIFO 1
 614                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
 615                  *   (legacy) TX_DATA_FIFO (TX data packets)
 616                  * RX: UNUSED
 617                  */
 618                 ASSERT(TX_AC_BE_FIFO == 1);
 619                 ASSERT(TX_DATA_FIFO == 1);
 620                 wlc_hw->di[1] = dma_attach(osh, name, wlc_hw->sih,
 621                                            DMAREG(wlc_hw, DMA_TX, 1), NULL,
 622                                            tune->ntxd, 0, 0, -1, 0, 0,
 623                                            &wl_msg_level);
 624                 dma_attach_err |= (NULL == wlc_hw->di[1]);
 625
 626                 /*
 627                  * FIFO 2
 628                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
 629                  * RX: UNUSED
 630                  */
 631                 ASSERT(TX_AC_VI_FIFO == 2);
 632                 wlc_hw->di[2] = dma_attach(osh, name, wlc_hw->sih,
 633                                            DMAREG(wlc_hw, DMA_TX, 2), NULL,
 634                                            tune->ntxd, 0, 0, -1, 0, 0,
 635                                            &wl_msg_level);
 636                 dma_attach_err |= (NULL == wlc_hw->di[2]);
 637                 /*
 638                  * FIFO 3
 639                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
 640                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
 641                  * RX: RX_TXSTATUS_FIFO (transmit-status packets)
 642                  *      for corerev < 5 only
 643                  */
 644                 ASSERT(TX_AC_VO_FIFO == 3);
 645                 ASSERT(TX_CTL_FIFO == 3);
 646                 if (D11REV_IS(wlc_hw->corerev, 4)) {
 647                         ASSERT(RX_TXSTATUS_FIFO == 3);
 648                         wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
 649                                                    DMAREG(wlc_hw, DMA_TX, 3),
 650                                                    DMAREG(wlc_hw, DMA_RX, 3),
 651                                                    tune->ntxd, tune->nrxd,
 652                                                    sizeof(tx_status_t), -1,
 653                                                    tune->nrxbufpost, 0,
 654                                                    &wl_msg_level);
 655                         dma_attach_err |= (NULL == wlc_hw->di[3]);
 656                 } else {
 657                         wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
 658                                                    DMAREG(wlc_hw, DMA_TX, 3),
 659                                                    NULL, tune->ntxd, 0, 0, -1,
 660                                                    0, 0, &wl_msg_level);
 661                         dma_attach_err |= (NULL == wlc_hw->di[3]);
 662                 }
 663 /* Cleaner to leave this as if with AP defined */
 664
 665                 if (dma_attach_err) {
 666                         WL_ERROR(("wl%d: wlc_attach: dma_attach failed\n",
 667                                   unit));
 668                         return false;
 669                 }
 670
 671                 /* get pointer to dma engine tx flow control variable */
 672                 for (i = 0; i < NFIFO; i++)
 673                         if (wlc_hw->di[i])
 674                                 wlc_hw->txavail[i] =
 675                                     (uint *) dma_getvar(wlc_hw->di[i],
 676                                                         "&txavail");
 677         }
 678
 679         /* initial ucode host flags */
 680         wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
 681
 682         return true;
 683 }
 684
 685 static void wlc_bmac_detach_dmapio(wlc_hw_info_t *wlc_hw)
 686 {
 687         uint j;
 688
 689         for (j = 0; j < NFIFO; j++) {
 690                 if (wlc_hw->di[j]) {
 691                         dma_detach(wlc_hw->di[j]);
 692                         wlc_hw->di[j] = NULL;
 693                 }
 694         }
 695 }
 696
 697 /* low level attach
 698  *    run backplane attach, init nvram
 699  *    run phy attach
 700  *    initialize software state for each core and band
 701  *    put the whole chip in reset(driver down state), no clock
 702  */
 703 int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
 704                     bool piomode, struct osl_info *osh, void *regsva,
 705                     uint bustype, void *btparam)
 706 {
 707         wlc_hw_info_t *wlc_hw;
 708         d11regs_t *regs;
 709         char *macaddr = NULL;
 710         char *vars;
 711         uint err = 0;
 712         uint j;
 713         bool wme = false;
 714         shared_phy_params_t sha_params;
 715
 716         WL_TRACE(("wl%d: wlc_bmac_attach: vendor 0x%x device 0x%x\n", unit,
 717                   vendor, device));
 718
 719         ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF);
 720
 721         wme = true;
 722
 723         wlc_hw = wlc->hw;
 724         wlc_hw->wlc = wlc;
 725         wlc_hw->unit = unit;
 726         wlc_hw->osh = osh;
 727         wlc_hw->band = wlc_hw->bandstate[0];
 728         wlc_hw->_piomode = piomode;
 729
 730         /* populate wlc_hw_info_t with default values  */
 731         wlc_bmac_info_init(wlc_hw);
 732
 733         /*
 734          * Do the hardware portion of the attach.
 735          * Also initialize software state that depends on the particular hardware
 736          * we are running.
 737          */
 738         wlc_hw->sih = si_attach((uint) device, osh, regsva, bustype, btparam,
 739                                 &wlc_hw->vars, &wlc_hw->vars_size);
 740         if (wlc_hw->sih == NULL) {
 741                 WL_ERROR(("wl%d: wlc_bmac_attach: si_attach failed\n", unit));
 742                 err = 11;
 743                 goto fail;
 744         }
 745         vars = wlc_hw->vars;
 746
 747         /*
 748          * Get vendid/devid nvram overwrites, which could be different
 749          * than those the BIOS recognizes for devices on PCMCIA_BUS,
 750          * SDIO_BUS, and SROMless devices on PCI_BUS.
 751          */
 752 #ifdef BCMBUSTYPE
 753         bustype = BCMBUSTYPE;
 754 #endif
 755         if (bustype != SI_BUS) {
 756                 char *var;
 757
 758                 var = getvar(vars, "vendid");
 759                 if (var) {
 760                         vendor = (u16) simple_strtoul(var, NULL, 0);
 761                         WL_ERROR(("Overriding vendor id = 0x%x\n", vendor));
 762                 }
 763                 var = getvar(vars, "devid");
 764                 if (var) {
 765                         u16 devid = (u16) simple_strtoul(var, NULL, 0);
 766                         if (devid != 0xffff) {
 767                                 device = devid;
 768                                 WL_ERROR(("Overriding device id = 0x%x\n",
 769                                           device));
 770                         }
 771                 }
 772
 773                 /* verify again the device is supported */
 774                 if (!wlc_chipmatch(vendor, device)) {
 775                         WL_ERROR(("wl%d: wlc_bmac_attach: Unsupported vendor/device (0x%x/0x%x)\n", unit, vendor, device));
 776                         err = 12;
 777                         goto fail;
 778                 }
 779         }
 780
 781         wlc_hw->vendorid = vendor;
 782         wlc_hw->deviceid = device;
 783
 784         /* set bar0 window to point at D11 core */
 785         wlc_hw->regs = (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID, 0);
 786         wlc_hw->corerev = si_corerev(wlc_hw->sih);
 787
 788         regs = wlc_hw->regs;
 789
 790         wlc->regs = wlc_hw->regs;
 791
 792         /* validate chip, chiprev and corerev */
 793         if (!wlc_isgoodchip(wlc_hw)) {
 794                 err = 13;
 795                 goto fail;
 796         }
 797
 798         /* initialize power control registers */
 799         si_clkctl_init(wlc_hw->sih);
 800
 801         /* request fastclock and force fastclock for the rest of attach
 802          * bring the d11 core out of reset.
 803          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
 804          *   But it will be called again inside wlc_corereset, after d11 is out of reset.
 805          */
 806         wlc_clkctl_clk(wlc_hw, CLK_FAST);
 807         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
 808
 809         if (!wlc_bmac_validate_chip_access(wlc_hw)) {
 810                 WL_ERROR(("wl%d: wlc_bmac_attach: validate_chip_access failed\n", unit));
 811                 err = 14;
 812                 goto fail;
 813         }
 814
 815         /* get the board rev, used just below */
 816         j = getintvar(vars, "boardrev");
 817         /* promote srom boardrev of 0xFF to 1 */
 818         if (j == BOARDREV_PROMOTABLE)
 819                 j = BOARDREV_PROMOTED;
 820         wlc_hw->boardrev = (u16) j;
 821         if (!wlc_validboardtype(wlc_hw)) {
 822                 WL_ERROR(("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n", unit, wlc_hw->sih->boardtype, wlc_hw->boardrev));
 823                 err = 15;
 824                 goto fail;
 825         }
 826         wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
 827         wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
 828         wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
 829
 830         if (D11REV_LE(wlc_hw->corerev, 4)
 831             || (wlc_hw->boardflags & BFL_NOPLLDOWN))
 832                 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
 833
 834         if ((wlc_hw->sih->bustype == PCI_BUS)
 835             && (si_pci_war16165(wlc_hw->sih)))
 836                 wlc->war16165 = true;
 837
 838         /* check device id(srom, nvram etc.) to set bands */
 839         if (wlc_hw->deviceid == BCM43224_D11N_ID) {
 840                 /* Dualband boards */
 841                 wlc_hw->_nbands = 2;
 842         } else
 843                 wlc_hw->_nbands = 1;
 844
 845         if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
 846                 wlc_hw->_nbands = 1;
 847
 848         /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
 849          * init of these values
 850          */
 851         wlc->vendorid = wlc_hw->vendorid;
 852         wlc->deviceid = wlc_hw->deviceid;
 853         wlc->pub->sih = wlc_hw->sih;
 854         wlc->pub->corerev = wlc_hw->corerev;
 855         wlc->pub->sromrev = wlc_hw->sromrev;
 856         wlc->pub->boardrev = wlc_hw->boardrev;
 857         wlc->pub->boardflags = wlc_hw->boardflags;
 858         wlc->pub->boardflags2 = wlc_hw->boardflags2;
 859         wlc->pub->_nbands = wlc_hw->_nbands;
 860
 861         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
 862
 863         if (wlc_hw->physhim == NULL) {
 864                 WL_ERROR(("wl%d: wlc_bmac_attach: wlc_phy_shim_attach failed\n",
 865                           unit));
 866                 err = 25;
 867                 goto fail;
 868         }
 869
 870         /* pass all the parameters to wlc_phy_shared_attach in one struct */
 871         sha_params.osh = osh;
 872         sha_params.sih = wlc_hw->sih;
 873         sha_params.physhim = wlc_hw->physhim;
 874         sha_params.unit = unit;
 875         sha_params.corerev = wlc_hw->corerev;
 876         sha_params.vars = vars;
 877         sha_params.vid = wlc_hw->vendorid;
 878         sha_params.did = wlc_hw->deviceid;
 879         sha_params.chip = wlc_hw->sih->chip;
 880         sha_params.chiprev = wlc_hw->sih->chiprev;
 881         sha_params.chippkg = wlc_hw->sih->chippkg;
 882         sha_params.sromrev = wlc_hw->sromrev;
 883         sha_params.boardtype = wlc_hw->sih->boardtype;
 884         sha_params.boardrev = wlc_hw->boardrev;
 885         sha_params.boardvendor = wlc_hw->sih->boardvendor;
 886         sha_params.boardflags = wlc_hw->boardflags;
 887         sha_params.boardflags2 = wlc_hw->boardflags2;
 888         sha_params.bustype = wlc_hw->sih->bustype;
 889         sha_params.buscorerev = wlc_hw->sih->buscorerev;
 890
 891         /* alloc and save pointer to shared phy state area */
 892         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
 893         if (!wlc_hw->phy_sh) {
 894                 err = 16;
 895                 goto fail;
 896         }
 897
 898         /* initialize software state for each core and band */
 899         for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
 900                 /*
 901                  * band0 is always 2.4Ghz
 902                  * band1, if present, is 5Ghz
 903                  */
 904
 905                 /* So if this is a single band 11a card, use band 1 */
 906                 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
 907                         j = BAND_5G_INDEX;
 908
 909                 wlc_setxband(wlc_hw, j);
 910
 911                 wlc_hw->band->bandunit = j;
 912                 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 913                 wlc->band->bandunit = j;
 914                 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 915                 wlc->core->coreidx = si_coreidx(wlc_hw->sih);
 916
 917                 if (D11REV_GE(wlc_hw->corerev, 13)) {
 918                         wlc_hw->machwcap = R_REG(wlc_hw->osh, &regs->machwcap);
 919                         wlc_hw->machwcap_backup = wlc_hw->machwcap;
 920                 }
 921
 922                 /* init tx fifo size */
 923                 ASSERT((wlc_hw->corerev - XMTFIFOTBL_STARTREV) <
 924                        ARRAY_SIZE(xmtfifo_sz));
 925                 wlc_hw->xmtfifo_sz =
 926                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
 927
 928                 /* Get a phy for this band */
 929                 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
 930                         (void *)regs, wlc_hw->band->bandtype, vars);
 931                 if (wlc_hw->band->pi == NULL) {
 932                         WL_ERROR(("wl%d: wlc_bmac_attach: wlc_phy_attach failed\n", unit));
 933                         err = 17;
 934                         goto fail;
 935                 }
 936
 937                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
 938
 939                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
 940                                        &wlc_hw->band->phyrev,
 941                                        &wlc_hw->band->radioid,
 942                                        &wlc_hw->band->radiorev);
 943                 wlc_hw->band->abgphy_encore =
 944                     wlc_phy_get_encore(wlc_hw->band->pi);
 945                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
 946                 wlc_hw->band->core_flags =
 947                     wlc_phy_get_coreflags(wlc_hw->band->pi);
 948
 949                 /* verify good phy_type & supported phy revision */
 950                 if (WLCISNPHY(wlc_hw->band)) {
 951                         if (NCONF_HAS(wlc_hw->band->phyrev))
 952                                 goto good_phy;
 953                         else
 954                                 goto bad_phy;
 955                 } else if (WLCISLCNPHY(wlc_hw->band)) {
 956                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
 957                                 goto good_phy;
 958                         else
 959                                 goto bad_phy;
 960                 } else {
 961  bad_phy:
 962                         WL_ERROR(("wl%d: wlc_bmac_attach: unsupported phy type/rev (%d/%d)\n", unit, wlc_hw->band->phytype, wlc_hw->band->phyrev));
 963                         err = 18;
 964                         goto fail;
 965                 }
 966
 967  good_phy:
 968                 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
 969                  * high level attach. However we can not make that change until all low level access
 970                  * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
 971                  * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
 972                  * low only init when all fns updated.
 973                  */
 974                 wlc->band->pi = wlc_hw->band->pi;
 975                 wlc->band->phytype = wlc_hw->band->phytype;
 976                 wlc->band->phyrev = wlc_hw->band->phyrev;
 977                 wlc->band->radioid = wlc_hw->band->radioid;
 978                 wlc->band->radiorev = wlc_hw->band->radiorev;
 979
 980                 /* default contention windows size limits */
 981                 wlc_hw->band->CWmin = APHY_CWMIN;
 982                 wlc_hw->band->CWmax = PHY_CWMAX;
 983
 984                 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
 985                         err = 19;
 986                         goto fail;
 987                 }
 988         }
 989
 990         /* disable core to match driver "down" state */
 991         wlc_coredisable(wlc_hw);
 992
 993         /* Match driver "down" state */
 994         if (wlc_hw->sih->bustype == PCI_BUS)
 995                 si_pci_down(wlc_hw->sih);
 996
 997         /* register sb interrupt callback functions */
 998         si_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
 999                                   (void *)wlc_wlintrsrestore, NULL, wlc);
1000
1001         /* turn off pll and xtal to match driver "down" state */
1002         wlc_bmac_xtal(wlc_hw, OFF);
1003
1004         /* *********************************************************************
1005          * The hardware is in the DOWN state at this point. D11 core
1006          * or cores are in reset with clocks off, and the board PLLs
1007          * are off if possible.
1008          *
1009          * Beyond this point, wlc->sbclk == false and chip registers
1010          * should not be touched.
1011          *********************************************************************
1012          */
1013
1014         /* init etheraddr state variables */
1015         macaddr = wlc_get_macaddr(wlc_hw);
1016         if (macaddr == NULL) {
1017                 WL_ERROR(("wl%d: wlc_bmac_attach: macaddr not found\n", unit));
1018                 err = 21;
1019                 goto fail;
1020         }
1021         bcm_ether_atoe(macaddr, &wlc_hw->etheraddr);
1022         if (ETHER_ISBCAST((char *)&wlc_hw->etheraddr) ||
1023             ETHER_ISNULLADDR((char *)&wlc_hw->etheraddr)) {
1024                 WL_ERROR(("wl%d: wlc_bmac_attach: bad macaddr %s\n", unit,
1025                           macaddr));
1026                 err = 22;
1027                 goto fail;
1028         }
1029
1030         WL_ERROR(("%s:: deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
1031                   __func__, wlc_hw->deviceid, wlc_hw->_nbands,
1032                   wlc_hw->sih->boardtype, macaddr));
1033
1034         return err;
1035
1036  fail:
1037         WL_ERROR(("wl%d: wlc_bmac_attach: failed with err %d\n", unit, err));
1038         return err;
1039 }
1040
1041 /*
1042  * Initialize wlc_info default values ...
1043  * may get overrides later in this function
1044  *  BMAC_NOTES, move low out and resolve the dangling ones
1045  */
1046 void wlc_bmac_info_init(wlc_hw_info_t *wlc_hw)
1047 {
1048         struct wlc_info *wlc = wlc_hw->wlc;
1049
1050         /* set default sw macintmask value */
1051         wlc->defmacintmask = DEF_MACINTMASK;
1052
1053         /* various 802.11g modes */
1054         wlc_hw->shortslot = false;
1055
1056         wlc_hw->SFBL = RETRY_SHORT_FB;
1057         wlc_hw->LFBL = RETRY_LONG_FB;
1058
1059         /* default mac retry limits */
1060         wlc_hw->SRL = RETRY_SHORT_DEF;
1061         wlc_hw->LRL = RETRY_LONG_DEF;
1062         wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
1063 }
1064
1065 /*
1066  * low level detach
1067  */
1068 int wlc_bmac_detach(struct wlc_info *wlc)
1069 {
1070         uint i;
1071         wlc_hwband_t *band;
1072         wlc_hw_info_t *wlc_hw = wlc->hw;
1073         int callbacks;
1074
1075         callbacks = 0;
1076
1077         if (wlc_hw->sih) {
1078                 /* detach interrupt sync mechanism since interrupt is disabled and per-port
1079                  * interrupt object may has been freed. this must be done before sb core switch
1080                  */
1081                 si_deregister_intr_callback(wlc_hw->sih);
1082
1083                 if (wlc_hw->sih->bustype == PCI_BUS)
1084                         si_pci_sleep(wlc_hw->sih);
1085         }
1086
1087         wlc_bmac_detach_dmapio(wlc_hw);
1088
1089         band = wlc_hw->band;
1090         for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
1091                 if (band->pi) {
1092                         /* Detach this band's phy */
1093                         wlc_phy_detach(band->pi);
1094                         band->pi = NULL;
1095                 }
1096                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1097         }
1098
1099         /* Free shared phy state */
1100         wlc_phy_shared_detach(wlc_hw->phy_sh);
1101
1102         wlc_phy_shim_detach(wlc_hw->physhim);
1103
1104         /* free vars */
1105         if (wlc_hw->vars) {
1106                 kfree(wlc_hw->vars);
1107                 wlc_hw->vars = NULL;
1108         }
1109
1110         if (wlc_hw->sih) {
1111                 si_detach(wlc_hw->sih);
1112                 wlc_hw->sih = NULL;
1113         }
1114
1115         return callbacks;
1116
1117 }
1118
1119 void wlc_bmac_reset(wlc_hw_info_t *wlc_hw)
1120 {
1121         WL_TRACE(("wl%d: wlc_bmac_reset\n", wlc_hw->unit));
1122
1123         WLCNTINCR(wlc_hw->wlc->pub->_cnt->reset);
1124
1125         /* reset the core */
1126         if (!DEVICEREMOVED(wlc_hw->wlc))
1127                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1128
1129         /* purge the dma rings */
1130         wlc_flushqueues(wlc_hw->wlc);
1131
1132         wlc_reset_bmac_done(wlc_hw->wlc);
1133 }
1134
1135 void
1136 wlc_bmac_init(wlc_hw_info_t *wlc_hw, chanspec_t chanspec,
1137                           bool mute) {
1138         u32 macintmask;
1139         bool fastclk;
1140         struct wlc_info *wlc = wlc_hw->wlc;
1141
1142         WL_TRACE(("wl%d: wlc_bmac_init\n", wlc_hw->unit));
1143
1144         /* request FAST clock if not on */
1145         fastclk = wlc_hw->forcefastclk;
1146         if (!fastclk)
1147                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1148
1149         /* disable interrupts */
1150         macintmask = wl_intrsoff(wlc->wl);
1151
1152         /* set up the specified band and chanspec */
1153         wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1154         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1155
1156         /* do one-time phy inits and calibration */
1157         wlc_phy_cal_init(wlc_hw->band->pi);
1158
1159         /* core-specific initialization */
1160         wlc_coreinit(wlc);
1161
1162         /* suspend the tx fifos and mute the phy for preism cac time */
1163         if (mute)
1164                 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1165
1166         /* band-specific inits */
1167         wlc_bmac_bsinit(wlc, chanspec);
1168
1169         /* restore macintmask */
1170         wl_intrsrestore(wlc->wl, macintmask);
1171
1172         /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1173          * and wlc_enable_mac() will clear this override bit.
1174          */
1175         mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1176
1177         /*
1178          * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1179          */
1180         wlc_hw->mac_suspend_depth = 1;
1181
1182         /* restore the clk */
1183         if (!fastclk)
1184                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1185 }
1186
1187 int wlc_bmac_up_prep(wlc_hw_info_t *wlc_hw)
1188 {
1189         uint coremask;
1190
1191         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1192
1193         ASSERT(wlc_hw->wlc->pub->hw_up && wlc_hw->wlc->macintmask == 0);
1194
1195         /*
1196          * Enable pll and xtal, initialize the power control registers,
1197          * and force fastclock for the remainder of wlc_up().
1198          */
1199         wlc_bmac_xtal(wlc_hw, ON);
1200         si_clkctl_init(wlc_hw->sih);
1201         wlc_clkctl_clk(wlc_hw, CLK_FAST);
1202
1203         /*
1204          * Configure pci/pcmcia here instead of in wlc_attach()
1205          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
1206          */
1207         coremask = (1 << wlc_hw->wlc->core->coreidx);
1208
1209         if (wlc_hw->sih->bustype == PCI_BUS)
1210                 si_pci_setup(wlc_hw->sih, coremask);
1211
1212         ASSERT(si_coreid(wlc_hw->sih) == D11_CORE_ID);
1213
1214         /*
1215          * Need to read the hwradio status here to cover the case where the system
1216          * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1217          */
1218         if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1219                 /* put SB PCI in down state again */
1220                 if (wlc_hw->sih->bustype == PCI_BUS)
1221                         si_pci_down(wlc_hw->sih);
1222                 wlc_bmac_xtal(wlc_hw, OFF);
1223                 return BCME_RADIOOFF;
1224         }
1225
1226         if (wlc_hw->sih->bustype == PCI_BUS)
1227                 si_pci_up(wlc_hw->sih);
1228
1229         /* reset the d11 core */
1230         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1231
1232         return 0;
1233 }
1234
1235 int wlc_bmac_up_finish(wlc_hw_info_t *wlc_hw)
1236 {
1237         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1238
1239         wlc_hw->up = true;
1240         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1241
1242         /* FULLY enable dynamic power control and d11 core interrupt */
1243         wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1244         ASSERT(wlc_hw->wlc->macintmask == 0);
1245         wl_intrson(wlc_hw->wlc->wl);
1246         return 0;
1247 }
1248
1249 int wlc_bmac_down_prep(wlc_hw_info_t *wlc_hw)
1250 {
1251         bool dev_gone;
1252         uint callbacks = 0;
1253
1254         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1255
1256         if (!wlc_hw->up)
1257                 return callbacks;
1258
1259         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1260
1261         /* disable interrupts */
1262         if (dev_gone)
1263                 wlc_hw->wlc->macintmask = 0;
1264         else {
1265                 /* now disable interrupts */
1266                 wl_intrsoff(wlc_hw->wlc->wl);
1267
1268                 /* ensure we're running on the pll clock again */
1269                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1270         }
1271         /* down phy at the last of this stage */
1272         callbacks += wlc_phy_down(wlc_hw->band->pi);
1273
1274         return callbacks;
1275 }
1276
1277 int wlc_bmac_down_finish(wlc_hw_info_t *wlc_hw)
1278 {
1279         uint callbacks = 0;
1280         bool dev_gone;
1281
1282         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1283
1284         if (!wlc_hw->up)
1285                 return callbacks;
1286
1287         wlc_hw->up = false;
1288         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1289
1290         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1291
1292         if (dev_gone) {
1293                 wlc_hw->sbclk = false;
1294                 wlc_hw->clk = false;
1295                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1296
1297                 /* reclaim any posted packets */
1298                 wlc_flushqueues(wlc_hw->wlc);
1299         } else {
1300
1301                 /* Reset and disable the core */
1302                 if (si_iscoreup(wlc_hw->sih)) {
1303                         if (R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) &
1304                             MCTL_EN_MAC)
1305                                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1306                         callbacks += wl_reset(wlc_hw->wlc->wl);
1307                         wlc_coredisable(wlc_hw);
1308                 }
1309
1310                 /* turn off primary xtal and pll */
1311                 if (!wlc_hw->noreset) {
1312                         if (wlc_hw->sih->bustype == PCI_BUS)
1313                                 si_pci_down(wlc_hw->sih);
1314                         wlc_bmac_xtal(wlc_hw, OFF);
1315                 }
1316         }
1317
1318         return callbacks;
1319 }
1320
1321 void wlc_bmac_wait_for_wake(wlc_hw_info_t *wlc_hw)
1322 {
1323         if (D11REV_IS(wlc_hw->corerev, 4))      /* no slowclock */
1324                 udelay(5);
1325         else {
1326                 /* delay before first read of ucode state */
1327                 udelay(40);
1328
1329                 /* wait until ucode is no longer asleep */
1330                 SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1331                           DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1332         }
1333
1334         ASSERT(wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) != DBGST_ASLEEP);
1335 }
1336
1337 void wlc_bmac_hw_etheraddr(wlc_hw_info_t *wlc_hw, struct ether_addr *ea)
1338 {
1339         bcopy(&wlc_hw->etheraddr, ea, ETHER_ADDR_LEN);
1340 }
1341
1342 void wlc_bmac_set_hw_etheraddr(wlc_hw_info_t *wlc_hw, struct ether_addr *ea)
1343 {
1344         bcopy(ea, &wlc_hw->etheraddr, ETHER_ADDR_LEN);
1345 }
1346
1347 int wlc_bmac_bandtype(wlc_hw_info_t *wlc_hw)
1348 {
1349         return wlc_hw->band->bandtype;
1350 }
1351
1352 void *wlc_cur_phy(struct wlc_info *wlc)
1353 {
1354         wlc_hw_info_t *wlc_hw = wlc->hw;
1355         return (void *)wlc_hw->band->pi;
1356 }
1357
1358 /* control chip clock to save power, enable dynamic clock or force fast clock */
1359 static void wlc_clkctl_clk(wlc_hw_info_t *wlc_hw, uint mode)
1360 {
1361         if (PMUCTL_ENAB(wlc_hw->sih)) {
1362                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1363                  *  but mac core will still run on ALP(not HT) when it enters powersave mode,
1364                  *      which means the FCA bit may not be set.
1365                  *      should wakeup mac if driver wants it to run on HT.
1366                  */
1367
1368                 if (wlc_hw->clk) {
1369                         if (mode == CLK_FAST) {
1370                                 OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1371                                        CCS_FORCEHT);
1372
1373                                 udelay(64);
1374
1375                                 SPINWAIT(((R_REG
1376                                            (wlc_hw->osh,
1377                                             &wlc_hw->regs->
1378                                             clk_ctl_st) & CCS_HTAVAIL) == 0),
1379                                          PMU_MAX_TRANSITION_DLY);
1380                                 ASSERT(R_REG
1381                                        (wlc_hw->osh,
1382                                         &wlc_hw->regs->
1383                                         clk_ctl_st) & CCS_HTAVAIL);
1384                         } else {
1385                                 if ((wlc_hw->sih->pmurev == 0) &&
1386                                     (R_REG
1387                                      (wlc_hw->osh,
1388                                       &wlc_hw->regs->
1389                                       clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1390                                         SPINWAIT(((R_REG
1391                                                    (wlc_hw->osh,
1392                                                     &wlc_hw->regs->
1393                                                     clk_ctl_st) & CCS_HTAVAIL)
1394                                                   == 0),
1395                                                  PMU_MAX_TRANSITION_DLY);
1396                                 AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1397                                         ~CCS_FORCEHT);
1398                         }
1399                 }
1400                 wlc_hw->forcefastclk = (mode == CLK_FAST);
1401         } else {
1402                 bool wakeup_ucode;
1403
1404                 /* old chips w/o PMU, force HT through cc,
1405                  * then use FCA to verify mac is running fast clock
1406                  */
1407
1408                 wakeup_ucode = D11REV_LT(wlc_hw->corerev, 9);
1409
1410                 if (wlc_hw->up && wakeup_ucode)
1411                         wlc_ucode_wake_override_set(wlc_hw,
1412                                                     WLC_WAKE_OVERRIDE_CLKCTL);
1413
1414                 wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
1415
1416                 if (D11REV_LT(wlc_hw->corerev, 11)) {
1417                         /* ucode WAR for old chips */
1418                         if (wlc_hw->forcefastclk)
1419                                 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK,
1420                                              MHF1_FORCEFASTCLK, WLC_BAND_ALL);
1421                         else
1422                                 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK, 0,
1423                                              WLC_BAND_ALL);
1424                 }
1425
1426                 /* check fast clock is available (if core is not in reset) */
1427                 if (D11REV_GT(wlc_hw->corerev, 4) && wlc_hw->forcefastclk
1428                     && wlc_hw->clk)
1429                         ASSERT(si_core_sflags(wlc_hw->sih, 0, 0) & SISF_FCLKA);
1430
1431                 /* keep the ucode wake bit on if forcefastclk is on
1432                  * since we do not want ucode to put us back to slow clock
1433                  * when it dozes for PM mode.
1434                  * Code below matches the wake override bit with current forcefastclk state
1435                  * Only setting bit in wake_override instead of waking ucode immediately
1436                  * since old code (wlc.c 1.4499) had this behavior. Older code set
1437                  * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1438                  * (protected by an up check) was executed just below.
1439                  */
1440                 if (wlc_hw->forcefastclk)
1441                         mboolset(wlc_hw->wake_override,
1442                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1443                 else
1444                         mboolclr(wlc_hw->wake_override,
1445                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1446
1447                 /* ok to clear the wakeup now */
1448                 if (wlc_hw->up && wakeup_ucode)
1449                         wlc_ucode_wake_override_clear(wlc_hw,
1450                                                       WLC_WAKE_OVERRIDE_CLKCTL);
1451         }
1452 }
1453
1454 /* set initial host flags value */
1455 static void
1456 wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1457 {
1458         wlc_hw_info_t *wlc_hw = wlc->hw;
1459
1460         memset(mhfs, 0, MHFMAX * sizeof(u16));
1461
1462         mhfs[MHF2] |= mhf2_init;
1463
1464         /* prohibit use of slowclock on multifunction boards */
1465         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1466                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1467
1468         if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1469                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1470                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1471         }
1472 }
1473
1474 /* set or clear ucode host flag bits
1475  * it has an optimization for no-change write
1476  * it only writes through shared memory when the core has clock;
1477  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1478  *
1479  *
1480  * bands values are: WLC_BAND_AUTO <--- Current band only
1481  *                   WLC_BAND_5G   <--- 5G band only
1482  *                   WLC_BAND_2G   <--- 2G band only
1483  *                   WLC_BAND_ALL  <--- All bands
1484  */
1485 void
1486 wlc_bmac_mhf(wlc_hw_info_t *wlc_hw, u8 idx, u16 mask, u16 val,
1487              int bands)
1488 {
1489         u16 save;
1490         u16 addr[MHFMAX] = {
1491                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1492                 M_HOST_FLAGS5
1493         };
1494         wlc_hwband_t *band;
1495
1496         ASSERT((val & ~mask) == 0);
1497         ASSERT(idx < MHFMAX);
1498         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1499
1500         switch (bands) {
1501                 /* Current band only or all bands,
1502                  * then set the band to current band
1503                  */
1504         case WLC_BAND_AUTO:
1505         case WLC_BAND_ALL:
1506                 band = wlc_hw->band;
1507                 break;
1508         case WLC_BAND_5G:
1509                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1510                 break;
1511         case WLC_BAND_2G:
1512                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1513                 break;
1514         default:
1515                 ASSERT(0);
1516                 band = NULL;
1517         }
1518
1519         if (band) {
1520                 save = band->mhfs[idx];
1521                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1522
1523                 /* optimization: only write through if changed, and
1524                  * changed band is the current band
1525                  */
1526                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1527                     && (band == wlc_hw->band))
1528                         wlc_bmac_write_shm(wlc_hw, addr[idx],
1529                                            (u16) band->mhfs[idx]);
1530         }
1531
1532         if (bands == WLC_BAND_ALL) {
1533                 wlc_hw->bandstate[0]->mhfs[idx] =
1534                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1535                 wlc_hw->bandstate[1]->mhfs[idx] =
1536                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1537         }
1538 }
1539
1540 u16 wlc_bmac_mhf_get(wlc_hw_info_t *wlc_hw, u8 idx, int bands)
1541 {
1542         wlc_hwband_t *band;
1543         ASSERT(idx < MHFMAX);
1544
1545         switch (bands) {
1546         case WLC_BAND_AUTO:
1547                 band = wlc_hw->band;
1548                 break;
1549         case WLC_BAND_5G:
1550                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1551                 break;
1552         case WLC_BAND_2G:
1553                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1554                 break;
1555         default:
1556                 ASSERT(0);
1557                 band = NULL;
1558         }
1559
1560         if (!band)
1561                 return 0;
1562
1563         return band->mhfs[idx];
1564 }
1565
1566 static void wlc_write_mhf(wlc_hw_info_t *wlc_hw, u16 *mhfs)
1567 {
1568         u8 idx;
1569         u16 addr[] = {
1570                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1571                 M_HOST_FLAGS5
1572         };
1573
1574         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1575
1576         for (idx = 0; idx < MHFMAX; idx++) {
1577                 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1578         }
1579 }
1580
1581 /* set the maccontrol register to desired reset state and
1582  * initialize the sw cache of the register
1583  */
1584 static void wlc_mctrl_reset(wlc_hw_info_t *wlc_hw)
1585 {
1586         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1587         wlc_hw->maccontrol = 0;
1588         wlc_hw->suspended_fifos = 0;
1589         wlc_hw->wake_override = 0;
1590         wlc_hw->mute_override = 0;
1591         wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1592 }
1593
1594 /* set or clear maccontrol bits */
1595 void wlc_bmac_mctrl(wlc_hw_info_t *wlc_hw, u32 mask, u32 val)
1596 {
1597         u32 maccontrol;
1598         u32 new_maccontrol;
1599
1600         ASSERT((val & ~mask) == 0);
1601
1602         maccontrol = wlc_hw->maccontrol;
1603         new_maccontrol = (maccontrol & ~mask) | val;
1604
1605         /* if the new maccontrol value is the same as the old, nothing to do */
1606         if (new_maccontrol == maccontrol)
1607                 return;
1608
1609         /* something changed, cache the new value */
1610         wlc_hw->maccontrol = new_maccontrol;
1611
1612         /* write the new values with overrides applied */
1613         wlc_mctrl_write(wlc_hw);
1614 }
1615
1616 /* write the software state of maccontrol and overrides to the maccontrol register */
1617 static void wlc_mctrl_write(wlc_hw_info_t *wlc_hw)
1618 {
1619         u32 maccontrol = wlc_hw->maccontrol;
1620
1621         /* OR in the wake bit if overridden */
1622         if (wlc_hw->wake_override)
1623                 maccontrol |= MCTL_WAKE;
1624
1625         /* set AP and INFRA bits for mute if needed */
1626         if (wlc_hw->mute_override) {
1627                 maccontrol &= ~(MCTL_AP);
1628                 maccontrol |= MCTL_INFRA;
1629         }
1630
1631         W_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol, maccontrol);
1632 }
1633
1634 void wlc_ucode_wake_override_set(wlc_hw_info_t *wlc_hw, u32 override_bit)
1635 {
1636         ASSERT((wlc_hw->wake_override & override_bit) == 0);
1637
1638         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1639                 mboolset(wlc_hw->wake_override, override_bit);
1640                 return;
1641         }
1642
1643         mboolset(wlc_hw->wake_override, override_bit);
1644
1645         wlc_mctrl_write(wlc_hw);
1646         wlc_bmac_wait_for_wake(wlc_hw);
1647
1648         return;
1649 }
1650
1651 void wlc_ucode_wake_override_clear(wlc_hw_info_t *wlc_hw, u32 override_bit)
1652 {
1653         ASSERT(wlc_hw->wake_override & override_bit);
1654
1655         mboolclr(wlc_hw->wake_override, override_bit);
1656
1657         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1658                 return;
1659
1660         wlc_mctrl_write(wlc_hw);
1661
1662         return;
1663 }
1664
1665 /* When driver needs ucode to stop beaconing, it has to make sure that
1666  * MCTL_AP is clear and MCTL_INFRA is set
1667  * Mode           MCTL_AP        MCTL_INFRA
1668  * AP                1              1
1669  * STA               0              1 <--- This will ensure no beacons
1670  * IBSS              0              0
1671  */
1672 static void wlc_ucode_mute_override_set(wlc_hw_info_t *wlc_hw)
1673 {
1674         wlc_hw->mute_override = 1;
1675
1676         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1677          * override, then there is no change to write
1678          */
1679         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1680                 return;
1681
1682         wlc_mctrl_write(wlc_hw);
1683
1684         return;
1685 }
1686
1687 /* Clear the override on AP and INFRA bits */
1688 static void wlc_ucode_mute_override_clear(wlc_hw_info_t *wlc_hw)
1689 {
1690         if (wlc_hw->mute_override == 0)
1691                 return;
1692
1693         wlc_hw->mute_override = 0;
1694
1695         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1696          * override, then there is no change to write
1697          */
1698         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1699                 return;
1700
1701         wlc_mctrl_write(wlc_hw);
1702 }
1703
1704 /*
1705  * Write a MAC address to the rcmta structure
1706  */
1707 void
1708 wlc_bmac_set_rcmta(wlc_hw_info_t *wlc_hw, int idx,
1709                    const struct ether_addr *addr)
1710 {
1711         d11regs_t *regs = wlc_hw->regs;
1712         volatile u16 *objdata16 = (volatile u16 *)&regs->objdata;
1713         u32 mac_hm;
1714         u16 mac_l;
1715         struct osl_info *osh;
1716
1717         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
1718
1719         ASSERT(wlc_hw->corerev > 4);
1720
1721         mac_hm =
1722             (addr->octet[3] << 24) | (addr->octet[2] << 16) | (addr->
1723                                                                octet[1] << 8) |
1724             addr->octet[0];
1725         mac_l = (addr->octet[5] << 8) | addr->octet[4];
1726
1727         osh = wlc_hw->osh;
1728
1729         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
1730         (void)R_REG(osh, &regs->objaddr);
1731         W_REG(osh, &regs->objdata, mac_hm);
1732         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
1733         (void)R_REG(osh, &regs->objaddr);
1734         W_REG(osh, objdata16, mac_l);
1735 }
1736
1737 /*
1738  * Write a MAC address to the given match reg offset in the RXE match engine.
1739  */
1740 void
1741 wlc_bmac_set_addrmatch(wlc_hw_info_t *wlc_hw, int match_reg_offset,
1742                        const struct ether_addr *addr)
1743 {
1744         d11regs_t *regs;
1745         u16 mac_l;
1746         u16 mac_m;
1747         u16 mac_h;
1748         struct osl_info *osh;
1749
1750         WL_TRACE(("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit));
1751
1752         ASSERT((match_reg_offset < RCM_SIZE) || (wlc_hw->corerev == 4));
1753
1754         regs = wlc_hw->regs;
1755         mac_l = addr->octet[0] | (addr->octet[1] << 8);
1756         mac_m = addr->octet[2] | (addr->octet[3] << 8);
1757         mac_h = addr->octet[4] | (addr->octet[5] << 8);
1758
1759         osh = wlc_hw->osh;
1760
1761         /* enter the MAC addr into the RXE match registers */
1762         W_REG(osh, &regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1763         W_REG(osh, &regs->rcm_mat_data, mac_l);
1764         W_REG(osh, &regs->rcm_mat_data, mac_m);
1765         W_REG(osh, &regs->rcm_mat_data, mac_h);
1766
1767 }
1768
1769 void
1770 wlc_bmac_write_template_ram(wlc_hw_info_t *wlc_hw, int offset, int len,
1771                             void *buf)
1772 {
1773         d11regs_t *regs;
1774         u32 word;
1775         bool be_bit;
1776 #ifdef IL_BIGENDIAN
1777         volatile u16 *dptr = NULL;
1778 #endif                          /* IL_BIGENDIAN */
1779         struct osl_info *osh;
1780
1781         WL_TRACE(("wl%d: wlc_bmac_write_template_ram\n", wlc_hw->unit));
1782
1783         regs = wlc_hw->regs;
1784         osh = wlc_hw->osh;
1785
1786         ASSERT(IS_ALIGNED(offset, sizeof(u32)));
1787         ASSERT(IS_ALIGNED(len, sizeof(u32)));
1788         ASSERT((offset & ~0xffff) == 0);
1789
1790         W_REG(osh, &regs->tplatewrptr, offset);
1791
1792         /* if MCTL_BIGEND bit set in mac control register,
1793          * the chip swaps data in fifo, as well as data in
1794          * template ram
1795          */
1796         be_bit = (R_REG(osh, &regs->maccontrol) & MCTL_BIGEND) != 0;
1797
1798         while (len > 0) {
1799                 bcopy((u8 *) buf, &word, sizeof(u32));
1800
1801                 if (be_bit)
1802                         word = hton32(word);
1803                 else
1804                         word = htol32(word);
1805
1806                 W_REG(osh, &regs->tplatewrdata, word);
1807
1808                 buf = (u8 *) buf + sizeof(u32);
1809                 len -= sizeof(u32);
1810         }
1811 }
1812
1813 void wlc_bmac_set_cwmin(wlc_hw_info_t *wlc_hw, u16 newmin)
1814 {
1815         struct osl_info *osh;
1816
1817         osh = wlc_hw->osh;
1818         wlc_hw->band->CWmin = newmin;
1819
1820         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1821         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1822         W_REG(osh, &wlc_hw->regs->objdata, newmin);
1823 }
1824
1825 void wlc_bmac_set_cwmax(wlc_hw_info_t *wlc_hw, u16 newmax)
1826 {
1827         struct osl_info *osh;
1828
1829         osh = wlc_hw->osh;
1830         wlc_hw->band->CWmax = newmax;
1831
1832         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1833         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1834         W_REG(osh, &wlc_hw->regs->objdata, newmax);
1835 }
1836
1837 void wlc_bmac_bw_set(wlc_hw_info_t *wlc_hw, u16 bw)
1838 {
1839         bool fastclk;
1840         u32 tmp;
1841
1842         /* request FAST clock if not on */
1843         fastclk = wlc_hw->forcefastclk;
1844         if (!fastclk)
1845                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1846
1847         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1848
1849         ASSERT(wlc_hw->clk);
1850         if (D11REV_LT(wlc_hw->corerev, 17))
1851                 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
1852
1853         wlc_bmac_phy_reset(wlc_hw);
1854         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1855
1856         /* restore the clk */
1857         if (!fastclk)
1858                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1859 }
1860
1861 static void
1862 wlc_write_hw_bcntemplate0(wlc_hw_info_t *wlc_hw, void *bcn, int len)
1863 {
1864         d11regs_t *regs = wlc_hw->regs;
1865
1866         wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1867                                     bcn);
1868         /* write beacon length to SCR */
1869         ASSERT(len < 65536);
1870         wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1871         /* mark beacon0 valid */
1872         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN0VLD);
1873 }
1874
1875 static void
1876 wlc_write_hw_bcntemplate1(wlc_hw_info_t *wlc_hw, void *bcn, int len)
1877 {
1878         d11regs_t *regs = wlc_hw->regs;
1879
1880         wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1881                                     bcn);
1882         /* write beacon length to SCR */
1883         ASSERT(len < 65536);
1884         wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1885         /* mark beacon1 valid */
1886         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN1VLD);
1887 }
1888
1889 /* mac is assumed to be suspended at this point */
1890 void
1891 wlc_bmac_write_hw_bcntemplates(wlc_hw_info_t *wlc_hw, void *bcn, int len,
1892                                bool both)
1893 {
1894         d11regs_t *regs = wlc_hw->regs;
1895
1896         if (both) {
1897                 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1898                 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1899         } else {
1900                 /* bcn 0 */
1901                 if (!(R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN0VLD))
1902                         wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1903                 /* bcn 1 */
1904                 else if (!
1905                          (R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN1VLD))
1906                         wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1907                 else            /* one template should always have been available */
1908                         ASSERT(0);
1909         }
1910 }
1911
1912 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (wlc_hw_info_t *wlc_hw)
1913 {
1914         u16 v;
1915         struct wlc_info *wlc = wlc_hw->wlc;
1916         /* update SYNTHPU_DLY */
1917
1918         if (WLCISLCNPHY(wlc->band)) {
1919                 v = SYNTHPU_DLY_LPPHY_US;
1920         } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1921                 v = SYNTHPU_DLY_NPHY_US;
1922         } else {
1923                 v = SYNTHPU_DLY_BPHY_US;
1924         }
1925
1926         wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1927 }
1928
1929 /* band-specific init */
1930 static void
1931 WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1932 {
1933         wlc_hw_info_t *wlc_hw = wlc->hw;
1934
1935         WL_TRACE(("wl%d: wlc_bmac_bsinit: bandunit %d\n", wlc_hw->unit,
1936                   wlc_hw->band->bandunit));
1937
1938         /* sanity check */
1939         if (PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion)) !=
1940             PHY_TYPE_LCNXN)
1941                 ASSERT((uint)
1942                        PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion))
1943                        == wlc_hw->band->phytype);
1944
1945         wlc_ucode_bsinit(wlc_hw);
1946
1947         wlc_phy_init(wlc_hw->band->pi, chanspec);
1948
1949         wlc_ucode_txant_set(wlc_hw);
1950
1951         /* cwmin is band-specific, update hardware with value for current band */
1952         wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1953         wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1954
1955         wlc_bmac_update_slot_timing(wlc_hw,
1956                                     BAND_5G(wlc_hw->band->
1957                                             bandtype) ? true : wlc_hw->
1958                                     shortslot);
1959
1960         /* write phytype and phyvers */
1961         wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1962         wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1963
1964         /* initialize the txphyctl1 rate table since shmem is shared between bands */
1965         wlc_upd_ofdm_pctl1_table(wlc_hw);
1966
1967         wlc_bmac_upd_synthpu(wlc_hw);
1968 }
1969
1970 void wlc_bmac_core_phy_clk(wlc_hw_info_t *wlc_hw, bool clk)
1971 {
1972         WL_TRACE(("wl%d: wlc_bmac_core_phy_clk: clk %d\n", wlc_hw->unit, clk));
1973
1974         wlc_hw->phyclk = clk;
1975
1976         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
1977
1978                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1979                                (SICF_PRST | SICF_FGC));
1980                 udelay(1);
1981                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1982                 udelay(1);
1983
1984         } else {                /* take phy out of reset */
1985
1986                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1987                 udelay(1);
1988                 si_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1989                 udelay(1);
1990
1991         }
1992 }
1993
1994 /* Perform a soft reset of the PHY PLL */
1995 void wlc_bmac_core_phypll_reset(wlc_hw_info_t *wlc_hw)
1996 {
1997         WL_TRACE(("wl%d: wlc_bmac_core_phypll_reset\n", wlc_hw->unit));
1998
1999         si_corereg(wlc_hw->sih, SI_CC_IDX,
2000                    offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
2001         udelay(1);
2002         si_corereg(wlc_hw->sih, SI_CC_IDX,
2003                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
2004         udelay(1);
2005         si_corereg(wlc_hw->sih, SI_CC_IDX,
2006                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
2007         udelay(1);
2008         si_corereg(wlc_hw->sih, SI_CC_IDX,
2009                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
2010         udelay(1);
2011 }
2012
2013 /* light way to turn on phy clock without reset for NPHY only
2014  *  refer to wlc_bmac_core_phy_clk for full version
2015  */
2016 void wlc_bmac_phyclk_fgc(wlc_hw_info_t *wlc_hw, bool clk)
2017 {
2018         /* support(necessary for NPHY and HYPHY) only */
2019         if (!WLCISNPHY(wlc_hw->band))
2020                 return;
2021
2022         if (ON == clk)
2023                 si_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
2024         else
2025                 si_core_cflags(wlc_hw->sih, SICF_FGC, 0);
2026
2027 }
2028
2029 void wlc_bmac_macphyclk_set(wlc_hw_info_t *wlc_hw, bool clk)
2030 {
2031         if (ON == clk)
2032                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
2033         else
2034                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
2035 }
2036
2037 void wlc_bmac_phy_reset(wlc_hw_info_t *wlc_hw)
2038 {
2039         wlc_phy_t *pih = wlc_hw->band->pi;
2040         u32 phy_bw_clkbits;
2041         bool phy_in_reset = false;
2042
2043         WL_TRACE(("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit));
2044
2045         if (pih == NULL)
2046                 return;
2047
2048         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
2049
2050         /* Specfic reset sequence required for NPHY rev 3 and 4 */
2051         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
2052             NREV_LE(wlc_hw->band->phyrev, 4)) {
2053                 /* Set the PHY bandwidth */
2054                 si_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
2055
2056                 udelay(1);
2057
2058                 /* Perform a soft reset of the PHY PLL */
2059                 wlc_bmac_core_phypll_reset(wlc_hw);
2060
2061                 /* reset the PHY */
2062                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
2063                                (SICF_PRST | SICF_PCLKE));
2064                 phy_in_reset = true;
2065         } else {
2066
2067                 si_core_cflags(wlc_hw->sih,
2068                                (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
2069                                (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
2070         }
2071
2072         udelay(2);
2073         wlc_bmac_core_phy_clk(wlc_hw, ON);
2074
2075         if (pih)
2076                 wlc_phy_anacore(pih, ON);
2077 }
2078
2079 /* switch to and initialize new band */
2080 static void
2081 WLBANDINITFN(wlc_bmac_setband) (wlc_hw_info_t *wlc_hw, uint bandunit,
2082                                 chanspec_t chanspec) {
2083         struct wlc_info *wlc = wlc_hw->wlc;
2084         u32 macintmask;
2085
2086         ASSERT(NBANDS_HW(wlc_hw) > 1);
2087         ASSERT(bandunit != wlc_hw->band->bandunit);
2088
2089         /* Enable the d11 core before accessing it */
2090         if (!si_iscoreup(wlc_hw->sih)) {
2091                 si_core_reset(wlc_hw->sih, 0, 0);
2092                 ASSERT(si_iscoreup(wlc_hw->sih));
2093                 wlc_mctrl_reset(wlc_hw);
2094         }
2095
2096         macintmask = wlc_setband_inact(wlc, bandunit);
2097
2098         if (!wlc_hw->up)
2099                 return;
2100
2101         wlc_bmac_core_phy_clk(wlc_hw, ON);
2102
2103         /* band-specific initializations */
2104         wlc_bmac_bsinit(wlc, chanspec);
2105
2106         /*
2107          * If there are any pending software interrupt bits,
2108          * then replace these with a harmless nonzero value
2109          * so wlc_dpc() will re-enable interrupts when done.
2110          */
2111         if (wlc->macintstatus)
2112                 wlc->macintstatus = MI_DMAINT;
2113
2114         /* restore macintmask */
2115         wl_intrsrestore(wlc->wl, macintmask);
2116
2117         /* ucode should still be suspended.. */
2118         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
2119                0);
2120 }
2121
2122 /* low-level band switch utility routine */
2123 void WLBANDINITFN(wlc_setxband) (wlc_hw_info_t *wlc_hw, uint bandunit)
2124 {
2125         WL_TRACE(("wl%d: wlc_setxband: bandunit %d\n", wlc_hw->unit, bandunit));
2126
2127         wlc_hw->band = wlc_hw->bandstate[bandunit];
2128
2129         /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
2130         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
2131
2132         /* set gmode core flag */
2133         if (wlc_hw->sbclk && !wlc_hw->noreset) {
2134                 si_core_cflags(wlc_hw->sih, SICF_GMODE,
2135                                ((bandunit == 0) ? SICF_GMODE : 0));
2136         }
2137 }
2138
2139 static bool wlc_isgoodchip(wlc_hw_info_t *wlc_hw)
2140 {
2141
2142         /* reject unsupported corerev */
2143         if (!VALID_COREREV(wlc_hw->corerev)) {
2144                 WL_ERROR(("unsupported core rev %d\n", wlc_hw->corerev));
2145                 return false;
2146         }
2147
2148         return true;
2149 }
2150
2151 static bool wlc_validboardtype(wlc_hw_info_t *wlc_hw)
2152 {
2153         bool goodboard = true;
2154         uint boardrev = wlc_hw->boardrev;
2155
2156         if (boardrev == 0)
2157                 goodboard = false;
2158         else if (boardrev > 0xff) {
2159                 uint brt = (boardrev & 0xf000) >> 12;
2160                 uint b0 = (boardrev & 0xf00) >> 8;
2161                 uint b1 = (boardrev & 0xf0) >> 4;
2162                 uint b2 = boardrev & 0xf;
2163
2164                 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
2165                     || (b2 > 9))
2166                         goodboard = false;
2167         }
2168
2169         if (wlc_hw->sih->boardvendor != VENDOR_BROADCOM)
2170                 return goodboard;
2171
2172         return goodboard;
2173 }
2174
2175 static char *wlc_get_macaddr(wlc_hw_info_t *wlc_hw)
2176 {
2177         const char *varname = "macaddr";
2178         char *macaddr;
2179
2180         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
2181         macaddr = getvar(wlc_hw->vars, varname);
2182         if (macaddr != NULL)
2183                 return macaddr;
2184
2185         if (NBANDS_HW(wlc_hw) > 1)
2186                 varname = "et1macaddr";
2187         else
2188                 varname = "il0macaddr";
2189
2190         macaddr = getvar(wlc_hw->vars, varname);
2191         if (macaddr == NULL) {
2192                 WL_ERROR(("wl%d: wlc_get_macaddr: macaddr getvar(%s) not found\n", wlc_hw->unit, varname));
2193         }
2194
2195         return macaddr;
2196 }
2197
2198 /*
2199  * Return true if radio is disabled, otherwise false.
2200  * hw radio disable signal is an external pin, users activate it asynchronously
2201  * this function could be called when driver is down and w/o clock
2202  * it operates on different registers depending on corerev and boardflag.
2203  */
2204 bool wlc_bmac_radio_read_hwdisabled(wlc_hw_info_t *wlc_hw)
2205 {
2206         bool v, clk, xtal;
2207         u32 resetbits = 0, flags = 0;
2208
2209         xtal = wlc_hw->sbclk;
2210         if (!xtal)
2211                 wlc_bmac_xtal(wlc_hw, ON);
2212
2213         /* may need to take core out of reset first */
2214         clk = wlc_hw->clk;
2215         if (!clk) {
2216                 if (D11REV_LE(wlc_hw->corerev, 11))
2217                         resetbits |= SICF_PCLKE;
2218
2219                 /*
2220                  * corerev >= 18, mac no longer enables phyclk automatically when driver accesses
2221                  * phyreg throughput mac. This can be skipped since only mac reg is accessed below
2222                  */
2223                 if (D11REV_GE(wlc_hw->corerev, 18))
2224                         flags |= SICF_PCLKE;
2225
2226                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2227                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2228                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2229                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2230                         wlc_hw->regs =
2231                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2232                                                      0);
2233                 si_core_reset(wlc_hw->sih, flags, resetbits);
2234                 wlc_mctrl_reset(wlc_hw);
2235         }
2236
2237         v = ((R_REG(wlc_hw->osh, &wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2238
2239         /* put core back into reset */
2240         if (!clk)
2241                 si_core_disable(wlc_hw->sih, 0);
2242
2243         if (!xtal)
2244                 wlc_bmac_xtal(wlc_hw, OFF);
2245
2246         return v;
2247 }
2248
2249 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2250 void wlc_bmac_hw_up(wlc_hw_info_t *wlc_hw)
2251 {
2252         if (wlc_hw->wlc->pub->hw_up)
2253                 return;
2254
2255         WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
2256
2257         /*
2258          * Enable pll and xtal, initialize the power control registers,
2259          * and force fastclock for the remainder of wlc_up().
2260          */
2261         wlc_bmac_xtal(wlc_hw, ON);
2262         si_clkctl_init(wlc_hw->sih);
2263         wlc_clkctl_clk(wlc_hw, CLK_FAST);
2264
2265         if (wlc_hw->sih->bustype == PCI_BUS) {
2266                 si_pci_fixcfg(wlc_hw->sih);
2267
2268                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2269                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2270                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2271                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2272                         wlc_hw->regs =
2273                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2274                                                      0);
2275         }
2276
2277         /* Inform phy that a POR reset has occurred so it does a complete phy init */
2278         wlc_phy_por_inform(wlc_hw->band->pi);
2279
2280         wlc_hw->ucode_loaded = false;
2281         wlc_hw->wlc->pub->hw_up = true;
2282
2283         if ((wlc_hw->boardflags & BFL_FEM)
2284             && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2285                 if (!
2286                     (wlc_hw->boardrev >= 0x1250
2287                      && (wlc_hw->boardflags & BFL_FEM_BT)))
2288                         si_epa_4313war(wlc_hw->sih);
2289         }
2290 }
2291
2292 static bool wlc_dma_rxreset(wlc_hw_info_t *wlc_hw, uint fifo)
2293 {
2294         hnddma_t *di = wlc_hw->di[fifo];
2295         struct osl_info *osh;
2296
2297         if (D11REV_LT(wlc_hw->corerev, 12)) {
2298                 bool rxidle = true;
2299                 u16 rcv_frm_cnt = 0;
2300
2301                 osh = wlc_hw->osh;
2302
2303                 W_REG(osh, &wlc_hw->regs->rcv_fifo_ctl, fifo << 8);
2304                 SPINWAIT((!(rxidle = dma_rxidle(di))) &&
2305                          ((rcv_frm_cnt =
2306                            R_REG(osh, &wlc_hw->regs->rcv_frm_cnt)) != 0),
2307                          50000);
2308
2309                 if (!rxidle && (rcv_frm_cnt != 0))
2310                         WL_ERROR(("wl%d: %s: rxdma[%d] not idle && rcv_frm_cnt(%d) not zero\n", wlc_hw->unit, __func__, fifo, rcv_frm_cnt));
2311                 mdelay(2);
2312         }
2313
2314         return dma_rxreset(di);
2315 }
2316
2317 /* d11 core reset
2318  *   ensure fask clock during reset
2319  *   reset dma
2320  *   reset d11(out of reset)
2321  *   reset phy(out of reset)
2322  *   clear software macintstatus for fresh new start
2323  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2324  */
2325 void wlc_bmac_corereset(wlc_hw_info_t *wlc_hw, u32 flags)
2326 {
2327         d11regs_t *regs;
2328         uint i;
2329         bool fastclk;
2330         u32 resetbits = 0;
2331
2332         if (flags == WLC_USE_COREFLAGS)
2333                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2334
2335         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
2336
2337         regs = wlc_hw->regs;
2338
2339         /* request FAST clock if not on  */
2340         fastclk = wlc_hw->forcefastclk;
2341         if (!fastclk)
2342                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2343
2344         /* reset the dma engines except first time thru */
2345         if (si_iscoreup(wlc_hw->sih)) {
2346                 for (i = 0; i < NFIFO; i++)
2347                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2348                                 WL_ERROR(("wl%d: %s: dma_txreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, i));
2349                         }
2350
2351                 if ((wlc_hw->di[RX_FIFO])
2352                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2353                         WL_ERROR(("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, RX_FIFO));
2354                 }
2355                 if (D11REV_IS(wlc_hw->corerev, 4)
2356                     && wlc_hw->di[RX_TXSTATUS_FIFO]
2357                     && (!wlc_dma_rxreset(wlc_hw, RX_TXSTATUS_FIFO))) {
2358                         WL_ERROR(("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, RX_TXSTATUS_FIFO));
2359                 }
2360         }
2361         /* if noreset, just stop the psm and return */
2362         if (wlc_hw->noreset) {
2363                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2364                 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2365                 return;
2366         }
2367
2368         if (D11REV_LE(wlc_hw->corerev, 11))
2369                 resetbits |= SICF_PCLKE;
2370
2371         /*
2372          * corerev >= 18, mac no longer enables phyclk automatically when driver accesses phyreg
2373          * throughput mac, AND phy_reset is skipped at early stage when band->pi is invalid
2374          * need to enable PHY CLK
2375          */
2376         if (D11REV_GE(wlc_hw->corerev, 18))
2377                 flags |= SICF_PCLKE;
2378
2379         /* reset the core
2380          * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2381          *  is cleared by the core_reset. have to re-request it.
2382          *  This adds some delay and we can optimize it by also requesting fastclk through
2383          *  chipcommon during this period if necessary. But that has to work coordinate
2384          *  with other driver like mips/arm since they may touch chipcommon as well.
2385          */
2386         wlc_hw->clk = false;
2387         si_core_reset(wlc_hw->sih, flags, resetbits);
2388         wlc_hw->clk = true;
2389         if (wlc_hw->band && wlc_hw->band->pi)
2390                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2391
2392         wlc_mctrl_reset(wlc_hw);
2393
2394         if (PMUCTL_ENAB(wlc_hw->sih))
2395                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2396
2397         wlc_bmac_phy_reset(wlc_hw);
2398
2399         /* turn on PHY_PLL */
2400         wlc_bmac_core_phypll_ctl(wlc_hw, true);
2401
2402         /* clear sw intstatus */
2403         wlc_hw->wlc->macintstatus = 0;
2404
2405         /* restore the clk setting */
2406         if (!fastclk)
2407                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2408 }
2409
2410 /* If the ucode that supports corerev 5 is used for corerev 9 and above,
2411  * txfifo sizes needs to be modified(increased) since the newer cores
2412  * have more memory.
2413  */
2414 static void wlc_corerev_fifofixup(wlc_hw_info_t *wlc_hw)
2415 {
2416         d11regs_t *regs = wlc_hw->regs;
2417         u16 fifo_nu;
2418         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2419         u16 txfifo_def, txfifo_def1;
2420         u16 txfifo_cmd;
2421         struct osl_info *osh;
2422
2423         if (D11REV_LT(wlc_hw->corerev, 9))
2424                 goto exit;
2425
2426         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2427         txfifo_startblk = TXFIFO_START_BLK;
2428
2429         osh = wlc_hw->osh;
2430
2431         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2432         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2433
2434                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2435                 txfifo_def = (txfifo_startblk & 0xff) |
2436                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2437                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2438                     ((((txfifo_endblk -
2439                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2440                 txfifo_cmd =
2441                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2442
2443                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2444                 W_REG(osh, &regs->xmtfifodef, txfifo_def);
2445                 if (D11REV_GE(wlc_hw->corerev, 16))
2446                         W_REG(osh, &regs->xmtfifodef1, txfifo_def1);
2447
2448                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2449
2450                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2451         }
2452  exit:
2453         /* need to propagate to shm location to be in sync since ucode/hw won't do this */
2454         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2455                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2456         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2457                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2458         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2459                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2460                             xmtfifo_sz[TX_AC_BK_FIFO]));
2461         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2462                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2463                             xmtfifo_sz[TX_BCMC_FIFO]));
2464 }
2465
2466 /* d11 core init
2467  *   reset PSM
2468  *   download ucode/PCM
2469  *   let ucode run to suspended
2470  *   download ucode inits
2471  *   config other core registers
2472  *   init dma
2473  */
2474 static void wlc_coreinit(struct wlc_info *wlc)
2475 {
2476         wlc_hw_info_t *wlc_hw = wlc->hw;
2477         d11regs_t *regs;
2478         u32 sflags;
2479         uint bcnint_us;
2480         uint i = 0;
2481         bool fifosz_fixup = false;
2482         struct osl_info *osh;
2483         int err = 0;
2484         u16 buf[NFIFO];
2485
2486         regs = wlc_hw->regs;
2487         osh = wlc_hw->osh;
2488
2489         WL_TRACE(("wl%d: wlc_coreinit\n", wlc_hw->unit));
2490
2491         /* reset PSM */
2492         wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2493
2494         wlc_ucode_download(wlc_hw);
2495         /*
2496          * FIFOSZ fixup
2497          * 1) core5-9 use ucode 5 to save space since the PSM is the same
2498          * 2) newer chips, driver wants to controls the fifo allocation
2499          */
2500         if (D11REV_GE(wlc_hw->corerev, 4))
2501                 fifosz_fixup = true;
2502
2503         /* let the PSM run to the suspended state, set mode to BSS STA */
2504         W_REG(osh, &regs->macintstatus, -1);
2505         wlc_bmac_mctrl(wlc_hw, ~0,
2506                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2507
2508         /* wait for ucode to self-suspend after auto-init */
2509         SPINWAIT(((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0),
2510                  1000 * 1000);
2511         if ((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0)
2512                 WL_ERROR(("wl%d: wlc_coreinit: ucode did not self-suspend!\n",
2513                           wlc_hw->unit));
2514
2515         wlc_gpio_init(wlc);
2516
2517         sflags = si_core_sflags(wlc_hw->sih, 0, 0);
2518
2519         if (D11REV_IS(wlc_hw->corerev, 23)) {
2520                 if (WLCISNPHY(wlc_hw->band))
2521                         wlc_write_inits(wlc_hw, d11n0initvals16);
2522                 else
2523                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2524                                   __func__, wlc_hw->unit, wlc_hw->corerev));
2525         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2526                 if (WLCISLCNPHY(wlc_hw->band)) {
2527                         wlc_write_inits(wlc_hw, d11lcn0initvals24);
2528                 } else {
2529                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2530                                   __func__, wlc_hw->unit, wlc_hw->corerev));
2531                 }
2532         } else {
2533                 WL_ERROR(("%s: wl%d: unsupported corerev %d\n",
2534                           __func__, wlc_hw->unit, wlc_hw->corerev));
2535         }
2536
2537         /* For old ucode, txfifo sizes needs to be modified(increased) for Corerev >= 9 */
2538         if (fifosz_fixup == true) {
2539                 wlc_corerev_fifofixup(wlc_hw);
2540         }
2541
2542         /* check txfifo allocations match between ucode and driver */
2543         buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2544         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2545                 i = TX_AC_BE_FIFO;
2546                 err = -1;
2547         }
2548         buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2549         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2550                 i = TX_AC_VI_FIFO;
2551                 err = -1;
2552         }
2553         buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2554         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2555         buf[TX_AC_BK_FIFO] &= 0xff;
2556         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2557                 i = TX_AC_BK_FIFO;
2558                 err = -1;
2559         }
2560         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2561                 i = TX_AC_VO_FIFO;
2562                 err = -1;
2563         }
2564         buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2565         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2566         buf[TX_BCMC_FIFO] &= 0xff;
2567         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2568                 i = TX_BCMC_FIFO;
2569                 err = -1;
2570         }
2571         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2572                 i = TX_ATIM_FIFO;
2573                 err = -1;
2574         }
2575         if (err != 0) {
2576                 WL_ERROR(("wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n", buf[i], wlc_hw->xmtfifo_sz[i], i));
2577                 /* DO NOT ASSERT corerev < 4 even there is a mismatch
2578                  * shmem, since driver don't overwrite those chip and
2579                  * ucode initialize data will be used.
2580                  */
2581                 if (D11REV_GE(wlc_hw->corerev, 4))
2582                         ASSERT(0);
2583         }
2584
2585         /* make sure we can still talk to the mac */
2586         ASSERT(R_REG(osh, &regs->maccontrol) != 0xffffffff);
2587
2588         /* band-specific inits done by wlc_bsinit() */
2589
2590         /* Set up frame burst size and antenna swap threshold init values */
2591         wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2592         wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2593
2594         /* enable one rx interrupt per received frame */
2595         W_REG(osh, &regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2596         if (D11REV_IS(wlc_hw->corerev, 4))
2597                 W_REG(osh, &regs->intrcvlazy[3], (1 << IRL_FC_SHIFT));
2598
2599         /* set the station mode (BSS STA) */
2600         wlc_bmac_mctrl(wlc_hw,
2601                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2602                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
2603
2604         /* set up Beacon interval */
2605         bcnint_us = 0x8000 << 10;
2606         W_REG(osh, &regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2607         W_REG(osh, &regs->tsf_cfpstart, bcnint_us);
2608         W_REG(osh, &regs->macintstatus, MI_GP1);
2609
2610         /* write interrupt mask */
2611         W_REG(osh, &regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2612         if (D11REV_IS(wlc_hw->corerev, 4))
2613                 W_REG(osh, &regs->intctrlregs[RX_TXSTATUS_FIFO].intmask,
2614                       DEF_RXINTMASK);
2615
2616         /* allow the MAC to control the PHY clock (dynamic on/off) */
2617         wlc_bmac_macphyclk_set(wlc_hw, ON);
2618
2619         /* program dynamic clock control fast powerup delay register */
2620         if (D11REV_GT(wlc_hw->corerev, 4)) {
2621                 wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
2622                 W_REG(osh, &regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2623         }
2624
2625         /* tell the ucode the corerev */
2626         wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2627
2628         /* tell the ucode MAC capabilities */
2629         if (D11REV_GE(wlc_hw->corerev, 13)) {
2630                 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2631                                    (u16) (wlc_hw->machwcap & 0xffff));
2632                 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2633                                    (u16) ((wlc_hw->
2634                                               machwcap >> 16) & 0xffff));
2635         }
2636
2637         /* write retry limits to SCR, this done after PSM init */
2638         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2639         (void)R_REG(osh, &regs->objaddr);
2640         W_REG(osh, &regs->objdata, wlc_hw->SRL);
2641         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2642         (void)R_REG(osh, &regs->objaddr);
2643         W_REG(osh, &regs->objdata, wlc_hw->LRL);
2644
2645         /* write rate fallback retry limits */
2646         wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2647         wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2648
2649         if (D11REV_GE(wlc_hw->corerev, 16)) {
2650                 AND_REG(osh, &regs->ifs_ctl, 0x0FFF);
2651                 W_REG(osh, &regs->ifs_aifsn, EDCF_AIFSN_MIN);
2652         }
2653
2654         /* dma initializations */
2655         wlc->txpend16165war = 0;
2656
2657         /* init the tx dma engines */
2658         for (i = 0; i < NFIFO; i++) {
2659                 if (wlc_hw->di[i])
2660                         dma_txinit(wlc_hw->di[i]);
2661         }
2662
2663         /* init the rx dma engine(s) and post receive buffers */
2664         dma_rxinit(wlc_hw->di[RX_FIFO]);
2665         dma_rxfill(wlc_hw->di[RX_FIFO]);
2666         if (D11REV_IS(wlc_hw->corerev, 4)) {
2667                 dma_rxinit(wlc_hw->di[RX_TXSTATUS_FIFO]);
2668                 dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
2669         }
2670 }
2671
2672 /* This function is used for changing the tsf frac register
2673  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2674  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2675  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2676  * HTPHY Formula is 2^26/freq(MHz) e.g.
2677  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2678  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2679  * For spuron: 123MHz -> 2^26/123    = 545600.5
2680  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2681  * For spur off: 120MHz -> 2^26/120    = 559240.5
2682  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2683  */
2684
2685 void wlc_bmac_switch_macfreq(wlc_hw_info_t *wlc_hw, u8 spurmode)
2686 {
2687         d11regs_t *regs;
2688         struct osl_info *osh;
2689         regs = wlc_hw->regs;
2690         osh = wlc_hw->osh;
2691
2692         if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2693             (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2694                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2695                         W_REG(osh, &regs->tsf_clk_frac_l, 0x2082);
2696                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2697                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2698                         W_REG(osh, &regs->tsf_clk_frac_l, 0x5341);
2699                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2700                 } else {        /* 120Mhz */
2701                         W_REG(osh, &regs->tsf_clk_frac_l, 0x8889);
2702                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2703                 }
2704         } else if (WLCISLCNPHY(wlc_hw->band)) {
2705                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2706                         W_REG(osh, &regs->tsf_clk_frac_l, 0x7CE0);
2707                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2708                 } else {        /* 80Mhz */
2709                         W_REG(osh, &regs->tsf_clk_frac_l, 0xCCCD);
2710                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2711                 }
2712         }
2713 }
2714
2715 /* Initialize GPIOs that are controlled by D11 core */
2716 static void wlc_gpio_init(struct wlc_info *wlc)
2717 {
2718         wlc_hw_info_t *wlc_hw = wlc->hw;
2719         d11regs_t *regs;
2720         u32 gc, gm;
2721         struct osl_info *osh;
2722
2723         regs = wlc_hw->regs;
2724         osh = wlc_hw->osh;
2725
2726         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2727         wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2728
2729         /*
2730          * Common GPIO setup:
2731          *      G0 = LED 0 = WLAN Activity
2732          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2733          *      G2 = LED 2 = WLAN 5 GHz Radio State
2734          *      G4 = radio disable input (HI enabled, LO disabled)
2735          */
2736
2737         gc = gm = 0;
2738
2739         /* Allocate GPIOs for mimo antenna diversity feature */
2740         if (WLANTSEL_ENAB(wlc)) {
2741                 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2742                         /* Enable antenna diversity, use 2x3 mode */
2743                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2744                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2745                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2746                                      MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2747
2748                         /* init superswitch control */
2749                         wlc_phy_antsel_init(wlc_hw->band->pi, false);
2750
2751                 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2752                         ASSERT((gm & BOARD_GPIO_12) == 0);
2753                         gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2754                         /* The board itself is powered by these GPIOs (when not sending pattern)
2755                          * So set them high
2756                          */
2757                         OR_REG(osh, &regs->psm_gpio_oe,
2758                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2759                         OR_REG(osh, &regs->psm_gpio_out,
2760                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2761
2762                         /* Enable antenna diversity, use 2x4 mode */
2763                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2764                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2765                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2766                                      WLC_BAND_ALL);
2767
2768                         /* Configure the desired clock to be 4Mhz */
2769                         wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2770                                            ANTSEL_CLKDIV_4MHZ);
2771                 }
2772         }
2773         /* gpio 9 controls the PA.  ucode is responsible for wiggling out and oe */
2774         if (wlc_hw->boardflags & BFL_PACTRL)
2775                 gm |= gc |= BOARD_GPIO_PACTRL;
2776
2777         /* apply to gpiocontrol register */
2778         si_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2779 }
2780
2781 static void wlc_ucode_download(wlc_hw_info_t *wlc_hw)
2782 {
2783         struct wlc_info *wlc;
2784         wlc = wlc_hw->wlc;
2785
2786         if (wlc_hw->ucode_loaded)
2787                 return;
2788
2789         if (D11REV_IS(wlc_hw->corerev, 23)) {
2790                 if (WLCISNPHY(wlc_hw->band)) {
2791                         wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2792                                         bcm43xx_16_mimosz);
2793                         wlc_hw->ucode_loaded = true;
2794                 } else
2795                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2796                                   __func__, wlc_hw->unit, wlc_hw->corerev));
2797         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2798                 if (WLCISLCNPHY(wlc_hw->band)) {
2799                         wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2800                                         bcm43xx_24_lcnsz);
2801                         wlc_hw->ucode_loaded = true;
2802                 } else {
2803                         WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2804                                   __func__, wlc_hw->unit, wlc_hw->corerev));
2805                 }
2806         }
2807 }
2808
2809 static void wlc_ucode_write(wlc_hw_info_t *wlc_hw, const u32 ucode[],
2810                               const uint nbytes) {
2811         struct osl_info *osh;
2812         d11regs_t *regs = wlc_hw->regs;
2813         uint i;
2814         uint count;
2815
2816         osh = wlc_hw->osh;
2817
2818         WL_TRACE(("wl%d: wlc_ucode_write\n", wlc_hw->unit));
2819
2820         ASSERT(IS_ALIGNED(nbytes, sizeof(u32)));
2821
2822         count = (nbytes / sizeof(u32));
2823
2824         W_REG(osh, &regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2825         (void)R_REG(osh, &regs->objaddr);
2826         for (i = 0; i < count; i++)
2827                 W_REG(osh, &regs->objdata, ucode[i]);
2828 }
2829
2830 static void wlc_write_inits(wlc_hw_info_t *wlc_hw, const d11init_t *inits)
2831 {
2832         int i;
2833         struct osl_info *osh;
2834         volatile u8 *base;
2835
2836         WL_TRACE(("wl%d: wlc_write_inits\n", wlc_hw->unit));
2837
2838         osh = wlc_hw->osh;
2839         base = (volatile u8 *)wlc_hw->regs;
2840
2841         for (i = 0; inits[i].addr != 0xffff; i++) {
2842                 ASSERT((inits[i].size == 2) || (inits[i].size == 4));
2843
2844                 if (inits[i].size == 2)
2845                         W_REG(osh, (u16 *)(base + inits[i].addr),
2846                               inits[i].value);
2847                 else if (inits[i].size == 4)
2848                         W_REG(osh, (u32 *)(base + inits[i].addr),
2849                               inits[i].value);
2850         }
2851 }
2852
2853 static void wlc_ucode_txant_set(wlc_hw_info_t *wlc_hw)
2854 {
2855         u16 phyctl;
2856         u16 phytxant = wlc_hw->bmac_phytxant;
2857         u16 mask = PHY_TXC_ANT_MASK;
2858
2859         /* set the Probe Response frame phy control word */
2860         phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2861         phyctl = (phyctl & ~mask) | phytxant;
2862         wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2863
2864         /* set the Response (ACK/CTS) frame phy control word */
2865         phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2866         phyctl = (phyctl & ~mask) | phytxant;
2867         wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2868 }
2869
2870 void wlc_bmac_txant_set(wlc_hw_info_t *wlc_hw, u16 phytxant)
2871 {
2872         /* update sw state */
2873         wlc_hw->bmac_phytxant = phytxant;
2874
2875         /* push to ucode if up */
2876         if (!wlc_hw->up)
2877                 return;
2878         wlc_ucode_txant_set(wlc_hw);
2879
2880 }
2881
2882 u16 wlc_bmac_get_txant(wlc_hw_info_t *wlc_hw)
2883 {
2884         return (u16) wlc_hw->wlc->stf->txant;
2885 }
2886
2887 void wlc_bmac_antsel_type_set(wlc_hw_info_t *wlc_hw, u8 antsel_type)
2888 {
2889         wlc_hw->antsel_type = antsel_type;
2890
2891         /* Update the antsel type for phy module to use */
2892         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2893 }
2894
2895 void wlc_bmac_fifoerrors(wlc_hw_info_t *wlc_hw)
2896 {
2897         bool fatal = false;
2898         uint unit;
2899         uint intstatus, idx;
2900         d11regs_t *regs = wlc_hw->regs;
2901
2902         unit = wlc_hw->unit;
2903
2904         for (idx = 0; idx < NFIFO; idx++) {
2905                 /* read intstatus register and ignore any non-error bits */
2906                 intstatus =
2907                     R_REG(wlc_hw->osh,
2908                           &regs->intctrlregs[idx].intstatus) & I_ERRORS;
2909                 if (!intstatus)
2910                         continue;
2911
2912                 WL_TRACE(("wl%d: wlc_bmac_fifoerrors: intstatus%d 0x%x\n", unit,
2913                           idx, intstatus));
2914
2915                 if (intstatus & I_RO) {
2916                         WL_ERROR(("wl%d: fifo %d: receive fifo overflow\n",
2917                                   unit, idx));
2918                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxoflo);
2919                         fatal = true;
2920                 }
2921
2922                 if (intstatus & I_PC) {
2923                         WL_ERROR(("wl%d: fifo %d: descriptor error\n", unit,
2924                                   idx));
2925                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmade);
2926                         fatal = true;
2927                 }
2928
2929                 if (intstatus & I_PD) {
2930                         WL_ERROR(("wl%d: fifo %d: data error\n", unit, idx));
2931                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmada);
2932                         fatal = true;
2933                 }
2934
2935                 if (intstatus & I_DE) {
2936                         WL_ERROR(("wl%d: fifo %d: descriptor protocol error\n",
2937                                   unit, idx));
2938                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmape);
2939                         fatal = true;
2940                 }
2941
2942                 if (intstatus & I_RU) {
2943                         WL_ERROR(("wl%d: fifo %d: receive descriptor underflow\n", unit, idx));
2944                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxuflo[idx]);
2945                 }
2946
2947                 if (intstatus & I_XU) {
2948                         WL_ERROR(("wl%d: fifo %d: transmit fifo underflow\n",
2949                                   idx, unit));
2950                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->txuflo);
2951                         fatal = true;
2952                 }
2953
2954                 if (fatal) {
2955                         wlc_fatal_error(wlc_hw->wlc);   /* big hammer */
2956                         break;
2957                 } else
2958                         W_REG(wlc_hw->osh, &regs->intctrlregs[idx].intstatus,
2959                               intstatus);
2960         }
2961 }
2962
2963 void wlc_intrson(struct wlc_info *wlc)
2964 {
2965         wlc_hw_info_t *wlc_hw = wlc->hw;
2966         ASSERT(wlc->defmacintmask);
2967         wlc->macintmask = wlc->defmacintmask;
2968         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2969 }
2970
2971 /* callback for siutils.c, which has only wlc handler, no wl
2972  * they both check up, not only because there is no need to off/restore d11 interrupt
2973  *  but also because per-port code may require sync with valid interrupt.
2974  */
2975
2976 static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2977 {
2978         if (!wlc->hw->up)
2979                 return 0;
2980
2981         return wl_intrsoff(wlc->wl);
2982 }
2983
2984 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2985 {
2986         if (!wlc->hw->up)
2987                 return;
2988
2989         wl_intrsrestore(wlc->wl, macintmask);
2990 }
2991
2992 u32 wlc_intrsoff(struct wlc_info *wlc)
2993 {
2994         wlc_hw_info_t *wlc_hw = wlc->hw;
2995         u32 macintmask;
2996
2997         if (!wlc_hw->clk)
2998                 return 0;
2999
3000         macintmask = wlc->macintmask;   /* isr can still happen */
3001
3002         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, 0);
3003         (void)R_REG(wlc_hw->osh, &wlc_hw->regs->macintmask);    /* sync readback */
3004         udelay(1);              /* ensure int line is no longer driven */
3005         wlc->macintmask = 0;
3006
3007         /* return previous macintmask; resolve race between us and our isr */
3008         return wlc->macintstatus ? 0 : macintmask;
3009 }
3010
3011 void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
3012 {
3013         wlc_hw_info_t *wlc_hw = wlc->hw;
3014         if (!wlc_hw->clk)
3015                 return;
3016
3017         wlc->macintmask = macintmask;
3018         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
3019 }
3020
3021 void wlc_bmac_mute(wlc_hw_info_t *wlc_hw, bool on, mbool flags)
3022 {
3023         struct ether_addr null_ether_addr = { {0, 0, 0, 0, 0, 0} };
3024
3025         if (on) {
3026                 /* suspend tx fifos */
3027                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
3028                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
3029                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
3030                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
3031
3032                 /* zero the address match register so we do not send ACKs */
3033                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
3034                                        &null_ether_addr);
3035         } else {
3036                 /* resume tx fifos */
3037                 if (!wlc_hw->wlc->tx_suspended) {
3038                         wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
3039                 }
3040                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
3041                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
3042                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
3043
3044                 /* Restore address */
3045                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
3046                                        &wlc_hw->etheraddr);
3047         }
3048
3049         wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
3050
3051         if (on)
3052                 wlc_ucode_mute_override_set(wlc_hw);
3053         else
3054                 wlc_ucode_mute_override_clear(wlc_hw);
3055 }
3056
3057 void wlc_bmac_set_deaf(wlc_hw_info_t *wlc_hw, bool user_flag)
3058 {
3059         wlc_phy_set_deaf(wlc_hw->band->pi, user_flag);
3060 }
3061
3062 int wlc_bmac_xmtfifo_sz_get(wlc_hw_info_t *wlc_hw, uint fifo, uint *blocks)
3063 {
3064         if (fifo >= NFIFO)
3065                 return BCME_RANGE;
3066
3067         *blocks = wlc_hw->xmtfifo_sz[fifo];
3068
3069         return 0;
3070 }
3071
3072 int wlc_bmac_xmtfifo_sz_set(wlc_hw_info_t *wlc_hw, uint fifo, uint blocks)
3073 {
3074         if (fifo >= NFIFO || blocks > 299)
3075                 return BCME_RANGE;
3076
3077         /* BMAC_NOTE, change blocks to u16 */
3078         wlc_hw->xmtfifo_sz[fifo] = (u16) blocks;
3079
3080         return 0;
3081 }
3082
3083 /* wlc_bmac_tx_fifo_suspended:
3084  * Check the MAC's tx suspend status for a tx fifo.
3085  *
3086  * When the MAC acknowledges a tx suspend, it indicates that no more
3087  * packets will be transmitted out the radio. This is independent of
3088  * DMA channel suspension---the DMA may have finished suspending, or may still
3089  * be pulling data into a tx fifo, by the time the MAC acks the suspend
3090  * request.
3091  */
3092 bool wlc_bmac_tx_fifo_suspended(wlc_hw_info_t *wlc_hw, uint tx_fifo)
3093 {
3094         /* check that a suspend has been requested and is no longer pending */
3095
3096         /*
3097          * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
3098          * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
3099          * chnstatus register.
3100          * The tx fifo suspend completion is independent of the DMA suspend completion and
3101          *   may be acked before or after the DMA is suspended.
3102          */
3103         if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
3104             (R_REG(wlc_hw->osh, &wlc_hw->regs->chnstatus) &
3105              (1 << tx_fifo)) == 0)
3106                 return true;
3107
3108         return false;
3109 }
3110
3111 void wlc_bmac_tx_fifo_suspend(wlc_hw_info_t *wlc_hw, uint tx_fifo)
3112 {
3113         u8 fifo = 1 << tx_fifo;
3114
3115         /* Two clients of this code, 11h Quiet period and scanning. */
3116
3117         /* only suspend if not already suspended */
3118         if ((wlc_hw->suspended_fifos & fifo) == fifo)
3119                 return;
3120
3121         /* force the core awake only if not already */
3122         if (wlc_hw->suspended_fifos == 0)
3123                 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
3124
3125         wlc_hw->suspended_fifos |= fifo;
3126
3127         if (wlc_hw->di[tx_fifo]) {
3128                 /* Suspending AMPDU transmissions in the middle can cause underflow
3129                  * which may result in mismatch between ucode and driver
3130                  * so suspend the mac before suspending the FIFO
3131                  */
3132                 if (WLC_PHY_11N_CAP(wlc_hw->band))
3133                         wlc_suspend_mac_and_wait(wlc_hw->wlc);
3134
3135                 dma_txsuspend(wlc_hw->di[tx_fifo]);
3136
3137                 if (WLC_PHY_11N_CAP(wlc_hw->band))
3138                         wlc_enable_mac(wlc_hw->wlc);
3139         }
3140 }
3141
3142 void wlc_bmac_tx_fifo_resume(wlc_hw_info_t *wlc_hw, uint tx_fifo)
3143 {
3144         /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
3145          * here for PIO otherwise the watchdog will catch the inconsistency and fire
3146          */
3147         /* Two clients of this code, 11h Quiet period and scanning. */
3148         if (wlc_hw->di[tx_fifo])
3149                 dma_txresume(wlc_hw->di[tx_fifo]);
3150
3151         /* allow core to sleep again */
3152         if (wlc_hw->suspended_fifos == 0)
3153                 return;
3154         else {
3155                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
3156                 if (wlc_hw->suspended_fifos == 0)
3157                         wlc_ucode_wake_override_clear(wlc_hw,
3158                                                       WLC_WAKE_OVERRIDE_TXFIFO);
3159         }
3160 }
3161
3162 /*
3163  * Read and clear macintmask and macintstatus and intstatus registers.
3164  * This routine should be called with interrupts off
3165  * Return:
3166  *   -1 if DEVICEREMOVED(wlc) evaluates to true;
3167  *   0 if the interrupt is not for us, or we are in some special cases;
3168  *   device interrupt status bits otherwise.
3169  */
3170 static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
3171 {
3172         wlc_hw_info_t *wlc_hw = wlc->hw;
3173         d11regs_t *regs = wlc_hw->regs;
3174         u32 macintstatus;
3175         u32 intstatus_rxfifo, intstatus_txsfifo;
3176         struct osl_info *osh;
3177
3178         osh = wlc_hw->osh;
3179
3180         /* macintstatus includes a DMA interrupt summary bit */
3181         macintstatus = R_REG(osh, &regs->macintstatus);
3182
3183         WL_TRACE(("wl%d: macintstatus: 0x%x\n", wlc_hw->unit, macintstatus));
3184
3185         /* detect cardbus removed, in power down(suspend) and in reset */
3186         if (DEVICEREMOVED(wlc))
3187                 return -1;
3188
3189         /* DEVICEREMOVED succeeds even when the core is still resetting,
3190          * handle that case here.
3191          */
3192         if (macintstatus == 0xffffffff)
3193                 return 0;
3194
3195         /* defer unsolicited interrupts */
3196         macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
3197
3198         /* if not for us */
3199         if (macintstatus == 0)
3200                 return 0;
3201
3202         /* interrupts are already turned off for CFE build
3203          * Caution: For CFE Turning off the interrupts again has some undesired
3204          * consequences
3205          */
3206         /* turn off the interrupts */
3207         W_REG(osh, &regs->macintmask, 0);
3208         (void)R_REG(osh, &regs->macintmask);    /* sync readback */
3209         wlc->macintmask = 0;
3210
3211         /* clear device interrupts */
3212         W_REG(osh, &regs->macintstatus, macintstatus);
3213
3214         /* MI_DMAINT is indication of non-zero intstatus */
3215         if (macintstatus & MI_DMAINT) {
3216                 if (D11REV_IS(wlc_hw->corerev, 4)) {
3217                         intstatus_rxfifo =
3218                             R_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus);
3219                         intstatus_txsfifo =
3220                             R_REG(osh,
3221                                   &regs->intctrlregs[RX_TXSTATUS_FIFO].
3222                                   intstatus);
3223                         WL_TRACE(("wl%d: intstatus_rxfifo 0x%x, intstatus_txsfifo 0x%x\n", wlc_hw->unit, intstatus_rxfifo, intstatus_txsfifo));
3224
3225                         /* defer unsolicited interrupt hints */
3226                         intstatus_rxfifo &= DEF_RXINTMASK;
3227                         intstatus_txsfifo &= DEF_RXINTMASK;
3228
3229                         /* MI_DMAINT bit in macintstatus is indication of RX_FIFO interrupt */
3230                         /* clear interrupt hints */
3231                         if (intstatus_rxfifo)
3232                                 W_REG(osh,
3233                                       &regs->intctrlregs[RX_FIFO].intstatus,
3234                                       intstatus_rxfifo);
3235                         else
3236                                 macintstatus &= ~MI_DMAINT;
3237
3238                         /* MI_TFS bit in macintstatus is encoding of RX_TXSTATUS_FIFO interrupt */
3239                         if (intstatus_txsfifo) {
3240                                 W_REG(osh,
3241                                       &regs->intctrlregs[RX_TXSTATUS_FIFO].
3242                                       intstatus, intstatus_txsfifo);
3243                                 macintstatus |= MI_TFS;
3244                         }
3245                 } else {
3246                         /*
3247                          * For corerevs >= 5, only fifo interrupt enabled is I_RI in RX_FIFO.
3248                          * If MI_DMAINT is set, assume it is set and clear the interrupt.
3249                          */
3250                         W_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus,
3251                               DEF_RXINTMASK);
3252                 }
3253         }
3254
3255         return macintstatus;
3256 }
3257
3258 /* Update wlc->macintstatus and wlc->intstatus[]. */
3259 /* Return true if they are updated successfully. false otherwise */
3260 bool wlc_intrsupd(struct wlc_info *wlc)
3261 {
3262         u32 macintstatus;
3263
3264         ASSERT(wlc->macintstatus != 0);
3265
3266         /* read and clear macintstatus and intstatus registers */
3267         macintstatus = wlc_intstatus(wlc, false);
3268
3269         /* device is removed */
3270         if (macintstatus == 0xffffffff)
3271                 return false;
3272
3273         /* update interrupt status in software */
3274         wlc->macintstatus |= macintstatus;
3275
3276         return true;
3277 }
3278
3279 /*
3280  * First-level interrupt processing.
3281  * Return true if this was our interrupt, false otherwise.
3282  * *wantdpc will be set to true if further wlc_dpc() processing is required,
3283  * false otherwise.
3284  */
3285 bool BCMFASTPATH wlc_isr(struct wlc_info *wlc, bool *wantdpc)
3286 {
3287         wlc_hw_info_t *wlc_hw = wlc->hw;
3288         u32 macintstatus;
3289
3290         *wantdpc = false;
3291
3292         if (!wlc_hw->up || !wlc->macintmask)
3293                 return false;
3294
3295         /* read and clear macintstatus and intstatus registers */
3296         macintstatus = wlc_intstatus(wlc, true);
3297
3298         if (macintstatus == 0xffffffff)
3299                 WL_ERROR(("DEVICEREMOVED detected in the ISR code path.\n"));
3300
3301         /* it is not for us */
3302         if (macintstatus == 0)
3303                 return false;
3304
3305         *wantdpc = true;
3306
3307         /* save interrupt status bits */
3308         ASSERT(wlc->macintstatus == 0);
3309         wlc->macintstatus = macintstatus;
3310
3311         return true;
3312
3313 }
3314
3315 /* process tx completion events for corerev < 5 */
3316 static bool wlc_bmac_txstatus_corerev4(wlc_hw_info_t *wlc_hw)
3317 {
3318         struct sk_buff *status_p;
3319         tx_status_t *txs;
3320         struct osl_info *osh;
3321         bool fatal = false;
3322
3323         WL_TRACE(("wl%d: wlc_txstatusrecv\n", wlc_hw->unit));
3324
3325         osh = wlc_hw->osh;
3326
3327         while (!fatal && (status_p = dma_rx(wlc_hw->di[RX_TXSTATUS_FIFO]))) {
3328
3329                 txs = (tx_status_t *) status_p->data;
3330                 /* MAC uses little endian only */
3331                 ltoh16_buf((void *)txs, sizeof(tx_status_t));
3332
3333                 /* shift low bits for tx_status_t status compatibility */
3334                 txs->status = (txs->status & ~TXS_COMPAT_MASK)
3335                     | (((txs->status & TXS_COMPAT_MASK) << TXS_COMPAT_SHIFT));
3336
3337                 fatal = wlc_bmac_dotxstatus(wlc_hw, txs, 0);
3338
3339                 PKTFREE(osh, status_p, false);
3340         }
3341
3342         if (fatal)
3343                 return true;
3344
3345         /* post more rbufs */
3346         dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
3347
3348         return false;
3349 }
3350
3351 static bool BCMFASTPATH
3352 wlc_bmac_dotxstatus(wlc_hw_info_t *wlc_hw, tx_status_t *txs, u32 s2)
3353 {
3354         /* discard intermediate indications for ucode with one legitimate case:
3355          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
3356          *   tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
3357          *   transmission count)
3358          */
3359         if (!(txs->status & TX_STATUS_AMPDU)
3360             && (txs->status & TX_STATUS_INTERMEDIATE)) {
3361                 return false;
3362         }
3363
3364         return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
3365 }
3366
3367 /* process tx completion events in BMAC
3368  * Return true if more tx status need to be processed. false otherwise.
3369  */
3370 static bool BCMFASTPATH
3371 wlc_bmac_txstatus(wlc_hw_info_t *wlc_hw, bool bound, bool *fatal)
3372 {
3373         bool morepending = false;
3374         struct wlc_info *wlc = wlc_hw->wlc;
3375
3376         WL_TRACE(("wl%d: wlc_bmac_txstatus\n", wlc_hw->unit));
3377
3378         if (D11REV_IS(wlc_hw->corerev, 4)) {
3379                 /* to retire soon */
3380                 *fatal = wlc_bmac_txstatus_corerev4(wlc->hw);
3381
3382                 if (*fatal)
3383                         return 0;
3384         } else {
3385                 /* corerev >= 5 */
3386                 d11regs_t *regs;
3387                 struct osl_info *osh;
3388                 tx_status_t txstatus, *txs;
3389                 u32 s1, s2;
3390                 uint n = 0;
3391                 /* Param 'max_tx_num' indicates max. # tx status to process before break out. */
3392                 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3393
3394                 txs = &txstatus;
3395                 regs = wlc_hw->regs;
3396                 osh = wlc_hw->osh;
3397                 while (!(*fatal)
3398                        && (s1 = R_REG(osh, &regs->frmtxstatus)) & TXS_V) {
3399
3400                         if (s1 == 0xffffffff) {
3401                                 WL_ERROR(("wl%d: %s: dead chip\n",
3402                                           wlc_hw->unit, __func__));
3403                                 ASSERT(s1 != 0xffffffff);
3404                                 return morepending;
3405                         }
3406
3407                         s2 = R_REG(osh, &regs->frmtxstatus2);
3408
3409                         txs->status = s1 & TXS_STATUS_MASK;
3410                         txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3411                         txs->sequence = s2 & TXS_SEQ_MASK;
3412                         txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3413                         txs->lasttxtime = 0;
3414
3415                         *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3416
3417                         /* !give others some time to run! */
3418                         if (++n >= max_tx_num)
3419                                 break;
3420                 }
3421
3422                 if (*fatal)
3423                         return 0;
3424
3425                 if (n >= max_tx_num)
3426                         morepending = true;
3427         }
3428
3429         if (!pktq_empty(&wlc->active_queue->q))
3430                 wlc_send_q(wlc, wlc->active_queue);
3431
3432         return morepending;
3433 }
3434
3435 void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3436 {
3437         wlc_hw_info_t *wlc_hw = wlc->hw;
3438         d11regs_t *regs = wlc_hw->regs;
3439         u32 mc, mi;
3440         struct osl_info *osh;
3441
3442         WL_TRACE(("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n", wlc_hw->unit,
3443                   wlc_hw->band->bandunit));
3444
3445         /*
3446          * Track overlapping suspend requests
3447          */
3448         wlc_hw->mac_suspend_depth++;
3449         if (wlc_hw->mac_suspend_depth > 1)
3450                 return;
3451
3452         osh = wlc_hw->osh;
3453
3454         /* force the core awake */
3455         wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3456
3457         mc = R_REG(osh, &regs->maccontrol);
3458
3459         if (mc == 0xffffffff) {
3460                 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3461                 wl_down(wlc->wl);
3462                 return;
3463         }
3464         ASSERT(!(mc & MCTL_PSM_JMP_0));
3465         ASSERT(mc & MCTL_PSM_RUN);
3466         ASSERT(mc & MCTL_EN_MAC);
3467
3468         mi = R_REG(osh, &regs->macintstatus);
3469         if (mi == 0xffffffff) {
3470                 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3471                 wl_down(wlc->wl);
3472                 return;
3473         }
3474         ASSERT(!(mi & MI_MACSSPNDD));
3475
3476         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3477
3478         SPINWAIT(!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD),
3479                  WLC_MAX_MAC_SUSPEND);
3480
3481         if (!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD)) {
3482                 WL_ERROR(("wl%d: wlc_suspend_mac_and_wait: waited %d uS and "
3483                           "MI_MACSSPNDD is still not on.\n",
3484                           wlc_hw->unit, WLC_MAX_MAC_SUSPEND));
3485                 WL_ERROR(("wl%d: psmdebug 0x%08x, phydebug 0x%08x, psm_brc 0x%04x\n", wlc_hw->unit, R_REG(osh, &regs->psmdebug), R_REG(osh, &regs->phydebug), R_REG(osh, &regs->psm_brc)));
3486         }
3487
3488         mc = R_REG(osh, &regs->maccontrol);
3489         if (mc == 0xffffffff) {
3490                 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3491                 wl_down(wlc->wl);
3492                 return;
3493         }
3494         ASSERT(!(mc & MCTL_PSM_JMP_0));
3495         ASSERT(mc & MCTL_PSM_RUN);
3496         ASSERT(!(mc & MCTL_EN_MAC));
3497 }
3498
3499 void wlc_enable_mac(struct wlc_info *wlc)
3500 {
3501         wlc_hw_info_t *wlc_hw = wlc->hw;
3502         d11regs_t *regs = wlc_hw->regs;
3503         u32 mc, mi;
3504         struct osl_info *osh;
3505
3506         WL_TRACE(("wl%d: wlc_enable_mac: bandunit %d\n", wlc_hw->unit,
3507                   wlc->band->bandunit));
3508
3509         /*
3510          * Track overlapping suspend requests
3511          */
3512         ASSERT(wlc_hw->mac_suspend_depth > 0);
3513         wlc_hw->mac_suspend_depth--;
3514         if (wlc_hw->mac_suspend_depth > 0)
3515                 return;
3516
3517         osh = wlc_hw->osh;
3518
3519         mc = R_REG(osh, &regs->maccontrol);
3520         ASSERT(!(mc & MCTL_PSM_JMP_0));
3521         ASSERT(!(mc & MCTL_EN_MAC));
3522         ASSERT(mc & MCTL_PSM_RUN);
3523
3524         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3525         W_REG(osh, &regs->macintstatus, MI_MACSSPNDD);
3526
3527         mc = R_REG(osh, &regs->maccontrol);
3528         ASSERT(!(mc & MCTL_PSM_JMP_0));
3529         ASSERT(mc & MCTL_EN_MAC);
3530         ASSERT(mc & MCTL_PSM_RUN);
3531
3532         mi = R_REG(osh, &regs->macintstatus);
3533         ASSERT(!(mi & MI_MACSSPNDD));
3534
3535         wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3536 }
3537
3538 void wlc_bmac_ifsctl_edcrs_set(wlc_hw_info_t *wlc_hw, bool abie, bool isht)
3539 {
3540         if (!(WLCISNPHY(wlc_hw->band) && (D11REV_GE(wlc_hw->corerev, 16))))
3541                 return;
3542
3543         if (isht) {
3544                 if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 3)) {
3545                         AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3546                                 ~IFS_CTL1_EDCRS);
3547                 }
3548         } else {
3549                 /* enable EDCRS for non-11n association */
3550                 OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1, IFS_CTL1_EDCRS);
3551         }
3552
3553         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3)) {
3554                 if (CHSPEC_IS20(wlc_hw->chanspec)) {
3555                         /* 20 mhz, use 20U ED only */
3556                         OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3557                                IFS_CTL1_EDCRS);
3558                         AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3559                                 ~IFS_CTL1_EDCRS_20L);
3560                         AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3561                                 ~IFS_CTL1_EDCRS_40);
3562                 } else {
3563                         /* 40 mhz, use 20U 20L and 40 ED */
3564                         OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3565                                IFS_CTL1_EDCRS);
3566                         OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3567                                IFS_CTL1_EDCRS_20L);
3568                         OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3569                                IFS_CTL1_EDCRS_40);
3570                 }
3571         }
3572 }
3573
3574 static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t *wlc_hw)
3575 {
3576         u8 rate;
3577         u8 rates[8] = {
3578                 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3579                 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3580         };
3581         u16 entry_ptr;
3582         u16 pctl1;
3583         uint i;
3584
3585         if (!WLC_PHY_11N_CAP(wlc_hw->band))
3586                 return;
3587
3588         /* walk the phy rate table and update the entries */
3589         for (i = 0; i < ARRAY_SIZE(rates); i++) {
3590                 rate = rates[i];
3591
3592                 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3593
3594                 /* read the SHM Rate Table entry OFDM PCTL1 values */
3595                 pctl1 =
3596                     wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3597
3598                 /* modify the value */
3599                 pctl1 &= ~PHY_TXC1_MODE_MASK;
3600                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3601
3602                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3603                 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3604                                    pctl1);
3605         }
3606 }
3607
3608 static u16 wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t *wlc_hw, u8 rate)
3609 {
3610         uint i;
3611         u8 plcp_rate = 0;
3612         struct plcp_signal_rate_lookup {
3613                 u8 rate;
3614                 u8 signal_rate;
3615         };
3616         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3617         const struct plcp_signal_rate_lookup rate_lookup[] = {
3618                 {WLC_RATE_6M, 0xB},
3619                 {WLC_RATE_9M, 0xF},
3620                 {WLC_RATE_12M, 0xA},
3621                 {WLC_RATE_18M, 0xE},
3622                 {WLC_RATE_24M, 0x9},
3623                 {WLC_RATE_36M, 0xD},
3624                 {WLC_RATE_48M, 0x8},
3625                 {WLC_RATE_54M, 0xC}
3626         };
3627
3628         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3629                 if (rate == rate_lookup[i].rate) {
3630                         plcp_rate = rate_lookup[i].signal_rate;
3631                         break;
3632                 }
3633         }
3634
3635         /* Find the SHM pointer to the rate table entry by looking in the
3636          * Direct-map Table
3637          */
3638         return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3639 }
3640
3641 void wlc_bmac_band_stf_ss_set(wlc_hw_info_t *wlc_hw, u8 stf_mode)
3642 {
3643         wlc_hw->hw_stf_ss_opmode = stf_mode;
3644
3645         if (wlc_hw->clk)
3646                 wlc_upd_ofdm_pctl1_table(wlc_hw);
3647 }
3648
3649 void BCMFASTPATH
3650 wlc_bmac_read_tsf(wlc_hw_info_t *wlc_hw, u32 *tsf_l_ptr,
3651                   u32 *tsf_h_ptr)
3652 {
3653         d11regs_t *regs = wlc_hw->regs;
3654
3655         /* read the tsf timer low, then high to get an atomic read */
3656         *tsf_l_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerlow);
3657         *tsf_h_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerhigh);
3658
3659         return;
3660 }
3661
3662 bool wlc_bmac_validate_chip_access(wlc_hw_info_t *wlc_hw)
3663 {
3664         d11regs_t *regs;
3665         u32 w, val;
3666         volatile u16 *reg16;
3667         struct osl_info *osh;
3668
3669         WL_TRACE(("wl%d: validate_chip_access\n", wlc_hw->unit));
3670
3671         regs = wlc_hw->regs;
3672         osh = wlc_hw->osh;
3673
3674         /* Validate dchip register access */
3675
3676         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3677         (void)R_REG(osh, &regs->objaddr);
3678         w = R_REG(osh, &regs->objdata);
3679
3680         /* Can we write and read back a 32bit register? */
3681         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3682         (void)R_REG(osh, &regs->objaddr);
3683         W_REG(osh, &regs->objdata, (u32) 0xaa5555aa);
3684
3685         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3686         (void)R_REG(osh, &regs->objaddr);
3687         val = R_REG(osh, &regs->objdata);
3688         if (val != (u32) 0xaa5555aa) {
3689                 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n", wlc_hw->unit, val));
3690                 return false;
3691         }
3692
3693         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3694         (void)R_REG(osh, &regs->objaddr);
3695         W_REG(osh, &regs->objdata, (u32) 0x55aaaa55);
3696
3697         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3698         (void)R_REG(osh, &regs->objaddr);
3699         val = R_REG(osh, &regs->objdata);
3700         if (val != (u32) 0x55aaaa55) {
3701                 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n", wlc_hw->unit, val));
3702                 return false;
3703         }
3704
3705         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3706         (void)R_REG(osh, &regs->objaddr);
3707         W_REG(osh, &regs->objdata, w);
3708
3709         if (D11REV_LT(wlc_hw->corerev, 11)) {
3710                 /* if 32 bit writes are split into 16 bit writes, are they in the correct order
3711                  * for our interface, low to high
3712                  */
3713                 reg16 = (volatile u16 *)&regs->tsf_cfpstart;
3714
3715                 /* write the CFPStart register low half explicitly, starting a buffered write */
3716                 W_REG(osh, reg16, 0xAAAA);
3717
3718                 /* Write a 32 bit value to CFPStart to test the 16 bit split order.
3719                  * If the low 16 bits are written first, followed by the high 16 bits then the
3720                  * 32 bit value 0xCCCCBBBB should end up in the register.
3721                  * If the order is reversed, then the write to the high half will trigger a buffered
3722                  * write of 0xCCCCAAAA.
3723                  * If the bus is 32 bits, then this is not much of a test, and the reg should
3724                  * have the correct value 0xCCCCBBBB.
3725                  */
3726                 W_REG(osh, &regs->tsf_cfpstart, 0xCCCCBBBB);
3727
3728                 /* verify with the 16 bit registers that have no side effects */
3729                 val = R_REG(osh, &regs->tsf_cfpstrt_l);
3730                 if (val != (uint) 0xBBBB) {
3731                         WL_ERROR(("wl%d: validate_chip_access: tsf_cfpstrt_l = 0x%x, expected" " 0x%x\n", wlc_hw->unit, val, 0xBBBB));
3732                         return false;
3733                 }
3734                 val = R_REG(osh, &regs->tsf_cfpstrt_h);
3735                 if (val != (uint) 0xCCCC) {
3736                         WL_ERROR(("wl%d: validate_chip_access: tsf_cfpstrt_h = 0x%x, expected" " 0x%x\n", wlc_hw->unit, val, 0xCCCC));
3737                         return false;
3738                 }
3739
3740         }
3741
3742         /* clear CFPStart */
3743         W_REG(osh, &regs->tsf_cfpstart, 0);
3744
3745         w = R_REG(osh, &regs->maccontrol);
3746         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3747             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3748                 WL_ERROR(("wl%d: validate_chip_access: maccontrol = 0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w, (MCTL_IHR_EN | MCTL_WAKE), (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE)));
3749                 return false;
3750         }
3751
3752         return true;
3753 }
3754
3755 #define PHYPLL_WAIT_US  100000
3756
3757 void wlc_bmac_core_phypll_ctl(wlc_hw_info_t *wlc_hw, bool on)
3758 {
3759         d11regs_t *regs;
3760         struct osl_info *osh;
3761         u32 tmp;
3762
3763         WL_TRACE(("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit));
3764
3765         tmp = 0;
3766         regs = wlc_hw->regs;
3767         osh = wlc_hw->osh;
3768
3769         if (D11REV_LE(wlc_hw->corerev, 16) || D11REV_IS(wlc_hw->corerev, 20))
3770                 return;
3771
3772         if (on) {
3773                 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3774                         OR_REG(osh, &regs->clk_ctl_st,
3775                                (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3776                                 CCS_ERSRC_REQ_PHYPLL));
3777                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3778                                   (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3779                                  PHYPLL_WAIT_US);
3780
3781                         tmp = R_REG(osh, &regs->clk_ctl_st);
3782                         if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3783                             (CCS_ERSRC_AVAIL_HT)) {
3784                                 WL_ERROR(("%s: turn on PHY PLL failed\n",
3785                                           __func__));
3786                                 ASSERT(0);
3787                         }
3788                 } else {
3789                         OR_REG(osh, &regs->clk_ctl_st,
3790                                (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3791                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3792                                   (CCS_ERSRC_AVAIL_D11PLL |
3793                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
3794                                  (CCS_ERSRC_AVAIL_D11PLL |
3795                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3796
3797                         tmp = R_REG(osh, &regs->clk_ctl_st);
3798                         if ((tmp &
3799                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3800                             !=
3801                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3802                                 WL_ERROR(("%s: turn on PHY PLL failed\n",
3803                                           __func__));
3804                                 ASSERT(0);
3805                         }
3806                 }
3807         } else {
3808                 /* Since the PLL may be shared, other cores can still be requesting it;
3809                  * so we'll deassert the request but not wait for status to comply.
3810                  */
3811                 AND_REG(osh, &regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3812                 tmp = R_REG(osh, &regs->clk_ctl_st);
3813         }
3814 }
3815
3816 void wlc_coredisable(wlc_hw_info_t *wlc_hw)
3817 {
3818         bool dev_gone;
3819
3820         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
3821
3822         ASSERT(!wlc_hw->up);
3823
3824         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3825
3826         if (dev_gone)
3827                 return;
3828
3829         if (wlc_hw->noreset)
3830                 return;
3831
3832         /* radio off */
3833         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3834
3835         /* turn off analog core */
3836         wlc_phy_anacore(wlc_hw->band->pi, OFF);
3837
3838         /* turn off PHYPLL to save power */
3839         wlc_bmac_core_phypll_ctl(wlc_hw, false);
3840
3841         /* No need to set wlc->pub->radio_active = OFF
3842          * because this function needs down capability and
3843          * radio_active is designed for BCMNODOWN.
3844          */
3845
3846         /* remove gpio controls */
3847         if (wlc_hw->ucode_dbgsel)
3848                 si_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3849
3850         wlc_hw->clk = false;
3851         si_core_disable(wlc_hw->sih, 0);
3852         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3853 }
3854
3855 /* power both the pll and external oscillator on/off */
3856 void wlc_bmac_xtal(wlc_hw_info_t *wlc_hw, bool want)
3857 {
3858         WL_TRACE(("wl%d: wlc_bmac_xtal: want %d\n", wlc_hw->unit, want));
3859
3860         /* dont power down if plldown is false or we must poll hw radio disable */
3861         if (!want && wlc_hw->pllreq)
3862                 return;
3863
3864         if (wlc_hw->sih)
3865                 si_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3866
3867         wlc_hw->sbclk = want;
3868         if (!wlc_hw->sbclk) {
3869                 wlc_hw->clk = false;
3870                 if (wlc_hw->band && wlc_hw->band->pi)
3871                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3872         }
3873 }
3874
3875 static void wlc_flushqueues(struct wlc_info *wlc)
3876 {
3877         wlc_hw_info_t *wlc_hw = wlc->hw;
3878         uint i;
3879
3880         wlc->txpend16165war = 0;
3881
3882         /* free any posted tx packets */
3883         for (i = 0; i < NFIFO; i++)
3884                 if (wlc_hw->di[i]) {
3885                         dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3886                         TXPKTPENDCLR(wlc, i);
3887                         WL_TRACE(("wlc_flushqueues: pktpend fifo %d cleared\n",
3888                                   i));
3889                 }
3890
3891         /* free any posted rx packets */
3892         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3893         if (D11REV_IS(wlc_hw->corerev, 4))
3894                 dma_rxreclaim(wlc_hw->di[RX_TXSTATUS_FIFO]);
3895 }
3896
3897 u16 wlc_bmac_read_shm(wlc_hw_info_t *wlc_hw, uint offset)
3898 {
3899         return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3900 }
3901
3902 void wlc_bmac_write_shm(wlc_hw_info_t *wlc_hw, uint offset, u16 v)
3903 {
3904         wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3905 }
3906
3907 /* Set a range of shared memory to a value.
3908  * SHM 'offset' needs to be an even address and
3909  * Buffer length 'len' must be an even number of bytes
3910  */
3911 void wlc_bmac_set_shm(wlc_hw_info_t *wlc_hw, uint offset, u16 v, int len)
3912 {
3913         int i;
3914
3915         /* offset and len need to be even */
3916         ASSERT((offset & 1) == 0);
3917         ASSERT((len & 1) == 0);
3918
3919         if (len <= 0)
3920                 return;
3921
3922         for (i = 0; i < len; i += 2) {
3923                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, OBJADDR_SHM_SEL);
3924         }
3925 }
3926
3927 static u16
3928 wlc_bmac_read_objmem(wlc_hw_info_t *wlc_hw, uint offset, u32 sel)
3929 {
3930         d11regs_t *regs = wlc_hw->regs;
3931         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3932         volatile u16 *objdata_hi = objdata_lo + 1;
3933         u16 v;
3934
3935         ASSERT((offset & 1) == 0);
3936
3937         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3938         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3939         if (offset & 2) {
3940                 v = R_REG(wlc_hw->osh, objdata_hi);
3941         } else {
3942                 v = R_REG(wlc_hw->osh, objdata_lo);
3943         }
3944
3945         return v;
3946 }
3947
3948 static void
3949 wlc_bmac_write_objmem(wlc_hw_info_t *wlc_hw, uint offset, u16 v, u32 sel)
3950 {
3951         d11regs_t *regs = wlc_hw->regs;
3952         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3953         volatile u16 *objdata_hi = objdata_lo + 1;
3954
3955         ASSERT((offset & 1) == 0);
3956
3957         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3958         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3959         if (offset & 2) {
3960                 W_REG(wlc_hw->osh, objdata_hi, v);
3961         } else {
3962                 W_REG(wlc_hw->osh, objdata_lo, v);
3963         }
3964 }
3965
3966 /* Copy a buffer to shared memory of specified type .
3967  * SHM 'offset' needs to be an even address and
3968  * Buffer length 'len' must be an even number of bytes
3969  * 'sel' selects the type of memory
3970  */
3971 void
3972 wlc_bmac_copyto_objmem(wlc_hw_info_t *wlc_hw, uint offset, const void *buf,
3973                        int len, u32 sel)
3974 {
3975         u16 v;
3976         const u8 *p = (const u8 *)buf;
3977         int i;
3978
3979         /* offset and len need to be even */
3980         ASSERT((offset & 1) == 0);
3981         ASSERT((len & 1) == 0);
3982
3983         if (len <= 0)
3984                 return;
3985
3986         for (i = 0; i < len; i += 2) {
3987                 v = p[i] | (p[i + 1] << 8);
3988                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3989         }
3990 }
3991
3992 /* Copy a piece of shared memory of specified type to a buffer .
3993  * SHM 'offset' needs to be an even address and
3994  * Buffer length 'len' must be an even number of bytes
3995  * 'sel' selects the type of memory
3996  */
3997 void
3998 wlc_bmac_copyfrom_objmem(wlc_hw_info_t *wlc_hw, uint offset, void *buf,
3999                          int len, u32 sel)
4000 {
4001         u16 v;
4002         u8 *p = (u8 *) buf;
4003         int i;
4004
4005         /* offset and len need to be even */
4006         ASSERT((offset & 1) == 0);
4007         ASSERT((len & 1) == 0);
4008
4009         if (len <= 0)
4010                 return;
4011
4012         for (i = 0; i < len; i += 2) {
4013                 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
4014                 p[i] = v & 0xFF;
4015                 p[i + 1] = (v >> 8) & 0xFF;
4016         }
4017 }
4018
4019 void wlc_bmac_copyfrom_vars(wlc_hw_info_t *wlc_hw, char **buf, uint *len)
4020 {
4021         WL_TRACE(("wlc_bmac_copyfrom_vars, nvram vars totlen=%d\n",
4022                   wlc_hw->vars_size));
4023
4024         *buf = wlc_hw->vars;
4025         *len = wlc_hw->vars_size;
4026 }
4027
4028 void wlc_bmac_retrylimit_upd(wlc_hw_info_t *wlc_hw, u16 SRL, u16 LRL)
4029 {
4030         wlc_hw->SRL = SRL;
4031         wlc_hw->LRL = LRL;
4032
4033         /* write retry limit to SCR, shouldn't need to suspend */
4034         if (wlc_hw->up) {
4035                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
4036                       OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
4037                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
4038                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->SRL);
4039                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
4040                       OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
4041                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
4042                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->LRL);
4043         }
4044 }
4045
4046 void wlc_bmac_set_noreset(wlc_hw_info_t *wlc_hw, bool noreset_flag)
4047 {
4048         wlc_hw->noreset = noreset_flag;
4049 }
4050
4051 void wlc_bmac_set_ucode_loaded(wlc_hw_info_t *wlc_hw, bool ucode_loaded)
4052 {
4053         wlc_hw->ucode_loaded = ucode_loaded;
4054 }
4055
4056 void wlc_bmac_pllreq(wlc_hw_info_t *wlc_hw, bool set, mbool req_bit)
4057 {
4058         ASSERT(req_bit);
4059
4060         if (set) {
4061                 if (mboolisset(wlc_hw->pllreq, req_bit))
4062                         return;
4063
4064                 mboolset(wlc_hw->pllreq, req_bit);
4065
4066                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
4067                         if (!wlc_hw->sbclk) {
4068                                 wlc_bmac_xtal(wlc_hw, ON);
4069                         }
4070                 }
4071         } else {
4072                 if (!mboolisset(wlc_hw->pllreq, req_bit))
4073                         return;
4074
4075                 mboolclr(wlc_hw->pllreq, req_bit);
4076
4077                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
4078                         if (wlc_hw->sbclk) {
4079                                 wlc_bmac_xtal(wlc_hw, OFF);
4080                         }
4081                 }
4082         }
4083
4084         return;
4085 }
4086
4087 void wlc_bmac_set_clk(wlc_hw_info_t *wlc_hw, bool on)
4088 {
4089         if (on) {
4090                 /* power up pll and oscillator */
4091                 wlc_bmac_xtal(wlc_hw, ON);
4092
4093                 /* enable core(s), ignore bandlocked
4094                  * Leave with the same band selected as we entered
4095                  */
4096                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
4097         } else {
4098                 /* if already down, must skip the core disable */
4099                 if (wlc_hw->clk) {
4100                         /* disable core(s), ignore bandlocked */
4101                         wlc_coredisable(wlc_hw);
4102                 }
4103                 /* power down pll and oscillator */
4104                 wlc_bmac_xtal(wlc_hw, OFF);
4105         }
4106 }
4107
4108 /* this will be true for all ai chips */
4109 bool wlc_bmac_taclear(wlc_hw_info_t *wlc_hw, bool ta_ok)
4110 {
4111         return true;
4112 }
4113
4114 /* Lower down relevant GPIOs like LED when going down w/o
4115  * doing PCI config cycles or touching interrupts
4116  */
4117 void wlc_gpio_fast_deinit(wlc_hw_info_t *wlc_hw)
4118 {
4119         if ((wlc_hw == NULL) || (wlc_hw->sih == NULL))
4120                 return;
4121
4122         /* Only chips with internal bus or PCIE cores or certain PCI cores
4123          * are able to switch cores w/o disabling interrupts
4124          */
4125         if (!((wlc_hw->sih->bustype == SI_BUS) ||
4126               ((wlc_hw->sih->bustype == PCI_BUS) &&
4127                ((wlc_hw->sih->buscoretype == PCIE_CORE_ID) ||
4128                 (wlc_hw->sih->buscorerev >= 13)))))
4129                 return;
4130
4131         WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
4132         return;
4133 }
4134
4135 bool wlc_bmac_radio_hw(wlc_hw_info_t *wlc_hw, bool enable)
4136 {
4137         /* Do not access Phy registers if core is not up */
4138         if (si_iscoreup(wlc_hw->sih) == false)
4139                 return false;
4140
4141         if (enable) {
4142                 if (PMUCTL_ENAB(wlc_hw->sih)) {
4143                         AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
4144                                 ~CCS_FORCEHWREQOFF);
4145                         si_pmu_radio_enable(wlc_hw->sih, true);
4146                 }
4147
4148                 wlc_phy_anacore(wlc_hw->band->pi, ON);
4149                 wlc_phy_switch_radio(wlc_hw->band->pi, ON);
4150
4151                 /* resume d11 core */
4152                 wlc_enable_mac(wlc_hw->wlc);
4153         } else {
4154                 /* suspend d11 core */
4155                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
4156
4157                 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
4158                 wlc_phy_anacore(wlc_hw->band->pi, OFF);
4159
4160                 if (PMUCTL_ENAB(wlc_hw->sih)) {
4161                         si_pmu_radio_enable(wlc_hw->sih, false);
4162                         OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
4163                                CCS_FORCEHWREQOFF);
4164                 }
4165         }
4166
4167         return true;
4168 }
4169
4170 u16 wlc_bmac_rate_shm_offset(wlc_hw_info_t *wlc_hw, u8 rate)
4171 {
4172         u16 table_ptr;
4173         u8 phy_rate, index;
4174
4175         /* get the phy specific rate encoding for the PLCP SIGNAL field */
4176         /* XXX4321 fixup needed ? */
4177         if (IS_OFDM(rate))
4178                 table_ptr = M_RT_DIRMAP_A;
4179         else
4180                 table_ptr = M_RT_DIRMAP_B;
4181
4182         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
4183          * the index into the rate table.
4184          */
4185         phy_rate = rate_info[rate] & RATE_MASK;
4186         index = phy_rate & 0xf;
4187
4188         /* Find the SHM pointer to the rate table entry by looking in the
4189          * Direct-map Table
4190          */
4191         return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
4192 }
4193
4194 void wlc_bmac_set_txpwr_percent(wlc_hw_info_t *wlc_hw, u8 val)
4195 {
4196         wlc_phy_txpwr_percent_set(wlc_hw->band->pi, val);
4197 }
4198
4199 void wlc_bmac_antsel_set(wlc_hw_info_t *wlc_hw, u32 antsel_avail)
4200 {
4201         wlc_hw->antsel_avail = antsel_avail;
4202 }