2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
26 * Data structure to export all chip specific common variables
27 * public (read-only) portion of siutils handle returned by si_attach()
30 uint socitype; /* SOCI_SB, SOCI_AI */
32 uint bustype; /* SI_BUS, PCI_BUS */
33 uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
34 uint buscorerev; /* buscore rev */
35 uint buscoreidx; /* buscore index */
36 int ccrev; /* chip common core rev */
37 u32 cccaps; /* chip common capabilities */
38 u32 cccaps_ext; /* chip common capabilities extension */
39 int pmurev; /* pmu core rev */
40 u32 pmucaps; /* pmu capabilities */
41 uint boardtype; /* board type */
42 uint boardvendor; /* board vendor */
43 uint boardflags; /* board flags */
44 uint boardflags2; /* board flags2 */
45 uint chip; /* chip number */
46 uint chiprev; /* chip revision */
47 uint chippkg; /* chip package option */
48 u32 chipst; /* chip status */
49 bool issim; /* chip is in simulation or emulation */
50 uint socirev; /* SOC interconnect rev */
58 /* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
59 * for monolithic driver, it is readonly to prevent accident change
62 typedef struct si_pub si_t;
64 typedef const struct si_pub si_t;
68 * Many of the routines below take an 'sih' handle as their first arg.
69 * Allocate this by calling si_attach(). Free it by calling si_detach().
70 * At any one time, the sih is logically focused on one particular si core
71 * (the "current core").
72 * Use si_setcore() or si_setcoreidx() to change the association to another core.
75 #define BADIDX (SI_MAXCORES + 1)
77 /* clkctl xtal what flags */
78 #define XTAL 0x1 /* primary crystal oscillator (2050) */
79 #define PLL 0x2 /* main chip pll */
82 #define CLK_FAST 0 /* force fast (pll) clock */
83 #define CLK_DYNAMIC 2 /* enable dynamic clock control */
85 /* GPIO usage priorities */
86 #define GPIO_DRV_PRIORITY 0 /* Driver */
87 #define GPIO_APP_PRIORITY 1 /* Application */
88 #define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
90 /* GPIO pull up/down */
94 /* GPIO event regtype */
95 #define GPIO_REGEVT 0 /* GPIO register event */
96 #define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
97 #define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
100 #define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
102 /* SI routine enumeration: to be used by update function with multiple hooks */
103 #define SI_DOATTACH 1
107 #define ISSIM_ENAB(sih) 0
109 /* PMU clock/power control */
110 #if defined(BCMPMUCTL)
111 #define PMUCTL_ENAB(sih) (BCMPMUCTL)
113 #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
116 /* chipcommon clock/power control (exclusive with PMU's) */
117 #if defined(BCMPMUCTL) && BCMPMUCTL
118 #define CCCTL_ENAB(sih) (0)
119 #define CCPLL_ENAB(sih) (0)
121 #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
122 #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
125 typedef void (*gpio_handler_t) (u32 stat, void *arg);
127 /* External PA enable mask */
128 #define GPIO_CTRL_EPA_EN_MASK 0x40
130 /* === exported functions === */
131 extern si_t *si_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
132 void *sdh, char **vars, uint *varsz);
134 extern void si_detach(si_t *sih);
135 extern bool si_pci_war16165(si_t *sih);
137 extern uint si_coreid(si_t *sih);
138 extern uint si_flag(si_t *sih);
139 extern uint si_coreidx(si_t *sih);
140 extern uint si_corerev(si_t *sih);
141 extern void *si_osh(si_t *sih);
142 extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
144 extern void si_write_wrapperreg(si_t *sih, u32 offset, u32 val);
145 extern u32 si_core_cflags(si_t *sih, u32 mask, u32 val);
146 extern u32 si_core_sflags(si_t *sih, u32 mask, u32 val);
147 extern bool si_iscoreup(si_t *sih);
148 extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
150 extern void *si_setcoreidx(si_t *sih, uint coreidx);
152 extern void *si_setcore(si_t *sih, uint coreid, uint coreunit);
153 extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx,
155 extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
156 extern void si_core_reset(si_t *sih, u32 bits, u32 resetbits);
157 extern void si_core_disable(si_t *sih, u32 bits);
158 extern u32 si_alp_clock(si_t *sih);
159 extern u32 si_ilp_clock(si_t *sih);
160 extern void si_pci_setup(si_t *sih, uint coremask);
161 extern void si_setint(si_t *sih, int siflag);
162 extern bool si_backplane64(si_t *sih);
163 extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn,
164 void *intrsrestore_fn,
165 void *intrsenabled_fn, void *intr_arg);
166 extern void si_deregister_intr_callback(si_t *sih);
167 extern void si_clkctl_init(si_t *sih);
168 extern u16 si_clkctl_fast_pwrup_delay(si_t *sih);
169 extern bool si_clkctl_cc(si_t *sih, uint mode);
170 extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
171 extern bool si_deviceremoved(si_t *sih);
172 extern u32 si_socram_size(si_t *sih);
174 extern void si_watchdog(si_t *sih, uint ticks);
175 extern u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val,
179 extern void si_sdio_init(si_t *sih);
182 #define si_eci(sih) 0
183 #define si_eci_init(sih) (0)
184 #define si_eci_notify_bt(sih, type, val) (0)
185 #define si_seci(sih) 0
186 static inline void *si_seci_init(si_t *sih, u8 use_seci)
192 extern bool si_is_otp_disabled(si_t *sih);
193 extern bool si_is_otp_powered(si_t *sih);
194 extern void si_otp_power(si_t *sih, bool on);
196 /* SPROM availability */
197 extern bool si_is_sprom_available(si_t *sih);
198 #ifdef SI_SPROM_PROBE
199 extern void si_sprom_init(si_t *sih);
200 #endif /* SI_SPROM_PROBE */
202 #define SI_ERROR(args)
205 #define SI_MSG(args) printf args
210 /* Define SI_VMSG to printf for verbose debugging, but don't check it in */
211 #define SI_VMSG(args)
213 #define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
215 typedef u32(*si_intrsoff_t) (void *intr_arg);
216 typedef void (*si_intrsrestore_t) (void *intr_arg, u32 arg);
217 typedef bool(*si_intrsenabled_t) (void *intr_arg);
219 typedef struct gpioh_item {
222 gpio_handler_t handler;
224 struct gpioh_item *next;
227 /* misc si info needed by some of the routines */
228 typedef struct si_info {
229 struct si_pub pub; /* back plane public state (must be first field) */
230 void *osh; /* osl os handle */
231 void *sdh; /* bcmsdh handle */
232 uint dev_coreid; /* the core provides driver functions */
233 void *intr_arg; /* interrupt callback function arg */
234 si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
235 si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
236 si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
238 void *pch; /* PCI/E core handle */
240 gpioh_item_t *gpioh_head; /* GPIO event handlers list */
242 bool memseg; /* flag to toggle MEM_SEG register */
247 void *curmap; /* current regs va */
248 void *regs[SI_MAXCORES]; /* other regs va */
250 uint curidx; /* current core index */
251 uint numcores; /* # discovered cores */
252 uint coreid[SI_MAXCORES]; /* id of each core */
253 u32 coresba[SI_MAXCORES]; /* backplane address of each core */
254 void *regs2[SI_MAXCORES]; /* va of each core second register set (usbh20) */
255 u32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */
256 u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
257 u32 coresba2_size[SI_MAXCORES]; /* second address space size */
259 void *curwrap; /* current wrapper va */
260 void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
261 u32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
263 u32 cia[SI_MAXCORES]; /* erom cia entry for each core */
264 u32 cib[SI_MAXCORES]; /* erom cia entry for each core */
265 u32 oob_router; /* oob router registers for axi */
268 #define SI_INFO(sih) (si_info_t *)sih
270 #define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
271 IS_ALIGNED((x), SI_CORE_SIZE))
272 #define GOODREGS(regs) ((regs) != NULL && IS_ALIGNED((unsigned long)(regs), SI_CORE_SIZE))
273 #define BADCOREADDR 0
274 #define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
275 #define NOREV -1 /* Invalid rev */
277 /* Newer chips can access PCI/PCIE and CC core without requiring to change
280 #define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
281 (((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13))
283 #define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
284 #define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
287 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts
288 * before after core switching to avoid invalid register accesss inside ISR.
290 #define INTR_OFF(si, intr_val) \
291 if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
292 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
293 #define INTR_RESTORE(si, intr_val) \
294 if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
295 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
297 /* dynamic clock control defines */
298 #define LPOMINFREQ 25000 /* low power oscillator min */
299 #define LPOMAXFREQ 43000 /* low power oscillator max */
300 #define XTALMINFREQ 19800000 /* 20 MHz - 1% */
301 #define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
302 #define PCIMINFREQ 25000000 /* 25 MHz */
303 #define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
305 #define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
306 #define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
308 #define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
309 ((si)->pub.buscoretype == PCI_CORE_ID))
310 #define PCIE(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
311 ((si)->pub.buscoretype == PCIE_CORE_ID))
312 #define PCI_FORCEHT(si) \
313 (PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))
315 /* GPIO Based LED powersave defines */
316 #define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
317 #define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
319 #ifndef DEFAULT_GPIOTIMERVAL
320 #define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
324 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
325 * The returned path is NULL terminated and has trailing '/'.
326 * Return 0 on success, nonzero otherwise.
328 extern int si_devpath(si_t *sih, char *path, int size);
329 /* Read variable with prepending the devpath to the name */
330 extern char *si_getdevpathvar(si_t *sih, const char *name);
331 extern int si_getdevpathintvar(si_t *sih, const char *name);
333 extern void si_war42780_clkreq(si_t *sih, bool clkreq);
334 extern void si_pci_sleep(si_t *sih);
335 extern void si_pci_down(si_t *sih);
336 extern void si_pci_up(si_t *sih);
337 extern void si_pcie_extendL1timer(si_t *sih, bool extend);
338 extern int si_pci_fixcfg(si_t *sih);
340 extern void si_chipcontrl_epa4331(si_t *sih, bool on);
341 /* Enable Ex-PA for 4313 */
342 extern void si_epa_4313war(si_t *sih);
344 char *si_getnvramflvar(si_t *sih, const char *name);
346 /* AMBA Interconnect exported externs */
347 extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
348 void *sdh, char **vars, uint *varsz);
349 extern si_t *ai_kattach(osl_t *osh);
350 extern void ai_scan(si_t *sih, void *regs, uint devid);
352 extern uint ai_flag(si_t *sih);
353 extern void ai_setint(si_t *sih, int siflag);
354 extern uint ai_coreidx(si_t *sih);
355 extern uint ai_corevendor(si_t *sih);
356 extern uint ai_corerev(si_t *sih);
357 extern bool ai_iscoreup(si_t *sih);
358 extern void *ai_setcoreidx(si_t *sih, uint coreidx);
359 extern u32 ai_core_cflags(si_t *sih, u32 mask, u32 val);
360 extern void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val);
361 extern u32 ai_core_sflags(si_t *sih, u32 mask, u32 val);
362 extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
364 extern void ai_core_reset(si_t *sih, u32 bits, u32 resetbits);
365 extern void ai_core_disable(si_t *sih, u32 bits);
366 extern int ai_numaddrspaces(si_t *sih);
367 extern u32 ai_addrspace(si_t *sih, uint asidx);
368 extern u32 ai_addrspacesize(si_t *sih, uint asidx);
369 extern void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val);
372 #define si_setcoreidx(sih, idx) sb_setcoreidx(sih, idx)
373 #define si_coreid(sih) sb_coreid(sih)
374 #define si_corerev(sih) sb_corerev(sih)
377 #endif /* _siutils_h_ */