drivers/staging/brcm80211/brcmsmac/wlc_bmac.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17
  18 #include <linux/kernel.h>
  19 #include <wlc_cfg.h>
  20 #include <linux/module.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <bcmdefs.h>
  25 #include <osl.h>
  26 #include <proto/802.11.h>
  27 #include <bcmwifi.h>
  28 #include <bcmutils.h>
  29 #include <siutils.h>
  30 #include <bcmendian.h>
  31 #include <wlioctl.h>
  32 #include <sbconfig.h>
  33 #include <sbchipc.h>
  34 #include <pcicfg.h>
  35 #include <sbhndpio.h>
  36 #include <sbhnddma.h>
  37 #include <hnddma.h>
  38 #include <hndpmu.h>
  39 #include <d11.h>
  40 #include <wlc_rate.h>
  41 #include <wlc_pub.h>
  42 #include <wlc_channel.h>
  43 #include <bcmsrom.h>
  44 #include <wlc_key.h>
  45 #include <bcmdevs.h>
  46 /* BMAC_NOTE: a WLC_HIGH compile include of wlc.h adds in more structures and type
  47  * dependencies. Need to include these to files to allow a clean include of wlc.h
  48  * with WLC_HIGH defined.
  49  * At some point we may be able to skip the include of wlc.h and instead just
  50  * define a stub wlc_info and band struct to allow rpc calls to get the rpc handle.
  51  */
  52 #include <wlc_event.h>
  53 #include <wlc_mac80211.h>
  54 #include <wlc_bmac.h>
  55 #include <wlc_phy_shim.h>
  56 #include <wlc_phy_hal.h>
  57 #include <wl_export.h>
  58 #include "wl_ucode.h"
  59 #include "d11ucode_ext.h"
  60 #include <bcmotp.h>
  61
  62 /* BMAC_NOTE: With WLC_HIGH defined, some fns in this file make calls to high level
  63  * functions defined in the headers below. We should be eliminating those calls and
  64  * will be able to delete these include lines.
  65  */
  66 #include <wlc_antsel.h>
  67
  68 #include <pcie_core.h>
  69
  70 #include <wlc_alloc.h>
  71 #include <wl_dbg.h>
  72
  73 #define TIMER_INTERVAL_WATCHDOG_BMAC    1000    /* watchdog timer, in unit of ms */
  74
  75 #define SYNTHPU_DLY_APHY_US     3700    /* a phy synthpu_dly time in us */
  76 #define SYNTHPU_DLY_BPHY_US     1050    /* b/g phy synthpu_dly time in us, default */
  77 #define SYNTHPU_DLY_NPHY_US     2048    /* n phy REV3 synthpu_dly time in us, default */
  78 #define SYNTHPU_DLY_LPPHY_US    300     /* lpphy synthpu_dly time in us */
  79
  80 #define SYNTHPU_DLY_PHY_US_QT   100     /* QT synthpu_dly time in us */
  81
  82 #ifndef BMAC_DUP_TO_REMOVE
  83 #define WLC_RM_WAIT_TX_SUSPEND          4       /* Wait Tx Suspend */
  84
  85 #define ANTCNT                  10      /* vanilla M_MAX_ANTCNT value */
  86
  87 #endif                          /* BMAC_DUP_TO_REMOVE */
  88
  89 #define DMAREG(wlc_hw, direction, fifonum) \
  90         ((direction == DMA_TX) ? \
  91                 (void *)&(wlc_hw->regs->fifo.f64regs[fifonum].dmaxmt) : \
  92                 (void *)&(wlc_hw->regs->fifo.f64regs[fifonum].dmarcv))
  93
  94 /*
  95  * The following table lists the buffer memory allocated to xmt fifos in HW.
  96  * the size is in units of 256bytes(one block), total size is HW dependent
  97  * ucode has default fifo partition, sw can overwrite if necessary
  98  *
  99  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
 100  * the twiki is updated before making changes.
 101  */
 102
 103 #define XMTFIFOTBL_STARTREV     20      /* Starting corerev for the fifo size table */
 104
 105 static u16 xmtfifo_sz[][NFIFO] = {
 106         {20, 192, 192, 21, 17, 5},      /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
 107         {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
 108         {20, 192, 192, 21, 17, 5},      /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
 109         {20, 192, 192, 21, 17, 5},      /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
 110         {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
 111 };
 112
 113 static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
 114 static void wlc_coreinit(struct wlc_info *wlc);
 115
 116 /* used by wlc_wakeucode_init() */
 117 static void wlc_write_inits(struct wlc_hw_info *wlc_hw, const d11init_t *inits);
 118 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
 119                             const uint nbytes);
 120 static void wlc_ucode_download(struct wlc_hw_info *wlc);
 121 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
 122
 123 /* used by wlc_dpc() */
 124 static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
 125                                 u32 s2);
 126 static bool wlc_bmac_txstatus_corerev4(struct wlc_hw_info *wlc);
 127 static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
 128 static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
 129
 130 /* used by wlc_down() */
 131 static void wlc_flushqueues(struct wlc_info *wlc);
 132
 133 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
 134 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
 135 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
 136
 137 /* Low Level Prototypes */
 138 static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 139                                    u32 sel);
 140 static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
 141                                   u16 v, u32 sel);
 142 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
 143 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
 144 static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
 145 static bool wlc_validboardtype(struct wlc_hw_info *wlc);
 146 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
 147 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
 148 static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
 149 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
 150 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
 151 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
 152 static u32 wlc_wlintrsoff(struct wlc_info *wlc);
 153 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
 154 static void wlc_gpio_init(struct wlc_info *wlc);
 155 static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
 156                                       int len);
 157 static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
 158                                       int len);
 159 static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
 160 static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
 161 static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
 162                              chanspec_t chanspec);
 163 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 164                                         bool shortslot);
 165 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
 166 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
 167                                              u8 rate);
 168
 169 /* === Low Level functions === */
 170
 171 void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
 172 {
 173         wlc_hw->shortslot = shortslot;
 174
 175         if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
 176                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
 177                 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
 178                 wlc_enable_mac(wlc_hw->wlc);
 179         }
 180 }
 181
 182 /*
 183  * Update the slot timing for standard 11b/g (20us slots)
 184  * or shortslot 11g (9us slots)
 185  * The PSM needs to be suspended for this call.
 186  */
 187 static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
 188                                         bool shortslot)
 189 {
 190         struct osl_info *osh;
 191         d11regs_t *regs;
 192
 193         osh = wlc_hw->osh;
 194         regs = wlc_hw->regs;
 195
 196         if (shortslot) {
 197                 /* 11g short slot: 11a timing */
 198                 W_REG(osh, &regs->ifs_slot, 0x0207);    /* APHY_SLOT_TIME */
 199                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 200         } else {
 201                 /* 11g long slot: 11b timing */
 202                 W_REG(osh, &regs->ifs_slot, 0x0212);    /* BPHY_SLOT_TIME */
 203                 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 204         }
 205 }
 206
 207 static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
 208 {
 209         /* init microcode host flags */
 210         wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 211
 212         /* do band-specific ucode IHR, SHM, and SCR inits */
 213         if (D11REV_IS(wlc_hw->corerev, 23)) {
 214                 if (WLCISNPHY(wlc_hw->band)) {
 215                         wlc_write_inits(wlc_hw, d11n0bsinitvals16);
 216                 } else {
 217                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
 218                                  __func__, wlc_hw->unit, wlc_hw->corerev);
 219                 }
 220         } else {
 221                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 222                         if (WLCISLCNPHY(wlc_hw->band)) {
 223                                 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
 224                         } else
 225                                 WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
 226                                          __func__, wlc_hw->unit,
 227                                          wlc_hw->corerev);
 228                 } else {
 229                         WL_ERROR("%s: wl%d: unsupported corerev %d\n",
 230                                  __func__, wlc_hw->unit, wlc_hw->corerev);
 231                 }
 232         }
 233 }
 234
 235 /* switch to new band but leave it inactive */
 236 static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
 237 {
 238         struct wlc_hw_info *wlc_hw = wlc->hw;
 239         u32 macintmask;
 240         u32 tmp;
 241
 242         WL_TRACE("wl%d: wlc_setband_inact\n", wlc_hw->unit);
 243
 244         ASSERT(bandunit != wlc_hw->band->bandunit);
 245         ASSERT(si_iscoreup(wlc_hw->sih));
 246         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
 247                0);
 248
 249         /* disable interrupts */
 250         macintmask = wl_intrsoff(wlc->wl);
 251
 252         /* radio off */
 253         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 254
 255         ASSERT(wlc_hw->clk);
 256
 257         if (D11REV_LT(wlc_hw->corerev, 17))
 258                 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
 259
 260         wlc_bmac_core_phy_clk(wlc_hw, OFF);
 261
 262         wlc_setxband(wlc_hw, bandunit);
 263
 264         return macintmask;
 265 }
 266
 267 /* Process received frames */
 268 /*
 269  * Return true if more frames need to be processed. false otherwise.
 270  * Param 'bound' indicates max. # frames to process before break out.
 271  */
 272 static bool BCMFASTPATH
 273 wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
 274 {
 275         struct sk_buff *p;
 276         struct sk_buff *head = NULL;
 277         struct sk_buff *tail = NULL;
 278         uint n = 0;
 279         uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
 280         u32 tsf_h, tsf_l;
 281         wlc_d11rxhdr_t *wlc_rxhdr = NULL;
 282
 283         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
 284         /* gather received frames */
 285         while ((p = dma_rx(wlc_hw->di[fifo]))) {
 286
 287                 if (!tail)
 288                         head = tail = p;
 289                 else {
 290                         tail->prev = p;
 291                         tail = p;
 292                 }
 293
 294                 /* !give others some time to run! */
 295                 if (++n >= bound_limit)
 296                         break;
 297         }
 298
 299         /* get the TSF REG reading */
 300         wlc_bmac_read_tsf(wlc_hw, &tsf_l, &tsf_h);
 301
 302         /* post more rbufs */
 303         dma_rxfill(wlc_hw->di[fifo]);
 304
 305         /* process each frame */
 306         while ((p = head) != NULL) {
 307                 head = head->prev;
 308                 p->prev = NULL;
 309
 310                 /* record the tsf_l in wlc_rxd11hdr */
 311                 wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
 312                 wlc_rxhdr->tsf_l = htol32(tsf_l);
 313
 314                 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
 315                 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
 316
 317                 wlc_recv(wlc_hw->wlc, p);
 318         }
 319
 320         return n >= bound_limit;
 321 }
 322
 323 /* second-level interrupt processing
 324  *   Return true if another dpc needs to be re-scheduled. false otherwise.
 325  *   Param 'bounded' indicates if applicable loops should be bounded.
 326  */
 327 bool BCMFASTPATH wlc_dpc(struct wlc_info *wlc, bool bounded)
 328 {
 329         u32 macintstatus;
 330         struct wlc_hw_info *wlc_hw = wlc->hw;
 331         d11regs_t *regs = wlc_hw->regs;
 332         bool fatal = false;
 333
 334         if (DEVICEREMOVED(wlc)) {
 335                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
 336                 wl_down(wlc->wl);
 337                 return false;
 338         }
 339
 340         /* grab and clear the saved software intstatus bits */
 341         macintstatus = wlc->macintstatus;
 342         wlc->macintstatus = 0;
 343
 344         WL_TRACE("wl%d: wlc_dpc: macintstatus 0x%x\n",
 345                  wlc_hw->unit, macintstatus);
 346
 347         if (macintstatus & MI_PRQ) {
 348                 /* Process probe request FIFO */
 349                 ASSERT(0 && "PRQ Interrupt in non-MBSS");
 350         }
 351
 352         /* BCN template is available */
 353         /* ZZZ: Use AP_ACTIVE ? */
 354         if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub) || wlc->aps_associated)
 355             && (macintstatus & MI_BCNTPL)) {
 356                 wlc_update_beacon(wlc);
 357         }
 358
 359         /* PMQ entry addition */
 360         if (macintstatus & MI_PMQ) {
 361         }
 362
 363         /* tx status */
 364         if (macintstatus & MI_TFS) {
 365                 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
 366                         wlc->macintstatus |= MI_TFS;
 367                 if (fatal) {
 368                         WL_ERROR("MI_TFS: fatal\n");
 369                         goto fatal;
 370                 }
 371         }
 372
 373         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
 374                 wlc_tbtt(wlc, regs);
 375
 376         /* ATIM window end */
 377         if (macintstatus & MI_ATIMWINEND) {
 378                 WL_TRACE("wlc_isr: end of ATIM window\n");
 379
 380                 OR_REG(wlc_hw->osh, &regs->maccommand, wlc->qvalid);
 381                 wlc->qvalid = 0;
 382         }
 383
 384         /* phy tx error */
 385         if (macintstatus & MI_PHYTXERR) {
 386                 WLCNTINCR(wlc->pub->_cnt->txphyerr);
 387         }
 388
 389         /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
 390         if (macintstatus & MI_DMAINT) {
 391                 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
 392                         wlc->macintstatus |= MI_DMAINT;
 393                 }
 394         }
 395
 396         /* TX FIFO suspend/flush completion */
 397         if (macintstatus & MI_TXSTOP) {
 398                 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
 399                         /*      WL_ERROR("dpc: fifo_suspend_comlete\n"); */
 400                 }
 401         }
 402
 403         /* noise sample collected */
 404         if (macintstatus & MI_BG_NOISE) {
 405                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
 406         }
 407
 408         if (macintstatus & MI_GP0) {
 409                 WL_ERROR("wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n",
 410                          wlc_hw->unit, wlc_hw->now);
 411
 412                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
 413                                         __func__, wlc_hw->sih->chip,
 414                                         wlc_hw->sih->chiprev);
 415
 416                 WLCNTINCR(wlc->pub->_cnt->psmwds);
 417
 418                 /* big hammer */
 419                 wl_init(wlc->wl);
 420         }
 421
 422         /* gptimer timeout */
 423         if (macintstatus & MI_TO) {
 424                 W_REG(wlc_hw->osh, &regs->gptimer, 0);
 425         }
 426
 427         if (macintstatus & MI_RFDISABLE) {
 428                 WL_TRACE("wl%d: BMAC Detected a change on the RF Disable Input\n", wlc_hw->unit);
 429
 430                 WLCNTINCR(wlc->pub->_cnt->rfdisable);
 431                 wl_rfkill_set_hw_state(wlc->wl);
 432         }
 433
 434         /* send any enq'd tx packets. Just makes sure to jump start tx */
 435         if (!pktq_empty(&wlc->active_queue->q))
 436                 wlc_send_q(wlc, wlc->active_queue);
 437
 438         ASSERT(wlc_ps_check(wlc));
 439
 440         /* make sure the bound indication and the implementation are in sync */
 441         ASSERT(bounded == true || wlc->macintstatus == 0);
 442
 443         /* it isn't done and needs to be resched if macintstatus is non-zero */
 444         return wlc->macintstatus != 0;
 445
 446  fatal:
 447         wl_init(wlc->wl);
 448         return wlc->macintstatus != 0;
 449 }
 450
 451 /* common low-level watchdog code */
 452 void wlc_bmac_watchdog(void *arg)
 453 {
 454         struct wlc_info *wlc = (struct wlc_info *) arg;
 455         struct wlc_hw_info *wlc_hw = wlc->hw;
 456
 457         WL_TRACE("wl%d: wlc_bmac_watchdog\n", wlc_hw->unit);
 458
 459         if (!wlc_hw->up)
 460                 return;
 461
 462         /* increment second count */
 463         wlc_hw->now++;
 464
 465         /* Check for FIFO error interrupts */
 466         wlc_bmac_fifoerrors(wlc_hw);
 467
 468         /* make sure RX dma has buffers */
 469         dma_rxfill(wlc->hw->di[RX_FIFO]);
 470         if (D11REV_IS(wlc_hw->corerev, 4)) {
 471                 dma_rxfill(wlc->hw->di[RX_TXSTATUS_FIFO]);
 472         }
 473
 474         wlc_phy_watchdog(wlc_hw->band->pi);
 475 }
 476
 477 void
 478 wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
 479                       bool mute, struct txpwr_limits *txpwr)
 480 {
 481         uint bandunit;
 482
 483         WL_TRACE("wl%d: wlc_bmac_set_chanspec 0x%x\n",
 484                  wlc_hw->unit, chanspec);
 485
 486         wlc_hw->chanspec = chanspec;
 487
 488         /* Switch bands if necessary */
 489         if (NBANDS_HW(wlc_hw) > 1) {
 490                 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
 491                 if (wlc_hw->band->bandunit != bandunit) {
 492                         /* wlc_bmac_setband disables other bandunit,
 493                          *  use light band switch if not up yet
 494                          */
 495                         if (wlc_hw->up) {
 496                                 wlc_phy_chanspec_radio_set(wlc_hw->
 497                                                            bandstate[bandunit]->
 498                                                            pi, chanspec);
 499                                 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
 500                         } else {
 501                                 wlc_setxband(wlc_hw, bandunit);
 502                         }
 503                 }
 504         }
 505
 506         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
 507
 508         if (!wlc_hw->up) {
 509                 if (wlc_hw->clk)
 510                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
 511                                                   chanspec);
 512                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
 513         } else {
 514                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
 515                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
 516
 517                 /* Update muting of the channel */
 518                 wlc_bmac_mute(wlc_hw, mute, 0);
 519         }
 520 }
 521
 522 int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
 523 {
 524         state->machwcap = wlc_hw->machwcap;
 525
 526         return 0;
 527 }
 528
 529 static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
 530 {
 531         uint i;
 532         char name[8];
 533         /* ucode host flag 2 needed for pio mode, independent of band and fifo */
 534         u16 pio_mhf2 = 0;
 535         struct wlc_hw_info *wlc_hw = wlc->hw;
 536         uint unit = wlc_hw->unit;
 537         wlc_tunables_t *tune = wlc->pub->tunables;
 538
 539         /* name and offsets for dma_attach */
 540         snprintf(name, sizeof(name), "wl%d", unit);
 541
 542         if (wlc_hw->di[0] == 0) {       /* Init FIFOs */
 543                 uint addrwidth;
 544                 int dma_attach_err = 0;
 545                 struct osl_info *osh = wlc_hw->osh;
 546
 547                 /* Find out the DMA addressing capability and let OS know
 548                  * All the channels within one DMA core have 'common-minimum' same
 549                  * capability
 550                  */
 551                 addrwidth =
 552                     dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
 553
 554                 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
 555                         WL_ERROR("wl%d: wlc_attach: alloc_dma_resources failed\n",
 556                                  unit);
 557                         return false;
 558                 }
 559
 560                 /*
 561                  * FIFO 0
 562                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
 563                  * RX: RX_FIFO (RX data packets)
 564                  */
 565                 ASSERT(TX_AC_BK_FIFO == 0);
 566                 ASSERT(RX_FIFO == 0);
 567                 wlc_hw->di[0] = dma_attach(osh, name, wlc_hw->sih,
 568                                            (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
 569                                             NULL), DMAREG(wlc_hw, DMA_RX, 0),
 570                                            (wme ? tune->ntxd : 0), tune->nrxd,
 571                                            tune->rxbufsz, -1, tune->nrxbufpost,
 572                                            WL_HWRXOFF, &wl_msg_level);
 573                 dma_attach_err |= (NULL == wlc_hw->di[0]);
 574
 575                 /*
 576                  * FIFO 1
 577                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
 578                  *   (legacy) TX_DATA_FIFO (TX data packets)
 579                  * RX: UNUSED
 580                  */
 581                 ASSERT(TX_AC_BE_FIFO == 1);
 582                 ASSERT(TX_DATA_FIFO == 1);
 583                 wlc_hw->di[1] = dma_attach(osh, name, wlc_hw->sih,
 584                                            DMAREG(wlc_hw, DMA_TX, 1), NULL,
 585                                            tune->ntxd, 0, 0, -1, 0, 0,
 586                                            &wl_msg_level);
 587                 dma_attach_err |= (NULL == wlc_hw->di[1]);
 588
 589                 /*
 590                  * FIFO 2
 591                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
 592                  * RX: UNUSED
 593                  */
 594                 ASSERT(TX_AC_VI_FIFO == 2);
 595                 wlc_hw->di[2] = dma_attach(osh, name, wlc_hw->sih,
 596                                            DMAREG(wlc_hw, DMA_TX, 2), NULL,
 597                                            tune->ntxd, 0, 0, -1, 0, 0,
 598                                            &wl_msg_level);
 599                 dma_attach_err |= (NULL == wlc_hw->di[2]);
 600                 /*
 601                  * FIFO 3
 602                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
 603                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
 604                  * RX: RX_TXSTATUS_FIFO (transmit-status packets)
 605                  *      for corerev < 5 only
 606                  */
 607                 ASSERT(TX_AC_VO_FIFO == 3);
 608                 ASSERT(TX_CTL_FIFO == 3);
 609                 if (D11REV_IS(wlc_hw->corerev, 4)) {
 610                         ASSERT(RX_TXSTATUS_FIFO == 3);
 611                         wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
 612                                                    DMAREG(wlc_hw, DMA_TX, 3),
 613                                                    DMAREG(wlc_hw, DMA_RX, 3),
 614                                                    tune->ntxd, tune->nrxd,
 615                                                    sizeof(tx_status_t), -1,
 616                                                    tune->nrxbufpost, 0,
 617                                                    &wl_msg_level);
 618                         dma_attach_err |= (NULL == wlc_hw->di[3]);
 619                 } else {
 620                         wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
 621                                                    DMAREG(wlc_hw, DMA_TX, 3),
 622                                                    NULL, tune->ntxd, 0, 0, -1,
 623                                                    0, 0, &wl_msg_level);
 624                         dma_attach_err |= (NULL == wlc_hw->di[3]);
 625                 }
 626 /* Cleaner to leave this as if with AP defined */
 627
 628                 if (dma_attach_err) {
 629                         WL_ERROR("wl%d: wlc_attach: dma_attach failed\n", unit);
 630                         return false;
 631                 }
 632
 633                 /* get pointer to dma engine tx flow control variable */
 634                 for (i = 0; i < NFIFO; i++)
 635                         if (wlc_hw->di[i])
 636                                 wlc_hw->txavail[i] =
 637                                     (uint *) dma_getvar(wlc_hw->di[i],
 638                                                         "&txavail");
 639         }
 640
 641         /* initial ucode host flags */
 642         wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
 643
 644         return true;
 645 }
 646
 647 static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
 648 {
 649         uint j;
 650
 651         for (j = 0; j < NFIFO; j++) {
 652                 if (wlc_hw->di[j]) {
 653                         dma_detach(wlc_hw->di[j]);
 654                         wlc_hw->di[j] = NULL;
 655                 }
 656         }
 657 }
 658
 659 /* low level attach
 660  *    run backplane attach, init nvram
 661  *    run phy attach
 662  *    initialize software state for each core and band
 663  *    put the whole chip in reset(driver down state), no clock
 664  */
 665 int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
 666                     bool piomode, struct osl_info *osh, void *regsva,
 667                     uint bustype, void *btparam)
 668 {
 669         struct wlc_hw_info *wlc_hw;
 670         d11regs_t *regs;
 671         char *macaddr = NULL;
 672         char *vars;
 673         uint err = 0;
 674         uint j;
 675         bool wme = false;
 676         shared_phy_params_t sha_params;
 677
 678         WL_TRACE("wl%d: wlc_bmac_attach: vendor 0x%x device 0x%x\n",
 679                  unit, vendor, device);
 680
 681         ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF);
 682
 683         wme = true;
 684
 685         wlc_hw = wlc->hw;
 686         wlc_hw->wlc = wlc;
 687         wlc_hw->unit = unit;
 688         wlc_hw->osh = osh;
 689         wlc_hw->band = wlc_hw->bandstate[0];
 690         wlc_hw->_piomode = piomode;
 691
 692         /* populate struct wlc_hw_info with default values  */
 693         wlc_bmac_info_init(wlc_hw);
 694
 695         /*
 696          * Do the hardware portion of the attach.
 697          * Also initialize software state that depends on the particular hardware
 698          * we are running.
 699          */
 700         wlc_hw->sih = si_attach((uint) device, osh, regsva, bustype, btparam,
 701                                 &wlc_hw->vars, &wlc_hw->vars_size);
 702         if (wlc_hw->sih == NULL) {
 703                 WL_ERROR("wl%d: wlc_bmac_attach: si_attach failed\n", unit);
 704                 err = 11;
 705                 goto fail;
 706         }
 707         vars = wlc_hw->vars;
 708
 709         /*
 710          * Get vendid/devid nvram overwrites, which could be different
 711          * than those the BIOS recognizes for devices on PCMCIA_BUS,
 712          * SDIO_BUS, and SROMless devices on PCI_BUS.
 713          */
 714 #ifdef BCMBUSTYPE
 715         bustype = BCMBUSTYPE;
 716 #endif
 717         if (bustype != SI_BUS) {
 718                 char *var;
 719
 720                 var = getvar(vars, "vendid");
 721                 if (var) {
 722                         vendor = (u16) simple_strtoul(var, NULL, 0);
 723                         WL_ERROR("Overriding vendor id = 0x%x\n", vendor);
 724                 }
 725                 var = getvar(vars, "devid");
 726                 if (var) {
 727                         u16 devid = (u16) simple_strtoul(var, NULL, 0);
 728                         if (devid != 0xffff) {
 729                                 device = devid;
 730                                 WL_ERROR("Overriding device id = 0x%x\n",
 731                                          device);
 732                         }
 733                 }
 734
 735                 /* verify again the device is supported */
 736                 if (!wlc_chipmatch(vendor, device)) {
 737                         WL_ERROR("wl%d: wlc_bmac_attach: Unsupported vendor/device (0x%x/0x%x)\n",
 738                                  unit, vendor, device);
 739                         err = 12;
 740                         goto fail;
 741                 }
 742         }
 743
 744         wlc_hw->vendorid = vendor;
 745         wlc_hw->deviceid = device;
 746
 747         /* set bar0 window to point at D11 core */
 748         wlc_hw->regs = (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID, 0);
 749         wlc_hw->corerev = si_corerev(wlc_hw->sih);
 750
 751         regs = wlc_hw->regs;
 752
 753         wlc->regs = wlc_hw->regs;
 754
 755         /* validate chip, chiprev and corerev */
 756         if (!wlc_isgoodchip(wlc_hw)) {
 757                 err = 13;
 758                 goto fail;
 759         }
 760
 761         /* initialize power control registers */
 762         si_clkctl_init(wlc_hw->sih);
 763
 764         /* request fastclock and force fastclock for the rest of attach
 765          * bring the d11 core out of reset.
 766          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
 767          *   But it will be called again inside wlc_corereset, after d11 is out of reset.
 768          */
 769         wlc_clkctl_clk(wlc_hw, CLK_FAST);
 770         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
 771
 772         if (!wlc_bmac_validate_chip_access(wlc_hw)) {
 773                 WL_ERROR("wl%d: wlc_bmac_attach: validate_chip_access failed\n",
 774                          unit);
 775                 err = 14;
 776                 goto fail;
 777         }
 778
 779         /* get the board rev, used just below */
 780         j = getintvar(vars, "boardrev");
 781         /* promote srom boardrev of 0xFF to 1 */
 782         if (j == BOARDREV_PROMOTABLE)
 783                 j = BOARDREV_PROMOTED;
 784         wlc_hw->boardrev = (u16) j;
 785         if (!wlc_validboardtype(wlc_hw)) {
 786                 WL_ERROR("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n",
 787                          unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
 788                 err = 15;
 789                 goto fail;
 790         }
 791         wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
 792         wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
 793         wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
 794
 795         if (D11REV_LE(wlc_hw->corerev, 4)
 796             || (wlc_hw->boardflags & BFL_NOPLLDOWN))
 797                 wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
 798
 799         if ((wlc_hw->sih->bustype == PCI_BUS)
 800             && (si_pci_war16165(wlc_hw->sih)))
 801                 wlc->war16165 = true;
 802
 803         /* check device id(srom, nvram etc.) to set bands */
 804         if (wlc_hw->deviceid == BCM43224_D11N_ID) {
 805                 /* Dualband boards */
 806                 wlc_hw->_nbands = 2;
 807         } else
 808                 wlc_hw->_nbands = 1;
 809
 810         if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
 811                 wlc_hw->_nbands = 1;
 812
 813         /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
 814          * init of these values
 815          */
 816         wlc->vendorid = wlc_hw->vendorid;
 817         wlc->deviceid = wlc_hw->deviceid;
 818         wlc->pub->sih = wlc_hw->sih;
 819         wlc->pub->corerev = wlc_hw->corerev;
 820         wlc->pub->sromrev = wlc_hw->sromrev;
 821         wlc->pub->boardrev = wlc_hw->boardrev;
 822         wlc->pub->boardflags = wlc_hw->boardflags;
 823         wlc->pub->boardflags2 = wlc_hw->boardflags2;
 824         wlc->pub->_nbands = wlc_hw->_nbands;
 825
 826         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
 827
 828         if (wlc_hw->physhim == NULL) {
 829                 WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_shim_attach failed\n",
 830                          unit);
 831                 err = 25;
 832                 goto fail;
 833         }
 834
 835         /* pass all the parameters to wlc_phy_shared_attach in one struct */
 836         sha_params.osh = osh;
 837         sha_params.sih = wlc_hw->sih;
 838         sha_params.physhim = wlc_hw->physhim;
 839         sha_params.unit = unit;
 840         sha_params.corerev = wlc_hw->corerev;
 841         sha_params.vars = vars;
 842         sha_params.vid = wlc_hw->vendorid;
 843         sha_params.did = wlc_hw->deviceid;
 844         sha_params.chip = wlc_hw->sih->chip;
 845         sha_params.chiprev = wlc_hw->sih->chiprev;
 846         sha_params.chippkg = wlc_hw->sih->chippkg;
 847         sha_params.sromrev = wlc_hw->sromrev;
 848         sha_params.boardtype = wlc_hw->sih->boardtype;
 849         sha_params.boardrev = wlc_hw->boardrev;
 850         sha_params.boardvendor = wlc_hw->sih->boardvendor;
 851         sha_params.boardflags = wlc_hw->boardflags;
 852         sha_params.boardflags2 = wlc_hw->boardflags2;
 853         sha_params.bustype = wlc_hw->sih->bustype;
 854         sha_params.buscorerev = wlc_hw->sih->buscorerev;
 855
 856         /* alloc and save pointer to shared phy state area */
 857         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
 858         if (!wlc_hw->phy_sh) {
 859                 err = 16;
 860                 goto fail;
 861         }
 862
 863         /* initialize software state for each core and band */
 864         for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
 865                 /*
 866                  * band0 is always 2.4Ghz
 867                  * band1, if present, is 5Ghz
 868                  */
 869
 870                 /* So if this is a single band 11a card, use band 1 */
 871                 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
 872                         j = BAND_5G_INDEX;
 873
 874                 wlc_setxband(wlc_hw, j);
 875
 876                 wlc_hw->band->bandunit = j;
 877                 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 878                 wlc->band->bandunit = j;
 879                 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
 880                 wlc->core->coreidx = si_coreidx(wlc_hw->sih);
 881
 882                 if (D11REV_GE(wlc_hw->corerev, 13)) {
 883                         wlc_hw->machwcap = R_REG(wlc_hw->osh, &regs->machwcap);
 884                         wlc_hw->machwcap_backup = wlc_hw->machwcap;
 885                 }
 886
 887                 /* init tx fifo size */
 888                 ASSERT((wlc_hw->corerev - XMTFIFOTBL_STARTREV) <
 889                        ARRAY_SIZE(xmtfifo_sz));
 890                 wlc_hw->xmtfifo_sz =
 891                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
 892
 893                 /* Get a phy for this band */
 894                 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
 895                         (void *)regs, wlc_bmac_bandtype(wlc_hw), vars);
 896                 if (wlc_hw->band->pi == NULL) {
 897                         WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_attach failed\n",
 898                                  unit);
 899                         err = 17;
 900                         goto fail;
 901                 }
 902
 903                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
 904
 905                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
 906                                        &wlc_hw->band->phyrev,
 907                                        &wlc_hw->band->radioid,
 908                                        &wlc_hw->band->radiorev);
 909                 wlc_hw->band->abgphy_encore =
 910                     wlc_phy_get_encore(wlc_hw->band->pi);
 911                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
 912                 wlc_hw->band->core_flags =
 913                     wlc_phy_get_coreflags(wlc_hw->band->pi);
 914
 915                 /* verify good phy_type & supported phy revision */
 916                 if (WLCISNPHY(wlc_hw->band)) {
 917                         if (NCONF_HAS(wlc_hw->band->phyrev))
 918                                 goto good_phy;
 919                         else
 920                                 goto bad_phy;
 921                 } else if (WLCISLCNPHY(wlc_hw->band)) {
 922                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
 923                                 goto good_phy;
 924                         else
 925                                 goto bad_phy;
 926                 } else {
 927  bad_phy:
 928                         WL_ERROR("wl%d: wlc_bmac_attach: unsupported phy type/rev (%d/%d)\n",
 929                                  unit,
 930                                  wlc_hw->band->phytype, wlc_hw->band->phyrev);
 931                         err = 18;
 932                         goto fail;
 933                 }
 934
 935  good_phy:
 936                 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
 937                  * high level attach. However we can not make that change until all low level access
 938                  * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
 939                  * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
 940                  * low only init when all fns updated.
 941                  */
 942                 wlc->band->pi = wlc_hw->band->pi;
 943                 wlc->band->phytype = wlc_hw->band->phytype;
 944                 wlc->band->phyrev = wlc_hw->band->phyrev;
 945                 wlc->band->radioid = wlc_hw->band->radioid;
 946                 wlc->band->radiorev = wlc_hw->band->radiorev;
 947
 948                 /* default contention windows size limits */
 949                 wlc_hw->band->CWmin = APHY_CWMIN;
 950                 wlc_hw->band->CWmax = PHY_CWMAX;
 951
 952                 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
 953                         err = 19;
 954                         goto fail;
 955                 }
 956         }
 957
 958         /* disable core to match driver "down" state */
 959         wlc_coredisable(wlc_hw);
 960
 961         /* Match driver "down" state */
 962         if (wlc_hw->sih->bustype == PCI_BUS)
 963                 si_pci_down(wlc_hw->sih);
 964
 965         /* register sb interrupt callback functions */
 966         si_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
 967                                   (void *)wlc_wlintrsrestore, NULL, wlc);
 968
 969         /* turn off pll and xtal to match driver "down" state */
 970         wlc_bmac_xtal(wlc_hw, OFF);
 971
 972         /* *********************************************************************
 973          * The hardware is in the DOWN state at this point. D11 core
 974          * or cores are in reset with clocks off, and the board PLLs
 975          * are off if possible.
 976          *
 977          * Beyond this point, wlc->sbclk == false and chip registers
 978          * should not be touched.
 979          *********************************************************************
 980          */
 981
 982         /* init etheraddr state variables */
 983         macaddr = wlc_get_macaddr(wlc_hw);
 984         if (macaddr == NULL) {
 985                 WL_ERROR("wl%d: wlc_bmac_attach: macaddr not found\n", unit);
 986                 err = 21;
 987                 goto fail;
 988         }
 989         bcm_ether_atoe(macaddr, wlc_hw->etheraddr);
 990         if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
 991             is_zero_ether_addr(wlc_hw->etheraddr)) {
 992                 WL_ERROR("wl%d: wlc_bmac_attach: bad macaddr %s\n",
 993                          unit, macaddr);
 994                 err = 22;
 995                 goto fail;
 996         }
 997
 998         WL_ERROR("%s:: deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
 999                  __func__, wlc_hw->deviceid, wlc_hw->_nbands,
1000                  wlc_hw->sih->boardtype, macaddr);
1001
1002         return err;
1003
1004  fail:
1005         WL_ERROR("wl%d: wlc_bmac_attach: failed with err %d\n", unit, err);
1006         return err;
1007 }
1008
1009 /*
1010  * Initialize wlc_info default values ...
1011  * may get overrides later in this function
1012  *  BMAC_NOTES, move low out and resolve the dangling ones
1013  */
1014 void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
1015 {
1016         struct wlc_info *wlc = wlc_hw->wlc;
1017
1018         /* set default sw macintmask value */
1019         wlc->defmacintmask = DEF_MACINTMASK;
1020
1021         /* various 802.11g modes */
1022         wlc_hw->shortslot = false;
1023
1024         wlc_hw->SFBL = RETRY_SHORT_FB;
1025         wlc_hw->LFBL = RETRY_LONG_FB;
1026
1027         /* default mac retry limits */
1028         wlc_hw->SRL = RETRY_SHORT_DEF;
1029         wlc_hw->LRL = RETRY_LONG_DEF;
1030         wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
1031 }
1032
1033 /*
1034  * low level detach
1035  */
1036 int wlc_bmac_detach(struct wlc_info *wlc)
1037 {
1038         uint i;
1039         wlc_hwband_t *band;
1040         struct wlc_hw_info *wlc_hw = wlc->hw;
1041         int callbacks;
1042
1043         callbacks = 0;
1044
1045         if (wlc_hw->sih) {
1046                 /* detach interrupt sync mechanism since interrupt is disabled and per-port
1047                  * interrupt object may has been freed. this must be done before sb core switch
1048                  */
1049                 si_deregister_intr_callback(wlc_hw->sih);
1050
1051                 if (wlc_hw->sih->bustype == PCI_BUS)
1052                         si_pci_sleep(wlc_hw->sih);
1053         }
1054
1055         wlc_bmac_detach_dmapio(wlc_hw);
1056
1057         band = wlc_hw->band;
1058         for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
1059                 if (band->pi) {
1060                         /* Detach this band's phy */
1061                         wlc_phy_detach(band->pi);
1062                         band->pi = NULL;
1063                 }
1064                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1065         }
1066
1067         /* Free shared phy state */
1068         wlc_phy_shared_detach(wlc_hw->phy_sh);
1069
1070         wlc_phy_shim_detach(wlc_hw->physhim);
1071
1072         /* free vars */
1073         if (wlc_hw->vars) {
1074                 kfree(wlc_hw->vars);
1075                 wlc_hw->vars = NULL;
1076         }
1077
1078         if (wlc_hw->sih) {
1079                 si_detach(wlc_hw->sih);
1080                 wlc_hw->sih = NULL;
1081         }
1082
1083         return callbacks;
1084
1085 }
1086
1087 void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
1088 {
1089         WL_TRACE("wl%d: wlc_bmac_reset\n", wlc_hw->unit);
1090
1091         WLCNTINCR(wlc_hw->wlc->pub->_cnt->reset);
1092
1093         /* reset the core */
1094         if (!DEVICEREMOVED(wlc_hw->wlc))
1095                 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1096
1097         /* purge the dma rings */
1098         wlc_flushqueues(wlc_hw->wlc);
1099
1100         wlc_reset_bmac_done(wlc_hw->wlc);
1101 }
1102
1103 void
1104 wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
1105                           bool mute) {
1106         u32 macintmask;
1107         bool fastclk;
1108         struct wlc_info *wlc = wlc_hw->wlc;
1109
1110         WL_TRACE("wl%d: wlc_bmac_init\n", wlc_hw->unit);
1111
1112         /* request FAST clock if not on */
1113         fastclk = wlc_hw->forcefastclk;
1114         if (!fastclk)
1115                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1116
1117         /* disable interrupts */
1118         macintmask = wl_intrsoff(wlc->wl);
1119
1120         /* set up the specified band and chanspec */
1121         wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1122         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1123
1124         /* do one-time phy inits and calibration */
1125         wlc_phy_cal_init(wlc_hw->band->pi);
1126
1127         /* core-specific initialization */
1128         wlc_coreinit(wlc);
1129
1130         /* suspend the tx fifos and mute the phy for preism cac time */
1131         if (mute)
1132                 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1133
1134         /* band-specific inits */
1135         wlc_bmac_bsinit(wlc, chanspec);
1136
1137         /* restore macintmask */
1138         wl_intrsrestore(wlc->wl, macintmask);
1139
1140         /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1141          * and wlc_enable_mac() will clear this override bit.
1142          */
1143         mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1144
1145         /*
1146          * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1147          */
1148         wlc_hw->mac_suspend_depth = 1;
1149
1150         /* restore the clk */
1151         if (!fastclk)
1152                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1153 }
1154
1155 int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
1156 {
1157         uint coremask;
1158
1159         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1160
1161         ASSERT(wlc_hw->wlc->pub->hw_up && wlc_hw->wlc->macintmask == 0);
1162
1163         /*
1164          * Enable pll and xtal, initialize the power control registers,
1165          * and force fastclock for the remainder of wlc_up().
1166          */
1167         wlc_bmac_xtal(wlc_hw, ON);
1168         si_clkctl_init(wlc_hw->sih);
1169         wlc_clkctl_clk(wlc_hw, CLK_FAST);
1170
1171         /*
1172          * Configure pci/pcmcia here instead of in wlc_attach()
1173          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
1174          */
1175         coremask = (1 << wlc_hw->wlc->core->coreidx);
1176
1177         if (wlc_hw->sih->bustype == PCI_BUS)
1178                 si_pci_setup(wlc_hw->sih, coremask);
1179
1180         ASSERT(si_coreid(wlc_hw->sih) == D11_CORE_ID);
1181
1182         /*
1183          * Need to read the hwradio status here to cover the case where the system
1184          * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1185          */
1186         if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1187                 /* put SB PCI in down state again */
1188                 if (wlc_hw->sih->bustype == PCI_BUS)
1189                         si_pci_down(wlc_hw->sih);
1190                 wlc_bmac_xtal(wlc_hw, OFF);
1191                 return BCME_RADIOOFF;
1192         }
1193
1194         if (wlc_hw->sih->bustype == PCI_BUS)
1195                 si_pci_up(wlc_hw->sih);
1196
1197         /* reset the d11 core */
1198         wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1199
1200         return 0;
1201 }
1202
1203 int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
1204 {
1205         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1206
1207         wlc_hw->up = true;
1208         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1209
1210         /* FULLY enable dynamic power control and d11 core interrupt */
1211         wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1212         ASSERT(wlc_hw->wlc->macintmask == 0);
1213         wl_intrson(wlc_hw->wlc->wl);
1214         return 0;
1215 }
1216
1217 int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
1218 {
1219         bool dev_gone;
1220         uint callbacks = 0;
1221
1222         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1223
1224         if (!wlc_hw->up)
1225                 return callbacks;
1226
1227         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1228
1229         /* disable interrupts */
1230         if (dev_gone)
1231                 wlc_hw->wlc->macintmask = 0;
1232         else {
1233                 /* now disable interrupts */
1234                 wl_intrsoff(wlc_hw->wlc->wl);
1235
1236                 /* ensure we're running on the pll clock again */
1237                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1238         }
1239         /* down phy at the last of this stage */
1240         callbacks += wlc_phy_down(wlc_hw->band->pi);
1241
1242         return callbacks;
1243 }
1244
1245 int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
1246 {
1247         uint callbacks = 0;
1248         bool dev_gone;
1249
1250         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
1251
1252         if (!wlc_hw->up)
1253                 return callbacks;
1254
1255         wlc_hw->up = false;
1256         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1257
1258         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1259
1260         if (dev_gone) {
1261                 wlc_hw->sbclk = false;
1262                 wlc_hw->clk = false;
1263                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1264
1265                 /* reclaim any posted packets */
1266                 wlc_flushqueues(wlc_hw->wlc);
1267         } else {
1268
1269                 /* Reset and disable the core */
1270                 if (si_iscoreup(wlc_hw->sih)) {
1271                         if (R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) &
1272                             MCTL_EN_MAC)
1273                                 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1274                         callbacks += wl_reset(wlc_hw->wlc->wl);
1275                         wlc_coredisable(wlc_hw);
1276                 }
1277
1278                 /* turn off primary xtal and pll */
1279                 if (!wlc_hw->noreset) {
1280                         if (wlc_hw->sih->bustype == PCI_BUS)
1281                                 si_pci_down(wlc_hw->sih);
1282                         wlc_bmac_xtal(wlc_hw, OFF);
1283                 }
1284         }
1285
1286         return callbacks;
1287 }
1288
1289 void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
1290 {
1291         if (D11REV_IS(wlc_hw->corerev, 4))      /* no slowclock */
1292                 udelay(5);
1293         else {
1294                 /* delay before first read of ucode state */
1295                 udelay(40);
1296
1297                 /* wait until ucode is no longer asleep */
1298                 SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1299                           DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1300         }
1301
1302         ASSERT(wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) != DBGST_ASLEEP);
1303 }
1304
1305 void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
1306 {
1307         bcopy(wlc_hw->etheraddr, ea, ETH_ALEN);
1308 }
1309
1310 int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
1311 {
1312         return wlc_hw->band->bandtype;
1313 }
1314
1315 /* control chip clock to save power, enable dynamic clock or force fast clock */
1316 static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
1317 {
1318         if (PMUCTL_ENAB(wlc_hw->sih)) {
1319                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1320                  *  but mac core will still run on ALP(not HT) when it enters powersave mode,
1321                  *      which means the FCA bit may not be set.
1322                  *      should wakeup mac if driver wants it to run on HT.
1323                  */
1324
1325                 if (wlc_hw->clk) {
1326                         if (mode == CLK_FAST) {
1327                                 OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1328                                        CCS_FORCEHT);
1329
1330                                 udelay(64);
1331
1332                                 SPINWAIT(((R_REG
1333                                            (wlc_hw->osh,
1334                                             &wlc_hw->regs->
1335                                             clk_ctl_st) & CCS_HTAVAIL) == 0),
1336                                          PMU_MAX_TRANSITION_DLY);
1337                                 ASSERT(R_REG
1338                                        (wlc_hw->osh,
1339                                         &wlc_hw->regs->
1340                                         clk_ctl_st) & CCS_HTAVAIL);
1341                         } else {
1342                                 if ((wlc_hw->sih->pmurev == 0) &&
1343                                     (R_REG
1344                                      (wlc_hw->osh,
1345                                       &wlc_hw->regs->
1346                                       clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1347                                         SPINWAIT(((R_REG
1348                                                    (wlc_hw->osh,
1349                                                     &wlc_hw->regs->
1350                                                     clk_ctl_st) & CCS_HTAVAIL)
1351                                                   == 0),
1352                                                  PMU_MAX_TRANSITION_DLY);
1353                                 AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1354                                         ~CCS_FORCEHT);
1355                         }
1356                 }
1357                 wlc_hw->forcefastclk = (mode == CLK_FAST);
1358         } else {
1359                 bool wakeup_ucode;
1360
1361                 /* old chips w/o PMU, force HT through cc,
1362                  * then use FCA to verify mac is running fast clock
1363                  */
1364
1365                 wakeup_ucode = D11REV_LT(wlc_hw->corerev, 9);
1366
1367                 if (wlc_hw->up && wakeup_ucode)
1368                         wlc_ucode_wake_override_set(wlc_hw,
1369                                                     WLC_WAKE_OVERRIDE_CLKCTL);
1370
1371                 wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
1372
1373                 if (D11REV_LT(wlc_hw->corerev, 11)) {
1374                         /* ucode WAR for old chips */
1375                         if (wlc_hw->forcefastclk)
1376                                 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK,
1377                                              MHF1_FORCEFASTCLK, WLC_BAND_ALL);
1378                         else
1379                                 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK, 0,
1380                                              WLC_BAND_ALL);
1381                 }
1382
1383                 /* check fast clock is available (if core is not in reset) */
1384                 if (D11REV_GT(wlc_hw->corerev, 4) && wlc_hw->forcefastclk
1385                     && wlc_hw->clk)
1386                         ASSERT(si_core_sflags(wlc_hw->sih, 0, 0) & SISF_FCLKA);
1387
1388                 /* keep the ucode wake bit on if forcefastclk is on
1389                  * since we do not want ucode to put us back to slow clock
1390                  * when it dozes for PM mode.
1391                  * Code below matches the wake override bit with current forcefastclk state
1392                  * Only setting bit in wake_override instead of waking ucode immediately
1393                  * since old code (wlc.c 1.4499) had this behavior. Older code set
1394                  * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1395                  * (protected by an up check) was executed just below.
1396                  */
1397                 if (wlc_hw->forcefastclk)
1398                         mboolset(wlc_hw->wake_override,
1399                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1400                 else
1401                         mboolclr(wlc_hw->wake_override,
1402                                  WLC_WAKE_OVERRIDE_FORCEFAST);
1403
1404                 /* ok to clear the wakeup now */
1405                 if (wlc_hw->up && wakeup_ucode)
1406                         wlc_ucode_wake_override_clear(wlc_hw,
1407                                                       WLC_WAKE_OVERRIDE_CLKCTL);
1408         }
1409 }
1410
1411 /* set initial host flags value */
1412 static void
1413 wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
1414 {
1415         struct wlc_hw_info *wlc_hw = wlc->hw;
1416
1417         memset(mhfs, 0, MHFMAX * sizeof(u16));
1418
1419         mhfs[MHF2] |= mhf2_init;
1420
1421         /* prohibit use of slowclock on multifunction boards */
1422         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1423                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1424
1425         if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1426                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1427                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1428         }
1429 }
1430
1431 /* set or clear ucode host flag bits
1432  * it has an optimization for no-change write
1433  * it only writes through shared memory when the core has clock;
1434  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1435  *
1436  *
1437  * bands values are: WLC_BAND_AUTO <--- Current band only
1438  *                   WLC_BAND_5G   <--- 5G band only
1439  *                   WLC_BAND_2G   <--- 2G band only
1440  *                   WLC_BAND_ALL  <--- All bands
1441  */
1442 void
1443 wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
1444              int bands)
1445 {
1446         u16 save;
1447         u16 addr[MHFMAX] = {
1448                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1449                 M_HOST_FLAGS5
1450         };
1451         wlc_hwband_t *band;
1452
1453         ASSERT((val & ~mask) == 0);
1454         ASSERT(idx < MHFMAX);
1455         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1456
1457         switch (bands) {
1458                 /* Current band only or all bands,
1459                  * then set the band to current band
1460                  */
1461         case WLC_BAND_AUTO:
1462         case WLC_BAND_ALL:
1463                 band = wlc_hw->band;
1464                 break;
1465         case WLC_BAND_5G:
1466                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1467                 break;
1468         case WLC_BAND_2G:
1469                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1470                 break;
1471         default:
1472                 ASSERT(0);
1473                 band = NULL;
1474         }
1475
1476         if (band) {
1477                 save = band->mhfs[idx];
1478                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1479
1480                 /* optimization: only write through if changed, and
1481                  * changed band is the current band
1482                  */
1483                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1484                     && (band == wlc_hw->band))
1485                         wlc_bmac_write_shm(wlc_hw, addr[idx],
1486                                            (u16) band->mhfs[idx]);
1487         }
1488
1489         if (bands == WLC_BAND_ALL) {
1490                 wlc_hw->bandstate[0]->mhfs[idx] =
1491                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1492                 wlc_hw->bandstate[1]->mhfs[idx] =
1493                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1494         }
1495 }
1496
1497 u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
1498 {
1499         wlc_hwband_t *band;
1500         ASSERT(idx < MHFMAX);
1501
1502         switch (bands) {
1503         case WLC_BAND_AUTO:
1504                 band = wlc_hw->band;
1505                 break;
1506         case WLC_BAND_5G:
1507                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1508                 break;
1509         case WLC_BAND_2G:
1510                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1511                 break;
1512         default:
1513                 ASSERT(0);
1514                 band = NULL;
1515         }
1516
1517         if (!band)
1518                 return 0;
1519
1520         return band->mhfs[idx];
1521 }
1522
1523 static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
1524 {
1525         u8 idx;
1526         u16 addr[] = {
1527                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1528                 M_HOST_FLAGS5
1529         };
1530
1531         ASSERT(ARRAY_SIZE(addr) == MHFMAX);
1532
1533         for (idx = 0; idx < MHFMAX; idx++) {
1534                 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1535         }
1536 }
1537
1538 /* set the maccontrol register to desired reset state and
1539  * initialize the sw cache of the register
1540  */
1541 static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
1542 {
1543         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1544         wlc_hw->maccontrol = 0;
1545         wlc_hw->suspended_fifos = 0;
1546         wlc_hw->wake_override = 0;
1547         wlc_hw->mute_override = 0;
1548         wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1549 }
1550
1551 /* set or clear maccontrol bits */
1552 void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
1553 {
1554         u32 maccontrol;
1555         u32 new_maccontrol;
1556
1557         ASSERT((val & ~mask) == 0);
1558
1559         maccontrol = wlc_hw->maccontrol;
1560         new_maccontrol = (maccontrol & ~mask) | val;
1561
1562         /* if the new maccontrol value is the same as the old, nothing to do */
1563         if (new_maccontrol == maccontrol)
1564                 return;
1565
1566         /* something changed, cache the new value */
1567         wlc_hw->maccontrol = new_maccontrol;
1568
1569         /* write the new values with overrides applied */
1570         wlc_mctrl_write(wlc_hw);
1571 }
1572
1573 /* write the software state of maccontrol and overrides to the maccontrol register */
1574 static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
1575 {
1576         u32 maccontrol = wlc_hw->maccontrol;
1577
1578         /* OR in the wake bit if overridden */
1579         if (wlc_hw->wake_override)
1580                 maccontrol |= MCTL_WAKE;
1581
1582         /* set AP and INFRA bits for mute if needed */
1583         if (wlc_hw->mute_override) {
1584                 maccontrol &= ~(MCTL_AP);
1585                 maccontrol |= MCTL_INFRA;
1586         }
1587
1588         W_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol, maccontrol);
1589 }
1590
1591 void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
1592 {
1593         ASSERT((wlc_hw->wake_override & override_bit) == 0);
1594
1595         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1596                 mboolset(wlc_hw->wake_override, override_bit);
1597                 return;
1598         }
1599
1600         mboolset(wlc_hw->wake_override, override_bit);
1601
1602         wlc_mctrl_write(wlc_hw);
1603         wlc_bmac_wait_for_wake(wlc_hw);
1604
1605         return;
1606 }
1607
1608 void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
1609 {
1610         ASSERT(wlc_hw->wake_override & override_bit);
1611
1612         mboolclr(wlc_hw->wake_override, override_bit);
1613
1614         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1615                 return;
1616
1617         wlc_mctrl_write(wlc_hw);
1618
1619         return;
1620 }
1621
1622 /* When driver needs ucode to stop beaconing, it has to make sure that
1623  * MCTL_AP is clear and MCTL_INFRA is set
1624  * Mode           MCTL_AP        MCTL_INFRA
1625  * AP                1              1
1626  * STA               0              1 <--- This will ensure no beacons
1627  * IBSS              0              0
1628  */
1629 static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
1630 {
1631         wlc_hw->mute_override = 1;
1632
1633         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1634          * override, then there is no change to write
1635          */
1636         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1637                 return;
1638
1639         wlc_mctrl_write(wlc_hw);
1640
1641         return;
1642 }
1643
1644 /* Clear the override on AP and INFRA bits */
1645 static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
1646 {
1647         if (wlc_hw->mute_override == 0)
1648                 return;
1649
1650         wlc_hw->mute_override = 0;
1651
1652         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1653          * override, then there is no change to write
1654          */
1655         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1656                 return;
1657
1658         wlc_mctrl_write(wlc_hw);
1659 }
1660
1661 /*
1662  * Write a MAC address to the rcmta structure
1663  */
1664 void
1665 wlc_bmac_set_rcmta(struct wlc_hw_info *wlc_hw, int idx,
1666                    const u8 *addr)
1667 {
1668         d11regs_t *regs = wlc_hw->regs;
1669         volatile u16 *objdata16 = (volatile u16 *)&regs->objdata;
1670         u32 mac_hm;
1671         u16 mac_l;
1672         struct osl_info *osh;
1673
1674         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
1675
1676         ASSERT(wlc_hw->corerev > 4);
1677
1678         mac_hm =
1679             (addr[3] << 24) | (addr[2] << 16) |
1680             (addr[1] << 8) | addr[0];
1681         mac_l = (addr[5] << 8) | addr[4];
1682
1683         osh = wlc_hw->osh;
1684
1685         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
1686         (void)R_REG(osh, &regs->objaddr);
1687         W_REG(osh, &regs->objdata, mac_hm);
1688         W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
1689         (void)R_REG(osh, &regs->objaddr);
1690         W_REG(osh, objdata16, mac_l);
1691 }
1692
1693 /*
1694  * Write a MAC address to the given match reg offset in the RXE match engine.
1695  */
1696 void
1697 wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
1698                        const u8 *addr)
1699 {
1700         d11regs_t *regs;
1701         u16 mac_l;
1702         u16 mac_m;
1703         u16 mac_h;
1704         struct osl_info *osh;
1705
1706         WL_TRACE("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit);
1707
1708         ASSERT((match_reg_offset < RCM_SIZE) || (wlc_hw->corerev == 4));
1709
1710         regs = wlc_hw->regs;
1711         mac_l = addr[0] | (addr[1] << 8);
1712         mac_m = addr[2] | (addr[3] << 8);
1713         mac_h = addr[4] | (addr[5] << 8);
1714
1715         osh = wlc_hw->osh;
1716
1717         /* enter the MAC addr into the RXE match registers */
1718         W_REG(osh, &regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1719         W_REG(osh, &regs->rcm_mat_data, mac_l);
1720         W_REG(osh, &regs->rcm_mat_data, mac_m);
1721         W_REG(osh, &regs->rcm_mat_data, mac_h);
1722
1723 }
1724
1725 void
1726 wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
1727                             void *buf)
1728 {
1729         d11regs_t *regs;
1730         u32 word;
1731         bool be_bit;
1732 #ifdef IL_BIGENDIAN
1733         volatile u16 *dptr = NULL;
1734 #endif                          /* IL_BIGENDIAN */
1735         struct osl_info *osh;
1736
1737         WL_TRACE("wl%d: wlc_bmac_write_template_ram\n", wlc_hw->unit);
1738
1739         regs = wlc_hw->regs;
1740         osh = wlc_hw->osh;
1741
1742         ASSERT(IS_ALIGNED(offset, sizeof(u32)));
1743         ASSERT(IS_ALIGNED(len, sizeof(u32)));
1744         ASSERT((offset & ~0xffff) == 0);
1745
1746         W_REG(osh, &regs->tplatewrptr, offset);
1747
1748         /* if MCTL_BIGEND bit set in mac control register,
1749          * the chip swaps data in fifo, as well as data in
1750          * template ram
1751          */
1752         be_bit = (R_REG(osh, &regs->maccontrol) & MCTL_BIGEND) != 0;
1753
1754         while (len > 0) {
1755                 bcopy((u8 *) buf, &word, sizeof(u32));
1756
1757                 if (be_bit)
1758                         word = hton32(word);
1759                 else
1760                         word = htol32(word);
1761
1762                 W_REG(osh, &regs->tplatewrdata, word);
1763
1764                 buf = (u8 *) buf + sizeof(u32);
1765                 len -= sizeof(u32);
1766         }
1767 }
1768
1769 void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
1770 {
1771         struct osl_info *osh;
1772
1773         osh = wlc_hw->osh;
1774         wlc_hw->band->CWmin = newmin;
1775
1776         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1777         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1778         W_REG(osh, &wlc_hw->regs->objdata, newmin);
1779 }
1780
1781 void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
1782 {
1783         struct osl_info *osh;
1784
1785         osh = wlc_hw->osh;
1786         wlc_hw->band->CWmax = newmax;
1787
1788         W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1789         (void)R_REG(osh, &wlc_hw->regs->objaddr);
1790         W_REG(osh, &wlc_hw->regs->objdata, newmax);
1791 }
1792
1793 void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
1794 {
1795         bool fastclk;
1796         u32 tmp;
1797
1798         /* request FAST clock if not on */
1799         fastclk = wlc_hw->forcefastclk;
1800         if (!fastclk)
1801                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1802
1803         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1804
1805         ASSERT(wlc_hw->clk);
1806         if (D11REV_LT(wlc_hw->corerev, 17))
1807                 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
1808
1809         wlc_bmac_phy_reset(wlc_hw);
1810         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1811
1812         /* restore the clk */
1813         if (!fastclk)
1814                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1815 }
1816
1817 static void
1818 wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1819 {
1820         d11regs_t *regs = wlc_hw->regs;
1821
1822         wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1823                                     bcn);
1824         /* write beacon length to SCR */
1825         ASSERT(len < 65536);
1826         wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1827         /* mark beacon0 valid */
1828         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN0VLD);
1829 }
1830
1831 static void
1832 wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
1833 {
1834         d11regs_t *regs = wlc_hw->regs;
1835
1836         wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1837                                     bcn);
1838         /* write beacon length to SCR */
1839         ASSERT(len < 65536);
1840         wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1841         /* mark beacon1 valid */
1842         OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN1VLD);
1843 }
1844
1845 /* mac is assumed to be suspended at this point */
1846 void
1847 wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
1848                                bool both)
1849 {
1850         d11regs_t *regs = wlc_hw->regs;
1851
1852         if (both) {
1853                 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1854                 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1855         } else {
1856                 /* bcn 0 */
1857                 if (!(R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN0VLD))
1858                         wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1859                 /* bcn 1 */
1860                 else if (!
1861                          (R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN1VLD))
1862                         wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1863                 else            /* one template should always have been available */
1864                         ASSERT(0);
1865         }
1866 }
1867
1868 static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
1869 {
1870         u16 v;
1871         struct wlc_info *wlc = wlc_hw->wlc;
1872         /* update SYNTHPU_DLY */
1873
1874         if (WLCISLCNPHY(wlc->band)) {
1875                 v = SYNTHPU_DLY_LPPHY_US;
1876         } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1877                 v = SYNTHPU_DLY_NPHY_US;
1878         } else {
1879                 v = SYNTHPU_DLY_BPHY_US;
1880         }
1881
1882         wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1883 }
1884
1885 /* band-specific init */
1886 static void
1887 WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
1888 {
1889         struct wlc_hw_info *wlc_hw = wlc->hw;
1890
1891         WL_TRACE("wl%d: wlc_bmac_bsinit: bandunit %d\n",
1892                  wlc_hw->unit, wlc_hw->band->bandunit);
1893
1894         /* sanity check */
1895         if (PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion)) !=
1896             PHY_TYPE_LCNXN)
1897                 ASSERT((uint)
1898                        PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion))
1899                        == wlc_hw->band->phytype);
1900
1901         wlc_ucode_bsinit(wlc_hw);
1902
1903         wlc_phy_init(wlc_hw->band->pi, chanspec);
1904
1905         wlc_ucode_txant_set(wlc_hw);
1906
1907         /* cwmin is band-specific, update hardware with value for current band */
1908         wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1909         wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1910
1911         wlc_bmac_update_slot_timing(wlc_hw,
1912                                     BAND_5G(wlc_hw->band->
1913                                             bandtype) ? true : wlc_hw->
1914                                     shortslot);
1915
1916         /* write phytype and phyvers */
1917         wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1918         wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1919
1920         /* initialize the txphyctl1 rate table since shmem is shared between bands */
1921         wlc_upd_ofdm_pctl1_table(wlc_hw);
1922
1923         wlc_bmac_upd_synthpu(wlc_hw);
1924 }
1925
1926 void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
1927 {
1928         WL_TRACE("wl%d: wlc_bmac_core_phy_clk: clk %d\n", wlc_hw->unit, clk);
1929
1930         wlc_hw->phyclk = clk;
1931
1932         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
1933
1934                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1935                                (SICF_PRST | SICF_FGC));
1936                 udelay(1);
1937                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1938                 udelay(1);
1939
1940         } else {                /* take phy out of reset */
1941
1942                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1943                 udelay(1);
1944                 si_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1945                 udelay(1);
1946
1947         }
1948 }
1949
1950 /* Perform a soft reset of the PHY PLL */
1951 void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
1952 {
1953         WL_TRACE("wl%d: wlc_bmac_core_phypll_reset\n", wlc_hw->unit);
1954
1955         si_corereg(wlc_hw->sih, SI_CC_IDX,
1956                    offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1957         udelay(1);
1958         si_corereg(wlc_hw->sih, SI_CC_IDX,
1959                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1960         udelay(1);
1961         si_corereg(wlc_hw->sih, SI_CC_IDX,
1962                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1963         udelay(1);
1964         si_corereg(wlc_hw->sih, SI_CC_IDX,
1965                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1966         udelay(1);
1967 }
1968
1969 /* light way to turn on phy clock without reset for NPHY only
1970  *  refer to wlc_bmac_core_phy_clk for full version
1971  */
1972 void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
1973 {
1974         /* support(necessary for NPHY and HYPHY) only */
1975         if (!WLCISNPHY(wlc_hw->band))
1976                 return;
1977
1978         if (ON == clk)
1979                 si_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1980         else
1981                 si_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1982
1983 }
1984
1985 void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
1986 {
1987         if (ON == clk)
1988                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1989         else
1990                 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1991 }
1992
1993 void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
1994 {
1995         wlc_phy_t *pih = wlc_hw->band->pi;
1996         u32 phy_bw_clkbits;
1997         bool phy_in_reset = false;
1998
1999         WL_TRACE("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit);
2000
2001         if (pih == NULL)
2002                 return;
2003
2004         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
2005
2006         /* Specfic reset sequence required for NPHY rev 3 and 4 */
2007         if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
2008             NREV_LE(wlc_hw->band->phyrev, 4)) {
2009                 /* Set the PHY bandwidth */
2010                 si_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
2011
2012                 udelay(1);
2013
2014                 /* Perform a soft reset of the PHY PLL */
2015                 wlc_bmac_core_phypll_reset(wlc_hw);
2016
2017                 /* reset the PHY */
2018                 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
2019                                (SICF_PRST | SICF_PCLKE));
2020                 phy_in_reset = true;
2021         } else {
2022
2023                 si_core_cflags(wlc_hw->sih,
2024                                (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
2025                                (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
2026         }
2027
2028         udelay(2);
2029         wlc_bmac_core_phy_clk(wlc_hw, ON);
2030
2031         if (pih)
2032                 wlc_phy_anacore(pih, ON);
2033 }
2034
2035 /* switch to and initialize new band */
2036 static void
2037 WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
2038                                 chanspec_t chanspec) {
2039         struct wlc_info *wlc = wlc_hw->wlc;
2040         u32 macintmask;
2041
2042         ASSERT(NBANDS_HW(wlc_hw) > 1);
2043         ASSERT(bandunit != wlc_hw->band->bandunit);
2044
2045         /* Enable the d11 core before accessing it */
2046         if (!si_iscoreup(wlc_hw->sih)) {
2047                 si_core_reset(wlc_hw->sih, 0, 0);
2048                 ASSERT(si_iscoreup(wlc_hw->sih));
2049                 wlc_mctrl_reset(wlc_hw);
2050         }
2051
2052         macintmask = wlc_setband_inact(wlc, bandunit);
2053
2054         if (!wlc_hw->up)
2055                 return;
2056
2057         wlc_bmac_core_phy_clk(wlc_hw, ON);
2058
2059         /* band-specific initializations */
2060         wlc_bmac_bsinit(wlc, chanspec);
2061
2062         /*
2063          * If there are any pending software interrupt bits,
2064          * then replace these with a harmless nonzero value
2065          * so wlc_dpc() will re-enable interrupts when done.
2066          */
2067         if (wlc->macintstatus)
2068                 wlc->macintstatus = MI_DMAINT;
2069
2070         /* restore macintmask */
2071         wl_intrsrestore(wlc->wl, macintmask);
2072
2073         /* ucode should still be suspended.. */
2074         ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
2075                0);
2076 }
2077
2078 /* low-level band switch utility routine */
2079 void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
2080 {
2081         WL_TRACE("wl%d: wlc_setxband: bandunit %d\n", wlc_hw->unit, bandunit);
2082
2083         wlc_hw->band = wlc_hw->bandstate[bandunit];
2084
2085         /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
2086         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
2087
2088         /* set gmode core flag */
2089         if (wlc_hw->sbclk && !wlc_hw->noreset) {
2090                 si_core_cflags(wlc_hw->sih, SICF_GMODE,
2091                                ((bandunit == 0) ? SICF_GMODE : 0));
2092         }
2093 }
2094
2095 static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
2096 {
2097
2098         /* reject unsupported corerev */
2099         if (!VALID_COREREV(wlc_hw->corerev)) {
2100                 WL_ERROR("unsupported core rev %d\n", wlc_hw->corerev);
2101                 return false;
2102         }
2103
2104         return true;
2105 }
2106
2107 static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
2108 {
2109         bool goodboard = true;
2110         uint boardrev = wlc_hw->boardrev;
2111
2112         if (boardrev == 0)
2113                 goodboard = false;
2114         else if (boardrev > 0xff) {
2115                 uint brt = (boardrev & 0xf000) >> 12;
2116                 uint b0 = (boardrev & 0xf00) >> 8;
2117                 uint b1 = (boardrev & 0xf0) >> 4;
2118                 uint b2 = boardrev & 0xf;
2119
2120                 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
2121                     || (b2 > 9))
2122                         goodboard = false;
2123         }
2124
2125         if (wlc_hw->sih->boardvendor != VENDOR_BROADCOM)
2126                 return goodboard;
2127
2128         return goodboard;
2129 }
2130
2131 static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
2132 {
2133         const char *varname = "macaddr";
2134         char *macaddr;
2135
2136         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
2137         macaddr = getvar(wlc_hw->vars, varname);
2138         if (macaddr != NULL)
2139                 return macaddr;
2140
2141         if (NBANDS_HW(wlc_hw) > 1)
2142                 varname = "et1macaddr";
2143         else
2144                 varname = "il0macaddr";
2145
2146         macaddr = getvar(wlc_hw->vars, varname);
2147         if (macaddr == NULL) {
2148                 WL_ERROR("wl%d: wlc_get_macaddr: macaddr getvar(%s) not found\n",
2149                          wlc_hw->unit, varname);
2150         }
2151
2152         return macaddr;
2153 }
2154
2155 /*
2156  * Return true if radio is disabled, otherwise false.
2157  * hw radio disable signal is an external pin, users activate it asynchronously
2158  * this function could be called when driver is down and w/o clock
2159  * it operates on different registers depending on corerev and boardflag.
2160  */
2161 bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
2162 {
2163         bool v, clk, xtal;
2164         u32 resetbits = 0, flags = 0;
2165
2166         xtal = wlc_hw->sbclk;
2167         if (!xtal)
2168                 wlc_bmac_xtal(wlc_hw, ON);
2169
2170         /* may need to take core out of reset first */
2171         clk = wlc_hw->clk;
2172         if (!clk) {
2173                 if (D11REV_LE(wlc_hw->corerev, 11))
2174                         resetbits |= SICF_PCLKE;
2175
2176                 /*
2177                  * corerev >= 18, mac no longer enables phyclk automatically when driver accesses
2178                  * phyreg throughput mac. This can be skipped since only mac reg is accessed below
2179                  */
2180                 if (D11REV_GE(wlc_hw->corerev, 18))
2181                         flags |= SICF_PCLKE;
2182
2183                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2184                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2185                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2186                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2187                         wlc_hw->regs =
2188                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2189                                                      0);
2190                 si_core_reset(wlc_hw->sih, flags, resetbits);
2191                 wlc_mctrl_reset(wlc_hw);
2192         }
2193
2194         v = ((R_REG(wlc_hw->osh, &wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2195
2196         /* put core back into reset */
2197         if (!clk)
2198                 si_core_disable(wlc_hw->sih, 0);
2199
2200         if (!xtal)
2201                 wlc_bmac_xtal(wlc_hw, OFF);
2202
2203         return v;
2204 }
2205
2206 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2207 void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
2208 {
2209         if (wlc_hw->wlc->pub->hw_up)
2210                 return;
2211
2212         WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
2213
2214         /*
2215          * Enable pll and xtal, initialize the power control registers,
2216          * and force fastclock for the remainder of wlc_up().
2217          */
2218         wlc_bmac_xtal(wlc_hw, ON);
2219         si_clkctl_init(wlc_hw->sih);
2220         wlc_clkctl_clk(wlc_hw, CLK_FAST);
2221
2222         if (wlc_hw->sih->bustype == PCI_BUS) {
2223                 si_pci_fixcfg(wlc_hw->sih);
2224
2225                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2226                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2227                     (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
2228                     (wlc_hw->sih->chip == BCM43421_CHIP_ID))
2229                         wlc_hw->regs =
2230                             (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2231                                                      0);
2232         }
2233
2234         /* Inform phy that a POR reset has occurred so it does a complete phy init */
2235         wlc_phy_por_inform(wlc_hw->band->pi);
2236
2237         wlc_hw->ucode_loaded = false;
2238         wlc_hw->wlc->pub->hw_up = true;
2239
2240         if ((wlc_hw->boardflags & BFL_FEM)
2241             && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2242                 if (!
2243                     (wlc_hw->boardrev >= 0x1250
2244                      && (wlc_hw->boardflags & BFL_FEM_BT)))
2245                         si_epa_4313war(wlc_hw->sih);
2246         }
2247 }
2248
2249 static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
2250 {
2251         struct hnddma_pub *di = wlc_hw->di[fifo];
2252         struct osl_info *osh;
2253
2254         if (D11REV_LT(wlc_hw->corerev, 12)) {
2255                 bool rxidle = true;
2256                 u16 rcv_frm_cnt = 0;
2257
2258                 osh = wlc_hw->osh;
2259
2260                 W_REG(osh, &wlc_hw->regs->rcv_fifo_ctl, fifo << 8);
2261                 SPINWAIT((!(rxidle = dma_rxidle(di))) &&
2262                          ((rcv_frm_cnt =
2263                            R_REG(osh, &wlc_hw->regs->rcv_frm_cnt)) != 0),
2264                          50000);
2265
2266                 if (!rxidle && (rcv_frm_cnt != 0))
2267                         WL_ERROR("wl%d: %s: rxdma[%d] not idle && rcv_frm_cnt(%d) not zero\n",
2268                                  wlc_hw->unit, __func__, fifo, rcv_frm_cnt);
2269                 mdelay(2);
2270         }
2271
2272         return dma_rxreset(di);
2273 }
2274
2275 /* d11 core reset
2276  *   ensure fask clock during reset
2277  *   reset dma
2278  *   reset d11(out of reset)
2279  *   reset phy(out of reset)
2280  *   clear software macintstatus for fresh new start
2281  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2282  */
2283 void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
2284 {
2285         d11regs_t *regs;
2286         uint i;
2287         bool fastclk;
2288         u32 resetbits = 0;
2289
2290         if (flags == WLC_USE_COREFLAGS)
2291                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2292
2293         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
2294
2295         regs = wlc_hw->regs;
2296
2297         /* request FAST clock if not on  */
2298         fastclk = wlc_hw->forcefastclk;
2299         if (!fastclk)
2300                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2301
2302         /* reset the dma engines except first time thru */
2303         if (si_iscoreup(wlc_hw->sih)) {
2304                 for (i = 0; i < NFIFO; i++)
2305                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2306                                 WL_ERROR("wl%d: %s: dma_txreset[%d]: cannot stop dma\n",
2307                                          wlc_hw->unit, __func__, i);
2308                         }
2309
2310                 if ((wlc_hw->di[RX_FIFO])
2311                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2312                         WL_ERROR("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n",
2313                                  wlc_hw->unit, __func__, RX_FIFO);
2314                 }
2315                 if (D11REV_IS(wlc_hw->corerev, 4)
2316                     && wlc_hw->di[RX_TXSTATUS_FIFO]
2317                     && (!wlc_dma_rxreset(wlc_hw, RX_TXSTATUS_FIFO))) {
2318                         WL_ERROR("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n",
2319                                  wlc_hw->unit, __func__, RX_TXSTATUS_FIFO);
2320                 }
2321         }
2322         /* if noreset, just stop the psm and return */
2323         if (wlc_hw->noreset) {
2324                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2325                 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2326                 return;
2327         }
2328
2329         if (D11REV_LE(wlc_hw->corerev, 11))
2330                 resetbits |= SICF_PCLKE;
2331
2332         /*
2333          * corerev >= 18, mac no longer enables phyclk automatically when driver accesses phyreg
2334          * throughput mac, AND phy_reset is skipped at early stage when band->pi is invalid
2335          * need to enable PHY CLK
2336          */
2337         if (D11REV_GE(wlc_hw->corerev, 18))
2338                 flags |= SICF_PCLKE;
2339
2340         /* reset the core
2341          * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2342          *  is cleared by the core_reset. have to re-request it.
2343          *  This adds some delay and we can optimize it by also requesting fastclk through
2344          *  chipcommon during this period if necessary. But that has to work coordinate
2345          *  with other driver like mips/arm since they may touch chipcommon as well.
2346          */
2347         wlc_hw->clk = false;
2348         si_core_reset(wlc_hw->sih, flags, resetbits);
2349         wlc_hw->clk = true;
2350         if (wlc_hw->band && wlc_hw->band->pi)
2351                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2352
2353         wlc_mctrl_reset(wlc_hw);
2354
2355         if (PMUCTL_ENAB(wlc_hw->sih))
2356                 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2357
2358         wlc_bmac_phy_reset(wlc_hw);
2359
2360         /* turn on PHY_PLL */
2361         wlc_bmac_core_phypll_ctl(wlc_hw, true);
2362
2363         /* clear sw intstatus */
2364         wlc_hw->wlc->macintstatus = 0;
2365
2366         /* restore the clk setting */
2367         if (!fastclk)
2368                 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2369 }
2370
2371 /* If the ucode that supports corerev 5 is used for corerev 9 and above,
2372  * txfifo sizes needs to be modified(increased) since the newer cores
2373  * have more memory.
2374  */
2375 static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
2376 {
2377         d11regs_t *regs = wlc_hw->regs;
2378         u16 fifo_nu;
2379         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2380         u16 txfifo_def, txfifo_def1;
2381         u16 txfifo_cmd;
2382         struct osl_info *osh;
2383
2384         if (D11REV_LT(wlc_hw->corerev, 9))
2385                 goto exit;
2386
2387         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2388         txfifo_startblk = TXFIFO_START_BLK;
2389
2390         osh = wlc_hw->osh;
2391
2392         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2393         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2394
2395                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2396                 txfifo_def = (txfifo_startblk & 0xff) |
2397                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2398                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2399                     ((((txfifo_endblk -
2400                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2401                 txfifo_cmd =
2402                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2403
2404                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2405                 W_REG(osh, &regs->xmtfifodef, txfifo_def);
2406                 if (D11REV_GE(wlc_hw->corerev, 16))
2407                         W_REG(osh, &regs->xmtfifodef1, txfifo_def1);
2408
2409                 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2410
2411                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2412         }
2413  exit:
2414         /* need to propagate to shm location to be in sync since ucode/hw won't do this */
2415         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2416                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2417         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2418                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2419         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2420                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2421                             xmtfifo_sz[TX_AC_BK_FIFO]));
2422         wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2423                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2424                             xmtfifo_sz[TX_BCMC_FIFO]));
2425 }
2426
2427 /* d11 core init
2428  *   reset PSM
2429  *   download ucode/PCM
2430  *   let ucode run to suspended
2431  *   download ucode inits
2432  *   config other core registers
2433  *   init dma
2434  */
2435 static void wlc_coreinit(struct wlc_info *wlc)
2436 {
2437         struct wlc_hw_info *wlc_hw = wlc->hw;
2438         d11regs_t *regs;
2439         u32 sflags;
2440         uint bcnint_us;
2441         uint i = 0;
2442         bool fifosz_fixup = false;
2443         struct osl_info *osh;
2444         int err = 0;
2445         u16 buf[NFIFO];
2446
2447         regs = wlc_hw->regs;
2448         osh = wlc_hw->osh;
2449
2450         WL_TRACE("wl%d: wlc_coreinit\n", wlc_hw->unit);
2451
2452         /* reset PSM */
2453         wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2454
2455         wlc_ucode_download(wlc_hw);
2456         /*
2457          * FIFOSZ fixup
2458          * 1) core5-9 use ucode 5 to save space since the PSM is the same
2459          * 2) newer chips, driver wants to controls the fifo allocation
2460          */
2461         if (D11REV_GE(wlc_hw->corerev, 4))
2462                 fifosz_fixup = true;
2463
2464         /* let the PSM run to the suspended state, set mode to BSS STA */
2465         W_REG(osh, &regs->macintstatus, -1);
2466         wlc_bmac_mctrl(wlc_hw, ~0,
2467                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2468
2469         /* wait for ucode to self-suspend after auto-init */
2470         SPINWAIT(((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0),
2471                  1000 * 1000);
2472         if ((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0)
2473                 WL_ERROR("wl%d: wlc_coreinit: ucode did not self-suspend!\n",
2474                          wlc_hw->unit);
2475
2476         wlc_gpio_init(wlc);
2477
2478         sflags = si_core_sflags(wlc_hw->sih, 0, 0);
2479
2480         if (D11REV_IS(wlc_hw->corerev, 23)) {
2481                 if (WLCISNPHY(wlc_hw->band))
2482                         wlc_write_inits(wlc_hw, d11n0initvals16);
2483                 else
2484                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2485                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2486         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2487                 if (WLCISLCNPHY(wlc_hw->band)) {
2488                         wlc_write_inits(wlc_hw, d11lcn0initvals24);
2489                 } else {
2490                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2491                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2492                 }
2493         } else {
2494                 WL_ERROR("%s: wl%d: unsupported corerev %d\n",
2495                          __func__, wlc_hw->unit, wlc_hw->corerev);
2496         }
2497
2498         /* For old ucode, txfifo sizes needs to be modified(increased) for Corerev >= 9 */
2499         if (fifosz_fixup == true) {
2500                 wlc_corerev_fifofixup(wlc_hw);
2501         }
2502
2503         /* check txfifo allocations match between ucode and driver */
2504         buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2505         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2506                 i = TX_AC_BE_FIFO;
2507                 err = -1;
2508         }
2509         buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2510         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2511                 i = TX_AC_VI_FIFO;
2512                 err = -1;
2513         }
2514         buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2515         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2516         buf[TX_AC_BK_FIFO] &= 0xff;
2517         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2518                 i = TX_AC_BK_FIFO;
2519                 err = -1;
2520         }
2521         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2522                 i = TX_AC_VO_FIFO;
2523                 err = -1;
2524         }
2525         buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2526         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2527         buf[TX_BCMC_FIFO] &= 0xff;
2528         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2529                 i = TX_BCMC_FIFO;
2530                 err = -1;
2531         }
2532         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2533                 i = TX_ATIM_FIFO;
2534                 err = -1;
2535         }
2536         if (err != 0) {
2537                 WL_ERROR("wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n",
2538                          buf[i], wlc_hw->xmtfifo_sz[i], i);
2539                 /* DO NOT ASSERT corerev < 4 even there is a mismatch
2540                  * shmem, since driver don't overwrite those chip and
2541                  * ucode initialize data will be used.
2542                  */
2543                 if (D11REV_GE(wlc_hw->corerev, 4))
2544                         ASSERT(0);
2545         }
2546
2547         /* make sure we can still talk to the mac */
2548         ASSERT(R_REG(osh, &regs->maccontrol) != 0xffffffff);
2549
2550         /* band-specific inits done by wlc_bsinit() */
2551
2552         /* Set up frame burst size and antenna swap threshold init values */
2553         wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2554         wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2555
2556         /* enable one rx interrupt per received frame */
2557         W_REG(osh, &regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2558         if (D11REV_IS(wlc_hw->corerev, 4))
2559                 W_REG(osh, &regs->intrcvlazy[3], (1 << IRL_FC_SHIFT));
2560
2561         /* set the station mode (BSS STA) */
2562         wlc_bmac_mctrl(wlc_hw,
2563                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2564                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
2565
2566         /* set up Beacon interval */
2567         bcnint_us = 0x8000 << 10;
2568         W_REG(osh, &regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2569         W_REG(osh, &regs->tsf_cfpstart, bcnint_us);
2570         W_REG(osh, &regs->macintstatus, MI_GP1);
2571
2572         /* write interrupt mask */
2573         W_REG(osh, &regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2574         if (D11REV_IS(wlc_hw->corerev, 4))
2575                 W_REG(osh, &regs->intctrlregs[RX_TXSTATUS_FIFO].intmask,
2576                       DEF_RXINTMASK);
2577
2578         /* allow the MAC to control the PHY clock (dynamic on/off) */
2579         wlc_bmac_macphyclk_set(wlc_hw, ON);
2580
2581         /* program dynamic clock control fast powerup delay register */
2582         if (D11REV_GT(wlc_hw->corerev, 4)) {
2583                 wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
2584                 W_REG(osh, &regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2585         }
2586
2587         /* tell the ucode the corerev */
2588         wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2589
2590         /* tell the ucode MAC capabilities */
2591         if (D11REV_GE(wlc_hw->corerev, 13)) {
2592                 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2593                                    (u16) (wlc_hw->machwcap & 0xffff));
2594                 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2595                                    (u16) ((wlc_hw->
2596                                               machwcap >> 16) & 0xffff));
2597         }
2598
2599         /* write retry limits to SCR, this done after PSM init */
2600         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2601         (void)R_REG(osh, &regs->objaddr);
2602         W_REG(osh, &regs->objdata, wlc_hw->SRL);
2603         W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2604         (void)R_REG(osh, &regs->objaddr);
2605         W_REG(osh, &regs->objdata, wlc_hw->LRL);
2606
2607         /* write rate fallback retry limits */
2608         wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2609         wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2610
2611         if (D11REV_GE(wlc_hw->corerev, 16)) {
2612                 AND_REG(osh, &regs->ifs_ctl, 0x0FFF);
2613                 W_REG(osh, &regs->ifs_aifsn, EDCF_AIFSN_MIN);
2614         }
2615
2616         /* dma initializations */
2617         wlc->txpend16165war = 0;
2618
2619         /* init the tx dma engines */
2620         for (i = 0; i < NFIFO; i++) {
2621                 if (wlc_hw->di[i])
2622                         dma_txinit(wlc_hw->di[i]);
2623         }
2624
2625         /* init the rx dma engine(s) and post receive buffers */
2626         dma_rxinit(wlc_hw->di[RX_FIFO]);
2627         dma_rxfill(wlc_hw->di[RX_FIFO]);
2628         if (D11REV_IS(wlc_hw->corerev, 4)) {
2629                 dma_rxinit(wlc_hw->di[RX_TXSTATUS_FIFO]);
2630                 dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
2631         }
2632 }
2633
2634 /* This function is used for changing the tsf frac register
2635  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2636  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2637  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2638  * HTPHY Formula is 2^26/freq(MHz) e.g.
2639  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2640  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2641  * For spuron: 123MHz -> 2^26/123    = 545600.5
2642  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2643  * For spur off: 120MHz -> 2^26/120    = 559240.5
2644  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2645  */
2646
2647 void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
2648 {
2649         d11regs_t *regs;
2650         struct osl_info *osh;
2651         regs = wlc_hw->regs;
2652         osh = wlc_hw->osh;
2653
2654         if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2655             (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2656                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2657                         W_REG(osh, &regs->tsf_clk_frac_l, 0x2082);
2658                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2659                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2660                         W_REG(osh, &regs->tsf_clk_frac_l, 0x5341);
2661                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2662                 } else {        /* 120Mhz */
2663                         W_REG(osh, &regs->tsf_clk_frac_l, 0x8889);
2664                         W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2665                 }
2666         } else if (WLCISLCNPHY(wlc_hw->band)) {
2667                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2668                         W_REG(osh, &regs->tsf_clk_frac_l, 0x7CE0);
2669                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2670                 } else {        /* 80Mhz */
2671                         W_REG(osh, &regs->tsf_clk_frac_l, 0xCCCD);
2672                         W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2673                 }
2674         }
2675 }
2676
2677 /* Initialize GPIOs that are controlled by D11 core */
2678 static void wlc_gpio_init(struct wlc_info *wlc)
2679 {
2680         struct wlc_hw_info *wlc_hw = wlc->hw;
2681         d11regs_t *regs;
2682         u32 gc, gm;
2683         struct osl_info *osh;
2684
2685         regs = wlc_hw->regs;
2686         osh = wlc_hw->osh;
2687
2688         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2689         wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2690
2691         /*
2692          * Common GPIO setup:
2693          *      G0 = LED 0 = WLAN Activity
2694          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2695          *      G2 = LED 2 = WLAN 5 GHz Radio State
2696          *      G4 = radio disable input (HI enabled, LO disabled)
2697          */
2698
2699         gc = gm = 0;
2700
2701         /* Allocate GPIOs for mimo antenna diversity feature */
2702         if (WLANTSEL_ENAB(wlc)) {
2703                 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2704                         /* Enable antenna diversity, use 2x3 mode */
2705                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2706                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2707                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2708                                      MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2709
2710                         /* init superswitch control */
2711                         wlc_phy_antsel_init(wlc_hw->band->pi, false);
2712
2713                 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2714                         ASSERT((gm & BOARD_GPIO_12) == 0);
2715                         gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2716                         /* The board itself is powered by these GPIOs (when not sending pattern)
2717                          * So set them high
2718                          */
2719                         OR_REG(osh, &regs->psm_gpio_oe,
2720                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2721                         OR_REG(osh, &regs->psm_gpio_out,
2722                                (BOARD_GPIO_12 | BOARD_GPIO_13));
2723
2724                         /* Enable antenna diversity, use 2x4 mode */
2725                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2726                                      MHF3_ANTSEL_EN, WLC_BAND_ALL);
2727                         wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2728                                      WLC_BAND_ALL);
2729
2730                         /* Configure the desired clock to be 4Mhz */
2731                         wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2732                                            ANTSEL_CLKDIV_4MHZ);
2733                 }
2734         }
2735         /* gpio 9 controls the PA.  ucode is responsible for wiggling out and oe */
2736         if (wlc_hw->boardflags & BFL_PACTRL)
2737                 gm |= gc |= BOARD_GPIO_PACTRL;
2738
2739         /* apply to gpiocontrol register */
2740         si_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2741 }
2742
2743 static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
2744 {
2745         struct wlc_info *wlc;
2746         wlc = wlc_hw->wlc;
2747
2748         if (wlc_hw->ucode_loaded)
2749                 return;
2750
2751         if (D11REV_IS(wlc_hw->corerev, 23)) {
2752                 if (WLCISNPHY(wlc_hw->band)) {
2753                         wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2754                                         bcm43xx_16_mimosz);
2755                         wlc_hw->ucode_loaded = true;
2756                 } else
2757                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2758                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2759         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2760                 if (WLCISLCNPHY(wlc_hw->band)) {
2761                         wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2762                                         bcm43xx_24_lcnsz);
2763                         wlc_hw->ucode_loaded = true;
2764                 } else {
2765                         WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
2766                                  __func__, wlc_hw->unit, wlc_hw->corerev);
2767                 }
2768         }
2769 }
2770
2771 static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
2772                               const uint nbytes) {
2773         struct osl_info *osh;
2774         d11regs_t *regs = wlc_hw->regs;
2775         uint i;
2776         uint count;
2777
2778         osh = wlc_hw->osh;
2779
2780         WL_TRACE("wl%d: wlc_ucode_write\n", wlc_hw->unit);
2781
2782         ASSERT(IS_ALIGNED(nbytes, sizeof(u32)));
2783
2784         count = (nbytes / sizeof(u32));
2785
2786         W_REG(osh, &regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2787         (void)R_REG(osh, &regs->objaddr);
2788         for (i = 0; i < count; i++)
2789                 W_REG(osh, &regs->objdata, ucode[i]);
2790 }
2791
2792 static void wlc_write_inits(struct wlc_hw_info *wlc_hw, const d11init_t *inits)
2793 {
2794         int i;
2795         struct osl_info *osh;
2796         volatile u8 *base;
2797
2798         WL_TRACE("wl%d: wlc_write_inits\n", wlc_hw->unit);
2799
2800         osh = wlc_hw->osh;
2801         base = (volatile u8 *)wlc_hw->regs;
2802
2803         for (i = 0; inits[i].addr != 0xffff; i++) {
2804                 ASSERT((inits[i].size == 2) || (inits[i].size == 4));
2805
2806                 if (inits[i].size == 2)
2807                         W_REG(osh, (u16 *)(base + inits[i].addr),
2808                               inits[i].value);
2809                 else if (inits[i].size == 4)
2810                         W_REG(osh, (u32 *)(base + inits[i].addr),
2811                               inits[i].value);
2812         }
2813 }
2814
2815 static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
2816 {
2817         u16 phyctl;
2818         u16 phytxant = wlc_hw->bmac_phytxant;
2819         u16 mask = PHY_TXC_ANT_MASK;
2820
2821         /* set the Probe Response frame phy control word */
2822         phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2823         phyctl = (phyctl & ~mask) | phytxant;
2824         wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2825
2826         /* set the Response (ACK/CTS) frame phy control word */
2827         phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2828         phyctl = (phyctl & ~mask) | phytxant;
2829         wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2830 }
2831
2832 void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
2833 {
2834         /* update sw state */
2835         wlc_hw->bmac_phytxant = phytxant;
2836
2837         /* push to ucode if up */
2838         if (!wlc_hw->up)
2839                 return;
2840         wlc_ucode_txant_set(wlc_hw);
2841
2842 }
2843
2844 u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
2845 {
2846         return (u16) wlc_hw->wlc->stf->txant;
2847 }
2848
2849 void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
2850 {
2851         wlc_hw->antsel_type = antsel_type;
2852
2853         /* Update the antsel type for phy module to use */
2854         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2855 }
2856
2857 void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
2858 {
2859         bool fatal = false;
2860         uint unit;
2861         uint intstatus, idx;
2862         d11regs_t *regs = wlc_hw->regs;
2863
2864         unit = wlc_hw->unit;
2865
2866         for (idx = 0; idx < NFIFO; idx++) {
2867                 /* read intstatus register and ignore any non-error bits */
2868                 intstatus =
2869                     R_REG(wlc_hw->osh,
2870                           &regs->intctrlregs[idx].intstatus) & I_ERRORS;
2871                 if (!intstatus)
2872                         continue;
2873
2874                 WL_TRACE("wl%d: wlc_bmac_fifoerrors: intstatus%d 0x%x\n",
2875                          unit, idx, intstatus);
2876
2877                 if (intstatus & I_RO) {
2878                         WL_ERROR("wl%d: fifo %d: receive fifo overflow\n",
2879                                  unit, idx);
2880                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxoflo);
2881                         fatal = true;
2882                 }
2883
2884                 if (intstatus & I_PC) {
2885                         WL_ERROR("wl%d: fifo %d: descriptor error\n",
2886                                  unit, idx);
2887                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmade);
2888                         fatal = true;
2889                 }
2890
2891                 if (intstatus & I_PD) {
2892                         WL_ERROR("wl%d: fifo %d: data error\n", unit, idx);
2893                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmada);
2894                         fatal = true;
2895                 }
2896
2897                 if (intstatus & I_DE) {
2898                         WL_ERROR("wl%d: fifo %d: descriptor protocol error\n",
2899                                  unit, idx);
2900                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmape);
2901                         fatal = true;
2902                 }
2903
2904                 if (intstatus & I_RU) {
2905                         WL_ERROR("wl%d: fifo %d: receive descriptor underflow\n",
2906                                  idx, unit);
2907                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxuflo[idx]);
2908                 }
2909
2910                 if (intstatus & I_XU) {
2911                         WL_ERROR("wl%d: fifo %d: transmit fifo underflow\n",
2912                                  idx, unit);
2913                         WLCNTINCR(wlc_hw->wlc->pub->_cnt->txuflo);
2914                         fatal = true;
2915                 }
2916
2917                 if (fatal) {
2918                         wlc_fatal_error(wlc_hw->wlc);   /* big hammer */
2919                         break;
2920                 } else
2921                         W_REG(wlc_hw->osh, &regs->intctrlregs[idx].intstatus,
2922                               intstatus);
2923         }
2924 }
2925
2926 void wlc_intrson(struct wlc_info *wlc)
2927 {
2928         struct wlc_hw_info *wlc_hw = wlc->hw;
2929         ASSERT(wlc->defmacintmask);
2930         wlc->macintmask = wlc->defmacintmask;
2931         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2932 }
2933
2934 /* callback for siutils.c, which has only wlc handler, no wl
2935  * they both check up, not only because there is no need to off/restore d11 interrupt
2936  *  but also because per-port code may require sync with valid interrupt.
2937  */
2938
2939 static u32 wlc_wlintrsoff(struct wlc_info *wlc)
2940 {
2941         if (!wlc->hw->up)
2942                 return 0;
2943
2944         return wl_intrsoff(wlc->wl);
2945 }
2946
2947 static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
2948 {
2949         if (!wlc->hw->up)
2950                 return;
2951
2952         wl_intrsrestore(wlc->wl, macintmask);
2953 }
2954
2955 u32 wlc_intrsoff(struct wlc_info *wlc)
2956 {
2957         struct wlc_hw_info *wlc_hw = wlc->hw;
2958         u32 macintmask;
2959
2960         if (!wlc_hw->clk)
2961                 return 0;
2962
2963         macintmask = wlc->macintmask;   /* isr can still happen */
2964
2965         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, 0);
2966         (void)R_REG(wlc_hw->osh, &wlc_hw->regs->macintmask);    /* sync readback */
2967         udelay(1);              /* ensure int line is no longer driven */
2968         wlc->macintmask = 0;
2969
2970         /* return previous macintmask; resolve race between us and our isr */
2971         return wlc->macintstatus ? 0 : macintmask;
2972 }
2973
2974 void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
2975 {
2976         struct wlc_hw_info *wlc_hw = wlc->hw;
2977         if (!wlc_hw->clk)
2978                 return;
2979
2980         wlc->macintmask = macintmask;
2981         W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2982 }
2983
2984 void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
2985 {
2986         u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2987
2988         if (on) {
2989                 /* suspend tx fifos */
2990                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2991                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2992                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2993                 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2994
2995                 /* zero the address match register so we do not send ACKs */
2996                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2997                                        null_ether_addr);
2998         } else {
2999                 /* resume tx fifos */
3000                 if (!wlc_hw->wlc->tx_suspended) {
3001                         wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
3002                 }
3003                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
3004                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
3005                 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
3006
3007                 /* Restore address */
3008                 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
3009                                        wlc_hw->etheraddr);
3010         }
3011
3012         wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
3013
3014         if (on)
3015                 wlc_ucode_mute_override_set(wlc_hw);
3016         else
3017                 wlc_ucode_mute_override_clear(wlc_hw);
3018 }
3019
3020 int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
3021 {
3022         if (fifo >= NFIFO)
3023                 return BCME_RANGE;
3024
3025         *blocks = wlc_hw->xmtfifo_sz[fifo];
3026
3027         return 0;
3028 }
3029
3030 /* wlc_bmac_tx_fifo_suspended:
3031  * Check the MAC's tx suspend status for a tx fifo.
3032  *
3033  * When the MAC acknowledges a tx suspend, it indicates that no more
3034  * packets will be transmitted out the radio. This is independent of
3035  * DMA channel suspension---the DMA may have finished suspending, or may still
3036  * be pulling data into a tx fifo, by the time the MAC acks the suspend
3037  * request.
3038  */
3039 bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
3040 {
3041         /* check that a suspend has been requested and is no longer pending */
3042
3043         /*
3044          * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
3045          * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
3046          * chnstatus register.
3047          * The tx fifo suspend completion is independent of the DMA suspend completion and
3048          *   may be acked before or after the DMA is suspended.
3049          */
3050         if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
3051             (R_REG(wlc_hw->osh, &wlc_hw->regs->chnstatus) &
3052              (1 << tx_fifo)) == 0)
3053                 return true;
3054
3055         return false;
3056 }
3057
3058 void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
3059 {
3060         u8 fifo = 1 << tx_fifo;
3061
3062         /* Two clients of this code, 11h Quiet period and scanning. */
3063
3064         /* only suspend if not already suspended */
3065         if ((wlc_hw->suspended_fifos & fifo) == fifo)
3066                 return;
3067
3068         /* force the core awake only if not already */
3069         if (wlc_hw->suspended_fifos == 0)
3070                 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
3071
3072         wlc_hw->suspended_fifos |= fifo;
3073
3074         if (wlc_hw->di[tx_fifo]) {
3075                 /* Suspending AMPDU transmissions in the middle can cause underflow
3076                  * which may result in mismatch between ucode and driver
3077                  * so suspend the mac before suspending the FIFO
3078                  */
3079                 if (WLC_PHY_11N_CAP(wlc_hw->band))
3080                         wlc_suspend_mac_and_wait(wlc_hw->wlc);
3081
3082                 dma_txsuspend(wlc_hw->di[tx_fifo]);
3083
3084                 if (WLC_PHY_11N_CAP(wlc_hw->band))
3085                         wlc_enable_mac(wlc_hw->wlc);
3086         }
3087 }
3088
3089 void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
3090 {
3091         /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
3092          * here for PIO otherwise the watchdog will catch the inconsistency and fire
3093          */
3094         /* Two clients of this code, 11h Quiet period and scanning. */
3095         if (wlc_hw->di[tx_fifo])
3096                 dma_txresume(wlc_hw->di[tx_fifo]);
3097
3098         /* allow core to sleep again */
3099         if (wlc_hw->suspended_fifos == 0)
3100                 return;
3101         else {
3102                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
3103                 if (wlc_hw->suspended_fifos == 0)
3104                         wlc_ucode_wake_override_clear(wlc_hw,
3105                                                       WLC_WAKE_OVERRIDE_TXFIFO);
3106         }
3107 }
3108
3109 /*
3110  * Read and clear macintmask and macintstatus and intstatus registers.
3111  * This routine should be called with interrupts off
3112  * Return:
3113  *   -1 if DEVICEREMOVED(wlc) evaluates to true;
3114  *   0 if the interrupt is not for us, or we are in some special cases;
3115  *   device interrupt status bits otherwise.
3116  */
3117 static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
3118 {
3119         struct wlc_hw_info *wlc_hw = wlc->hw;
3120         d11regs_t *regs = wlc_hw->regs;
3121         u32 macintstatus;
3122         u32 intstatus_rxfifo, intstatus_txsfifo;
3123         struct osl_info *osh;
3124
3125         osh = wlc_hw->osh;
3126
3127         /* macintstatus includes a DMA interrupt summary bit */
3128         macintstatus = R_REG(osh, &regs->macintstatus);
3129
3130         WL_TRACE("wl%d: macintstatus: 0x%x\n", wlc_hw->unit, macintstatus);
3131
3132         /* detect cardbus removed, in power down(suspend) and in reset */
3133         if (DEVICEREMOVED(wlc))
3134                 return -1;
3135
3136         /* DEVICEREMOVED succeeds even when the core is still resetting,
3137          * handle that case here.
3138          */
3139         if (macintstatus == 0xffffffff)
3140                 return 0;
3141
3142         /* defer unsolicited interrupts */
3143         macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
3144
3145         /* if not for us */
3146         if (macintstatus == 0)
3147                 return 0;
3148
3149         /* interrupts are already turned off for CFE build
3150          * Caution: For CFE Turning off the interrupts again has some undesired
3151          * consequences
3152          */
3153         /* turn off the interrupts */
3154         W_REG(osh, &regs->macintmask, 0);
3155         (void)R_REG(osh, &regs->macintmask);    /* sync readback */
3156         wlc->macintmask = 0;
3157
3158         /* clear device interrupts */
3159         W_REG(osh, &regs->macintstatus, macintstatus);
3160
3161         /* MI_DMAINT is indication of non-zero intstatus */
3162         if (macintstatus & MI_DMAINT) {
3163                 if (D11REV_IS(wlc_hw->corerev, 4)) {
3164                         intstatus_rxfifo =
3165                             R_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus);
3166                         intstatus_txsfifo =
3167                             R_REG(osh,
3168                                   &regs->intctrlregs[RX_TXSTATUS_FIFO].
3169                                   intstatus);
3170                         WL_TRACE("wl%d: intstatus_rxfifo 0x%x, intstatus_txsfifo 0x%x\n",
3171                                  wlc_hw->unit,
3172                                  intstatus_rxfifo, intstatus_txsfifo);
3173
3174                         /* defer unsolicited interrupt hints */
3175                         intstatus_rxfifo &= DEF_RXINTMASK;
3176                         intstatus_txsfifo &= DEF_RXINTMASK;
3177
3178                         /* MI_DMAINT bit in macintstatus is indication of RX_FIFO interrupt */
3179                         /* clear interrupt hints */
3180                         if (intstatus_rxfifo)
3181                                 W_REG(osh,
3182                                       &regs->intctrlregs[RX_FIFO].intstatus,
3183                                       intstatus_rxfifo);
3184                         else
3185                                 macintstatus &= ~MI_DMAINT;
3186
3187                         /* MI_TFS bit in macintstatus is encoding of RX_TXSTATUS_FIFO interrupt */
3188                         if (intstatus_txsfifo) {
3189                                 W_REG(osh,
3190                                       &regs->intctrlregs[RX_TXSTATUS_FIFO].
3191                                       intstatus, intstatus_txsfifo);
3192                                 macintstatus |= MI_TFS;
3193                         }
3194                 } else {
3195                         /*
3196                          * For corerevs >= 5, only fifo interrupt enabled is I_RI in RX_FIFO.
3197                          * If MI_DMAINT is set, assume it is set and clear the interrupt.
3198                          */
3199                         W_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus,
3200                               DEF_RXINTMASK);
3201                 }
3202         }
3203
3204         return macintstatus;
3205 }
3206
3207 /* Update wlc->macintstatus and wlc->intstatus[]. */
3208 /* Return true if they are updated successfully. false otherwise */
3209 bool wlc_intrsupd(struct wlc_info *wlc)
3210 {
3211         u32 macintstatus;
3212
3213         ASSERT(wlc->macintstatus != 0);
3214
3215         /* read and clear macintstatus and intstatus registers */
3216         macintstatus = wlc_intstatus(wlc, false);
3217
3218         /* device is removed */
3219         if (macintstatus == 0xffffffff)
3220                 return false;
3221
3222         /* update interrupt status in software */
3223         wlc->macintstatus |= macintstatus;
3224
3225         return true;
3226 }
3227
3228 /*
3229  * First-level interrupt processing.
3230  * Return true if this was our interrupt, false otherwise.
3231  * *wantdpc will be set to true if further wlc_dpc() processing is required,
3232  * false otherwise.
3233  */
3234 bool BCMFASTPATH wlc_isr(struct wlc_info *wlc, bool *wantdpc)
3235 {
3236         struct wlc_hw_info *wlc_hw = wlc->hw;
3237         u32 macintstatus;
3238
3239         *wantdpc = false;
3240
3241         if (!wlc_hw->up || !wlc->macintmask)
3242                 return false;
3243
3244         /* read and clear macintstatus and intstatus registers */
3245         macintstatus = wlc_intstatus(wlc, true);
3246
3247         if (macintstatus == 0xffffffff)
3248                 WL_ERROR("DEVICEREMOVED detected in the ISR code path\n");
3249
3250         /* it is not for us */
3251         if (macintstatus == 0)
3252                 return false;
3253
3254         *wantdpc = true;
3255
3256         /* save interrupt status bits */
3257         ASSERT(wlc->macintstatus == 0);
3258         wlc->macintstatus = macintstatus;
3259
3260         return true;
3261
3262 }
3263
3264 /* process tx completion events for corerev < 5 */
3265 static bool wlc_bmac_txstatus_corerev4(struct wlc_hw_info *wlc_hw)
3266 {
3267         struct sk_buff *status_p;
3268         tx_status_t *txs;
3269         struct osl_info *osh;
3270         bool fatal = false;
3271
3272         WL_TRACE("wl%d: wlc_txstatusrecv\n", wlc_hw->unit);
3273
3274         osh = wlc_hw->osh;
3275
3276         while (!fatal && (status_p = dma_rx(wlc_hw->di[RX_TXSTATUS_FIFO]))) {
3277
3278                 txs = (tx_status_t *) status_p->data;
3279                 /* MAC uses little endian only */
3280                 ltoh16_buf((void *)txs, sizeof(tx_status_t));
3281
3282                 /* shift low bits for tx_status_t status compatibility */
3283                 txs->status = (txs->status & ~TXS_COMPAT_MASK)
3284                     | (((txs->status & TXS_COMPAT_MASK) << TXS_COMPAT_SHIFT));
3285
3286                 fatal = wlc_bmac_dotxstatus(wlc_hw, txs, 0);
3287
3288                 pkt_buf_free_skb(osh, status_p, false);
3289         }
3290
3291         if (fatal)
3292                 return true;
3293
3294         /* post more rbufs */
3295         dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
3296
3297         return false;
3298 }
3299
3300 static bool BCMFASTPATH
3301 wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
3302 {
3303         /* discard intermediate indications for ucode with one legitimate case:
3304          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
3305          *   tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
3306          *   transmission count)
3307          */
3308         if (!(txs->status & TX_STATUS_AMPDU)
3309             && (txs->status & TX_STATUS_INTERMEDIATE)) {
3310                 return false;
3311         }
3312
3313         return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
3314 }
3315
3316 /* process tx completion events in BMAC
3317  * Return true if more tx status need to be processed. false otherwise.
3318  */
3319 static bool BCMFASTPATH
3320 wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
3321 {
3322         bool morepending = false;
3323         struct wlc_info *wlc = wlc_hw->wlc;
3324
3325         WL_TRACE("wl%d: wlc_bmac_txstatus\n", wlc_hw->unit);
3326
3327         if (D11REV_IS(wlc_hw->corerev, 4)) {
3328                 /* to retire soon */
3329                 *fatal = wlc_bmac_txstatus_corerev4(wlc->hw);
3330
3331                 if (*fatal)
3332                         return 0;
3333         } else {
3334                 /* corerev >= 5 */
3335                 d11regs_t *regs;
3336                 struct osl_info *osh;
3337                 tx_status_t txstatus, *txs;
3338                 u32 s1, s2;
3339                 uint n = 0;
3340                 /* Param 'max_tx_num' indicates max. # tx status to process before break out. */
3341                 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3342
3343                 txs = &txstatus;
3344                 regs = wlc_hw->regs;
3345                 osh = wlc_hw->osh;
3346                 while (!(*fatal)
3347                        && (s1 = R_REG(osh, &regs->frmtxstatus)) & TXS_V) {
3348
3349                         if (s1 == 0xffffffff) {
3350                                 WL_ERROR("wl%d: %s: dead chip\n",
3351                                          wlc_hw->unit, __func__);
3352                                 ASSERT(s1 != 0xffffffff);
3353                                 return morepending;
3354                         }
3355
3356                         s2 = R_REG(osh, &regs->frmtxstatus2);
3357
3358                         txs->status = s1 & TXS_STATUS_MASK;
3359                         txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3360                         txs->sequence = s2 & TXS_SEQ_MASK;
3361                         txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3362                         txs->lasttxtime = 0;
3363
3364                         *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3365
3366                         /* !give others some time to run! */
3367                         if (++n >= max_tx_num)
3368                                 break;
3369                 }
3370
3371                 if (*fatal)
3372                         return 0;
3373
3374                 if (n >= max_tx_num)
3375                         morepending = true;
3376         }
3377
3378         if (!pktq_empty(&wlc->active_queue->q))
3379                 wlc_send_q(wlc, wlc->active_queue);
3380
3381         return morepending;
3382 }
3383
3384 void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
3385 {
3386         struct wlc_hw_info *wlc_hw = wlc->hw;
3387         d11regs_t *regs = wlc_hw->regs;
3388         u32 mc, mi;
3389         struct osl_info *osh;
3390
3391         WL_TRACE("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n",
3392                  wlc_hw->unit, wlc_hw->band->bandunit);
3393
3394         /*
3395          * Track overlapping suspend requests
3396          */
3397         wlc_hw->mac_suspend_depth++;
3398         if (wlc_hw->mac_suspend_depth > 1)
3399                 return;
3400
3401         osh = wlc_hw->osh;
3402
3403         /* force the core awake */
3404         wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3405
3406         mc = R_REG(osh, &regs->maccontrol);
3407
3408         if (mc == 0xffffffff) {
3409                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3410                 wl_down(wlc->wl);
3411                 return;
3412         }
3413         ASSERT(!(mc & MCTL_PSM_JMP_0));
3414         ASSERT(mc & MCTL_PSM_RUN);
3415         ASSERT(mc & MCTL_EN_MAC);
3416
3417         mi = R_REG(osh, &regs->macintstatus);
3418         if (mi == 0xffffffff) {
3419                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3420                 wl_down(wlc->wl);
3421                 return;
3422         }
3423         ASSERT(!(mi & MI_MACSSPNDD));
3424
3425         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3426
3427         SPINWAIT(!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD),
3428                  WLC_MAX_MAC_SUSPEND);
3429
3430         if (!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD)) {
3431                 WL_ERROR("wl%d: wlc_suspend_mac_and_wait: waited %d uS and MI_MACSSPNDD is still not on.\n",
3432                          wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
3433                 WL_ERROR("wl%d: psmdebug 0x%08x, phydebug 0x%08x, psm_brc 0x%04x\n",
3434                          wlc_hw->unit,
3435                          R_REG(osh, &regs->psmdebug),
3436                          R_REG(osh, &regs->phydebug),
3437                          R_REG(osh, &regs->psm_brc));
3438         }
3439
3440         mc = R_REG(osh, &regs->maccontrol);
3441         if (mc == 0xffffffff) {
3442                 WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
3443                 wl_down(wlc->wl);
3444                 return;
3445         }
3446         ASSERT(!(mc & MCTL_PSM_JMP_0));
3447         ASSERT(mc & MCTL_PSM_RUN);
3448         ASSERT(!(mc & MCTL_EN_MAC));
3449 }
3450
3451 void wlc_enable_mac(struct wlc_info *wlc)
3452 {
3453         struct wlc_hw_info *wlc_hw = wlc->hw;
3454         d11regs_t *regs = wlc_hw->regs;
3455         u32 mc, mi;
3456         struct osl_info *osh;
3457
3458         WL_TRACE("wl%d: wlc_enable_mac: bandunit %d\n",
3459                  wlc_hw->unit, wlc->band->bandunit);
3460
3461         /*
3462          * Track overlapping suspend requests
3463          */
3464         ASSERT(wlc_hw->mac_suspend_depth > 0);
3465         wlc_hw->mac_suspend_depth--;
3466         if (wlc_hw->mac_suspend_depth > 0)
3467                 return;
3468
3469         osh = wlc_hw->osh;
3470
3471         mc = R_REG(osh, &regs->maccontrol);
3472         ASSERT(!(mc & MCTL_PSM_JMP_0));
3473         ASSERT(!(mc & MCTL_EN_MAC));
3474         ASSERT(mc & MCTL_PSM_RUN);
3475
3476         wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3477         W_REG(osh, &regs->macintstatus, MI_MACSSPNDD);
3478
3479         mc = R_REG(osh, &regs->maccontrol);
3480         ASSERT(!(mc & MCTL_PSM_JMP_0));
3481         ASSERT(mc & MCTL_EN_MAC);
3482         ASSERT(mc & MCTL_PSM_RUN);
3483
3484         mi = R_REG(osh, &regs->macintstatus);
3485         ASSERT(!(mi & MI_MACSSPNDD));
3486
3487         wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3488 }
3489
3490 static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
3491 {
3492         u8 rate;
3493         u8 rates[8] = {
3494                 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3495                 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3496         };
3497         u16 entry_ptr;
3498         u16 pctl1;
3499         uint i;
3500
3501         if (!WLC_PHY_11N_CAP(wlc_hw->band))
3502                 return;
3503
3504         /* walk the phy rate table and update the entries */
3505         for (i = 0; i < ARRAY_SIZE(rates); i++) {
3506                 rate = rates[i];
3507
3508                 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3509
3510                 /* read the SHM Rate Table entry OFDM PCTL1 values */
3511                 pctl1 =
3512                     wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3513
3514                 /* modify the value */
3515                 pctl1 &= ~PHY_TXC1_MODE_MASK;
3516                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3517
3518                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3519                 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3520                                    pctl1);
3521         }
3522 }
3523
3524 static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
3525 {
3526         uint i;
3527         u8 plcp_rate = 0;
3528         struct plcp_signal_rate_lookup {
3529                 u8 rate;
3530                 u8 signal_rate;
3531         };
3532         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3533         const struct plcp_signal_rate_lookup rate_lookup[] = {
3534                 {WLC_RATE_6M, 0xB},
3535                 {WLC_RATE_9M, 0xF},
3536                 {WLC_RATE_12M, 0xA},
3537                 {WLC_RATE_18M, 0xE},
3538                 {WLC_RATE_24M, 0x9},
3539                 {WLC_RATE_36M, 0xD},
3540                 {WLC_RATE_48M, 0x8},
3541                 {WLC_RATE_54M, 0xC}
3542         };
3543
3544         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3545                 if (rate == rate_lookup[i].rate) {
3546                         plcp_rate = rate_lookup[i].signal_rate;
3547                         break;
3548                 }
3549         }
3550
3551         /* Find the SHM pointer to the rate table entry by looking in the
3552          * Direct-map Table
3553          */
3554         return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3555 }
3556
3557 void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
3558 {
3559         wlc_hw->hw_stf_ss_opmode = stf_mode;
3560
3561         if (wlc_hw->clk)
3562                 wlc_upd_ofdm_pctl1_table(wlc_hw);
3563 }
3564
3565 void BCMFASTPATH
3566 wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
3567                   u32 *tsf_h_ptr)
3568 {
3569         d11regs_t *regs = wlc_hw->regs;
3570
3571         /* read the tsf timer low, then high to get an atomic read */
3572         *tsf_l_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerlow);
3573         *tsf_h_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerhigh);
3574
3575         return;
3576 }
3577
3578 bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
3579 {
3580         d11regs_t *regs;
3581         u32 w, val;
3582         volatile u16 *reg16;
3583         struct osl_info *osh;
3584
3585         WL_TRACE("wl%d: validate_chip_access\n", wlc_hw->unit);
3586
3587         regs = wlc_hw->regs;
3588         osh = wlc_hw->osh;
3589
3590         /* Validate dchip register access */
3591
3592         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3593         (void)R_REG(osh, &regs->objaddr);
3594         w = R_REG(osh, &regs->objdata);
3595
3596         /* Can we write and read back a 32bit register? */
3597         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3598         (void)R_REG(osh, &regs->objaddr);
3599         W_REG(osh, &regs->objdata, (u32) 0xaa5555aa);
3600
3601         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3602         (void)R_REG(osh, &regs->objaddr);
3603         val = R_REG(osh, &regs->objdata);
3604         if (val != (u32) 0xaa5555aa) {
3605                 WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n",
3606                          wlc_hw->unit, val);
3607                 return false;
3608         }
3609
3610         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3611         (void)R_REG(osh, &regs->objaddr);
3612         W_REG(osh, &regs->objdata, (u32) 0x55aaaa55);
3613
3614         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3615         (void)R_REG(osh, &regs->objaddr);
3616         val = R_REG(osh, &regs->objdata);
3617         if (val != (u32) 0x55aaaa55) {
3618                 WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n",
3619                          wlc_hw->unit, val);
3620                 return false;
3621         }
3622
3623         W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3624         (void)R_REG(osh, &regs->objaddr);
3625         W_REG(osh, &regs->objdata, w);
3626
3627         if (D11REV_LT(wlc_hw->corerev, 11)) {
3628                 /* if 32 bit writes are split into 16 bit writes, are they in the correct order
3629                  * for our interface, low to high
3630                  */
3631                 reg16 = (volatile u16 *)&regs->tsf_cfpstart;
3632
3633                 /* write the CFPStart register low half explicitly, starting a buffered write */
3634                 W_REG(osh, reg16, 0xAAAA);
3635
3636                 /* Write a 32 bit value to CFPStart to test the 16 bit split order.
3637                  * If the low 16 bits are written first, followed by the high 16 bits then the
3638                  * 32 bit value 0xCCCCBBBB should end up in the register.
3639                  * If the order is reversed, then the write to the high half will trigger a buffered
3640                  * write of 0xCCCCAAAA.
3641                  * If the bus is 32 bits, then this is not much of a test, and the reg should
3642                  * have the correct value 0xCCCCBBBB.
3643                  */
3644                 W_REG(osh, &regs->tsf_cfpstart, 0xCCCCBBBB);
3645
3646                 /* verify with the 16 bit registers that have no side effects */
3647                 val = R_REG(osh, &regs->tsf_cfpstrt_l);
3648                 if (val != (uint) 0xBBBB) {
3649                         WL_ERROR("wl%d: validate_chip_access: tsf_cfpstrt_l = 0x%x, expected 0x%x\n",
3650                                  wlc_hw->unit, val, 0xBBBB);
3651                         return false;
3652                 }
3653                 val = R_REG(osh, &regs->tsf_cfpstrt_h);
3654                 if (val != (uint) 0xCCCC) {
3655                         WL_ERROR("wl%d: validate_chip_access: tsf_cfpstrt_h = 0x%x, expected 0x%x\n",
3656                                  wlc_hw->unit, val, 0xCCCC);
3657                         return false;
3658                 }
3659
3660         }
3661
3662         /* clear CFPStart */
3663         W_REG(osh, &regs->tsf_cfpstart, 0);
3664
3665         w = R_REG(osh, &regs->maccontrol);
3666         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3667             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3668                 WL_ERROR("wl%d: validate_chip_access: maccontrol = 0x%x, expected 0x%x or 0x%x\n",
3669                          wlc_hw->unit, w,
3670                          (MCTL_IHR_EN | MCTL_WAKE),
3671                          (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3672                 return false;
3673         }
3674
3675         return true;
3676 }
3677
3678 #define PHYPLL_WAIT_US  100000
3679
3680 void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
3681 {
3682         d11regs_t *regs;
3683         struct osl_info *osh;
3684         u32 tmp;
3685
3686         WL_TRACE("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit);
3687
3688         tmp = 0;
3689         regs = wlc_hw->regs;
3690         osh = wlc_hw->osh;
3691
3692         if (D11REV_LE(wlc_hw->corerev, 16) || D11REV_IS(wlc_hw->corerev, 20))
3693                 return;
3694
3695         if (on) {
3696                 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3697                         OR_REG(osh, &regs->clk_ctl_st,
3698                                (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3699                                 CCS_ERSRC_REQ_PHYPLL));
3700                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3701                                   (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3702                                  PHYPLL_WAIT_US);
3703
3704                         tmp = R_REG(osh, &regs->clk_ctl_st);
3705                         if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3706                             (CCS_ERSRC_AVAIL_HT)) {
3707                                 WL_ERROR("%s: turn on PHY PLL failed\n",
3708                                          __func__);
3709                                 ASSERT(0);
3710                         }
3711                 } else {
3712                         OR_REG(osh, &regs->clk_ctl_st,
3713                                (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3714                         SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3715                                   (CCS_ERSRC_AVAIL_D11PLL |
3716                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
3717                                  (CCS_ERSRC_AVAIL_D11PLL |
3718                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3719
3720                         tmp = R_REG(osh, &regs->clk_ctl_st);
3721                         if ((tmp &
3722                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3723                             !=
3724                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3725                                 WL_ERROR("%s: turn on PHY PLL failed\n",
3726                                          __func__);
3727                                 ASSERT(0);
3728                         }
3729                 }
3730         } else {
3731                 /* Since the PLL may be shared, other cores can still be requesting it;
3732                  * so we'll deassert the request but not wait for status to comply.
3733                  */
3734                 AND_REG(osh, &regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3735                 tmp = R_REG(osh, &regs->clk_ctl_st);
3736         }
3737 }
3738
3739 void wlc_coredisable(struct wlc_hw_info *wlc_hw)
3740 {
3741         bool dev_gone;
3742
3743         WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
3744
3745         ASSERT(!wlc_hw->up);
3746
3747         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3748
3749         if (dev_gone)
3750                 return;
3751
3752         if (wlc_hw->noreset)
3753                 return;
3754
3755         /* radio off */
3756         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3757
3758         /* turn off analog core */
3759         wlc_phy_anacore(wlc_hw->band->pi, OFF);
3760
3761         /* turn off PHYPLL to save power */
3762         wlc_bmac_core_phypll_ctl(wlc_hw, false);
3763
3764         /* No need to set wlc->pub->radio_active = OFF
3765          * because this function needs down capability and
3766          * radio_active is designed for BCMNODOWN.
3767          */
3768
3769         /* remove gpio controls */
3770         if (wlc_hw->ucode_dbgsel)
3771                 si_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3772
3773         wlc_hw->clk = false;
3774         si_core_disable(wlc_hw->sih, 0);
3775         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3776 }
3777
3778 /* power both the pll and external oscillator on/off */
3779 void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
3780 {
3781         WL_TRACE("wl%d: wlc_bmac_xtal: want %d\n", wlc_hw->unit, want);
3782
3783         /* dont power down if plldown is false or we must poll hw radio disable */
3784         if (!want && wlc_hw->pllreq)
3785                 return;
3786
3787         if (wlc_hw->sih)
3788                 si_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3789
3790         wlc_hw->sbclk = want;
3791         if (!wlc_hw->sbclk) {
3792                 wlc_hw->clk = false;
3793                 if (wlc_hw->band && wlc_hw->band->pi)
3794                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3795         }
3796 }
3797
3798 static void wlc_flushqueues(struct wlc_info *wlc)
3799 {
3800         struct wlc_hw_info *wlc_hw = wlc->hw;
3801         uint i;
3802
3803         wlc->txpend16165war = 0;
3804
3805         /* free any posted tx packets */
3806         for (i = 0; i < NFIFO; i++)
3807                 if (wlc_hw->di[i]) {
3808                         dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3809                         TXPKTPENDCLR(wlc, i);
3810                         WL_TRACE("wlc_flushqueues: pktpend fifo %d cleared\n",
3811                                  i);
3812                 }
3813
3814         /* free any posted rx packets */
3815         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3816         if (D11REV_IS(wlc_hw->corerev, 4))
3817                 dma_rxreclaim(wlc_hw->di[RX_TXSTATUS_FIFO]);
3818 }
3819
3820 u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
3821 {
3822         return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3823 }
3824
3825 void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
3826 {
3827         wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3828 }
3829
3830 /* Set a range of shared memory to a value.
3831  * SHM 'offset' needs to be an even address and
3832  * Buffer length 'len' must be an even number of bytes
3833  */
3834 void wlc_bmac_set_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v, int len)
3835 {
3836         int i;
3837
3838         /* offset and len need to be even */
3839         ASSERT((offset & 1) == 0);
3840         ASSERT((len & 1) == 0);
3841
3842         if (len <= 0)
3843                 return;
3844
3845         for (i = 0; i < len; i += 2) {
3846                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, OBJADDR_SHM_SEL);
3847         }
3848 }
3849
3850 static u16
3851 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
3852 {
3853         d11regs_t *regs = wlc_hw->regs;
3854         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3855         volatile u16 *objdata_hi = objdata_lo + 1;
3856         u16 v;
3857
3858         ASSERT((offset & 1) == 0);
3859
3860         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3861         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3862         if (offset & 2) {
3863                 v = R_REG(wlc_hw->osh, objdata_hi);
3864         } else {
3865                 v = R_REG(wlc_hw->osh, objdata_lo);
3866         }
3867
3868         return v;
3869 }
3870
3871 static void
3872 wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
3873 {
3874         d11regs_t *regs = wlc_hw->regs;
3875         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3876         volatile u16 *objdata_hi = objdata_lo + 1;
3877
3878         ASSERT((offset & 1) == 0);
3879
3880         W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3881         (void)R_REG(wlc_hw->osh, &regs->objaddr);
3882         if (offset & 2) {
3883                 W_REG(wlc_hw->osh, objdata_hi, v);
3884         } else {
3885                 W_REG(wlc_hw->osh, objdata_lo, v);
3886         }
3887 }
3888
3889 /* Copy a buffer to shared memory of specified type .
3890  * SHM 'offset' needs to be an even address and
3891  * Buffer length 'len' must be an even number of bytes
3892  * 'sel' selects the type of memory
3893  */
3894 void
3895 wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
3896                        int len, u32 sel)
3897 {
3898         u16 v;
3899         const u8 *p = (const u8 *)buf;
3900         int i;
3901
3902         /* offset and len need to be even */
3903         ASSERT((offset & 1) == 0);
3904         ASSERT((len & 1) == 0);
3905
3906         if (len <= 0)
3907                 return;
3908
3909         for (i = 0; i < len; i += 2) {
3910                 v = p[i] | (p[i + 1] << 8);
3911                 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3912         }
3913 }
3914
3915 /* Copy a piece of shared memory of specified type to a buffer .
3916  * SHM 'offset' needs to be an even address and
3917  * Buffer length 'len' must be an even number of bytes
3918  * 'sel' selects the type of memory
3919  */
3920 void
3921 wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
3922                          int len, u32 sel)
3923 {
3924         u16 v;
3925         u8 *p = (u8 *) buf;
3926         int i;
3927
3928         /* offset and len need to be even */
3929         ASSERT((offset & 1) == 0);
3930         ASSERT((len & 1) == 0);
3931
3932         if (len <= 0)
3933                 return;
3934
3935         for (i = 0; i < len; i += 2) {
3936                 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
3937                 p[i] = v & 0xFF;
3938                 p[i + 1] = (v >> 8) & 0xFF;
3939         }
3940 }
3941
3942 void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
3943 {
3944         WL_TRACE("wlc_bmac_copyfrom_vars, nvram vars totlen=%d\n",
3945                  wlc_hw->vars_size);
3946
3947         *buf = wlc_hw->vars;
3948         *len = wlc_hw->vars_size;
3949 }
3950
3951 void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
3952 {
3953         wlc_hw->SRL = SRL;
3954         wlc_hw->LRL = LRL;
3955
3956         /* write retry limit to SCR, shouldn't need to suspend */
3957         if (wlc_hw->up) {
3958                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
3959                       OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3960                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
3961                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->SRL);
3962                 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
3963                       OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3964                 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
3965                 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->LRL);
3966         }
3967 }
3968
3969 void wlc_bmac_set_noreset(struct wlc_hw_info *wlc_hw, bool noreset_flag)
3970 {
3971         wlc_hw->noreset = noreset_flag;
3972 }
3973
3974 void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
3975 {
3976         ASSERT(req_bit);
3977
3978         if (set) {
3979                 if (mboolisset(wlc_hw->pllreq, req_bit))
3980                         return;
3981
3982                 mboolset(wlc_hw->pllreq, req_bit);
3983
3984                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3985                         if (!wlc_hw->sbclk) {
3986                                 wlc_bmac_xtal(wlc_hw, ON);
3987                         }
3988                 }
3989         } else {
3990                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3991                         return;
3992
3993                 mboolclr(wlc_hw->pllreq, req_bit);
3994
3995                 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
3996                         if (wlc_hw->sbclk) {
3997                                 wlc_bmac_xtal(wlc_hw, OFF);
3998                         }
3999                 }
4000         }
4001
4002         return;
4003 }
4004
4005 /* this will be true for all ai chips */
4006 bool wlc_bmac_taclear(struct wlc_hw_info *wlc_hw, bool ta_ok)
4007 {
4008         return true;
4009 }
4010
4011 u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
4012 {
4013         u16 table_ptr;
4014         u8 phy_rate, index;
4015
4016         /* get the phy specific rate encoding for the PLCP SIGNAL field */
4017         /* XXX4321 fixup needed ? */
4018         if (IS_OFDM(rate))
4019                 table_ptr = M_RT_DIRMAP_A;
4020         else
4021                 table_ptr = M_RT_DIRMAP_B;
4022
4023         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
4024          * the index into the rate table.
4025          */
4026         phy_rate = rate_info[rate] & RATE_MASK;
4027         index = phy_rate & 0xf;
4028
4029         /* Find the SHM pointer to the rate table entry by looking in the
4030          * Direct-map Table
4031          */
4032         return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
4033 }
4034
4035 void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
4036 {
4037         wlc_hw->antsel_avail = antsel_avail;
4038 }