drivers/staging/brcm80211/brcmsmac/bmac.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16 #include <linux/pci.h>
  17 #include <net/mac80211.h>
  18
  19 #include <brcm_hw_ids.h>
  20 #include <aiutils.h>
  21 #include <chipcommon.h>
  22 #include "types.h"
  23 #include "rate.h"
  24 #include "phy/phy_hal.h"
  25 #include "channel.h"
  26 #include "main.h"
  27 #include "ucode_loader.h"
  28 #include "mac80211_if.h"
  29 #include "bmac.h"
  30
  31 #define TIMER_INTERVAL_WATCHDOG_BMAC    1000    /* watchdog timer, in unit of ms */
  32
  33 #define SYNTHPU_DLY_APHY_US     3700    /* a phy synthpu_dly time in us */
  34 #define SYNTHPU_DLY_BPHY_US     1050    /* b/g phy synthpu_dly time in us, default */
  35 #define SYNTHPU_DLY_NPHY_US     2048    /* n phy REV3 synthpu_dly time in us, default */
  36 #define SYNTHPU_DLY_LPPHY_US    300     /* lpphy synthpu_dly time in us */
  37
  38 #define SYNTHPU_DLY_PHY_US_QT   100     /* QT synthpu_dly time in us */
  39
  40 #ifndef BMAC_DUP_TO_REMOVE
  41
  42 #define ANTCNT                  10      /* vanilla M_MAX_ANTCNT value */
  43
  44 #endif                          /* BMAC_DUP_TO_REMOVE */
  45
  46 #define DMAREG(wlc_hw, direction, fifonum) \
  47         ((direction == DMA_TX) ? \
  48                 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
  49                 (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
  50
  51 #define APHY_SLOT_TIME          9
  52 #define BPHY_SLOT_TIME          20
  53
  54 /*
  55  * The following table lists the buffer memory allocated to xmt fifos in HW.
  56  * the size is in units of 256bytes(one block), total size is HW dependent
  57  * ucode has default fifo partition, sw can overwrite if necessary
  58  *
  59  * This is documented in twiki under the topic UcodeTxFifo. Please ensure
  60  * the twiki is updated before making changes.
  61  */
  62
  63 #define XMTFIFOTBL_STARTREV     20      /* Starting corerev for the fifo size table */
  64
  65 static u16 xmtfifo_sz[][NFIFO] = {
  66         {20, 192, 192, 21, 17, 5},      /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
  67         {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
  68         {20, 192, 192, 21, 17, 5},      /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
  69         {20, 192, 192, 21, 17, 5},      /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
  70         {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
  71 };
  72
  73 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc, uint mode);
  74 static void brcms_b_coreinit(struct brcms_c_info *wlc);
  75
  76 /* used by wlc_wakeucode_init() */
  77 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
  78                             const struct d11init *inits);
  79 static void brcms_ucode_write(struct brcms_hardware *wlc_hw, const u32 ucode[],
  80                             const uint nbytes);
  81 static void brcms_ucode_download(struct brcms_hardware *wlc);
  82 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw);
  83
  84 /* used by brcms_c_dpc() */
  85 static bool brcms_b_dotxstatus(struct brcms_hardware *wlc,
  86                                struct tx_status *txs, u32 s2);
  87 static bool brcms_b_txstatus(struct brcms_hardware *wlc, bool bound,
  88                              bool *fatal);
  89 static bool brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound);
  90
  91 /* used by brcms_c_down() */
  92 static void brcms_c_flushqueues(struct brcms_c_info *wlc);
  93
  94 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs);
  95 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw);
  96 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw);
  97 static bool brcms_b_tx_fifo_suspended(struct brcms_hardware *wlc_hw,
  98                                        uint tx_fifo);
  99 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
 100                                     uint tx_fifo);
 101 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
 102                                    uint tx_fifo);
 103
 104 /* Low Level Prototypes */
 105 static int brcms_b_bandtype(struct brcms_hardware *wlc_hw);
 106 static void brcms_b_info_init(struct brcms_hardware *wlc_hw);
 107 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want);
 108 static u16 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset,
 109                                    u32 sel);
 110 static void brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset,
 111                                   u16 v, u32 sel);
 112 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk);
 113 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme);
 114 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw);
 115 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw);
 116 static bool brcms_c_validboardtype(struct brcms_hardware *wlc);
 117 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw);
 118 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw);
 119 static char *brcms_c_get_macaddr(struct brcms_hardware *wlc_hw);
 120 static void brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init);
 121 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw);
 122 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool want,
 123                          mbool flags);
 124 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw);
 125 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw);
 126 static u32 brcms_c_wlintrsoff(struct brcms_c_info *wlc);
 127 static void brcms_c_wlintrsrestore(struct brcms_c_info *wlc, u32 macintmask);
 128 static void brcms_c_gpio_init(struct brcms_c_info *wlc);
 129 static void brcms_c_write_hw_bcntemplate0(struct brcms_hardware *wlc_hw,
 130                                           void *bcn, int len);
 131 static void brcms_c_write_hw_bcntemplate1(struct brcms_hardware *wlc_hw,
 132                                           void *bcn, int len);
 133 static void brcms_b_bsinit(struct brcms_c_info *wlc, chanspec_t chanspec);
 134 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit);
 135 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
 136                              chanspec_t chanspec);
 137 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
 138                                         bool shortslot);
 139 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw);
 140 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
 141                                              u8 rate);
 142
 143 /* === Low Level functions === */
 144
 145 void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
 146 {
 147         wlc_hw->shortslot = shortslot;
 148
 149         if (BAND_2G(brcms_b_bandtype(wlc_hw)) && wlc_hw->up) {
 150                 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
 151                 brcms_b_update_slot_timing(wlc_hw, shortslot);
 152                 brcms_c_enable_mac(wlc_hw->wlc);
 153         }
 154 }
 155
 156 /*
 157  * Update the slot timing for standard 11b/g (20us slots)
 158  * or shortslot 11g (9us slots)
 159  * The PSM needs to be suspended for this call.
 160  */
 161 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
 162                                         bool shortslot)
 163 {
 164         d11regs_t *regs;
 165
 166         regs = wlc_hw->regs;
 167
 168         if (shortslot) {
 169                 /* 11g short slot: 11a timing */
 170                 W_REG(&regs->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
 171                 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
 172         } else {
 173                 /* 11g long slot: 11b timing */
 174                 W_REG(&regs->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
 175                 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
 176         }
 177 }
 178
 179 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
 180 {
 181         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
 182
 183         /* init microcode host flags */
 184         brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
 185
 186         /* do band-specific ucode IHR, SHM, and SCR inits */
 187         if (D11REV_IS(wlc_hw->corerev, 23)) {
 188                 if (BRCMS_ISNPHY(wlc_hw->band)) {
 189                         brcms_c_write_inits(wlc_hw, d11n0bsinitvals16);
 190                 } else {
 191                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
 192                                   " %d\n", __func__, wlc_hw->unit,
 193                                   wlc_hw->corerev);
 194                 }
 195         } else {
 196                 if (D11REV_IS(wlc_hw->corerev, 24)) {
 197                         if (BRCMS_ISLCNPHY(wlc_hw->band)) {
 198                                 brcms_c_write_inits(wlc_hw,
 199                                                     d11lcn0bsinitvals24);
 200                         } else
 201                                 wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
 202                                           " core rev %d\n", __func__,
 203                                           wlc_hw->unit, wlc_hw->corerev);
 204                 } else {
 205                         wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
 206                                 __func__, wlc_hw->unit, wlc_hw->corerev);
 207                 }
 208         }
 209 }
 210
 211 /* switch to new band but leave it inactive */
 212 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc,
 213                                             uint bandunit)
 214 {
 215         struct brcms_hardware *wlc_hw = wlc->hw;
 216         u32 macintmask;
 217
 218         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
 219
 220         WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
 221
 222         /* disable interrupts */
 223         macintmask = brcms_intrsoff(wlc->wl);
 224
 225         /* radio off */
 226         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
 227
 228         brcms_b_core_phy_clk(wlc_hw, OFF);
 229
 230         brcms_c_setxband(wlc_hw, bandunit);
 231
 232         return macintmask;
 233 }
 234
 235 /* Process received frames */
 236 /*
 237  * Return true if more frames need to be processed. false otherwise.
 238  * Param 'bound' indicates max. # frames to process before break out.
 239  */
 240 static bool
 241 brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
 242 {
 243         struct sk_buff *p;
 244         struct sk_buff *head = NULL;
 245         struct sk_buff *tail = NULL;
 246         uint n = 0;
 247         uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
 248         struct brcms_d11rxhdr *wlc_rxhdr = NULL;
 249
 250         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
 251         /* gather received frames */
 252         while ((p = dma_rx(wlc_hw->di[fifo]))) {
 253
 254                 if (!tail)
 255                         head = tail = p;
 256                 else {
 257                         tail->prev = p;
 258                         tail = p;
 259                 }
 260
 261                 /* !give others some time to run! */
 262                 if (++n >= bound_limit)
 263                         break;
 264         }
 265
 266         /* post more rbufs */
 267         dma_rxfill(wlc_hw->di[fifo]);
 268
 269         /* process each frame */
 270         while ((p = head) != NULL) {
 271                 head = head->prev;
 272                 p->prev = NULL;
 273
 274                 wlc_rxhdr = (struct brcms_d11rxhdr *) p->data;
 275
 276                 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
 277                 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
 278
 279                 brcms_c_recv(wlc_hw->wlc, p);
 280         }
 281
 282         return n >= bound_limit;
 283 }
 284
 285 /* second-level interrupt processing
 286  *   Return true if another dpc needs to be re-scheduled. false otherwise.
 287  *   Param 'bounded' indicates if applicable loops should be bounded.
 288  */
 289 bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
 290 {
 291         u32 macintstatus;
 292         struct brcms_hardware *wlc_hw = wlc->hw;
 293         d11regs_t *regs = wlc_hw->regs;
 294         bool fatal = false;
 295         struct wiphy *wiphy = wlc->wiphy;
 296
 297         if (DEVICEREMOVED(wlc)) {
 298                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
 299                           __func__);
 300                 brcms_down(wlc->wl);
 301                 return false;
 302         }
 303
 304         /* grab and clear the saved software intstatus bits */
 305         macintstatus = wlc->macintstatus;
 306         wlc->macintstatus = 0;
 307
 308         BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
 309                wlc_hw->unit, macintstatus);
 310
 311         WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
 312
 313         /* BCN template is available */
 314         /* ZZZ: Use AP_ACTIVE ? */
 315         if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub))
 316             && (macintstatus & MI_BCNTPL)) {
 317                 brcms_c_update_beacon(wlc);
 318         }
 319
 320         /* tx status */
 321         if (macintstatus & MI_TFS) {
 322                 if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
 323                         wlc->macintstatus |= MI_TFS;
 324                 if (fatal) {
 325                         wiphy_err(wiphy, "MI_TFS: fatal\n");
 326                         goto fatal;
 327                 }
 328         }
 329
 330         if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
 331                 brcms_c_tbtt(wlc);
 332
 333         /* ATIM window end */
 334         if (macintstatus & MI_ATIMWINEND) {
 335                 BCMMSG(wlc->wiphy, "end of ATIM window\n");
 336                 OR_REG(&regs->maccommand, wlc->qvalid);
 337                 wlc->qvalid = 0;
 338         }
 339
 340         /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
 341         if (macintstatus & MI_DMAINT)
 342                 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
 343                         wlc->macintstatus |= MI_DMAINT;
 344
 345         /* TX FIFO suspend/flush completion */
 346         if (macintstatus & MI_TXSTOP)
 347                 brcms_b_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO);
 348
 349         /* noise sample collected */
 350         if (macintstatus & MI_BG_NOISE) {
 351                 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
 352         }
 353
 354         if (macintstatus & MI_GP0) {
 355                 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
 356                         "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
 357
 358                 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
 359                                         __func__, wlc_hw->sih->chip,
 360                                         wlc_hw->sih->chiprev);
 361                 /* big hammer */
 362                 brcms_init(wlc->wl);
 363         }
 364
 365         /* gptimer timeout */
 366         if (macintstatus & MI_TO) {
 367                 W_REG(&regs->gptimer, 0);
 368         }
 369
 370         if (macintstatus & MI_RFDISABLE) {
 371                 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
 372                        " RF Disable Input\n", wlc_hw->unit);
 373                 brcms_rfkill_set_hw_state(wlc->wl);
 374         }
 375
 376         /* send any enq'd tx packets. Just makes sure to jump start tx */
 377         if (!pktq_empty(&wlc->pkt_queue->q))
 378                 brcms_c_send_q(wlc);
 379
 380         /* it isn't done and needs to be resched if macintstatus is non-zero */
 381         return wlc->macintstatus != 0;
 382
 383  fatal:
 384         brcms_init(wlc->wl);
 385         return wlc->macintstatus != 0;
 386 }
 387
 388 /* common low-level watchdog code */
 389 void brcms_b_watchdog(void *arg)
 390 {
 391         struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
 392         struct brcms_hardware *wlc_hw = wlc->hw;
 393
 394         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
 395
 396         if (!wlc_hw->up)
 397                 return;
 398
 399         /* increment second count */
 400         wlc_hw->now++;
 401
 402         /* Check for FIFO error interrupts */
 403         brcms_b_fifoerrors(wlc_hw);
 404
 405         /* make sure RX dma has buffers */
 406         dma_rxfill(wlc->hw->di[RX_FIFO]);
 407
 408         wlc_phy_watchdog(wlc_hw->band->pi);
 409 }
 410
 411 void
 412 brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, chanspec_t chanspec,
 413                       bool mute, struct txpwr_limits *txpwr)
 414 {
 415         uint bandunit;
 416
 417         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
 418
 419         wlc_hw->chanspec = chanspec;
 420
 421         /* Switch bands if necessary */
 422         if (NBANDS_HW(wlc_hw) > 1) {
 423                 bandunit = CHSPEC_BANDUNIT(chanspec);
 424                 if (wlc_hw->band->bandunit != bandunit) {
 425                         /* brcms_b_setband disables other bandunit,
 426                          *  use light band switch if not up yet
 427                          */
 428                         if (wlc_hw->up) {
 429                                 wlc_phy_chanspec_radio_set(wlc_hw->
 430                                                            bandstate[bandunit]->
 431                                                            pi, chanspec);
 432                                 brcms_b_setband(wlc_hw, bandunit, chanspec);
 433                         } else {
 434                                 brcms_c_setxband(wlc_hw, bandunit);
 435                         }
 436                 }
 437         }
 438
 439         wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
 440
 441         if (!wlc_hw->up) {
 442                 if (wlc_hw->clk)
 443                         wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
 444                                                   chanspec);
 445                 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
 446         } else {
 447                 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
 448                 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
 449
 450                 /* Update muting of the channel */
 451                 brcms_b_mute(wlc_hw, mute, 0);
 452         }
 453 }
 454
 455 int brcms_b_state_get(struct brcms_hardware *wlc_hw,
 456                       struct brcms_b_state *state)
 457 {
 458         state->machwcap = wlc_hw->machwcap;
 459
 460         return 0;
 461 }
 462
 463 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
 464 {
 465         uint i;
 466         char name[8];
 467         /* ucode host flag 2 needed for pio mode, independent of band and fifo */
 468         u16 pio_mhf2 = 0;
 469         struct brcms_hardware *wlc_hw = wlc->hw;
 470         uint unit = wlc_hw->unit;
 471         struct brcms_tunables *tune = wlc->pub->tunables;
 472         struct wiphy *wiphy = wlc->wiphy;
 473
 474         /* name and offsets for dma_attach */
 475         snprintf(name, sizeof(name), "wl%d", unit);
 476
 477         if (wlc_hw->di[0] == 0) {       /* Init FIFOs */
 478                 uint addrwidth;
 479                 int dma_attach_err = 0;
 480                 /* Find out the DMA addressing capability and let OS know
 481                  * All the channels within one DMA core have 'common-minimum' same
 482                  * capability
 483                  */
 484                 addrwidth =
 485                     dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
 486
 487                 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
 488                         wiphy_err(wiphy, "wl%d: wlc_attach: alloc_dma_"
 489                                   "resources failed\n", unit);
 490                         return false;
 491                 }
 492
 493                 /*
 494                  * FIFO 0
 495                  * TX: TX_AC_BK_FIFO (TX AC Background data packets)
 496                  * RX: RX_FIFO (RX data packets)
 497                  */
 498                 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih,
 499                                            (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
 500                                             NULL), DMAREG(wlc_hw, DMA_RX, 0),
 501                                            (wme ? tune->ntxd : 0), tune->nrxd,
 502                                            tune->rxbufsz, -1, tune->nrxbufpost,
 503                                            BRCMS_HWRXOFF, &brcm_msg_level);
 504                 dma_attach_err |= (NULL == wlc_hw->di[0]);
 505
 506                 /*
 507                  * FIFO 1
 508                  * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
 509                  *   (legacy) TX_DATA_FIFO (TX data packets)
 510                  * RX: UNUSED
 511                  */
 512                 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
 513                                            DMAREG(wlc_hw, DMA_TX, 1), NULL,
 514                                            tune->ntxd, 0, 0, -1, 0, 0,
 515                                            &brcm_msg_level);
 516                 dma_attach_err |= (NULL == wlc_hw->di[1]);
 517
 518                 /*
 519                  * FIFO 2
 520                  * TX: TX_AC_VI_FIFO (TX AC Video data packets)
 521                  * RX: UNUSED
 522                  */
 523                 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
 524                                            DMAREG(wlc_hw, DMA_TX, 2), NULL,
 525                                            tune->ntxd, 0, 0, -1, 0, 0,
 526                                            &brcm_msg_level);
 527                 dma_attach_err |= (NULL == wlc_hw->di[2]);
 528                 /*
 529                  * FIFO 3
 530                  * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
 531                  *   (legacy) TX_CTL_FIFO (TX control & mgmt packets)
 532                  */
 533                 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
 534                                            DMAREG(wlc_hw, DMA_TX, 3),
 535                                            NULL, tune->ntxd, 0, 0, -1,
 536                                            0, 0, &brcm_msg_level);
 537                 dma_attach_err |= (NULL == wlc_hw->di[3]);
 538 /* Cleaner to leave this as if with AP defined */
 539
 540                 if (dma_attach_err) {
 541                         wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
 542                                   "\n", unit);
 543                         return false;
 544                 }
 545
 546                 /* get pointer to dma engine tx flow control variable */
 547                 for (i = 0; i < NFIFO; i++)
 548                         if (wlc_hw->di[i])
 549                                 wlc_hw->txavail[i] =
 550                                     (uint *) dma_getvar(wlc_hw->di[i],
 551                                                         "&txavail");
 552         }
 553
 554         /* initial ucode host flags */
 555         brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
 556
 557         return true;
 558 }
 559
 560 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
 561 {
 562         uint j;
 563
 564         for (j = 0; j < NFIFO; j++) {
 565                 if (wlc_hw->di[j]) {
 566                         dma_detach(wlc_hw->di[j]);
 567                         wlc_hw->di[j] = NULL;
 568                 }
 569         }
 570 }
 571
 572 /* low level attach
 573  *    run backplane attach, init nvram
 574  *    run phy attach
 575  *    initialize software state for each core and band
 576  *    put the whole chip in reset(driver down state), no clock
 577  */
 578 int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device, uint unit,
 579                     bool piomode, void *regsva, uint bustype, void *btparam)
 580 {
 581         struct brcms_hardware *wlc_hw;
 582         d11regs_t *regs;
 583         char *macaddr = NULL;
 584         char *vars;
 585         uint err = 0;
 586         uint j;
 587         bool wme = false;
 588         struct shared_phy_params sha_params;
 589         struct wiphy *wiphy = wlc->wiphy;
 590
 591         BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, vendor,
 592                 device);
 593
 594         wme = true;
 595
 596         wlc_hw = wlc->hw;
 597         wlc_hw->wlc = wlc;
 598         wlc_hw->unit = unit;
 599         wlc_hw->band = wlc_hw->bandstate[0];
 600         wlc_hw->_piomode = piomode;
 601
 602         /* populate struct brcms_hardware with default values  */
 603         brcms_b_info_init(wlc_hw);
 604
 605         /*
 606          * Do the hardware portion of the attach.
 607          * Also initialize software state that depends on the particular hardware
 608          * we are running.
 609          */
 610         wlc_hw->sih = ai_attach(regsva, bustype, btparam,
 611                                 &wlc_hw->vars, &wlc_hw->vars_size);
 612         if (wlc_hw->sih == NULL) {
 613                 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
 614                           unit);
 615                 err = 11;
 616                 goto fail;
 617         }
 618         vars = wlc_hw->vars;
 619
 620         /*
 621          * Get vendid/devid nvram overwrites, which could be different
 622          * than those the BIOS recognizes for devices on PCMCIA_BUS,
 623          * SDIO_BUS, and SROMless devices on PCI_BUS.
 624          */
 625 #ifdef BCMBUSTYPE
 626         bustype = BCMBUSTYPE;
 627 #endif
 628         if (bustype != SI_BUS) {
 629                 char *var;
 630
 631                 var = getvar(vars, "vendid");
 632                 if (var) {
 633                         vendor = (u16) simple_strtoul(var, NULL, 0);
 634                         wiphy_err(wiphy, "Overriding vendor id = 0x%x\n",
 635                                   vendor);
 636                 }
 637                 var = getvar(vars, "devid");
 638                 if (var) {
 639                         u16 devid = (u16) simple_strtoul(var, NULL, 0);
 640                         if (devid != 0xffff) {
 641                                 device = devid;
 642                                 wiphy_err(wiphy, "Overriding device id = 0x%x"
 643                                           "\n", device);
 644                         }
 645                 }
 646
 647                 /* verify again the device is supported */
 648                 if (!brcms_c_chipmatch(vendor, device)) {
 649                         wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported "
 650                                 "vendor/device (0x%x/0x%x)\n",
 651                                  unit, vendor, device);
 652                         err = 12;
 653                         goto fail;
 654                 }
 655         }
 656
 657         wlc_hw->vendorid = vendor;
 658         wlc_hw->deviceid = device;
 659
 660         /* set bar0 window to point at D11 core */
 661         wlc_hw->regs = (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
 662         wlc_hw->corerev = ai_corerev(wlc_hw->sih);
 663
 664         regs = wlc_hw->regs;
 665
 666         wlc->regs = wlc_hw->regs;
 667
 668         /* validate chip, chiprev and corerev */
 669         if (!brcms_c_isgoodchip(wlc_hw)) {
 670                 err = 13;
 671                 goto fail;
 672         }
 673
 674         /* initialize power control registers */
 675         ai_clkctl_init(wlc_hw->sih);
 676
 677         /* request fastclock and force fastclock for the rest of attach
 678          * bring the d11 core out of reset.
 679          *   For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
 680          *   But it will be called again inside wlc_corereset, after d11 is out of reset.
 681          */
 682         brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
 683         brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
 684
 685         if (!brcms_b_validate_chip_access(wlc_hw)) {
 686                 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
 687                         "failed\n", unit);
 688                 err = 14;
 689                 goto fail;
 690         }
 691
 692         /* get the board rev, used just below */
 693         j = getintvar(vars, "boardrev");
 694         /* promote srom boardrev of 0xFF to 1 */
 695         if (j == BOARDREV_PROMOTABLE)
 696                 j = BOARDREV_PROMOTED;
 697         wlc_hw->boardrev = (u16) j;
 698         if (!brcms_c_validboardtype(wlc_hw)) {
 699                 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
 700                         "board type (0x%x)" " or revision level (0x%x)\n",
 701                          unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
 702                 err = 15;
 703                 goto fail;
 704         }
 705         wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
 706         wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
 707         wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
 708
 709         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
 710                 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
 711
 712         if ((wlc_hw->sih->bustype == PCI_BUS)
 713             && (ai_pci_war16165(wlc_hw->sih)))
 714                 wlc->war16165 = true;
 715
 716         /* check device id(srom, nvram etc.) to set bands */
 717         if (wlc_hw->deviceid == BCM43224_D11N_ID ||
 718             wlc_hw->deviceid == BCM43224_D11N_ID_VEN1) {
 719                 /* Dualband boards */
 720                 wlc_hw->_nbands = 2;
 721         } else
 722                 wlc_hw->_nbands = 1;
 723
 724         if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
 725                 wlc_hw->_nbands = 1;
 726
 727         /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
 728          * unconditionally does the init of these values
 729          */
 730         wlc->vendorid = wlc_hw->vendorid;
 731         wlc->deviceid = wlc_hw->deviceid;
 732         wlc->pub->sih = wlc_hw->sih;
 733         wlc->pub->corerev = wlc_hw->corerev;
 734         wlc->pub->sromrev = wlc_hw->sromrev;
 735         wlc->pub->boardrev = wlc_hw->boardrev;
 736         wlc->pub->boardflags = wlc_hw->boardflags;
 737         wlc->pub->boardflags2 = wlc_hw->boardflags2;
 738         wlc->pub->_nbands = wlc_hw->_nbands;
 739
 740         wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
 741
 742         if (wlc_hw->physhim == NULL) {
 743                 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
 744                         "failed\n", unit);
 745                 err = 25;
 746                 goto fail;
 747         }
 748
 749         /* pass all the parameters to wlc_phy_shared_attach in one struct */
 750         sha_params.sih = wlc_hw->sih;
 751         sha_params.physhim = wlc_hw->physhim;
 752         sha_params.unit = unit;
 753         sha_params.corerev = wlc_hw->corerev;
 754         sha_params.vars = vars;
 755         sha_params.vid = wlc_hw->vendorid;
 756         sha_params.did = wlc_hw->deviceid;
 757         sha_params.chip = wlc_hw->sih->chip;
 758         sha_params.chiprev = wlc_hw->sih->chiprev;
 759         sha_params.chippkg = wlc_hw->sih->chippkg;
 760         sha_params.sromrev = wlc_hw->sromrev;
 761         sha_params.boardtype = wlc_hw->sih->boardtype;
 762         sha_params.boardrev = wlc_hw->boardrev;
 763         sha_params.boardvendor = wlc_hw->sih->boardvendor;
 764         sha_params.boardflags = wlc_hw->boardflags;
 765         sha_params.boardflags2 = wlc_hw->boardflags2;
 766         sha_params.bustype = wlc_hw->sih->bustype;
 767         sha_params.buscorerev = wlc_hw->sih->buscorerev;
 768
 769         /* alloc and save pointer to shared phy state area */
 770         wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
 771         if (!wlc_hw->phy_sh) {
 772                 err = 16;
 773                 goto fail;
 774         }
 775
 776         /* initialize software state for each core and band */
 777         for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
 778                 /*
 779                  * band0 is always 2.4Ghz
 780                  * band1, if present, is 5Ghz
 781                  */
 782
 783                 /* So if this is a single band 11a card, use band 1 */
 784                 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
 785                         j = BAND_5G_INDEX;
 786
 787                 brcms_c_setxband(wlc_hw, j);
 788
 789                 wlc_hw->band->bandunit = j;
 790                 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
 791                 wlc->band->bandunit = j;
 792                 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
 793                 wlc->core->coreidx = ai_coreidx(wlc_hw->sih);
 794
 795                 wlc_hw->machwcap = R_REG(&regs->machwcap);
 796                 wlc_hw->machwcap_backup = wlc_hw->machwcap;
 797
 798                 /* init tx fifo size */
 799                 wlc_hw->xmtfifo_sz =
 800                     xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
 801
 802                 /* Get a phy for this band */
 803                 wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
 804                         (void *)regs, brcms_b_bandtype(wlc_hw), vars,
 805                         wlc->wiphy);
 806                 if (wlc_hw->band->pi == NULL) {
 807                         wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
 808                                   "attach failed\n", unit);
 809                         err = 17;
 810                         goto fail;
 811                 }
 812
 813                 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
 814
 815                 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
 816                                        &wlc_hw->band->phyrev,
 817                                        &wlc_hw->band->radioid,
 818                                        &wlc_hw->band->radiorev);
 819                 wlc_hw->band->abgphy_encore =
 820                     wlc_phy_get_encore(wlc_hw->band->pi);
 821                 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
 822                 wlc_hw->band->core_flags =
 823                     wlc_phy_get_coreflags(wlc_hw->band->pi);
 824
 825                 /* verify good phy_type & supported phy revision */
 826                 if (BRCMS_ISNPHY(wlc_hw->band)) {
 827                         if (NCONF_HAS(wlc_hw->band->phyrev))
 828                                 goto good_phy;
 829                         else
 830                                 goto bad_phy;
 831                 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
 832                         if (LCNCONF_HAS(wlc_hw->band->phyrev))
 833                                 goto good_phy;
 834                         else
 835                                 goto bad_phy;
 836                 } else {
 837  bad_phy:
 838                         wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
 839                                   "phy type/rev (%d/%d)\n", unit,
 840                                   wlc_hw->band->phytype, wlc_hw->band->phyrev);
 841                         err = 18;
 842                         goto fail;
 843                 }
 844
 845  good_phy:
 846                 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
 847                  * high level attach. However we can not make that change until all low level access
 848                  * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
 849                  * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
 850                  * low only init when all fns updated.
 851                  */
 852                 wlc->band->pi = wlc_hw->band->pi;
 853                 wlc->band->phytype = wlc_hw->band->phytype;
 854                 wlc->band->phyrev = wlc_hw->band->phyrev;
 855                 wlc->band->radioid = wlc_hw->band->radioid;
 856                 wlc->band->radiorev = wlc_hw->band->radiorev;
 857
 858                 /* default contention windows size limits */
 859                 wlc_hw->band->CWmin = APHY_CWMIN;
 860                 wlc_hw->band->CWmax = PHY_CWMAX;
 861
 862                 if (!brcms_b_attach_dmapio(wlc, j, wme)) {
 863                         err = 19;
 864                         goto fail;
 865                 }
 866         }
 867
 868         /* disable core to match driver "down" state */
 869         brcms_c_coredisable(wlc_hw);
 870
 871         /* Match driver "down" state */
 872         if (wlc_hw->sih->bustype == PCI_BUS)
 873                 ai_pci_down(wlc_hw->sih);
 874
 875         /* register sb interrupt callback functions */
 876         ai_register_intr_callback(wlc_hw->sih, (void *)brcms_c_wlintrsoff,
 877                                   (void *)brcms_c_wlintrsrestore, NULL, wlc);
 878
 879         /* turn off pll and xtal to match driver "down" state */
 880         brcms_b_xtal(wlc_hw, OFF);
 881
 882         /* *********************************************************************
 883          * The hardware is in the DOWN state at this point. D11 core
 884          * or cores are in reset with clocks off, and the board PLLs
 885          * are off if possible.
 886          *
 887          * Beyond this point, wlc->sbclk == false and chip registers
 888          * should not be touched.
 889          *********************************************************************
 890          */
 891
 892         /* init etheraddr state variables */
 893         macaddr = brcms_c_get_macaddr(wlc_hw);
 894         if (macaddr == NULL) {
 895                 wiphy_err(wiphy, "wl%d: brcms_b_attach: macaddr not found\n",
 896                           unit);
 897                 err = 21;
 898                 goto fail;
 899         }
 900         brcmu_ether_atoe(macaddr, wlc_hw->etheraddr);
 901         if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
 902             is_zero_ether_addr(wlc_hw->etheraddr)) {
 903                 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr %s\n",
 904                           unit, macaddr);
 905                 err = 22;
 906                 goto fail;
 907         }
 908
 909         BCMMSG(wlc->wiphy,
 910                  "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
 911                  wlc_hw->deviceid, wlc_hw->_nbands,
 912                  wlc_hw->sih->boardtype, macaddr);
 913
 914         return err;
 915
 916  fail:
 917         wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
 918                   err);
 919         return err;
 920 }
 921
 922 /*
 923  * Initialize brcms_c_info default values ...
 924  * may get overrides later in this function
 925  *  BMAC_NOTES, move low out and resolve the dangling ones
 926  */
 927 static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
 928 {
 929         struct brcms_c_info *wlc = wlc_hw->wlc;
 930
 931         /* set default sw macintmask value */
 932         wlc->defmacintmask = DEF_MACINTMASK;
 933
 934         /* various 802.11g modes */
 935         wlc_hw->shortslot = false;
 936
 937         wlc_hw->SFBL = RETRY_SHORT_FB;
 938         wlc_hw->LFBL = RETRY_LONG_FB;
 939
 940         /* default mac retry limits */
 941         wlc_hw->SRL = RETRY_SHORT_DEF;
 942         wlc_hw->LRL = RETRY_LONG_DEF;
 943         wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
 944 }
 945
 946 /*
 947  * low level detach
 948  */
 949 int brcms_b_detach(struct brcms_c_info *wlc)
 950 {
 951         uint i;
 952         struct brcms_hw_band *band;
 953         struct brcms_hardware *wlc_hw = wlc->hw;
 954         int callbacks;
 955
 956         callbacks = 0;
 957
 958         if (wlc_hw->sih) {
 959                 /* detach interrupt sync mechanism since interrupt is disabled and per-port
 960                  * interrupt object may has been freed. this must be done before sb core switch
 961                  */
 962                 ai_deregister_intr_callback(wlc_hw->sih);
 963
 964                 if (wlc_hw->sih->bustype == PCI_BUS)
 965                         ai_pci_sleep(wlc_hw->sih);
 966         }
 967
 968         brcms_b_detach_dmapio(wlc_hw);
 969
 970         band = wlc_hw->band;
 971         for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
 972                 if (band->pi) {
 973                         /* Detach this band's phy */
 974                         wlc_phy_detach(band->pi);
 975                         band->pi = NULL;
 976                 }
 977                 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
 978         }
 979
 980         /* Free shared phy state */
 981         kfree(wlc_hw->phy_sh);
 982
 983         wlc_phy_shim_detach(wlc_hw->physhim);
 984
 985         /* free vars */
 986         kfree(wlc_hw->vars);
 987         wlc_hw->vars = NULL;
 988
 989         if (wlc_hw->sih) {
 990                 ai_detach(wlc_hw->sih);
 991                 wlc_hw->sih = NULL;
 992         }
 993
 994         return callbacks;
 995
 996 }
 997
 998 void brcms_b_reset(struct brcms_hardware *wlc_hw)
 999 {
1000         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1001
1002         /* reset the core */
1003         if (!DEVICEREMOVED(wlc_hw->wlc))
1004                 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
1005
1006         /* purge the dma rings */
1007         brcms_c_flushqueues(wlc_hw->wlc);
1008
1009         brcms_c_reset_bmac_done(wlc_hw->wlc);
1010 }
1011
1012 void
1013 brcms_b_init(struct brcms_hardware *wlc_hw, chanspec_t chanspec,
1014                           bool mute) {
1015         u32 macintmask;
1016         bool fastclk;
1017         struct brcms_c_info *wlc = wlc_hw->wlc;
1018
1019         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1020
1021         /* request FAST clock if not on */
1022         fastclk = wlc_hw->forcefastclk;
1023         if (!fastclk)
1024                 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1025
1026         /* disable interrupts */
1027         macintmask = brcms_intrsoff(wlc->wl);
1028
1029         /* set up the specified band and chanspec */
1030         brcms_c_setxband(wlc_hw, CHSPEC_BANDUNIT(chanspec));
1031         wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1032
1033         /* do one-time phy inits and calibration */
1034         wlc_phy_cal_init(wlc_hw->band->pi);
1035
1036         /* core-specific initialization */
1037         brcms_b_coreinit(wlc);
1038
1039         /* suspend the tx fifos and mute the phy for preism cac time */
1040         if (mute)
1041                 brcms_b_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1042
1043         /* band-specific inits */
1044         brcms_b_bsinit(wlc, chanspec);
1045
1046         /* restore macintmask */
1047         brcms_intrsrestore(wlc->wl, macintmask);
1048
1049         /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
1050          * is suspended and brcms_c_enable_mac() will clear this override bit.
1051          */
1052         mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
1053
1054         /*
1055          * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1056          */
1057         wlc_hw->mac_suspend_depth = 1;
1058
1059         /* restore the clk */
1060         if (!fastclk)
1061                 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1062 }
1063
1064 int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
1065 {
1066         uint coremask;
1067
1068         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1069
1070         /*
1071          * Enable pll and xtal, initialize the power control registers,
1072          * and force fastclock for the remainder of brcms_c_up().
1073          */
1074         brcms_b_xtal(wlc_hw, ON);
1075         ai_clkctl_init(wlc_hw->sih);
1076         brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1077
1078         /*
1079          * Configure pci/pcmcia here instead of in brcms_c_attach()
1080          * to allow mfg hotswap:  down, hotswap (chip power cycle), up.
1081          */
1082         coremask = (1 << wlc_hw->wlc->core->coreidx);
1083
1084         if (wlc_hw->sih->bustype == PCI_BUS)
1085                 ai_pci_setup(wlc_hw->sih, coremask);
1086
1087         /*
1088          * Need to read the hwradio status here to cover the case where the system
1089          * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1090          */
1091         if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
1092                 /* put SB PCI in down state again */
1093                 if (wlc_hw->sih->bustype == PCI_BUS)
1094                         ai_pci_down(wlc_hw->sih);
1095                 brcms_b_xtal(wlc_hw, OFF);
1096                 return -ENOMEDIUM;
1097         }
1098
1099         if (wlc_hw->sih->bustype == PCI_BUS)
1100                 ai_pci_up(wlc_hw->sih);
1101
1102         /* reset the d11 core */
1103         brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
1104
1105         return 0;
1106 }
1107
1108 int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
1109 {
1110         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1111
1112         wlc_hw->up = true;
1113         wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
1114
1115         /* FULLY enable dynamic power control and d11 core interrupt */
1116         brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1117         brcms_intrson(wlc_hw->wlc->wl);
1118         return 0;
1119 }
1120
1121 int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
1122 {
1123         bool dev_gone;
1124         uint callbacks = 0;
1125
1126         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1127
1128         if (!wlc_hw->up)
1129                 return callbacks;
1130
1131         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1132
1133         /* disable interrupts */
1134         if (dev_gone)
1135                 wlc_hw->wlc->macintmask = 0;
1136         else {
1137                 /* now disable interrupts */
1138                 brcms_intrsoff(wlc_hw->wlc->wl);
1139
1140                 /* ensure we're running on the pll clock again */
1141                 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1142         }
1143         /* down phy at the last of this stage */
1144         callbacks += wlc_phy_down(wlc_hw->band->pi);
1145
1146         return callbacks;
1147 }
1148
1149 int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
1150 {
1151         uint callbacks = 0;
1152         bool dev_gone;
1153
1154         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1155
1156         if (!wlc_hw->up)
1157                 return callbacks;
1158
1159         wlc_hw->up = false;
1160         wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
1161
1162         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1163
1164         if (dev_gone) {
1165                 wlc_hw->sbclk = false;
1166                 wlc_hw->clk = false;
1167                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1168
1169                 /* reclaim any posted packets */
1170                 brcms_c_flushqueues(wlc_hw->wlc);
1171         } else {
1172
1173                 /* Reset and disable the core */
1174                 if (ai_iscoreup(wlc_hw->sih)) {
1175                         if (R_REG(&wlc_hw->regs->maccontrol) &
1176                             MCTL_EN_MAC)
1177                                 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
1178                         callbacks += brcms_reset(wlc_hw->wlc->wl);
1179                         brcms_c_coredisable(wlc_hw);
1180                 }
1181
1182                 /* turn off primary xtal and pll */
1183                 if (!wlc_hw->noreset) {
1184                         if (wlc_hw->sih->bustype == PCI_BUS)
1185                                 ai_pci_down(wlc_hw->sih);
1186                         brcms_b_xtal(wlc_hw, OFF);
1187                 }
1188         }
1189
1190         return callbacks;
1191 }
1192
1193 void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1194 {
1195         /* delay before first read of ucode state */
1196         udelay(40);
1197
1198         /* wait until ucode is no longer asleep */
1199         SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1200                   DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1201 }
1202
1203 void brcms_b_hw_etheraddr(struct brcms_hardware *wlc_hw, u8 *ea)
1204 {
1205         memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
1206 }
1207
1208 static int brcms_b_bandtype(struct brcms_hardware *wlc_hw)
1209 {
1210         return wlc_hw->band->bandtype;
1211 }
1212
1213 /* control chip clock to save power, enable dynamic clock or force fast clock */
1214 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode)
1215 {
1216         if (PMUCTL_ENAB(wlc_hw->sih)) {
1217                 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1218                  *  but mac core will still run on ALP(not HT) when it enters powersave mode,
1219                  *      which means the FCA bit may not be set.
1220                  *      should wakeup mac if driver wants it to run on HT.
1221                  */
1222
1223                 if (wlc_hw->clk) {
1224                         if (mode == CLK_FAST) {
1225                                 OR_REG(&wlc_hw->regs->clk_ctl_st,
1226                                        CCS_FORCEHT);
1227
1228                                 udelay(64);
1229
1230                                 SPINWAIT(((R_REG
1231                                            (&wlc_hw->regs->
1232                                             clk_ctl_st) & CCS_HTAVAIL) == 0),
1233                                          PMU_MAX_TRANSITION_DLY);
1234                                 WARN_ON(!(R_REG
1235                                           (&wlc_hw->regs->
1236                                            clk_ctl_st) & CCS_HTAVAIL));
1237                         } else {
1238                                 if ((wlc_hw->sih->pmurev == 0) &&
1239                                     (R_REG
1240                                      (&wlc_hw->regs->
1241                                       clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1242                                         SPINWAIT(((R_REG
1243                                                    (&wlc_hw->regs->
1244                                                     clk_ctl_st) & CCS_HTAVAIL)
1245                                                   == 0),
1246                                                  PMU_MAX_TRANSITION_DLY);
1247                                 AND_REG(&wlc_hw->regs->clk_ctl_st,
1248                                         ~CCS_FORCEHT);
1249                         }
1250                 }
1251                 wlc_hw->forcefastclk = (mode == CLK_FAST);
1252         } else {
1253
1254                 /* old chips w/o PMU, force HT through cc,
1255                  * then use FCA to verify mac is running fast clock
1256                  */
1257
1258                 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1259
1260                 /* check fast clock is available (if core is not in reset) */
1261                 if (wlc_hw->forcefastclk && wlc_hw->clk)
1262                         WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) &
1263                                   SISF_FCLKA));
1264
1265                 /* keep the ucode wake bit on if forcefastclk is on
1266                  * since we do not want ucode to put us back to slow clock
1267                  * when it dozes for PM mode.
1268                  * Code below matches the wake override bit with current forcefastclk state
1269                  * Only setting bit in wake_override instead of waking ucode immediately
1270                  * since old code (wlc.c 1.4499) had this behavior. Older code set
1271                  * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1272                  * (protected by an up check) was executed just below.
1273                  */
1274                 if (wlc_hw->forcefastclk)
1275                         mboolset(wlc_hw->wake_override,
1276                                  BRCMS_WAKE_OVERRIDE_FORCEFAST);
1277                 else
1278                         mboolclr(wlc_hw->wake_override,
1279                                  BRCMS_WAKE_OVERRIDE_FORCEFAST);
1280         }
1281 }
1282
1283 /* set initial host flags value */
1284 static void
1285 brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1286 {
1287         struct brcms_hardware *wlc_hw = wlc->hw;
1288
1289         memset(mhfs, 0, MHFMAX * sizeof(u16));
1290
1291         mhfs[MHF2] |= mhf2_init;
1292
1293         /* prohibit use of slowclock on multifunction boards */
1294         if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1295                 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1296
1297         if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1298                 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1299                 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1300         }
1301 }
1302
1303 /* set or clear ucode host flag bits
1304  * it has an optimization for no-change write
1305  * it only writes through shared memory when the core has clock;
1306  * pre-CLK changes should use wlc_write_mhf to get around the optimization
1307  *
1308  *
1309  * bands values are: BRCM_BAND_AUTO <--- Current band only
1310  *                   BRCM_BAND_5G   <--- 5G band only
1311  *                   BRCM_BAND_2G   <--- 2G band only
1312  *                   BRCM_BAND_ALL  <--- All bands
1313  */
1314 void
1315 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1316              int bands)
1317 {
1318         u16 save;
1319         u16 addr[MHFMAX] = {
1320                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1321                 M_HOST_FLAGS5
1322         };
1323         struct brcms_hw_band *band;
1324
1325         if ((val & ~mask) || idx >= MHFMAX)
1326                 return; /* error condition */
1327
1328         switch (bands) {
1329                 /* Current band only or all bands,
1330                  * then set the band to current band
1331                  */
1332         case BRCM_BAND_AUTO:
1333         case BRCM_BAND_ALL:
1334                 band = wlc_hw->band;
1335                 break;
1336         case BRCM_BAND_5G:
1337                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1338                 break;
1339         case BRCM_BAND_2G:
1340                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1341                 break;
1342         default:
1343                 band = NULL;    /* error condition */
1344         }
1345
1346         if (band) {
1347                 save = band->mhfs[idx];
1348                 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1349
1350                 /* optimization: only write through if changed, and
1351                  * changed band is the current band
1352                  */
1353                 if (wlc_hw->clk && (band->mhfs[idx] != save)
1354                     && (band == wlc_hw->band))
1355                         brcms_b_write_shm(wlc_hw, addr[idx],
1356                                            (u16) band->mhfs[idx]);
1357         }
1358
1359         if (bands == BRCM_BAND_ALL) {
1360                 wlc_hw->bandstate[0]->mhfs[idx] =
1361                     (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1362                 wlc_hw->bandstate[1]->mhfs[idx] =
1363                     (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1364         }
1365 }
1366
1367 u16 brcms_b_mhf_get(struct brcms_hardware *wlc_hw, u8 idx, int bands)
1368 {
1369         struct brcms_hw_band *band;
1370
1371         if (idx >= MHFMAX)
1372                 return 0; /* error condition */
1373         switch (bands) {
1374         case BRCM_BAND_AUTO:
1375                 band = wlc_hw->band;
1376                 break;
1377         case BRCM_BAND_5G:
1378                 band = wlc_hw->bandstate[BAND_5G_INDEX];
1379                 break;
1380         case BRCM_BAND_2G:
1381                 band = wlc_hw->bandstate[BAND_2G_INDEX];
1382                 break;
1383         default:
1384                 band = NULL;            /* error condition */
1385         }
1386
1387         if (!band)
1388                 return 0;
1389
1390         return band->mhfs[idx];
1391 }
1392
1393 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
1394 {
1395         u8 idx;
1396         u16 addr[] = {
1397                 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1398                 M_HOST_FLAGS5
1399         };
1400
1401         for (idx = 0; idx < MHFMAX; idx++) {
1402                 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1403         }
1404 }
1405
1406 /* set the maccontrol register to desired reset state and
1407  * initialize the sw cache of the register
1408  */
1409 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1410 {
1411         /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1412         wlc_hw->maccontrol = 0;
1413         wlc_hw->suspended_fifos = 0;
1414         wlc_hw->wake_override = 0;
1415         wlc_hw->mute_override = 0;
1416         brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1417 }
1418
1419 /* set or clear maccontrol bits */
1420 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1421 {
1422         u32 maccontrol;
1423         u32 new_maccontrol;
1424
1425         if (val & ~mask)
1426                 return; /* error condition */
1427         maccontrol = wlc_hw->maccontrol;
1428         new_maccontrol = (maccontrol & ~mask) | val;
1429
1430         /* if the new maccontrol value is the same as the old, nothing to do */
1431         if (new_maccontrol == maccontrol)
1432                 return;
1433
1434         /* something changed, cache the new value */
1435         wlc_hw->maccontrol = new_maccontrol;
1436
1437         /* write the new values with overrides applied */
1438         brcms_c_mctrl_write(wlc_hw);
1439 }
1440
1441 /* write the software state of maccontrol and overrides to the maccontrol register */
1442 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1443 {
1444         u32 maccontrol = wlc_hw->maccontrol;
1445
1446         /* OR in the wake bit if overridden */
1447         if (wlc_hw->wake_override)
1448                 maccontrol |= MCTL_WAKE;
1449
1450         /* set AP and INFRA bits for mute if needed */
1451         if (wlc_hw->mute_override) {
1452                 maccontrol &= ~(MCTL_AP);
1453                 maccontrol |= MCTL_INFRA;
1454         }
1455
1456         W_REG(&wlc_hw->regs->maccontrol, maccontrol);
1457 }
1458
1459 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1460                                  u32 override_bit)
1461 {
1462         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1463                 mboolset(wlc_hw->wake_override, override_bit);
1464                 return;
1465         }
1466
1467         mboolset(wlc_hw->wake_override, override_bit);
1468
1469         brcms_c_mctrl_write(wlc_hw);
1470         brcms_b_wait_for_wake(wlc_hw);
1471
1472         return;
1473 }
1474
1475 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1476                                    u32 override_bit)
1477 {
1478         mboolclr(wlc_hw->wake_override, override_bit);
1479
1480         if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1481                 return;
1482
1483         brcms_c_mctrl_write(wlc_hw);
1484
1485         return;
1486 }
1487
1488 /* When driver needs ucode to stop beaconing, it has to make sure that
1489  * MCTL_AP is clear and MCTL_INFRA is set
1490  * Mode           MCTL_AP        MCTL_INFRA
1491  * AP                1              1
1492  * STA               0              1 <--- This will ensure no beacons
1493  * IBSS              0              0
1494  */
1495 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1496 {
1497         wlc_hw->mute_override = 1;
1498
1499         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1500          * override, then there is no change to write
1501          */
1502         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1503                 return;
1504
1505         brcms_c_mctrl_write(wlc_hw);
1506
1507         return;
1508 }
1509
1510 /* Clear the override on AP and INFRA bits */
1511 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1512 {
1513         if (wlc_hw->mute_override == 0)
1514                 return;
1515
1516         wlc_hw->mute_override = 0;
1517
1518         /* if maccontrol already has AP == 0 and INFRA == 1 without this
1519          * override, then there is no change to write
1520          */
1521         if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1522                 return;
1523
1524         brcms_c_mctrl_write(wlc_hw);
1525 }
1526
1527 /*
1528  * Write a MAC address to the given match reg offset in the RXE match engine.
1529  */
1530 void
1531 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1532                        const u8 *addr)
1533 {
1534         d11regs_t *regs;
1535         u16 mac_l;
1536         u16 mac_m;
1537         u16 mac_h;
1538
1539         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: brcms_b_set_addrmatch\n",
1540                  wlc_hw->unit);
1541
1542         regs = wlc_hw->regs;
1543         mac_l = addr[0] | (addr[1] << 8);
1544         mac_m = addr[2] | (addr[3] << 8);
1545         mac_h = addr[4] | (addr[5] << 8);
1546
1547         /* enter the MAC addr into the RXE match registers */
1548         W_REG(&regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1549         W_REG(&regs->rcm_mat_data, mac_l);
1550         W_REG(&regs->rcm_mat_data, mac_m);
1551         W_REG(&regs->rcm_mat_data, mac_h);
1552
1553 }
1554
1555 void
1556 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1557                             void *buf)
1558 {
1559         d11regs_t *regs;
1560         u32 word;
1561         bool be_bit;
1562         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1563
1564         regs = wlc_hw->regs;
1565         W_REG(&regs->tplatewrptr, offset);
1566
1567         /* if MCTL_BIGEND bit set in mac control register,
1568          * the chip swaps data in fifo, as well as data in
1569          * template ram
1570          */
1571         be_bit = (R_REG(&regs->maccontrol) & MCTL_BIGEND) != 0;
1572
1573         while (len > 0) {
1574                 memcpy(&word, buf, sizeof(u32));
1575
1576                 if (be_bit)
1577                         word = cpu_to_be32(word);
1578                 else
1579                         word = cpu_to_le32(word);
1580
1581                 W_REG(&regs->tplatewrdata, word);
1582
1583                 buf = (u8 *) buf + sizeof(u32);
1584                 len -= sizeof(u32);
1585         }
1586 }
1587
1588 void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1589 {
1590         wlc_hw->band->CWmin = newmin;
1591
1592         W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1593         (void)R_REG(&wlc_hw->regs->objaddr);
1594         W_REG(&wlc_hw->regs->objdata, newmin);
1595 }
1596
1597 void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1598 {
1599         wlc_hw->band->CWmax = newmax;
1600
1601         W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1602         (void)R_REG(&wlc_hw->regs->objaddr);
1603         W_REG(&wlc_hw->regs->objdata, newmax);
1604 }
1605
1606 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1607 {
1608         bool fastclk;
1609
1610         /* request FAST clock if not on */
1611         fastclk = wlc_hw->forcefastclk;
1612         if (!fastclk)
1613                 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
1614
1615         wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1616
1617         brcms_b_phy_reset(wlc_hw);
1618         wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1619
1620         /* restore the clk */
1621         if (!fastclk)
1622                 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1623 }
1624
1625 static void
1626 brcms_c_write_hw_bcntemplate0(struct brcms_hardware *wlc_hw, void *bcn,
1627                               int len)
1628 {
1629         d11regs_t *regs = wlc_hw->regs;
1630
1631         brcms_b_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1632                                     bcn);
1633         /* write beacon length to SCR */
1634         brcms_b_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
1635         /* mark beacon0 valid */
1636         OR_REG(&regs->maccommand, MCMD_BCN0VLD);
1637 }
1638
1639 static void
1640 brcms_c_write_hw_bcntemplate1(struct brcms_hardware *wlc_hw, void *bcn,
1641                               int len)
1642 {
1643         d11regs_t *regs = wlc_hw->regs;
1644
1645         brcms_b_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1646                                     bcn);
1647         /* write beacon length to SCR */
1648         brcms_b_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
1649         /* mark beacon1 valid */
1650         OR_REG(&regs->maccommand, MCMD_BCN1VLD);
1651 }
1652
1653 /* mac is assumed to be suspended at this point */
1654 void
1655 brcms_b_write_hw_bcntemplates(struct brcms_hardware *wlc_hw, void *bcn,
1656                               int len, bool both)
1657 {
1658         d11regs_t *regs = wlc_hw->regs;
1659
1660         if (both) {
1661                 brcms_c_write_hw_bcntemplate0(wlc_hw, bcn, len);
1662                 brcms_c_write_hw_bcntemplate1(wlc_hw, bcn, len);
1663         } else {
1664                 /* bcn 0 */
1665                 if (!(R_REG(&regs->maccommand) & MCMD_BCN0VLD))
1666                         brcms_c_write_hw_bcntemplate0(wlc_hw, bcn, len);
1667                 /* bcn 1 */
1668                 else if (!
1669                          (R_REG(&regs->maccommand) & MCMD_BCN1VLD))
1670                         brcms_c_write_hw_bcntemplate1(wlc_hw, bcn, len);
1671         }
1672 }
1673
1674 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1675 {
1676         u16 v;
1677         struct brcms_c_info *wlc = wlc_hw->wlc;
1678         /* update SYNTHPU_DLY */
1679
1680         if (BRCMS_ISLCNPHY(wlc->band)) {
1681                 v = SYNTHPU_DLY_LPPHY_US;
1682         } else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1683                 v = SYNTHPU_DLY_NPHY_US;
1684         } else {
1685                 v = SYNTHPU_DLY_BPHY_US;
1686         }
1687
1688         brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1689 }
1690
1691 /* band-specific init */
1692 static void
1693 brcms_b_bsinit(struct brcms_c_info *wlc, chanspec_t chanspec)
1694 {
1695         struct brcms_hardware *wlc_hw = wlc->hw;
1696
1697         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1698                 wlc_hw->band->bandunit);
1699
1700         brcms_c_ucode_bsinit(wlc_hw);
1701
1702         wlc_phy_init(wlc_hw->band->pi, chanspec);
1703
1704         brcms_c_ucode_txant_set(wlc_hw);
1705
1706         /* cwmin is band-specific, update hardware with value for current band */
1707         brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1708         brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1709
1710         brcms_b_update_slot_timing(wlc_hw,
1711                                     BAND_5G(wlc_hw->band->
1712                                             bandtype) ? true : wlc_hw->
1713                                     shortslot);
1714
1715         /* write phytype and phyvers */
1716         brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1717         brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1718
1719         /* initialize the txphyctl1 rate table since shmem is shared between bands */
1720         brcms_upd_ofdm_pctl1_table(wlc_hw);
1721
1722         brcms_b_upd_synthpu(wlc_hw);
1723 }
1724
1725 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
1726 {
1727         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
1728
1729         wlc_hw->phyclk = clk;
1730
1731         if (OFF == clk) {       /* clear gmode bit, put phy into reset */
1732
1733                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1734                                (SICF_PRST | SICF_FGC));
1735                 udelay(1);
1736                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1737                 udelay(1);
1738
1739         } else {                /* take phy out of reset */
1740
1741                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1742                 udelay(1);
1743                 ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1744                 udelay(1);
1745
1746         }
1747 }
1748
1749 /* Perform a soft reset of the PHY PLL */
1750 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1751 {
1752         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1753
1754         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1755                    offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
1756         udelay(1);
1757         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1758                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1759         udelay(1);
1760         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1761                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
1762         udelay(1);
1763         ai_corereg(wlc_hw->sih, SI_CC_IDX,
1764                    offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
1765         udelay(1);
1766 }
1767
1768 /* light way to turn on phy clock without reset for NPHY only
1769  *  refer to brcms_b_core_phy_clk for full version
1770  */
1771 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1772 {
1773         /* support(necessary for NPHY and HYPHY) only */
1774         if (!BRCMS_ISNPHY(wlc_hw->band))
1775                 return;
1776
1777         if (ON == clk)
1778                 ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
1779         else
1780                 ai_core_cflags(wlc_hw->sih, SICF_FGC, 0);
1781
1782 }
1783
1784 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1785 {
1786         if (ON == clk)
1787                 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
1788         else
1789                 ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
1790 }
1791
1792 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1793 {
1794         struct brcms_phy_pub *pih = wlc_hw->band->pi;
1795         u32 phy_bw_clkbits;
1796         bool phy_in_reset = false;
1797
1798         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1799
1800         if (pih == NULL)
1801                 return;
1802
1803         phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1804
1805         /* Specific reset sequence required for NPHY rev 3 and 4 */
1806         if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1807             NREV_LE(wlc_hw->band->phyrev, 4)) {
1808                 /* Set the PHY bandwidth */
1809                 ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
1810
1811                 udelay(1);
1812
1813                 /* Perform a soft reset of the PHY PLL */
1814                 brcms_b_core_phypll_reset(wlc_hw);
1815
1816                 /* reset the PHY */
1817                 ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
1818                                (SICF_PRST | SICF_PCLKE));
1819                 phy_in_reset = true;
1820         } else {
1821
1822                 ai_core_cflags(wlc_hw->sih,
1823                                (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1824                                (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1825         }
1826
1827         udelay(2);
1828         brcms_b_core_phy_clk(wlc_hw, ON);
1829
1830         if (pih)
1831                 wlc_phy_anacore(pih, ON);
1832 }
1833
1834 /* switch to and initialize new band */
1835 static void
1836 brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1837                                 chanspec_t chanspec) {
1838         struct brcms_c_info *wlc = wlc_hw->wlc;
1839         u32 macintmask;
1840
1841         /* Enable the d11 core before accessing it */
1842         if (!ai_iscoreup(wlc_hw->sih)) {
1843                 ai_core_reset(wlc_hw->sih, 0, 0);
1844                 brcms_c_mctrl_reset(wlc_hw);
1845         }
1846
1847         macintmask = brcms_c_setband_inact(wlc, bandunit);
1848
1849         if (!wlc_hw->up)
1850                 return;
1851
1852         brcms_b_core_phy_clk(wlc_hw, ON);
1853
1854         /* band-specific initializations */
1855         brcms_b_bsinit(wlc, chanspec);
1856
1857         /*
1858          * If there are any pending software interrupt bits,
1859          * then replace these with a harmless nonzero value
1860          * so brcms_c_dpc() will re-enable interrupts when done.
1861          */
1862         if (wlc->macintstatus)
1863                 wlc->macintstatus = MI_DMAINT;
1864
1865         /* restore macintmask */
1866         brcms_intrsrestore(wlc->wl, macintmask);
1867
1868         /* ucode should still be suspended.. */
1869         WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
1870 }
1871
1872 /* low-level band switch utility routine */
1873 void brcms_c_setxband(struct brcms_hardware *wlc_hw,
1874                                      uint bandunit)
1875 {
1876         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1877                 bandunit);
1878
1879         wlc_hw->band = wlc_hw->bandstate[bandunit];
1880
1881         /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
1882         wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
1883
1884         /* set gmode core flag */
1885         if (wlc_hw->sbclk && !wlc_hw->noreset) {
1886                 ai_core_cflags(wlc_hw->sih, SICF_GMODE,
1887                                ((bandunit == 0) ? SICF_GMODE : 0));
1888         }
1889 }
1890
1891 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1892 {
1893
1894         /* reject unsupported corerev */
1895         if (!VALID_COREREV(wlc_hw->corerev)) {
1896                 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1897                           wlc_hw->corerev);
1898                 return false;
1899         }
1900
1901         return true;
1902 }
1903
1904 /* Validate some board info parameters */
1905 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1906 {
1907         uint boardrev = wlc_hw->boardrev;
1908
1909         /* 4 bits each for board type, major, minor, and tiny version */
1910         uint brt = (boardrev & 0xf000) >> 12;
1911         uint b0 = (boardrev & 0xf00) >> 8;
1912         uint b1 = (boardrev & 0xf0) >> 4;
1913         uint b2 = boardrev & 0xf;
1914
1915         /* voards from other vendors are always considered valid */
1916         if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM)
1917                 return true;
1918
1919         /* do some boardrev sanity checks when boardvendor is Broadcom */
1920         if (boardrev == 0)
1921                 return false;
1922
1923         if (boardrev <= 0xff)
1924                 return true;
1925
1926         if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1927                 || (b2 > 9))
1928                 return false;
1929
1930         return true;
1931 }
1932
1933 static char *brcms_c_get_macaddr(struct brcms_hardware *wlc_hw)
1934 {
1935         const char *varname = "macaddr";
1936         char *macaddr;
1937
1938         /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1939         macaddr = getvar(wlc_hw->vars, varname);
1940         if (macaddr != NULL)
1941                 return macaddr;
1942
1943         if (NBANDS_HW(wlc_hw) > 1)
1944                 varname = "et1macaddr";
1945         else
1946                 varname = "il0macaddr";
1947
1948         macaddr = getvar(wlc_hw->vars, varname);
1949         if (macaddr == NULL) {
1950                 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
1951                           "getvar(%s) not found\n", wlc_hw->unit, varname);
1952         }
1953
1954         return macaddr;
1955 }
1956
1957 /*
1958  * Return true if radio is disabled, otherwise false.
1959  * hw radio disable signal is an external pin, users activate it asynchronously
1960  * this function could be called when driver is down and w/o clock
1961  * it operates on different registers depending on corerev and boardflag.
1962  */
1963 bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1964 {
1965         bool v, clk, xtal;
1966         u32 resetbits = 0, flags = 0;
1967
1968         xtal = wlc_hw->sbclk;
1969         if (!xtal)
1970                 brcms_b_xtal(wlc_hw, ON);
1971
1972         /* may need to take core out of reset first */
1973         clk = wlc_hw->clk;
1974         if (!clk) {
1975                 /*
1976                  * mac no longer enables phyclk automatically when driver
1977                  * accesses phyreg throughput mac. This can be skipped since
1978                  * only mac reg is accessed below
1979                  */
1980                 flags |= SICF_PCLKE;
1981
1982                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
1983                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
1984                     (wlc_hw->sih->chip == BCM43225_CHIP_ID))
1985                         wlc_hw->regs =
1986                             (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
1987                                                      0);
1988                 ai_core_reset(wlc_hw->sih, flags, resetbits);
1989                 brcms_c_mctrl_reset(wlc_hw);
1990         }
1991
1992         v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
1993
1994         /* put core back into reset */
1995         if (!clk)
1996                 ai_core_disable(wlc_hw->sih, 0);
1997
1998         if (!xtal)
1999                 brcms_b_xtal(wlc_hw, OFF);
2000
2001         return v;
2002 }
2003
2004 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
2005 void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
2006 {
2007         if (wlc_hw->wlc->pub->hw_up)
2008                 return;
2009
2010         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2011
2012         /*
2013          * Enable pll and xtal, initialize the power control registers,
2014          * and force fastclock for the remainder of brcms_c_up().
2015          */
2016         brcms_b_xtal(wlc_hw, ON);
2017         ai_clkctl_init(wlc_hw->sih);
2018         brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
2019
2020         if (wlc_hw->sih->bustype == PCI_BUS) {
2021                 ai_pci_fixcfg(wlc_hw->sih);
2022
2023                 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2024                 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2025                     (wlc_hw->sih->chip == BCM43225_CHIP_ID))
2026                         wlc_hw->regs =
2027                             (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
2028                                                      0);
2029         }
2030
2031         /* Inform phy that a POR reset has occurred so it does a complete phy init */
2032         wlc_phy_por_inform(wlc_hw->band->pi);
2033
2034         wlc_hw->ucode_loaded = false;
2035         wlc_hw->wlc->pub->hw_up = true;
2036
2037         if ((wlc_hw->boardflags & BFL_FEM)
2038             && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
2039                 if (!
2040                     (wlc_hw->boardrev >= 0x1250
2041                      && (wlc_hw->boardflags & BFL_FEM_BT)))
2042                         ai_epa_4313war(wlc_hw->sih);
2043         }
2044 }
2045
2046 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
2047 {
2048         struct dma_pub *di = wlc_hw->di[fifo];
2049         return dma_rxreset(di);
2050 }
2051
2052 /* d11 core reset
2053  *   ensure fask clock during reset
2054  *   reset dma
2055  *   reset d11(out of reset)
2056  *   reset phy(out of reset)
2057  *   clear software macintstatus for fresh new start
2058  * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2059  */
2060 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
2061 {
2062         d11regs_t *regs;
2063         uint i;
2064         bool fastclk;
2065         u32 resetbits = 0;
2066
2067         if (flags == BRCMS_USE_COREFLAGS)
2068                 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2069
2070         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2071
2072         regs = wlc_hw->regs;
2073
2074         /* request FAST clock if not on  */
2075         fastclk = wlc_hw->forcefastclk;
2076         if (!fastclk)
2077                 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
2078
2079         /* reset the dma engines except first time thru */
2080         if (ai_iscoreup(wlc_hw->sih)) {
2081                 for (i = 0; i < NFIFO; i++)
2082                         if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2083                                 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
2084                                           "dma_txreset[%d]: cannot stop dma\n",
2085                                            wlc_hw->unit, __func__, i);
2086                         }
2087
2088                 if ((wlc_hw->di[RX_FIFO])
2089                     && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2090                         wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
2091                                   "[%d]: cannot stop dma\n",
2092                                   wlc_hw->unit, __func__, RX_FIFO);
2093                 }
2094         }
2095         /* if noreset, just stop the psm and return */
2096         if (wlc_hw->noreset) {
2097                 wlc_hw->wlc->macintstatus = 0;  /* skip wl_dpc after down */
2098                 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2099                 return;
2100         }
2101
2102         /*
2103          * mac no longer enables phyclk automatically when driver accesses
2104          * phyreg throughput mac, AND phy_reset is skipped at early stage when
2105          * band->pi is invalid. need to enable PHY CLK
2106          */
2107         flags |= SICF_PCLKE;
2108
2109         /* reset the core
2110          * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2111          *  is cleared by the core_reset. have to re-request it.
2112          *  This adds some delay and we can optimize it by also requesting fastclk through
2113          *  chipcommon during this period if necessary. But that has to work coordinate
2114          *  with other driver like mips/arm since they may touch chipcommon as well.
2115          */
2116         wlc_hw->clk = false;
2117         ai_core_reset(wlc_hw->sih, flags, resetbits);
2118         wlc_hw->clk = true;
2119         if (wlc_hw->band && wlc_hw->band->pi)
2120                 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2121
2122         brcms_c_mctrl_reset(wlc_hw);
2123
2124         if (PMUCTL_ENAB(wlc_hw->sih))
2125                 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
2126
2127         brcms_b_phy_reset(wlc_hw);
2128
2129         /* turn on PHY_PLL */
2130         brcms_b_core_phypll_ctl(wlc_hw, true);
2131
2132         /* clear sw intstatus */
2133         wlc_hw->wlc->macintstatus = 0;
2134
2135         /* restore the clk setting */
2136         if (!fastclk)
2137                 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2138 }
2139
2140 /* txfifo sizes needs to be modified(increased) since the newer cores
2141  * have more memory.
2142  */
2143 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2144 {
2145         d11regs_t *regs = wlc_hw->regs;
2146         u16 fifo_nu;
2147         u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2148         u16 txfifo_def, txfifo_def1;
2149         u16 txfifo_cmd;
2150
2151         /* tx fifos start at TXFIFO_START_BLK from the Base address */
2152         txfifo_startblk = TXFIFO_START_BLK;
2153
2154         /* sequence of operations:  reset fifo, set fifo size, reset fifo */
2155         for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2156
2157                 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2158                 txfifo_def = (txfifo_startblk & 0xff) |
2159                     (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2160                 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2161                     ((((txfifo_endblk -
2162                         1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2163                 txfifo_cmd =
2164                     TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2165
2166                 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2167                 W_REG(&regs->xmtfifodef, txfifo_def);
2168                 W_REG(&regs->xmtfifodef1, txfifo_def1);
2169
2170                 W_REG(&regs->xmtfifocmd, txfifo_cmd);
2171
2172                 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2173         }
2174         /*
2175          * need to propagate to shm location to be in sync since ucode/hw won't
2176          * do this
2177          */
2178         brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2179                            wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2180         brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2181                            wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2182         brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2183                            ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2184                             xmtfifo_sz[TX_AC_BK_FIFO]));
2185         brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2186                            ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2187                             xmtfifo_sz[TX_BCMC_FIFO]));
2188 }
2189
2190 /* d11 core init
2191  *   reset PSM
2192  *   download ucode/PCM
2193  *   let ucode run to suspended
2194  *   download ucode inits
2195  *   config other core registers
2196  *   init dma
2197  */
2198 static void brcms_b_coreinit(struct brcms_c_info *wlc)
2199 {
2200         struct brcms_hardware *wlc_hw = wlc->hw;
2201         d11regs_t *regs;
2202         u32 sflags;
2203         uint bcnint_us;
2204         uint i = 0;
2205         bool fifosz_fixup = false;
2206         int err = 0;
2207         u16 buf[NFIFO];
2208         struct wiphy *wiphy = wlc->wiphy;
2209
2210         regs = wlc_hw->regs;
2211
2212         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
2213
2214         /* reset PSM */
2215         brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2216
2217         brcms_ucode_download(wlc_hw);
2218         /*
2219          * FIFOSZ fixup. driver wants to controls the fifo allocation.
2220          */
2221         fifosz_fixup = true;
2222
2223         /* let the PSM run to the suspended state, set mode to BSS STA */
2224         W_REG(&regs->macintstatus, -1);
2225         brcms_b_mctrl(wlc_hw, ~0,
2226                        (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2227
2228         /* wait for ucode to self-suspend after auto-init */
2229         SPINWAIT(((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0),
2230                  1000 * 1000);
2231         if ((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0)
2232                 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
2233                           "suspend!\n", wlc_hw->unit);
2234
2235         brcms_c_gpio_init(wlc);
2236
2237         sflags = ai_core_sflags(wlc_hw->sih, 0, 0);
2238
2239         if (D11REV_IS(wlc_hw->corerev, 23)) {
2240                 if (BRCMS_ISNPHY(wlc_hw->band))
2241                         brcms_c_write_inits(wlc_hw, d11n0initvals16);
2242                 else
2243                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2244                                   " %d\n", __func__, wlc_hw->unit,
2245                                   wlc_hw->corerev);
2246         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2247                 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2248                         brcms_c_write_inits(wlc_hw, d11lcn0initvals24);
2249                 } else {
2250                         wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
2251                                   " %d\n", __func__, wlc_hw->unit,
2252                                   wlc_hw->corerev);
2253                 }
2254         } else {
2255                 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
2256                           __func__, wlc_hw->unit, wlc_hw->corerev);
2257         }
2258
2259         /* For old ucode, txfifo sizes needs to be modified(increased) */
2260         if (fifosz_fixup == true) {
2261                 brcms_b_corerev_fifofixup(wlc_hw);
2262         }
2263
2264         /* check txfifo allocations match between ucode and driver */
2265         buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
2266         if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2267                 i = TX_AC_BE_FIFO;
2268                 err = -1;
2269         }
2270         buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
2271         if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2272                 i = TX_AC_VI_FIFO;
2273                 err = -1;
2274         }
2275         buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
2276         buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2277         buf[TX_AC_BK_FIFO] &= 0xff;
2278         if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2279                 i = TX_AC_BK_FIFO;
2280                 err = -1;
2281         }
2282         if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2283                 i = TX_AC_VO_FIFO;
2284                 err = -1;
2285         }
2286         buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
2287         buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2288         buf[TX_BCMC_FIFO] &= 0xff;
2289         if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2290                 i = TX_BCMC_FIFO;
2291                 err = -1;
2292         }
2293         if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2294                 i = TX_ATIM_FIFO;
2295                 err = -1;
2296         }
2297         if (err != 0) {
2298                 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
2299                           " driver size %d index %d\n", buf[i],
2300                           wlc_hw->xmtfifo_sz[i], i);
2301         }
2302
2303         /* make sure we can still talk to the mac */
2304         WARN_ON(R_REG(&regs->maccontrol) == 0xffffffff);
2305
2306         /* band-specific inits done by wlc_bsinit() */
2307
2308         /* Set up frame burst size and antenna swap threshold init values */
2309         brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2310         brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2311
2312         /* enable one rx interrupt per received frame */
2313         W_REG(&regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2314
2315         /* set the station mode (BSS STA) */
2316         brcms_b_mctrl(wlc_hw,
2317                        (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2318                        (MCTL_INFRA | MCTL_DISCARD_PMQ));
2319
2320         /* set up Beacon interval */
2321         bcnint_us = 0x8000 << 10;
2322         W_REG(&regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2323         W_REG(&regs->tsf_cfpstart, bcnint_us);
2324         W_REG(&regs->macintstatus, MI_GP1);
2325
2326         /* write interrupt mask */
2327         W_REG(&regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2328
2329         /* allow the MAC to control the PHY clock (dynamic on/off) */
2330         brcms_b_macphyclk_set(wlc_hw, ON);
2331
2332         /* program dynamic clock control fast powerup delay register */
2333         wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
2334         W_REG(&regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2335
2336         /* tell the ucode the corerev */
2337         brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
2338
2339         /* tell the ucode MAC capabilities */
2340         brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
2341                            (u16) (wlc_hw->machwcap & 0xffff));
2342         brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
2343                            (u16) ((wlc_hw->
2344                                       machwcap >> 16) & 0xffff));
2345
2346         /* write retry limits to SCR, this done after PSM init */
2347         W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2348         (void)R_REG(&regs->objaddr);
2349         W_REG(&regs->objdata, wlc_hw->SRL);
2350         W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2351         (void)R_REG(&regs->objaddr);
2352         W_REG(&regs->objdata, wlc_hw->LRL);
2353
2354         /* write rate fallback retry limits */
2355         brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2356         brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2357
2358         AND_REG(&regs->ifs_ctl, 0x0FFF);
2359         W_REG(&regs->ifs_aifsn, EDCF_AIFSN_MIN);
2360
2361         /* dma initializations */
2362         wlc->txpend16165war = 0;
2363
2364         /* init the tx dma engines */
2365         for (i = 0; i < NFIFO; i++) {
2366                 if (wlc_hw->di[i])
2367                         dma_txinit(wlc_hw->di[i]);
2368         }
2369
2370         /* init the rx dma engine(s) and post receive buffers */
2371         dma_rxinit(wlc_hw->di[RX_FIFO]);
2372         dma_rxfill(wlc_hw->di[RX_FIFO]);
2373 }
2374
2375 /* This function is used for changing the tsf frac register
2376  * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2377  * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2378  * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2379  * HTPHY Formula is 2^26/freq(MHz) e.g.
2380  * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2381  *  - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2382  * For spuron: 123MHz -> 2^26/123    = 545600.5
2383  *  - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2384  * For spur off: 120MHz -> 2^26/120    = 559240.5
2385  *  - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2386  */
2387
2388 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2389 {
2390         d11regs_t *regs;
2391         regs = wlc_hw->regs;
2392
2393         if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
2394             (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
2395                 if (spurmode == WL_SPURAVOID_ON2) {     /* 126Mhz */
2396                         W_REG(&regs->tsf_clk_frac_l, 0x2082);
2397                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2398                 } else if (spurmode == WL_SPURAVOID_ON1) {      /* 123Mhz */
2399                         W_REG(&regs->tsf_clk_frac_l, 0x5341);
2400                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2401                 } else {        /* 120Mhz */
2402                         W_REG(&regs->tsf_clk_frac_l, 0x8889);
2403                         W_REG(&regs->tsf_clk_frac_h, 0x8);
2404                 }
2405         } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2406                 if (spurmode == WL_SPURAVOID_ON1) {     /* 82Mhz */
2407                         W_REG(&regs->tsf_clk_frac_l, 0x7CE0);
2408                         W_REG(&regs->tsf_clk_frac_h, 0xC);
2409                 } else {        /* 80Mhz */
2410                         W_REG(&regs->tsf_clk_frac_l, 0xCCCD);
2411                         W_REG(&regs->tsf_clk_frac_h, 0xC);
2412                 }
2413         }
2414 }
2415
2416 /* Initialize GPIOs that are controlled by D11 core */
2417 static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2418 {
2419         struct brcms_hardware *wlc_hw = wlc->hw;
2420         d11regs_t *regs;
2421         u32 gc, gm;
2422
2423         regs = wlc_hw->regs;
2424
2425         /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2426         brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2427
2428         /*
2429          * Common GPIO setup:
2430          *      G0 = LED 0 = WLAN Activity
2431          *      G1 = LED 1 = WLAN 2.4 GHz Radio State
2432          *      G2 = LED 2 = WLAN 5 GHz Radio State
2433          *      G4 = radio disable input (HI enabled, LO disabled)
2434          */
2435
2436         gc = gm = 0;
2437
2438         /* Allocate GPIOs for mimo antenna diversity feature */
2439         if (wlc_hw->antsel_type == ANTSEL_2x3) {
2440                 /* Enable antenna diversity, use 2x3 mode */
2441                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2442                              MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2443                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2444                              MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2445
2446                 /* init superswitch control */
2447                 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2448
2449         } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2450                 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2451                 /*
2452                  * The board itself is powered by these GPIOs
2453                  * (when not sending pattern) so set them high
2454                  */
2455                 OR_REG(&regs->psm_gpio_oe,
2456                        (BOARD_GPIO_12 | BOARD_GPIO_13));
2457                 OR_REG(&regs->psm_gpio_out,
2458                        (BOARD_GPIO_12 | BOARD_GPIO_13));
2459
2460                 /* Enable antenna diversity, use 2x4 mode */
2461                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2462                              MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2463                 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2464                              BRCM_BAND_ALL);
2465
2466                 /* Configure the desired clock to be 4Mhz */
2467                 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2468                                    ANTSEL_CLKDIV_4MHZ);
2469         }
2470
2471         /* gpio 9 controls the PA.  ucode is responsible for wiggling out and oe */
2472         if (wlc_hw->boardflags & BFL_PACTRL)
2473                 gm |= gc |= BOARD_GPIO_PACTRL;
2474
2475         /* apply to gpiocontrol register */
2476         ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2477 }
2478
2479 static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2480 {
2481         struct brcms_c_info *wlc;
2482         wlc = wlc_hw->wlc;
2483
2484         if (wlc_hw->ucode_loaded)
2485                 return;
2486
2487         if (D11REV_IS(wlc_hw->corerev, 23)) {
2488                 if (BRCMS_ISNPHY(wlc_hw->band)) {
2489                         brcms_ucode_write(wlc_hw, bcm43xx_16_mimo,
2490                                         bcm43xx_16_mimosz);
2491                         wlc_hw->ucode_loaded = true;
2492                 } else
2493                         wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2494                                   "corerev %d\n",
2495                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2496         } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2497                 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2498                         brcms_ucode_write(wlc_hw, bcm43xx_24_lcn,
2499                                         bcm43xx_24_lcnsz);
2500                         wlc_hw->ucode_loaded = true;
2501                 } else {
2502                         wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2503                                   "corerev %d\n",
2504                                   __func__, wlc_hw->unit, wlc_hw->corerev);
2505                 }
2506         }
2507 }
2508
2509 static void brcms_ucode_write(struct brcms_hardware *wlc_hw, const u32 ucode[],
2510                               const uint nbytes) {
2511         d11regs_t *regs = wlc_hw->regs;
2512         uint i;
2513         uint count;
2514
2515         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2516
2517         count = (nbytes / sizeof(u32));
2518
2519         W_REG(&regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2520         (void)R_REG(&regs->objaddr);
2521         for (i = 0; i < count; i++)
2522                 W_REG(&regs->objdata, ucode[i]);
2523 }
2524
2525 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
2526                             const struct d11init *inits)
2527 {
2528         int i;
2529         volatile u8 *base;
2530
2531         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2532
2533         base = (volatile u8 *)wlc_hw->regs;
2534
2535         for (i = 0; inits[i].addr != 0xffff; i++) {
2536                 if (inits[i].size == 2)
2537                         W_REG((u16 *)(base + inits[i].addr),
2538                               inits[i].value);
2539                 else if (inits[i].size == 4)
2540                         W_REG((u32 *)(base + inits[i].addr),
2541                               inits[i].value);
2542         }
2543 }
2544
2545 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
2546 {
2547         u16 phyctl;
2548         u16 phytxant = wlc_hw->bmac_phytxant;
2549         u16 mask = PHY_TXC_ANT_MASK;
2550
2551         /* set the Probe Response frame phy control word */
2552         phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2553         phyctl = (phyctl & ~mask) | phytxant;
2554         brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2555
2556         /* set the Response (ACK/CTS) frame phy control word */
2557         phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
2558         phyctl = (phyctl & ~mask) | phytxant;
2559         brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2560 }
2561
2562 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2563 {
2564         /* update sw state */
2565         wlc_hw->bmac_phytxant = phytxant;
2566
2567         /* push to ucode if up */
2568         if (!wlc_hw->up)
2569                 return;
2570         brcms_c_ucode_txant_set(wlc_hw);
2571
2572 }
2573
2574 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2575 {
2576         return (u16) wlc_hw->wlc->stf->txant;
2577 }
2578
2579 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2580 {
2581         wlc_hw->antsel_type = antsel_type;
2582
2583         /* Update the antsel type for phy module to use */
2584         wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2585 }
2586
2587 void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2588 {
2589         bool fatal = false;
2590         uint unit;
2591         uint intstatus, idx;
2592         d11regs_t *regs = wlc_hw->regs;
2593         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2594
2595         unit = wlc_hw->unit;
2596
2597         for (idx = 0; idx < NFIFO; idx++) {
2598                 /* read intstatus register and ignore any non-error bits */
2599                 intstatus =
2600                     R_REG(&regs->intctrlregs[idx].intstatus) & I_ERRORS;
2601                 if (!intstatus)
2602                         continue;
2603
2604                 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
2605                         unit, idx, intstatus);
2606
2607                 if (intstatus & I_RO) {
2608                         wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
2609                                   "overflow\n", unit, idx);
2610                         fatal = true;
2611                 }
2612
2613                 if (intstatus & I_PC) {
2614                         wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
2615                                  unit, idx);
2616                         fatal = true;
2617                 }
2618
2619                 if (intstatus & I_PD) {
2620                         wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
2621                                   idx);
2622                         fatal = true;
2623                 }
2624
2625                 if (intstatus & I_DE) {
2626                         wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
2627                                   "error\n", unit, idx);
2628                         fatal = true;
2629                 }
2630
2631                 if (intstatus & I_RU) {
2632                         wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
2633                                   "underflow\n", idx, unit);
2634                 }
2635
2636                 if (intstatus & I_XU) {
2637                         wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
2638                                   "underflow\n", idx, unit);
2639                         fatal = true;
2640                 }
2641
2642                 if (fatal) {
2643                         brcms_c_fatal_error(wlc_hw->wlc);       /* big hammer */
2644                         break;
2645                 } else
2646                         W_REG(&regs->intctrlregs[idx].intstatus,
2647                               intstatus);
2648         }
2649 }
2650
2651 void brcms_c_intrson(struct brcms_c_info *wlc)
2652 {
2653         struct brcms_hardware *wlc_hw = wlc->hw;
2654         wlc->macintmask = wlc->defmacintmask;
2655         W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2656 }
2657
2658 /* callback for siutils.c, which has only wlc handler, no wl
2659  * they both check up, not only because there is no need to off/restore d11 interrupt
2660  *  but also because per-port code may require sync with valid interrupt.
2661  */
2662
2663 static u32 brcms_c_wlintrsoff(struct brcms_c_info *wlc)
2664 {
2665         if (!wlc->hw->up)
2666                 return 0;
2667
2668         return brcms_intrsoff(wlc->wl);
2669 }
2670
2671 static void brcms_c_wlintrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2672 {
2673         if (!wlc->hw->up)
2674                 return;
2675
2676         brcms_intrsrestore(wlc->wl, macintmask);
2677 }
2678
2679 u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2680 {
2681         struct brcms_hardware *wlc_hw = wlc->hw;
2682         u32 macintmask;
2683
2684         if (!wlc_hw->clk)
2685                 return 0;
2686
2687         macintmask = wlc->macintmask;   /* isr can still happen */
2688
2689         W_REG(&wlc_hw->regs->macintmask, 0);
2690         (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */
2691         udelay(1);              /* ensure int line is no longer driven */
2692         wlc->macintmask = 0;
2693
2694         /* return previous macintmask; resolve race between us and our isr */
2695         return wlc->macintstatus ? 0 : macintmask;
2696 }
2697
2698 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2699 {
2700         struct brcms_hardware *wlc_hw = wlc->hw;
2701         if (!wlc_hw->clk)
2702                 return;
2703
2704         wlc->macintmask = macintmask;
2705         W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
2706 }
2707
2708 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool on, mbool flags)
2709 {
2710         u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2711
2712         if (on) {
2713                 /* suspend tx fifos */
2714                 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2715                 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2716                 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2717                 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2718
2719                 /* zero the address match register so we do not send ACKs */
2720                 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2721                                        null_ether_addr);
2722         } else {
2723                 /* resume tx fifos */
2724                 if (!wlc_hw->wlc->tx_suspended) {
2725                         brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2726                 }
2727                 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2728                 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2729                 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2730
2731                 /* Restore address */
2732                 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2733                                        wlc_hw->etheraddr);
2734         }
2735
2736         wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
2737
2738         if (on)
2739                 brcms_c_ucode_mute_override_set(wlc_hw);
2740         else
2741                 brcms_c_ucode_mute_override_clear(wlc_hw);
2742 }
2743
2744 int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
2745                            uint *blocks)
2746 {
2747         if (fifo >= NFIFO)
2748                 return -EINVAL;
2749
2750         *blocks = wlc_hw->xmtfifo_sz[fifo];
2751
2752         return 0;
2753 }
2754
2755 /* brcms_b_tx_fifo_suspended:
2756  * Check the MAC's tx suspend status for a tx fifo.
2757  *
2758  * When the MAC acknowledges a tx suspend, it indicates that no more
2759  * packets will be transmitted out the radio. This is independent of
2760  * DMA channel suspension---the DMA may have finished suspending, or may still
2761  * be pulling data into a tx fifo, by the time the MAC acks the suspend
2762  * request.
2763  */
2764 static bool brcms_b_tx_fifo_suspended(struct brcms_hardware *wlc_hw,
2765                                       uint tx_fifo)
2766 {
2767         /* check that a suspend has been requested and is no longer pending */
2768
2769         /*
2770          * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
2771          * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
2772          * chnstatus register.
2773          * The tx fifo suspend completion is independent of the DMA suspend completion and
2774          *   may be acked before or after the DMA is suspended.
2775          */
2776         if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
2777             (R_REG(&wlc_hw->regs->chnstatus) &
2778              (1 << tx_fifo)) == 0)
2779                 return true;
2780
2781         return false;
2782 }
2783
2784 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2785                                     uint tx_fifo)
2786 {
2787         u8 fifo = 1 << tx_fifo;
2788
2789         /* Two clients of this code, 11h Quiet period and scanning. */
2790
2791         /* only suspend if not already suspended */
2792         if ((wlc_hw->suspended_fifos & fifo) == fifo)
2793                 return;
2794
2795         /* force the core awake only if not already */
2796         if (wlc_hw->suspended_fifos == 0)
2797                 brcms_c_ucode_wake_override_set(wlc_hw,
2798                                                 BRCMS_WAKE_OVERRIDE_TXFIFO);
2799
2800         wlc_hw->suspended_fifos |= fifo;
2801
2802         if (wlc_hw->di[tx_fifo]) {
2803                 /* Suspending AMPDU transmissions in the middle can cause underflow
2804                  * which may result in mismatch between ucode and driver
2805                  * so suspend the mac before suspending the FIFO
2806                  */
2807                 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2808                         brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2809
2810                 dma_txsuspend(wlc_hw->di[tx_fifo]);
2811
2812                 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2813                         brcms_c_enable_mac(wlc_hw->wlc);
2814         }
2815 }
2816
2817 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2818                                    uint tx_fifo)
2819 {
2820         /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2821          * but need to be done here for PIO otherwise the watchdog will catch
2822          * the inconsistency and fire
2823          */
2824         /* Two clients of this code, 11h Quiet period and scanning. */
2825         if (wlc_hw->di[tx_fifo])
2826                 dma_txresume(wlc_hw->di[tx_fifo]);
2827
2828         /* allow core to sleep again */
2829         if (wlc_hw->suspended_fifos == 0)
2830                 return;
2831         else {
2832                 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2833                 if (wlc_hw->suspended_fifos == 0)
2834                         brcms_c_ucode_wake_override_clear(wlc_hw,
2835                                                 BRCMS_WAKE_OVERRIDE_TXFIFO);
2836         }
2837 }
2838
2839 /*
2840  * Read and clear macintmask and macintstatus and intstatus registers.
2841  * This routine should be called with interrupts off
2842  * Return:
2843  *   -1 if DEVICEREMOVED(wlc) evaluates to true;
2844  *   0 if the interrupt is not for us, or we are in some special cases;
2845  *   device interrupt status bits otherwise.
2846  */
2847 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2848 {
2849         struct brcms_hardware *wlc_hw = wlc->hw;
2850         d11regs_t *regs = wlc_hw->regs;
2851         u32 macintstatus;
2852
2853         /* macintstatus includes a DMA interrupt summary bit */
2854         macintstatus = R_REG(&regs->macintstatus);
2855
2856         BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
2857                  macintstatus);
2858
2859         /* detect cardbus removed, in power down(suspend) and in reset */
2860         if (DEVICEREMOVED(wlc))
2861                 return -1;
2862
2863         /* DEVICEREMOVED succeeds even when the core is still resetting,
2864          * handle that case here.
2865          */
2866         if (macintstatus == 0xffffffff)
2867                 return 0;
2868
2869         /* defer unsolicited interrupts */
2870         macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2871
2872         /* if not for us */
2873         if (macintstatus == 0)
2874                 return 0;
2875
2876         /* interrupts are already turned off for CFE build
2877          * Caution: For CFE Turning off the interrupts again has some undesired
2878          * consequences
2879          */
2880         /* turn off the interrupts */
2881         W_REG(&regs->macintmask, 0);
2882         (void)R_REG(&regs->macintmask); /* sync readback */
2883         wlc->macintmask = 0;
2884
2885         /* clear device interrupts */
2886         W_REG(&regs->macintstatus, macintstatus);
2887
2888         /* MI_DMAINT is indication of non-zero intstatus */
2889         if (macintstatus & MI_DMAINT) {
2890                 /*
2891                  * only fifo interrupt enabled is I_RI in
2892                  * RX_FIFO. If MI_DMAINT is set, assume it
2893                  * is set and clear the interrupt.
2894                  */
2895                 W_REG(&regs->intctrlregs[RX_FIFO].intstatus,
2896                       DEF_RXINTMASK);
2897         }
2898
2899         return macintstatus;
2900 }
2901
2902 /* Update wlc->macintstatus and wlc->intstatus[]. */
2903 /* Return true if they are updated successfully. false otherwise */
2904 bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2905 {
2906         u32 macintstatus;
2907
2908         /* read and clear macintstatus and intstatus registers */
2909         macintstatus = wlc_intstatus(wlc, false);
2910
2911         /* device is removed */
2912         if (macintstatus == 0xffffffff)
2913                 return false;
2914
2915         /* update interrupt status in software */
2916         wlc->macintstatus |= macintstatus;
2917
2918         return true;
2919 }
2920
2921 /*
2922  * First-level interrupt processing.
2923  * Return true if this was our interrupt, false otherwise.
2924  * *wantdpc will be set to true if further brcms_c_dpc() processing is required,
2925  * false otherwise.
2926  */
2927 bool brcms_c_isr(struct brcms_c_info *wlc, bool *wantdpc)
2928 {
2929         struct brcms_hardware *wlc_hw = wlc->hw;
2930         u32 macintstatus;
2931
2932         *wantdpc = false;
2933
2934         if (!wlc_hw->up || !wlc->macintmask)
2935                 return false;
2936
2937         /* read and clear macintstatus and intstatus registers */
2938         macintstatus = wlc_intstatus(wlc, true);
2939
2940         if (macintstatus == 0xffffffff)
2941                 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
2942                           " path\n");
2943
2944         /* it is not for us */
2945         if (macintstatus == 0)
2946                 return false;
2947
2948         *wantdpc = true;
2949
2950         /* save interrupt status bits */
2951         wlc->macintstatus = macintstatus;
2952
2953         return true;
2954
2955 }
2956
2957 static bool
2958 brcms_b_dotxstatus(struct brcms_hardware *wlc_hw, struct tx_status *txs,
2959                    u32 s2)
2960 {
2961         /* discard intermediate indications for ucode with one legitimate case:
2962          *   e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
2963          *   tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
2964          *   transmission count)
2965          */
2966         if (!(txs->status & TX_STATUS_AMPDU)
2967             && (txs->status & TX_STATUS_INTERMEDIATE)) {
2968                 return false;
2969         }
2970
2971         return brcms_c_dotxstatus(wlc_hw->wlc, txs, s2);
2972 }
2973
2974 /* process tx completion events in BMAC
2975  * Return true if more tx status need to be processed. false otherwise.
2976  */
2977 static bool
2978 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
2979 {
2980         bool morepending = false;
2981         struct brcms_c_info *wlc = wlc_hw->wlc;
2982         d11regs_t *regs;
2983         struct tx_status txstatus, *txs;
2984         u32 s1, s2;
2985         uint n = 0;
2986         /*
2987          * Param 'max_tx_num' indicates max. # tx status to process before
2988          * break out.
2989          */
2990         uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
2991
2992         BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
2993
2994         txs = &txstatus;
2995         regs = wlc_hw->regs;
2996         while (!(*fatal)
2997                && (s1 = R_REG(&regs->frmtxstatus)) & TXS_V) {
2998
2999                 if (s1 == 0xffffffff) {
3000                         wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
3001                                 wlc_hw->unit, __func__);
3002                         return morepending;
3003                 }
3004
3005                         s2 = R_REG(&regs->frmtxstatus2);
3006
3007                 txs->status = s1 & TXS_STATUS_MASK;
3008                 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3009                 txs->sequence = s2 & TXS_SEQ_MASK;
3010                 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3011                 txs->lasttxtime = 0;
3012
3013                 *fatal = brcms_b_dotxstatus(wlc_hw, txs, s2);
3014
3015                 /* !give others some time to run! */
3016                 if (++n >= max_tx_num)
3017                         break;
3018         }
3019
3020         if (*fatal)
3021                 return 0;
3022
3023         if (n >= max_tx_num)
3024                 morepending = true;
3025
3026         if (!pktq_empty(&wlc->pkt_queue->q))
3027                 brcms_c_send_q(wlc);
3028
3029         return morepending;
3030 }
3031
3032 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
3033 {
3034         struct brcms_hardware *wlc_hw = wlc->hw;
3035         d11regs_t *regs = wlc_hw->regs;
3036         u32 mc, mi;
3037         struct wiphy *wiphy = wlc->wiphy;
3038
3039         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3040                 wlc_hw->band->bandunit);
3041
3042         /*
3043          * Track overlapping suspend requests
3044          */
3045         wlc_hw->mac_suspend_depth++;
3046         if (wlc_hw->mac_suspend_depth > 1)
3047                 return;
3048
3049         /* force the core awake */
3050         brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3051
3052         mc = R_REG(&regs->maccontrol);
3053
3054         if (mc == 0xffffffff) {
3055                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3056                           __func__);
3057                 brcms_down(wlc->wl);
3058                 return;
3059         }
3060         WARN_ON(mc & MCTL_PSM_JMP_0);
3061         WARN_ON(!(mc & MCTL_PSM_RUN));
3062         WARN_ON(!(mc & MCTL_EN_MAC));
3063
3064         mi = R_REG(&regs->macintstatus);
3065         if (mi == 0xffffffff) {
3066                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3067                           __func__);
3068                 brcms_down(wlc->wl);
3069                 return;
3070         }
3071         WARN_ON(mi & MI_MACSSPNDD);
3072
3073         brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3074
3075         SPINWAIT(!(R_REG(&regs->macintstatus) & MI_MACSSPNDD),
3076                  BRCMS_MAX_MAC_SUSPEND);
3077
3078         if (!(R_REG(&regs->macintstatus) & MI_MACSSPNDD)) {
3079                 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
3080                           " and MI_MACSSPNDD is still not on.\n",
3081                           wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
3082                 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
3083                           "psm_brc 0x%04x\n", wlc_hw->unit,
3084                           R_REG(&regs->psmdebug),
3085                           R_REG(&regs->phydebug),
3086                           R_REG(&regs->psm_brc));
3087         }
3088
3089         mc = R_REG(&regs->maccontrol);
3090         if (mc == 0xffffffff) {
3091                 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
3092                           __func__);
3093                 brcms_down(wlc->wl);
3094                 return;
3095         }
3096         WARN_ON(mc & MCTL_PSM_JMP_0);
3097         WARN_ON(!(mc & MCTL_PSM_RUN));
3098         WARN_ON(mc & MCTL_EN_MAC);
3099 }
3100
3101 void brcms_c_enable_mac(struct brcms_c_info *wlc)
3102 {
3103         struct brcms_hardware *wlc_hw = wlc->hw;
3104         d11regs_t *regs = wlc_hw->regs;
3105         u32 mc, mi;
3106
3107         BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
3108                 wlc->band->bandunit);
3109
3110         /*
3111          * Track overlapping suspend requests
3112          */
3113         wlc_hw->mac_suspend_depth--;
3114         if (wlc_hw->mac_suspend_depth > 0)
3115                 return;
3116
3117         mc = R_REG(&regs->maccontrol);
3118         WARN_ON(mc & MCTL_PSM_JMP_0);
3119         WARN_ON(mc & MCTL_EN_MAC);
3120         WARN_ON(!(mc & MCTL_PSM_RUN));
3121
3122         brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3123         W_REG(&regs->macintstatus, MI_MACSSPNDD);
3124
3125         mc = R_REG(&regs->maccontrol);
3126         WARN_ON(mc & MCTL_PSM_JMP_0);
3127         WARN_ON(!(mc & MCTL_EN_MAC));
3128         WARN_ON(!(mc & MCTL_PSM_RUN));
3129
3130         mi = R_REG(&regs->macintstatus);
3131         WARN_ON(mi & MI_MACSSPNDD);
3132
3133         brcms_c_ucode_wake_override_clear(wlc_hw,
3134                                           BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3135 }
3136
3137 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
3138 {
3139         u8 rate;
3140         u8 rates[8] = {
3141                 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
3142                 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
3143         };
3144         u16 entry_ptr;
3145         u16 pctl1;
3146         uint i;
3147
3148         if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
3149                 return;
3150
3151         /* walk the phy rate table and update the entries */
3152         for (i = 0; i < ARRAY_SIZE(rates); i++) {
3153                 rate = rates[i];
3154
3155                 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
3156
3157                 /* read the SHM Rate Table entry OFDM PCTL1 values */
3158                 pctl1 =
3159                     brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3160
3161                 /* modify the value */
3162                 pctl1 &= ~PHY_TXC1_MODE_MASK;
3163                 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3164
3165                 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3166                 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3167                                    pctl1);
3168         }
3169 }
3170
3171 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
3172                                          u8 rate)
3173 {
3174         uint i;
3175         u8 plcp_rate = 0;
3176         struct plcp_signal_rate_lookup {
3177                 u8 rate;
3178                 u8 signal_rate;
3179         };
3180         /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3181         const struct plcp_signal_rate_lookup rate_lookup[] = {
3182                 {BRCM_RATE_6M, 0xB},
3183                 {BRCM_RATE_9M, 0xF},
3184                 {BRCM_RATE_12M, 0xA},
3185                 {BRCM_RATE_18M, 0xE},
3186                 {BRCM_RATE_24M, 0x9},
3187                 {BRCM_RATE_36M, 0xD},
3188                 {BRCM_RATE_48M, 0x8},
3189                 {BRCM_RATE_54M, 0xC}
3190         };
3191
3192         for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
3193                 if (rate == rate_lookup[i].rate) {
3194                         plcp_rate = rate_lookup[i].signal_rate;
3195                         break;
3196                 }
3197         }
3198
3199         /* Find the SHM pointer to the rate table entry by looking in the
3200          * Direct-map Table
3201          */
3202         return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
3203 }
3204
3205 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
3206 {
3207         wlc_hw->hw_stf_ss_opmode = stf_mode;
3208
3209         if (wlc_hw->clk)
3210                 brcms_upd_ofdm_pctl1_table(wlc_hw);
3211 }
3212
3213 void
3214 brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
3215                   u32 *tsf_h_ptr)
3216 {
3217         d11regs_t *regs = wlc_hw->regs;
3218
3219         /* read the tsf timer low, then high to get an atomic read */
3220         *tsf_l_ptr = R_REG(&regs->tsf_timerlow);
3221         *tsf_h_ptr = R_REG(&regs->tsf_timerhigh);
3222
3223         return;
3224 }
3225
3226 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
3227 {
3228         d11regs_t *regs;
3229         u32 w, val;
3230         struct wiphy *wiphy = wlc_hw->wlc->wiphy;
3231
3232         BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
3233
3234         regs = wlc_hw->regs;
3235
3236         /* Validate dchip register access */
3237
3238         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3239         (void)R_REG(&regs->objaddr);
3240         w = R_REG(&regs->objdata);
3241
3242         /* Can we write and read back a 32bit register? */
3243         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3244         (void)R_REG(&regs->objaddr);
3245         W_REG(&regs->objdata, (u32) 0xaa5555aa);
3246
3247         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3248         (void)R_REG(&regs->objaddr);
3249         val = R_REG(&regs->objdata);
3250         if (val != (u32) 0xaa5555aa) {
3251                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3252                           "expected 0xaa5555aa\n", wlc_hw->unit, val);
3253                 return false;
3254         }
3255
3256         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3257         (void)R_REG(&regs->objaddr);
3258         W_REG(&regs->objdata, (u32) 0x55aaaa55);
3259
3260         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3261         (void)R_REG(&regs->objaddr);
3262         val = R_REG(&regs->objdata);
3263         if (val != (u32) 0x55aaaa55) {
3264                 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
3265                           "expected 0x55aaaa55\n", wlc_hw->unit, val);
3266                 return false;
3267         }
3268
3269         W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
3270         (void)R_REG(&regs->objaddr);
3271         W_REG(&regs->objdata, w);
3272
3273         /* clear CFPStart */
3274         W_REG(&regs->tsf_cfpstart, 0);
3275
3276         w = R_REG(&regs->maccontrol);
3277         if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3278             (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3279                 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
3280                           "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
3281                           (MCTL_IHR_EN | MCTL_WAKE),
3282                           (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
3283                 return false;
3284         }
3285
3286         return true;
3287 }
3288
3289 #define PHYPLL_WAIT_US  100000
3290
3291 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
3292 {
3293         d11regs_t *regs;
3294         u32 tmp;
3295
3296         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3297
3298         tmp = 0;
3299         regs = wlc_hw->regs;
3300
3301         if (on) {
3302                 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3303                         OR_REG(&regs->clk_ctl_st,
3304                                (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3305                                 CCS_ERSRC_REQ_PHYPLL));
3306                         SPINWAIT((R_REG(&regs->clk_ctl_st) &
3307                                   (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3308                                  PHYPLL_WAIT_US);
3309
3310                         tmp = R_REG(&regs->clk_ctl_st);
3311                         if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3312                             (CCS_ERSRC_AVAIL_HT)) {
3313                                 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
3314                                           " PLL failed\n", __func__);
3315                         }
3316                 } else {
3317                         OR_REG(&regs->clk_ctl_st,
3318                                (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3319                         SPINWAIT((R_REG(&regs->clk_ctl_st) &
3320                                   (CCS_ERSRC_AVAIL_D11PLL |
3321                                    CCS_ERSRC_AVAIL_PHYPLL)) !=
3322                                  (CCS_ERSRC_AVAIL_D11PLL |
3323                                   CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3324
3325                         tmp = R_REG(&regs->clk_ctl_st);
3326                         if ((tmp &
3327                              (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3328                             !=
3329                             (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3330                                 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
3331                                           "PHY PLL failed\n", __func__);
3332                         }
3333                 }
3334         } else {
3335                 /* Since the PLL may be shared, other cores can still be requesting it;
3336                  * so we'll deassert the request but not wait for status to comply.
3337                  */
3338                 AND_REG(&regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3339                 tmp = R_REG(&regs->clk_ctl_st);
3340         }
3341 }
3342
3343 void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
3344 {
3345         bool dev_gone;
3346
3347         BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3348
3349         dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3350
3351         if (dev_gone)
3352                 return;
3353
3354         if (wlc_hw->noreset)
3355                 return;
3356
3357         /* radio off */
3358         wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3359
3360         /* turn off analog core */
3361         wlc_phy_anacore(wlc_hw->band->pi, OFF);
3362
3363         /* turn off PHYPLL to save power */
3364         brcms_b_core_phypll_ctl(wlc_hw, false);
3365
3366         /* No need to set wlc->pub->radio_active = OFF
3367          * because this function needs down capability and
3368          * radio_active is designed for BCMNODOWN.
3369          */
3370
3371         /* remove gpio controls */
3372         if (wlc_hw->ucode_dbgsel)
3373                 ai_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3374
3375         wlc_hw->clk = false;
3376         ai_core_disable(wlc_hw->sih, 0);
3377         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3378 }
3379
3380 /* power both the pll and external oscillator on/off */
3381 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
3382 {
3383         BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
3384
3385         /* dont power down if plldown is false or we must poll hw radio disable */
3386         if (!want && wlc_hw->pllreq)
3387                 return;
3388
3389         if (wlc_hw->sih)
3390                 ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3391
3392         wlc_hw->sbclk = want;
3393         if (!wlc_hw->sbclk) {
3394                 wlc_hw->clk = false;
3395                 if (wlc_hw->band && wlc_hw->band->pi)
3396                         wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
3397         }
3398 }
3399
3400 static void brcms_c_flushqueues(struct brcms_c_info *wlc)
3401 {
3402         struct brcms_hardware *wlc_hw = wlc->hw;
3403         uint i;
3404
3405         wlc->txpend16165war = 0;
3406
3407         /* free any posted tx packets */
3408         for (i = 0; i < NFIFO; i++)
3409                 if (wlc_hw->di[i]) {
3410                         dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
3411                         TXPKTPENDCLR(wlc, i);
3412                         BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
3413                 }
3414
3415         /* free any posted rx packets */
3416         dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3417 }
3418
3419 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
3420 {
3421         return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3422 }
3423
3424 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
3425 {
3426         brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3427 }
3428
3429 static u16
3430 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
3431 {
3432         d11regs_t *regs = wlc_hw->regs;
3433         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3434         volatile u16 *objdata_hi = objdata_lo + 1;
3435         u16 v;
3436
3437         W_REG(&regs->objaddr, sel | (offset >> 2));
3438         (void)R_REG(&regs->objaddr);
3439         if (offset & 2) {
3440                 v = R_REG(objdata_hi);
3441         } else {
3442                 v = R_REG(objdata_lo);
3443         }
3444
3445         return v;
3446 }
3447
3448 static void
3449 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
3450                      u32 sel)
3451 {
3452         d11regs_t *regs = wlc_hw->regs;
3453         volatile u16 *objdata_lo = (volatile u16 *)&regs->objdata;
3454         volatile u16 *objdata_hi = objdata_lo + 1;
3455
3456         W_REG(&regs->objaddr, sel | (offset >> 2));
3457         (void)R_REG(&regs->objaddr);
3458         if (offset & 2) {
3459                 W_REG(objdata_hi, v);
3460         } else {
3461                 W_REG(objdata_lo, v);
3462         }
3463 }
3464
3465 /* Copy a buffer to shared memory of specified type .
3466  * SHM 'offset' needs to be an even address and
3467  * Buffer length 'len' must be an even number of bytes
3468  * 'sel' selects the type of memory
3469  */
3470 void
3471 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
3472                       const void *buf, int len, u32 sel)
3473 {
3474         u16 v;
3475         const u8 *p = (const u8 *)buf;
3476         int i;
3477
3478         if (len <= 0 || (offset & 1) || (len & 1))
3479                 return;
3480
3481         for (i = 0; i < len; i += 2) {
3482                 v = p[i] | (p[i + 1] << 8);
3483                 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
3484         }
3485 }
3486
3487 /* Copy a piece of shared memory of specified type to a buffer .
3488  * SHM 'offset' needs to be an even address and
3489  * Buffer length 'len' must be an even number of bytes
3490  * 'sel' selects the type of memory
3491  */
3492 void
3493 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
3494                          int len, u32 sel)
3495 {
3496         u16 v;
3497         u8 *p = (u8 *) buf;
3498         int i;
3499
3500         if (len <= 0 || (offset & 1) || (len & 1))
3501                 return;
3502
3503         for (i = 0; i < len; i += 2) {
3504                 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
3505                 p[i] = v & 0xFF;
3506                 p[i + 1] = (v >> 8) & 0xFF;
3507         }
3508 }
3509
3510 void brcms_b_copyfrom_vars(struct brcms_hardware *wlc_hw, char **buf,
3511                            uint *len)
3512 {
3513         BCMMSG(wlc_hw->wlc->wiphy, "nvram vars totlen=%d\n",
3514                 wlc_hw->vars_size);
3515
3516         *buf = wlc_hw->vars;
3517         *len = wlc_hw->vars_size;
3518 }
3519
3520 void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw, u16 SRL, u16 LRL)
3521 {
3522         wlc_hw->SRL = SRL;
3523         wlc_hw->LRL = LRL;
3524
3525         /* write retry limit to SCR, shouldn't need to suspend */
3526         if (wlc_hw->up) {
3527                 W_REG(&wlc_hw->regs->objaddr,
3528                       OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3529                 (void)R_REG(&wlc_hw->regs->objaddr);
3530                 W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL);
3531                 W_REG(&wlc_hw->regs->objaddr,
3532                       OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3533                 (void)R_REG(&wlc_hw->regs->objaddr);
3534                 W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL);
3535         }
3536 }
3537
3538 void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, mbool req_bit)
3539 {
3540         if (set) {
3541                 if (mboolisset(wlc_hw->pllreq, req_bit))
3542                         return;
3543
3544                 mboolset(wlc_hw->pllreq, req_bit);
3545
3546                 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3547                         if (!wlc_hw->sbclk) {
3548                                 brcms_b_xtal(wlc_hw, ON);
3549                         }
3550                 }
3551         } else {
3552                 if (!mboolisset(wlc_hw->pllreq, req_bit))
3553                         return;
3554
3555                 mboolclr(wlc_hw->pllreq, req_bit);
3556
3557                 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3558                         if (wlc_hw->sbclk) {
3559                                 brcms_b_xtal(wlc_hw, OFF);
3560                         }
3561                 }
3562         }
3563
3564         return;
3565 }
3566
3567 u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
3568 {
3569         u16 table_ptr;
3570         u8 phy_rate, index;
3571
3572         /* get the phy specific rate encoding for the PLCP SIGNAL field */
3573         if (IS_OFDM(rate))
3574                 table_ptr = M_RT_DIRMAP_A;
3575         else
3576                 table_ptr = M_RT_DIRMAP_B;
3577
3578         /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
3579          * the index into the rate table.
3580          */
3581         phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
3582         index = phy_rate & 0xf;
3583
3584         /* Find the SHM pointer to the rate table entry by looking in the
3585          * Direct-map Table
3586          */
3587         return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
3588 }
3589
3590 void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3591 {
3592         wlc_hw->antsel_avail = antsel_avail;
3593 }