2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 #include <linux/types.h>
17 #include <linux/netdevice.h>
21 #include <sdio.h> /* SDIO Device and Protocol Specs */
22 #include <sdioh.h> /* SDIO Host Controller Specification */
23 #include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
24 #include <sdiovar.h> /* ioctl/iovars */
26 #include <linux/mmc/core.h>
27 #include <linux/mmc/sdio_func.h>
28 #include <linux/mmc/sdio_ids.h>
29 #include <linux/suspend.h>
31 #include <dngl_stats.h>
34 #include "bcmsdh_sdmmc.h"
36 extern int sdio_function_init(void);
37 extern void sdio_function_cleanup(void);
39 #if !defined(OOB_INTR_ONLY)
40 static void IRQHandler(struct sdio_func *func);
41 static void IRQHandlerF2(struct sdio_func *func);
42 #endif /* !defined(OOB_INTR_ONLY) */
43 static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, u32 regaddr);
44 extern int sdio_reset_comm(struct mmc_card *card);
46 extern PBCMSDH_SDMMC_INSTANCE gInstance;
48 uint sd_sdmode = SDIOH_MODE_SD4; /* Use SD4 mode by default */
49 uint sd_f2_blocksize = 512; /* Default blocksize */
51 uint sd_divisor = 2; /* Default 48MHz/2 = 24MHz */
53 uint sd_power = 1; /* Default to SD Slot powered ON */
54 uint sd_clock = 1; /* Default to SD Clock turned ON */
55 uint sd_hiok = false; /* Don't use hi-speed mode by default */
56 uint sd_msglevel = 0x01;
57 uint sd_use_dma = true;
58 DHD_PM_RESUME_WAIT_INIT(sdioh_request_byte_wait);
59 DHD_PM_RESUME_WAIT_INIT(sdioh_request_word_wait);
60 DHD_PM_RESUME_WAIT_INIT(sdioh_request_packet_wait);
61 DHD_PM_RESUME_WAIT_INIT(sdioh_request_buffer_wait);
63 #define DMA_ALIGN_MASK 0x03
65 int sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, u32 regaddr,
66 int regsize, u32 *data);
68 void sdioh_sdio_set_host_pm_flags(int flag)
70 if (sdio_set_host_pm_flags(gInstance->func[1], flag))
71 printk(KERN_ERR "%s: Failed to set pm_flags 0x%08x\n",\
72 __func__, (unsigned int)flag);
75 static int sdioh_sdmmc_card_enablefuncs(sdioh_info_t *sd)
81 sd_trace(("%s\n", __func__));
83 /* Get the Card's common CIS address */
84 sd->com_cis_ptr = sdioh_sdmmc_get_cisaddr(sd, SDIOD_CCCR_CISPTR_0);
85 sd->func_cis_ptr[0] = sd->com_cis_ptr;
86 sd_info(("%s: Card's Common CIS Ptr = 0x%x\n", __func__,
89 /* Get the Card's function CIS (for each function) */
90 for (fbraddr = SDIOD_FBR_STARTADDR, func = 1;
91 func <= sd->num_funcs; func++, fbraddr += SDIOD_FBR_SIZE) {
92 sd->func_cis_ptr[func] =
93 sdioh_sdmmc_get_cisaddr(sd, SDIOD_FBR_CISPTR_0 + fbraddr);
94 sd_info(("%s: Function %d CIS Ptr = 0x%x\n", __func__, func,
95 sd->func_cis_ptr[func]));
98 sd->func_cis_ptr[0] = sd->com_cis_ptr;
99 sd_info(("%s: Card's Common CIS Ptr = 0x%x\n", __func__,
102 /* Enable Function 1 */
103 sdio_claim_host(gInstance->func[1]);
104 err_ret = sdio_enable_func(gInstance->func[1]);
105 sdio_release_host(gInstance->func[1]);
107 sd_err(("bcmsdh_sdmmc: Failed to enable F1 Err: 0x%08x",
115 * Public entry points & extern's
117 sdioh_info_t *sdioh_attach(void *bar0, uint irq)
122 sd_trace(("%s\n", __func__));
124 if (gInstance == NULL) {
125 sd_err(("%s: SDIO Device not present\n", __func__));
129 sd = kzalloc(sizeof(sdioh_info_t), GFP_ATOMIC);
131 sd_err(("sdioh_attach: out of memory\n"));
134 if (sdioh_sdmmc_osinit(sd) != 0) {
135 sd_err(("%s:sdioh_sdmmc_osinit() failed\n", __func__));
141 sd->sd_blockmode = true;
142 sd->use_client_ints = true;
143 sd->client_block_size[0] = 64;
147 /* Claim host controller */
148 sdio_claim_host(gInstance->func[1]);
150 sd->client_block_size[1] = 64;
151 err_ret = sdio_set_block_size(gInstance->func[1], 64);
153 sd_err(("bcmsdh_sdmmc: Failed to set F1 blocksize\n"));
155 /* Release host controller F1 */
156 sdio_release_host(gInstance->func[1]);
158 if (gInstance->func[2]) {
159 /* Claim host controller F2 */
160 sdio_claim_host(gInstance->func[2]);
162 sd->client_block_size[2] = sd_f2_blocksize;
164 sdio_set_block_size(gInstance->func[2], sd_f2_blocksize);
166 sd_err(("bcmsdh_sdmmc: Failed to set F2 blocksize "
167 "to %d\n", sd_f2_blocksize));
169 /* Release host controller F2 */
170 sdio_release_host(gInstance->func[2]);
173 sdioh_sdmmc_card_enablefuncs(sd);
175 sd_trace(("%s: Done\n", __func__));
179 extern SDIOH_API_RC sdioh_detach(sdioh_info_t *sd)
181 sd_trace(("%s\n", __func__));
185 /* Disable Function 2 */
186 sdio_claim_host(gInstance->func[2]);
187 sdio_disable_func(gInstance->func[2]);
188 sdio_release_host(gInstance->func[2]);
190 /* Disable Function 1 */
191 sdio_claim_host(gInstance->func[1]);
192 sdio_disable_func(gInstance->func[1]);
193 sdio_release_host(gInstance->func[1]);
196 sdioh_sdmmc_osfree(sd);
200 return SDIOH_API_RC_SUCCESS;
203 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
205 extern SDIOH_API_RC sdioh_enable_func_intr(void)
210 if (gInstance->func[0]) {
211 sdio_claim_host(gInstance->func[0]);
213 reg = sdio_readb(gInstance->func[0], SDIOD_CCCR_INTEN, &err);
215 sd_err(("%s: error for read SDIO_CCCR_IENx : 0x%x\n",
217 sdio_release_host(gInstance->func[0]);
218 return SDIOH_API_RC_FAIL;
221 /* Enable F1 and F2 interrupts, set master enable */
223 (INTR_CTL_FUNC1_EN | INTR_CTL_FUNC2_EN |
226 sdio_writeb(gInstance->func[0], reg, SDIOD_CCCR_INTEN, &err);
227 sdio_release_host(gInstance->func[0]);
230 sd_err(("%s: error for write SDIO_CCCR_IENx : 0x%x\n",
232 return SDIOH_API_RC_FAIL;
236 return SDIOH_API_RC_SUCCESS;
239 extern SDIOH_API_RC sdioh_disable_func_intr(void)
244 if (gInstance->func[0]) {
245 sdio_claim_host(gInstance->func[0]);
246 reg = sdio_readb(gInstance->func[0], SDIOD_CCCR_INTEN, &err);
248 sd_err(("%s: error for read SDIO_CCCR_IENx : 0x%x\n",
250 sdio_release_host(gInstance->func[0]);
251 return SDIOH_API_RC_FAIL;
254 reg &= ~(INTR_CTL_FUNC1_EN | INTR_CTL_FUNC2_EN);
255 /* Disable master interrupt with the last function interrupt */
258 sdio_writeb(gInstance->func[0], reg, SDIOD_CCCR_INTEN, &err);
260 sdio_release_host(gInstance->func[0]);
262 sd_err(("%s: error for write SDIO_CCCR_IENx : 0x%x\n",
264 return SDIOH_API_RC_FAIL;
267 return SDIOH_API_RC_SUCCESS;
269 #endif /* defined(OOB_INTR_ONLY) && defined(HW_OOB) */
271 /* Configure callback to client when we receive client interrupt */
273 sdioh_interrupt_register(sdioh_info_t *sd, sdioh_cb_fn_t fn, void *argh)
275 sd_trace(("%s: Entering\n", __func__));
277 sd_err(("%s: interrupt handler is NULL, not registering\n",
279 return SDIOH_API_RC_FAIL;
281 #if !defined(OOB_INTR_ONLY)
282 sd->intr_handler = fn;
283 sd->intr_handler_arg = argh;
284 sd->intr_handler_valid = true;
286 /* register and unmask irq */
287 if (gInstance->func[2]) {
288 sdio_claim_host(gInstance->func[2]);
289 sdio_claim_irq(gInstance->func[2], IRQHandlerF2);
290 sdio_release_host(gInstance->func[2]);
293 if (gInstance->func[1]) {
294 sdio_claim_host(gInstance->func[1]);
295 sdio_claim_irq(gInstance->func[1], IRQHandler);
296 sdio_release_host(gInstance->func[1]);
298 #elif defined(HW_OOB)
299 sdioh_enable_func_intr();
300 #endif /* defined(OOB_INTR_ONLY) */
301 return SDIOH_API_RC_SUCCESS;
304 extern SDIOH_API_RC sdioh_interrupt_deregister(sdioh_info_t *sd)
306 sd_trace(("%s: Entering\n", __func__));
308 #if !defined(OOB_INTR_ONLY)
309 if (gInstance->func[1]) {
310 /* register and unmask irq */
311 sdio_claim_host(gInstance->func[1]);
312 sdio_release_irq(gInstance->func[1]);
313 sdio_release_host(gInstance->func[1]);
316 if (gInstance->func[2]) {
317 /* Claim host controller F2 */
318 sdio_claim_host(gInstance->func[2]);
319 sdio_release_irq(gInstance->func[2]);
320 /* Release host controller F2 */
321 sdio_release_host(gInstance->func[2]);
324 sd->intr_handler_valid = false;
325 sd->intr_handler = NULL;
326 sd->intr_handler_arg = NULL;
327 #elif defined(HW_OOB)
328 sdioh_disable_func_intr();
329 #endif /* !defined(OOB_INTR_ONLY) */
330 return SDIOH_API_RC_SUCCESS;
333 extern SDIOH_API_RC sdioh_interrupt_query(sdioh_info_t *sd, bool *onoff)
335 sd_trace(("%s: Entering\n", __func__));
336 *onoff = sd->client_intr_enabled;
337 return SDIOH_API_RC_SUCCESS;
340 #if defined(DHD_DEBUG)
341 extern bool sdioh_interrupt_pending(sdioh_info_t *sd)
347 uint sdioh_query_iofnum(sdioh_info_t *sd)
349 return sd->num_funcs;
372 const bcm_iovar_t sdioh_iovars[] = {
373 {"sd_msglevel", IOV_MSGLEVEL, 0, IOVT_UINT32, 0},
374 {"sd_blockmode", IOV_BLOCKMODE, 0, IOVT_BOOL, 0},
375 {"sd_blocksize", IOV_BLOCKSIZE, 0, IOVT_UINT32, 0},/* ((fn << 16) |
377 {"sd_dma", IOV_DMA, 0, IOVT_BOOL, 0},
378 {"sd_ints", IOV_USEINTS, 0, IOVT_BOOL, 0},
379 {"sd_numints", IOV_NUMINTS, 0, IOVT_UINT32, 0},
380 {"sd_numlocalints", IOV_NUMLOCALINTS, 0, IOVT_UINT32, 0},
381 {"sd_hostreg", IOV_HOSTREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
383 {"sd_devreg", IOV_DEVREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
385 {"sd_divisor", IOV_DIVISOR, 0, IOVT_UINT32, 0}
387 {"sd_power", IOV_POWER, 0, IOVT_UINT32, 0}
389 {"sd_clock", IOV_CLOCK, 0, IOVT_UINT32, 0}
391 {"sd_mode", IOV_SDMODE, 0, IOVT_UINT32, 100}
393 {"sd_highspeed", IOV_HISPEED, 0, IOVT_UINT32, 0}
395 {"sd_rxchain", IOV_RXCHAIN, 0, IOVT_BOOL, 0}
401 sdioh_iovar_op(sdioh_info_t *si, const char *name,
402 void *params, int plen, void *arg, int len, bool set)
404 const bcm_iovar_t *vi = NULL;
414 /* Get must have return space; Set does not take qualifiers */
415 ASSERT(set || (arg && len));
416 ASSERT(!set || (!params && !plen));
418 sd_trace(("%s: Enter (%s %s)\n", __func__, (set ? "set" : "get"),
421 vi = bcm_iovar_lookup(sdioh_iovars, name);
423 bcmerror = -ENOTSUPP;
427 bcmerror = bcm_iovar_lencheck(vi, arg, len, set);
431 /* Set up params so get and set can share the convenience variables */
432 if (params == NULL) {
437 if (vi->type == IOVT_VOID)
439 else if (vi->type == IOVT_BUFFER)
442 val_size = sizeof(int);
444 if (plen >= (int)sizeof(int_val))
445 memcpy(&int_val, params, sizeof(int_val));
447 bool_val = (int_val != 0) ? true : false;
449 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
451 case IOV_GVAL(IOV_MSGLEVEL):
452 int_val = (s32) sd_msglevel;
453 memcpy(arg, &int_val, val_size);
456 case IOV_SVAL(IOV_MSGLEVEL):
457 sd_msglevel = int_val;
460 case IOV_GVAL(IOV_BLOCKMODE):
461 int_val = (s32) si->sd_blockmode;
462 memcpy(arg, &int_val, val_size);
465 case IOV_SVAL(IOV_BLOCKMODE):
466 si->sd_blockmode = (bool) int_val;
467 /* Haven't figured out how to make non-block mode with DMA */
470 case IOV_GVAL(IOV_BLOCKSIZE):
471 if ((u32) int_val > si->num_funcs) {
475 int_val = (s32) si->client_block_size[int_val];
476 memcpy(arg, &int_val, val_size);
479 case IOV_SVAL(IOV_BLOCKSIZE):
481 uint func = ((u32) int_val >> 16);
482 uint blksize = (u16) int_val;
485 if (func > si->num_funcs) {
495 maxsize = BLOCK_SIZE_4318;
498 maxsize = BLOCK_SIZE_4328;
503 if (blksize > maxsize) {
511 si->client_block_size[func] = blksize;
516 case IOV_GVAL(IOV_RXCHAIN):
518 memcpy(arg, &int_val, val_size);
521 case IOV_GVAL(IOV_DMA):
522 int_val = (s32) si->sd_use_dma;
523 memcpy(arg, &int_val, val_size);
526 case IOV_SVAL(IOV_DMA):
527 si->sd_use_dma = (bool) int_val;
530 case IOV_GVAL(IOV_USEINTS):
531 int_val = (s32) si->use_client_ints;
532 memcpy(arg, &int_val, val_size);
535 case IOV_SVAL(IOV_USEINTS):
536 si->use_client_ints = (bool) int_val;
537 if (si->use_client_ints)
538 si->intmask |= CLIENT_INTR;
540 si->intmask &= ~CLIENT_INTR;
544 case IOV_GVAL(IOV_DIVISOR):
545 int_val = (u32) sd_divisor;
546 memcpy(arg, &int_val, val_size);
549 case IOV_SVAL(IOV_DIVISOR):
550 sd_divisor = int_val;
553 case IOV_GVAL(IOV_POWER):
554 int_val = (u32) sd_power;
555 memcpy(arg, &int_val, val_size);
558 case IOV_SVAL(IOV_POWER):
562 case IOV_GVAL(IOV_CLOCK):
563 int_val = (u32) sd_clock;
564 memcpy(arg, &int_val, val_size);
567 case IOV_SVAL(IOV_CLOCK):
571 case IOV_GVAL(IOV_SDMODE):
572 int_val = (u32) sd_sdmode;
573 memcpy(arg, &int_val, val_size);
576 case IOV_SVAL(IOV_SDMODE):
580 case IOV_GVAL(IOV_HISPEED):
581 int_val = (u32) sd_hiok;
582 memcpy(arg, &int_val, val_size);
585 case IOV_SVAL(IOV_HISPEED):
589 case IOV_GVAL(IOV_NUMINTS):
590 int_val = (s32) si->intrcount;
591 memcpy(arg, &int_val, val_size);
594 case IOV_GVAL(IOV_NUMLOCALINTS):
596 memcpy(arg, &int_val, val_size);
599 case IOV_GVAL(IOV_HOSTREG):
601 sdreg_t *sd_ptr = (sdreg_t *) params;
603 if (sd_ptr->offset < SD_SysAddr
604 || sd_ptr->offset > SD_MaxCurCap) {
605 sd_err(("%s: bad offset 0x%x\n", __func__,
611 sd_trace(("%s: rreg%d at offset %d\n", __func__,
612 (sd_ptr->offset & 1) ? 8
613 : ((sd_ptr->offset & 2) ? 16 : 32),
615 if (sd_ptr->offset & 1)
616 int_val = 8; /* sdioh_sdmmc_rreg8(si,
618 else if (sd_ptr->offset & 2)
619 int_val = 16; /* sdioh_sdmmc_rreg16(si,
622 int_val = 32; /* sdioh_sdmmc_rreg(si,
625 memcpy(arg, &int_val, sizeof(int_val));
629 case IOV_SVAL(IOV_HOSTREG):
631 sdreg_t *sd_ptr = (sdreg_t *) params;
633 if (sd_ptr->offset < SD_SysAddr
634 || sd_ptr->offset > SD_MaxCurCap) {
635 sd_err(("%s: bad offset 0x%x\n", __func__,
641 sd_trace(("%s: wreg%d value 0x%08x at offset %d\n",
642 __func__, sd_ptr->value,
643 (sd_ptr->offset & 1) ? 8
644 : ((sd_ptr->offset & 2) ? 16 : 32),
649 case IOV_GVAL(IOV_DEVREG):
651 sdreg_t *sd_ptr = (sdreg_t *) params;
655 (si, sd_ptr->func, sd_ptr->offset, &data)) {
661 memcpy(arg, &int_val, sizeof(int_val));
665 case IOV_SVAL(IOV_DEVREG):
667 sdreg_t *sd_ptr = (sdreg_t *) params;
668 u8 data = (u8) sd_ptr->value;
671 (si, sd_ptr->func, sd_ptr->offset, &data)) {
679 bcmerror = -ENOTSUPP;
687 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
689 SDIOH_API_RC sdioh_enable_hw_oob_intr(sdioh_info_t *sd, bool enable)
695 data = 3; /* enable hw oob interrupt */
697 data = 4; /* disable hw oob interrupt */
698 data |= 4; /* Active HIGH */
700 status = sdioh_request_byte(sd, SDIOH_WRITE, 0, 0xf2, &data);
703 #endif /* defined(OOB_INTR_ONLY) && defined(HW_OOB) */
706 sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, u32 addr, u8 *data)
709 /* No lock needed since sdioh_request_byte does locking */
710 status = sdioh_request_byte(sd, SDIOH_READ, fnc_num, addr, data);
715 sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, u32 addr, u8 *data)
717 /* No lock needed since sdioh_request_byte does locking */
719 status = sdioh_request_byte(sd, SDIOH_WRITE, fnc_num, addr, data);
723 static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, u32 regaddr)
725 /* read 24 bits and return valid 17 bit addr */
727 u32 scratch, regdata;
728 u8 *ptr = (u8 *)&scratch;
729 for (i = 0; i < 3; i++) {
730 if ((sdioh_sdmmc_card_regread(sd, 0, regaddr, 1, ®data)) !=
732 sd_err(("%s: Can't read!\n", __func__));
734 *ptr++ = (u8) regdata;
738 /* Only the lower 17-bits are valid */
739 scratch = le32_to_cpu(scratch);
740 scratch &= 0x0001FFFF;
745 sdioh_cis_read(sdioh_info_t *sd, uint func, u8 *cisd, u32 length)
752 sd_trace(("%s: Func = %d\n", __func__, func));
754 if (!sd->func_cis_ptr[func]) {
755 memset(cis, 0, length);
756 sd_err(("%s: no func_cis_ptr[%d]\n", __func__, func));
757 return SDIOH_API_RC_FAIL;
760 sd_err(("%s: func_cis_ptr[%d]=0x%04x\n", __func__, func,
761 sd->func_cis_ptr[func]));
763 for (count = 0; count < length; count++) {
764 offset = sd->func_cis_ptr[func] + count;
765 if (sdioh_sdmmc_card_regread(sd, 0, offset, 1, &foo) < 0) {
766 sd_err(("%s: regread failed: Can't read CIS\n",
768 return SDIOH_API_RC_FAIL;
771 *cis = (u8) (foo & 0xff);
775 return SDIOH_API_RC_SUCCESS;
779 sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr,
784 sd_info(("%s: rw=%d, func=%d, addr=0x%05x\n", __func__, rw, func,
787 DHD_PM_RESUME_WAIT(sdioh_request_byte_wait);
788 DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
789 if (rw) { /* CMD52 Write */
791 /* Can only directly write to some F0 registers.
795 if (regaddr == SDIOD_CCCR_IOEN) {
796 if (gInstance->func[2]) {
797 sdio_claim_host(gInstance->func[2]);
798 if (*byte & SDIO_FUNC_ENABLE_2) {
799 /* Enable Function 2 */
802 (gInstance->func[2]);
804 sd_err(("bcmsdh_sdmmc: enable F2 failed:%d",
807 /* Disable Function 2 */
810 (gInstance->func[2]);
812 sd_err(("bcmsdh_sdmmc: Disab F2 failed:%d",
815 sdio_release_host(gInstance->func[2]);
818 #if defined(MMC_SDIO_ABORT)
819 /* to allow abort command through F1 */
820 else if (regaddr == SDIOD_CCCR_IOABORT) {
821 sdio_claim_host(gInstance->func[func]);
823 * this sdio_f0_writeb() can be replaced
825 * depending upon MMC driver change.
826 * As of this time, this is temporaray one
828 sdio_writeb(gInstance->func[func], *byte,
830 sdio_release_host(gInstance->func[func]);
832 #endif /* MMC_SDIO_ABORT */
833 else if (regaddr < 0xF0) {
834 sd_err(("bcmsdh_sdmmc: F0 Wr:0x%02x: write "
835 "disallowed\n", regaddr));
837 /* Claim host controller, perform F0 write,
839 sdio_claim_host(gInstance->func[func]);
840 sdio_f0_writeb(gInstance->func[func], *byte,
842 sdio_release_host(gInstance->func[func]);
845 /* Claim host controller, perform Fn write,
847 sdio_claim_host(gInstance->func[func]);
848 sdio_writeb(gInstance->func[func], *byte, regaddr,
850 sdio_release_host(gInstance->func[func]);
852 } else { /* CMD52 Read */
853 /* Claim host controller, perform Fn read, and release */
854 sdio_claim_host(gInstance->func[func]);
858 sdio_f0_readb(gInstance->func[func], regaddr,
862 sdio_readb(gInstance->func[func], regaddr,
866 sdio_release_host(gInstance->func[func]);
870 sd_err(("bcmsdh_sdmmc: Failed to %s byte F%d:@0x%05x=%02x, "
871 "Err: %d\n", rw ? "Write" : "Read", func, regaddr,
874 return ((err_ret == 0) ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
878 sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func,
879 uint addr, u32 *word, uint nbytes)
881 int err_ret = SDIOH_API_RC_FAIL;
884 sd_err(("%s: Only CMD52 allowed to F0.\n", __func__));
885 return SDIOH_API_RC_FAIL;
888 sd_info(("%s: cmd_type=%d, rw=%d, func=%d, addr=0x%05x, nbytes=%d\n",
889 __func__, cmd_type, rw, func, addr, nbytes));
891 DHD_PM_RESUME_WAIT(sdioh_request_word_wait);
892 DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
893 /* Claim host controller */
894 sdio_claim_host(gInstance->func[func]);
896 if (rw) { /* CMD52 Write */
898 sdio_writel(gInstance->func[func], *word, addr,
900 } else if (nbytes == 2) {
901 sdio_writew(gInstance->func[func], (*word & 0xFFFF),
904 sd_err(("%s: Invalid nbytes: %d\n", __func__, nbytes));
906 } else { /* CMD52 Read */
909 sdio_readl(gInstance->func[func], addr, &err_ret);
910 } else if (nbytes == 2) {
912 sdio_readw(gInstance->func[func], addr,
915 sd_err(("%s: Invalid nbytes: %d\n", __func__, nbytes));
919 /* Release host controller */
920 sdio_release_host(gInstance->func[func]);
923 sd_err(("bcmsdh_sdmmc: Failed to %s word, Err: 0x%08x",
924 rw ? "Write" : "Read", err_ret));
927 return ((err_ret == 0) ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
931 sdioh_request_packet(sdioh_info_t *sd, uint fix_inc, uint write, uint func,
932 uint addr, struct sk_buff *pkt)
934 bool fifo = (fix_inc == SDIOH_DATA_FIX);
938 struct sk_buff *pnext;
940 sd_trace(("%s: Enter\n", __func__));
943 DHD_PM_RESUME_WAIT(sdioh_request_packet_wait);
944 DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
946 /* Claim host controller */
947 sdio_claim_host(gInstance->func[func]);
948 for (pnext = pkt; pnext; pnext = pnext->next) {
949 uint pkt_len = pnext->len;
951 pkt_len &= 0xFFFFFFFC;
953 #ifdef CONFIG_MMC_MSM7X00A
954 if ((pkt_len % 64) == 32) {
955 sd_trace(("%s: Rounding up TX packet +=32\n",
959 #endif /* CONFIG_MMC_MSM7X00A */
960 /* Make sure the packet is aligned properly.
961 * If it isn't, then this
962 * is the fault of sdioh_request_buffer() which
963 * is supposed to give
964 * us something we can work with.
966 ASSERT(((u32) (pkt->data) & DMA_ALIGN_MASK) == 0);
968 if ((write) && (!fifo)) {
969 err_ret = sdio_memcpy_toio(gInstance->func[func], addr,
970 ((u8 *) (pnext->data)),
973 err_ret = sdio_memcpy_toio(gInstance->func[func], addr,
974 ((u8 *) (pnext->data)),
977 err_ret = sdio_readsb(gInstance->func[func],
978 ((u8 *) (pnext->data)),
981 err_ret = sdio_memcpy_fromio(gInstance->func[func],
982 ((u8 *) (pnext->data)),
987 sd_err(("%s: %s FAILED %p[%d], addr=0x%05x, pkt_len=%d,"
988 "ERR=0x%08x\n", __func__,
989 (write) ? "TX" : "RX",
990 pnext, SGCount, addr, pkt_len, err_ret));
992 sd_trace(("%s: %s xfr'd %p[%d], addr=0x%05x, len=%d\n",
994 (write) ? "TX" : "RX",
995 pnext, SGCount, addr, pkt_len));
1004 /* Release host controller */
1005 sdio_release_host(gInstance->func[func]);
1007 sd_trace(("%s: Exit\n", __func__));
1008 return ((err_ret == 0) ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
1012 * This function takes a buffer or packet, and fixes everything up
1013 * so that in the end, a DMA-able packet is created.
1015 * A buffer does not have an associated packet pointer,
1016 * and may or may not be aligned.
1017 * A packet may consist of a single packet, or a packet chain.
1018 * If it is a packet chain, then all the packets in the chain
1019 * must be properly aligned.
1021 * If the packet data is not aligned, then there may only be
1022 * one packet, and in this case, it is copied to a new
1027 sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint write,
1028 uint func, uint addr, uint reg_width, uint buflen_u,
1029 u8 *buffer, struct sk_buff *pkt)
1031 SDIOH_API_RC Status;
1032 struct sk_buff *mypkt = NULL;
1034 sd_trace(("%s: Enter\n", __func__));
1036 DHD_PM_RESUME_WAIT(sdioh_request_buffer_wait);
1037 DHD_PM_RESUME_RETURN_ERROR(SDIOH_API_RC_FAIL);
1038 /* Case 1: we don't have a packet. */
1040 sd_data(("%s: Creating new %s Packet, len=%d\n",
1041 __func__, write ? "TX" : "RX", buflen_u));
1042 mypkt = bcm_pkt_buf_get_skb(buflen_u);
1044 sd_err(("%s: bcm_pkt_buf_get_skb failed: len %d\n",
1045 __func__, buflen_u));
1046 return SDIOH_API_RC_FAIL;
1049 /* For a write, copy the buffer data into the packet. */
1051 memcpy(mypkt->data, buffer, buflen_u);
1054 sdioh_request_packet(sd, fix_inc, write, func, addr, mypkt);
1056 /* For a read, copy the packet data back to the buffer. */
1058 memcpy(buffer, mypkt->data, buflen_u);
1060 bcm_pkt_buf_free_skb(mypkt);
1061 } else if (((u32) (pkt->data) & DMA_ALIGN_MASK) != 0) {
1062 /* Case 2: We have a packet, but it is unaligned. */
1064 /* In this case, we cannot have a chain. */
1065 ASSERT(pkt->next == NULL);
1067 sd_data(("%s: Creating aligned %s Packet, len=%d\n",
1068 __func__, write ? "TX" : "RX", pkt->len));
1069 mypkt = bcm_pkt_buf_get_skb(pkt->len);
1071 sd_err(("%s: bcm_pkt_buf_get_skb failed: len %d\n",
1072 __func__, pkt->len));
1073 return SDIOH_API_RC_FAIL;
1076 /* For a write, copy the buffer data into the packet. */
1078 memcpy(mypkt->data, pkt->data, pkt->len);
1081 sdioh_request_packet(sd, fix_inc, write, func, addr, mypkt);
1083 /* For a read, copy the packet data back to the buffer. */
1085 memcpy(pkt->data, mypkt->data, mypkt->len);
1087 bcm_pkt_buf_free_skb(mypkt);
1088 } else { /* case 3: We have a packet and
1090 sd_data(("%s: Aligned %s Packet, direct DMA\n",
1091 __func__, write ? "Tx" : "Rx"));
1093 sdioh_request_packet(sd, fix_inc, write, func, addr, pkt);
1099 /* this function performs "abort" for both of host & device */
1100 extern int sdioh_abort(sdioh_info_t *sd, uint func)
1102 #if defined(MMC_SDIO_ABORT)
1103 char t_func = (char)func;
1104 #endif /* defined(MMC_SDIO_ABORT) */
1105 sd_trace(("%s: Enter\n", __func__));
1107 #if defined(MMC_SDIO_ABORT)
1108 /* issue abort cmd52 command through F1 */
1109 sdioh_request_byte(sd, SD_IO_OP_WRITE, SDIO_FUNC_0, SDIOD_CCCR_IOABORT,
1111 #endif /* defined(MMC_SDIO_ABORT) */
1113 sd_trace(("%s: Exit\n", __func__));
1114 return SDIOH_API_RC_SUCCESS;
1117 /* Reset and re-initialize the device */
1118 int sdioh_sdio_reset(sdioh_info_t *si)
1120 sd_trace(("%s: Enter\n", __func__));
1121 sd_trace(("%s: Exit\n", __func__));
1122 return SDIOH_API_RC_SUCCESS;
1125 /* Disable device interrupt */
1126 void sdioh_sdmmc_devintr_off(sdioh_info_t *sd)
1128 sd_trace(("%s: %d\n", __func__, sd->use_client_ints));
1129 sd->intmask &= ~CLIENT_INTR;
1132 /* Enable device interrupt */
1133 void sdioh_sdmmc_devintr_on(sdioh_info_t *sd)
1135 sd_trace(("%s: %d\n", __func__, sd->use_client_ints));
1136 sd->intmask |= CLIENT_INTR;
1139 /* Read client card reg */
1141 sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, u32 regaddr,
1142 int regsize, u32 *data)
1145 if ((func == 0) || (regsize == 1)) {
1148 sdioh_request_byte(sd, SDIOH_READ, func, regaddr, &temp);
1151 sd_data(("%s: byte read data=0x%02x\n", __func__, *data));
1153 sdioh_request_word(sd, 0, SDIOH_READ, func, regaddr, data,
1158 sd_data(("%s: word read data=0x%08x\n", __func__, *data));
1164 #if !defined(OOB_INTR_ONLY)
1165 /* bcmsdh_sdmmc interrupt handler */
1166 static void IRQHandler(struct sdio_func *func)
1170 sd_trace(("bcmsdh_sdmmc: ***IRQHandler\n"));
1174 sdio_release_host(gInstance->func[0]);
1176 if (sd->use_client_ints) {
1178 ASSERT(sd->intr_handler);
1179 ASSERT(sd->intr_handler_arg);
1180 (sd->intr_handler) (sd->intr_handler_arg);
1182 sd_err(("bcmsdh_sdmmc: ***IRQHandler\n"));
1184 sd_err(("%s: Not ready for intr: enabled %d, handler %p\n",
1185 __func__, sd->client_intr_enabled, sd->intr_handler));
1188 sdio_claim_host(gInstance->func[0]);
1191 /* bcmsdh_sdmmc interrupt handler for F2 (dummy handler) */
1192 static void IRQHandlerF2(struct sdio_func *func)
1196 sd_trace(("bcmsdh_sdmmc: ***IRQHandlerF2\n"));
1202 #endif /* !defined(OOB_INTR_ONLY) */
1205 /* Write client card reg */
1207 sdioh_sdmmc_card_regwrite(sdioh_info_t *sd, int func, u32 regaddr,
1208 int regsize, u32 data)
1211 if ((func == 0) || (regsize == 1)) {
1215 sdioh_request_byte(sd, SDIOH_READ, func, regaddr, &temp);
1216 sd_data(("%s: byte write data=0x%02x\n", __func__, data));
1221 sdioh_request_word(sd, 0, SDIOH_READ, func, regaddr, &data,
1224 sd_data(("%s: word write data=0x%08x\n", __func__, data));
1229 #endif /* NOTUSED */
1231 int sdioh_start(sdioh_info_t *si, int stage)
1236 int sdioh_stop(sdioh_info_t *si)