1 // ------------------------------------------------------------------
2 // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
5 // Permission to use, copy, modify, and/or distribute this software for any
6 // purpose with or without fee is hereby granted, provided that the above
7 // copyright notice and this permission notice appear in all copies.
9 // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 // ------------------------------------------------------------------
19 //===================================================================
20 // Author(s): ="Atheros"
21 //===================================================================
24 #ifndef _UMBOX_WLAN_REG_REG_H_
25 #define _UMBOX_WLAN_REG_REG_H_
27 #define UMBOX_FIFO_ADDRESS 0x00000000
28 #define UMBOX_FIFO_OFFSET 0x00000000
29 #define UMBOX_FIFO_DATA_MSB 8
30 #define UMBOX_FIFO_DATA_LSB 0
31 #define UMBOX_FIFO_DATA_MASK 0x000001ff
32 #define UMBOX_FIFO_DATA_GET(x) (((x) & UMBOX_FIFO_DATA_MASK) >> UMBOX_FIFO_DATA_LSB)
33 #define UMBOX_FIFO_DATA_SET(x) (((x) << UMBOX_FIFO_DATA_LSB) & UMBOX_FIFO_DATA_MASK)
35 #define UMBOX_FIFO_STATUS_ADDRESS 0x00000008
36 #define UMBOX_FIFO_STATUS_OFFSET 0x00000008
37 #define UMBOX_FIFO_STATUS_TX_EMPTY_MSB 3
38 #define UMBOX_FIFO_STATUS_TX_EMPTY_LSB 3
39 #define UMBOX_FIFO_STATUS_TX_EMPTY_MASK 0x00000008
40 #define UMBOX_FIFO_STATUS_TX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_TX_EMPTY_LSB)
41 #define UMBOX_FIFO_STATUS_TX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_EMPTY_LSB) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK)
42 #define UMBOX_FIFO_STATUS_TX_FULL_MSB 2
43 #define UMBOX_FIFO_STATUS_TX_FULL_LSB 2
44 #define UMBOX_FIFO_STATUS_TX_FULL_MASK 0x00000004
45 #define UMBOX_FIFO_STATUS_TX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_FULL_MASK) >> UMBOX_FIFO_STATUS_TX_FULL_LSB)
46 #define UMBOX_FIFO_STATUS_TX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_FULL_LSB) & UMBOX_FIFO_STATUS_TX_FULL_MASK)
47 #define UMBOX_FIFO_STATUS_RX_EMPTY_MSB 1
48 #define UMBOX_FIFO_STATUS_RX_EMPTY_LSB 1
49 #define UMBOX_FIFO_STATUS_RX_EMPTY_MASK 0x00000002
50 #define UMBOX_FIFO_STATUS_RX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_RX_EMPTY_LSB)
51 #define UMBOX_FIFO_STATUS_RX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_EMPTY_LSB) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK)
52 #define UMBOX_FIFO_STATUS_RX_FULL_MSB 0
53 #define UMBOX_FIFO_STATUS_RX_FULL_LSB 0
54 #define UMBOX_FIFO_STATUS_RX_FULL_MASK 0x00000001
55 #define UMBOX_FIFO_STATUS_RX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_FULL_MASK) >> UMBOX_FIFO_STATUS_RX_FULL_LSB)
56 #define UMBOX_FIFO_STATUS_RX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_FULL_LSB) & UMBOX_FIFO_STATUS_RX_FULL_MASK)
58 #define UMBOX_DMA_POLICY_ADDRESS 0x0000000c
59 #define UMBOX_DMA_POLICY_OFFSET 0x0000000c
60 #define UMBOX_DMA_POLICY_TX_QUANTUM_MSB 3
61 #define UMBOX_DMA_POLICY_TX_QUANTUM_LSB 3
62 #define UMBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008
63 #define UMBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_TX_QUANTUM_LSB)
64 #define UMBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_TX_QUANTUM_LSB) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK)
65 #define UMBOX_DMA_POLICY_TX_ORDER_MSB 2
66 #define UMBOX_DMA_POLICY_TX_ORDER_LSB 2
67 #define UMBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004
68 #define UMBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_TX_ORDER_MASK) >> UMBOX_DMA_POLICY_TX_ORDER_LSB)
69 #define UMBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_TX_ORDER_LSB) & UMBOX_DMA_POLICY_TX_ORDER_MASK)
70 #define UMBOX_DMA_POLICY_RX_QUANTUM_MSB 1
71 #define UMBOX_DMA_POLICY_RX_QUANTUM_LSB 1
72 #define UMBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002
73 #define UMBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_RX_QUANTUM_LSB)
74 #define UMBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_RX_QUANTUM_LSB) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK)
75 #define UMBOX_DMA_POLICY_RX_ORDER_MSB 0
76 #define UMBOX_DMA_POLICY_RX_ORDER_LSB 0
77 #define UMBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001
78 #define UMBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_RX_ORDER_MASK) >> UMBOX_DMA_POLICY_RX_ORDER_LSB)
79 #define UMBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_RX_ORDER_LSB) & UMBOX_DMA_POLICY_RX_ORDER_MASK)
81 #define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000010
82 #define UMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000010
83 #define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
84 #define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
85 #define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
86 #define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
87 #define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
89 #define UMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000014
90 #define UMBOX0_DMA_RX_CONTROL_OFFSET 0x00000014
91 #define UMBOX0_DMA_RX_CONTROL_RESUME_MSB 2
92 #define UMBOX0_DMA_RX_CONTROL_RESUME_LSB 2
93 #define UMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
94 #define UMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_RX_CONTROL_RESUME_LSB)
95 #define UMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_RESUME_LSB) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK)
96 #define UMBOX0_DMA_RX_CONTROL_START_MSB 1
97 #define UMBOX0_DMA_RX_CONTROL_START_LSB 1
98 #define UMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
99 #define UMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_START_MASK) >> UMBOX0_DMA_RX_CONTROL_START_LSB)
100 #define UMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_START_LSB) & UMBOX0_DMA_RX_CONTROL_START_MASK)
101 #define UMBOX0_DMA_RX_CONTROL_STOP_MSB 0
102 #define UMBOX0_DMA_RX_CONTROL_STOP_LSB 0
103 #define UMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
104 #define UMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_STOP_MASK) >> UMBOX0_DMA_RX_CONTROL_STOP_LSB)
105 #define UMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_STOP_LSB) & UMBOX0_DMA_RX_CONTROL_STOP_MASK)
107 #define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000018
108 #define UMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000018
109 #define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
110 #define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
111 #define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
112 #define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
113 #define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
115 #define UMBOX0_DMA_TX_CONTROL_ADDRESS 0x0000001c
116 #define UMBOX0_DMA_TX_CONTROL_OFFSET 0x0000001c
117 #define UMBOX0_DMA_TX_CONTROL_RESUME_MSB 2
118 #define UMBOX0_DMA_TX_CONTROL_RESUME_LSB 2
119 #define UMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
120 #define UMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_TX_CONTROL_RESUME_LSB)
121 #define UMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_RESUME_LSB) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK)
122 #define UMBOX0_DMA_TX_CONTROL_START_MSB 1
123 #define UMBOX0_DMA_TX_CONTROL_START_LSB 1
124 #define UMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
125 #define UMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_START_MASK) >> UMBOX0_DMA_TX_CONTROL_START_LSB)
126 #define UMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_START_LSB) & UMBOX0_DMA_TX_CONTROL_START_MASK)
127 #define UMBOX0_DMA_TX_CONTROL_STOP_MSB 0
128 #define UMBOX0_DMA_TX_CONTROL_STOP_LSB 0
129 #define UMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
130 #define UMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_STOP_MASK) >> UMBOX0_DMA_TX_CONTROL_STOP_LSB)
131 #define UMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_STOP_LSB) & UMBOX0_DMA_TX_CONTROL_STOP_MASK)
133 #define UMBOX_FIFO_TIMEOUT_ADDRESS 0x00000020
134 #define UMBOX_FIFO_TIMEOUT_OFFSET 0x00000020
135 #define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MSB 8
136 #define UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB 8
137 #define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000100
138 #define UMBOX_FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK) >> UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB)
139 #define UMBOX_FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK)
140 #define UMBOX_FIFO_TIMEOUT_VALUE_MSB 7
141 #define UMBOX_FIFO_TIMEOUT_VALUE_LSB 0
142 #define UMBOX_FIFO_TIMEOUT_VALUE_MASK 0x000000ff
143 #define UMBOX_FIFO_TIMEOUT_VALUE_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_VALUE_MASK) >> UMBOX_FIFO_TIMEOUT_VALUE_LSB)
144 #define UMBOX_FIFO_TIMEOUT_VALUE_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_VALUE_LSB) & UMBOX_FIFO_TIMEOUT_VALUE_MASK)
146 #define UMBOX_INT_STATUS_ADDRESS 0x00000024
147 #define UMBOX_INT_STATUS_OFFSET 0x00000024
148 #define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MSB 9
149 #define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB 9
150 #define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK 0x00000200
151 #define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB)
152 #define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK)
153 #define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MSB 8
154 #define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB 8
155 #define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK 0x00000100
156 #define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB)
157 #define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK)
158 #define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 7
159 #define UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 7
160 #define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000080
161 #define UMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
162 #define UMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
163 #define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 6
164 #define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 6
165 #define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000040
166 #define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
167 #define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
168 #define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 5
169 #define UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 5
170 #define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000020
171 #define UMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
172 #define UMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
173 #define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MSB 4
174 #define UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB 4
175 #define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK 0x00000010
176 #define UMBOX_INT_STATUS_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB)
177 #define UMBOX_INT_STATUS_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK)
178 #define UMBOX_INT_STATUS_TX_OVERFLOW_MSB 3
179 #define UMBOX_INT_STATUS_TX_OVERFLOW_LSB 3
180 #define UMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000008
181 #define UMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> UMBOX_INT_STATUS_TX_OVERFLOW_LSB)
182 #define UMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_TX_OVERFLOW_LSB) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK)
183 #define UMBOX_INT_STATUS_RX_UNDERFLOW_MSB 2
184 #define UMBOX_INT_STATUS_RX_UNDERFLOW_LSB 2
185 #define UMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000004
186 #define UMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_RX_UNDERFLOW_LSB)
187 #define UMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK)
188 #define UMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1
189 #define UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1
190 #define UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002
191 #define UMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
192 #define UMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
193 #define UMBOX_INT_STATUS_RX_NOT_FULL_MSB 0
194 #define UMBOX_INT_STATUS_RX_NOT_FULL_LSB 0
195 #define UMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001
196 #define UMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> UMBOX_INT_STATUS_RX_NOT_FULL_LSB)
197 #define UMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_STATUS_RX_NOT_FULL_LSB) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK)
199 #define UMBOX_INT_ENABLE_ADDRESS 0x00000028
200 #define UMBOX_INT_ENABLE_OFFSET 0x00000028
201 #define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MSB 9
202 #define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB 9
203 #define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK 0x00000200
204 #define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB)
205 #define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK)
206 #define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MSB 8
207 #define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB 8
208 #define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK 0x00000100
209 #define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB)
210 #define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK)
211 #define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 7
212 #define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 7
213 #define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000080
214 #define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
215 #define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
216 #define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 6
217 #define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 6
218 #define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000040
219 #define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
220 #define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
221 #define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 5
222 #define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 5
223 #define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000020
224 #define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
225 #define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
226 #define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MSB 4
227 #define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB 4
228 #define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK 0x00000010
229 #define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB)
230 #define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK)
231 #define UMBOX_INT_ENABLE_TX_OVERFLOW_MSB 3
232 #define UMBOX_INT_ENABLE_TX_OVERFLOW_LSB 3
233 #define UMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000008
234 #define UMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_TX_OVERFLOW_LSB)
235 #define UMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK)
236 #define UMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 2
237 #define UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 2
238 #define UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000004
239 #define UMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
240 #define UMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
241 #define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1
242 #define UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1
243 #define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002
244 #define UMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
245 #define UMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
246 #define UMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0
247 #define UMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0
248 #define UMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001
249 #define UMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> UMBOX_INT_ENABLE_RX_NOT_FULL_LSB)
250 #define UMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK)
252 #define UMBOX_DEBUG_ADDRESS 0x0000002c
253 #define UMBOX_DEBUG_OFFSET 0x0000002c
254 #define UMBOX_DEBUG_SEL_MSB 2
255 #define UMBOX_DEBUG_SEL_LSB 0
256 #define UMBOX_DEBUG_SEL_MASK 0x00000007
257 #define UMBOX_DEBUG_SEL_GET(x) (((x) & UMBOX_DEBUG_SEL_MASK) >> UMBOX_DEBUG_SEL_LSB)
258 #define UMBOX_DEBUG_SEL_SET(x) (((x) << UMBOX_DEBUG_SEL_LSB) & UMBOX_DEBUG_SEL_MASK)
260 #define UMBOX_FIFO_RESET_ADDRESS 0x00000030
261 #define UMBOX_FIFO_RESET_OFFSET 0x00000030
262 #define UMBOX_FIFO_RESET_INIT_MSB 0
263 #define UMBOX_FIFO_RESET_INIT_LSB 0
264 #define UMBOX_FIFO_RESET_INIT_MASK 0x00000001
265 #define UMBOX_FIFO_RESET_INIT_GET(x) (((x) & UMBOX_FIFO_RESET_INIT_MASK) >> UMBOX_FIFO_RESET_INIT_LSB)
266 #define UMBOX_FIFO_RESET_INIT_SET(x) (((x) << UMBOX_FIFO_RESET_INIT_LSB) & UMBOX_FIFO_RESET_INIT_MASK)
268 #define UMBOX_HCI_FRAMER_ADDRESS 0x00000034
269 #define UMBOX_HCI_FRAMER_OFFSET 0x00000034
270 #define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MSB 6
271 #define UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB 6
272 #define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK 0x00000040
273 #define UMBOX_HCI_FRAMER_CRC_OVERRIDE_GET(x) (((x) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK) >> UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB)
274 #define UMBOX_HCI_FRAMER_CRC_OVERRIDE_SET(x) (((x) << UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK)
275 #define UMBOX_HCI_FRAMER_ENABLE_MSB 5
276 #define UMBOX_HCI_FRAMER_ENABLE_LSB 5
277 #define UMBOX_HCI_FRAMER_ENABLE_MASK 0x00000020
278 #define UMBOX_HCI_FRAMER_ENABLE_GET(x) (((x) & UMBOX_HCI_FRAMER_ENABLE_MASK) >> UMBOX_HCI_FRAMER_ENABLE_LSB)
279 #define UMBOX_HCI_FRAMER_ENABLE_SET(x) (((x) << UMBOX_HCI_FRAMER_ENABLE_LSB) & UMBOX_HCI_FRAMER_ENABLE_MASK)
280 #define UMBOX_HCI_FRAMER_SYNC_ERROR_MSB 4
281 #define UMBOX_HCI_FRAMER_SYNC_ERROR_LSB 4
282 #define UMBOX_HCI_FRAMER_SYNC_ERROR_MASK 0x00000010
283 #define UMBOX_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK) >> UMBOX_HCI_FRAMER_SYNC_ERROR_LSB)
284 #define UMBOX_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << UMBOX_HCI_FRAMER_SYNC_ERROR_LSB) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK)
285 #define UMBOX_HCI_FRAMER_UNDERFLOW_MSB 3
286 #define UMBOX_HCI_FRAMER_UNDERFLOW_LSB 3
287 #define UMBOX_HCI_FRAMER_UNDERFLOW_MASK 0x00000008
288 #define UMBOX_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_HCI_FRAMER_UNDERFLOW_LSB)
289 #define UMBOX_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK)
290 #define UMBOX_HCI_FRAMER_OVERFLOW_MSB 2
291 #define UMBOX_HCI_FRAMER_OVERFLOW_LSB 2
292 #define UMBOX_HCI_FRAMER_OVERFLOW_MASK 0x00000004
293 #define UMBOX_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_HCI_FRAMER_OVERFLOW_LSB)
294 #define UMBOX_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_HCI_FRAMER_OVERFLOW_MASK)
295 #define UMBOX_HCI_FRAMER_CONFIG_MODE_MSB 1
296 #define UMBOX_HCI_FRAMER_CONFIG_MODE_LSB 0
297 #define UMBOX_HCI_FRAMER_CONFIG_MODE_MASK 0x00000003
298 #define UMBOX_HCI_FRAMER_CONFIG_MODE_GET(x) (((x) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK) >> UMBOX_HCI_FRAMER_CONFIG_MODE_LSB)
299 #define UMBOX_HCI_FRAMER_CONFIG_MODE_SET(x) (((x) << UMBOX_HCI_FRAMER_CONFIG_MODE_LSB) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK)
302 #ifndef __ASSEMBLER__
304 typedef struct umbox_wlan_reg_reg_s {
305 volatile unsigned int umbox_fifo[2];
306 volatile unsigned int umbox_fifo_status;
307 volatile unsigned int umbox_dma_policy;
308 volatile unsigned int umbox0_dma_rx_descriptor_base;
309 volatile unsigned int umbox0_dma_rx_control;
310 volatile unsigned int umbox0_dma_tx_descriptor_base;
311 volatile unsigned int umbox0_dma_tx_control;
312 volatile unsigned int umbox_fifo_timeout;
313 volatile unsigned int umbox_int_status;
314 volatile unsigned int umbox_int_enable;
315 volatile unsigned int umbox_debug;
316 volatile unsigned int umbox_fifo_reset;
317 volatile unsigned int umbox_hci_framer;
318 } umbox_wlan_reg_reg_t;
320 #endif /* __ASSEMBLER__ */
322 #endif /* _UMBOX_WLAN_REG_H_ */
git.openpandora.org / pandora-kernel.git / blob