1 // ------------------------------------------------------------------
2 // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
5 // Permission to use, copy, modify, and/or distribute this software for any
6 // purpose with or without fee is hereby granted, provided that the above
7 // copyright notice and this permission notice appear in all copies.
9 // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 // ------------------------------------------------------------------
19 //===================================================================
20 // Author(s): ="Atheros"
21 //===================================================================
23 /* Copyright (C) 2009 Denali Software Inc. All rights reserved */
24 /* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */
27 #ifndef _BB_LC_REG_REG_H_
28 #define _BB_LC_REG_REG_H_
31 /* macros for BB_test_controls */
32 #define PHY_BB_TEST_CONTROLS_ADDRESS 0x00009800
33 #define PHY_BB_TEST_CONTROLS_OFFSET 0x00009800
34 #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MSB 3
35 #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_LSB 0
36 #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MASK 0x0000000f
37 #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_GET(x) (((x) & 0x0000000f) >> 0)
38 #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_SET(x) (((x) << 0) & 0x0000000f)
39 #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MSB 4
40 #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_LSB 4
41 #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MASK 0x00000010
42 #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_GET(x) (((x) & 0x00000010) >> 4)
43 #define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SET(x) (((x) << 4) & 0x00000010)
44 #define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MSB 6
45 #define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_LSB 5
46 #define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MASK 0x00000060
47 #define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_GET(x) (((x) & 0x00000060) >> 5)
48 #define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_SET(x) (((x) << 5) & 0x00000060)
49 #define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MSB 9
50 #define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_LSB 8
51 #define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MASK 0x00000300
52 #define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_GET(x) (((x) & 0x00000300) >> 8)
53 #define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_SET(x) (((x) << 8) & 0x00000300)
54 #define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MSB 10
55 #define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_LSB 10
56 #define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MASK 0x00000400
57 #define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_GET(x) (((x) & 0x00000400) >> 10)
58 #define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_SET(x) (((x) << 10) & 0x00000400)
59 #define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MSB 13
60 #define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_LSB 13
61 #define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MASK 0x00002000
62 #define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_GET(x) (((x) & 0x00002000) >> 13)
63 #define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_SET(x) (((x) << 13) & 0x00002000)
64 #define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MSB 15
65 #define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_LSB 15
66 #define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MASK 0x00008000
67 #define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_GET(x) (((x) & 0x00008000) >> 15)
68 #define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_SET(x) (((x) << 15) & 0x00008000)
69 #define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MSB 17
70 #define PHY_BB_TEST_CONTROLS_SLOW_CLK160_LSB 17
71 #define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MASK 0x00020000
72 #define PHY_BB_TEST_CONTROLS_SLOW_CLK160_GET(x) (((x) & 0x00020000) >> 17)
73 #define PHY_BB_TEST_CONTROLS_SLOW_CLK160_SET(x) (((x) << 17) & 0x00020000)
74 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MSB 18
75 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_LSB 18
76 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MASK 0x00040000
77 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_GET(x) (((x) & 0x00040000) >> 18)
78 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_SET(x) (((x) << 18) & 0x00040000)
79 #define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MSB 22
80 #define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_LSB 19
81 #define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MASK 0x00780000
82 #define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_GET(x) (((x) & 0x00780000) >> 19)
83 #define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_SET(x) (((x) << 19) & 0x00780000)
84 #define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MSB 23
85 #define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_LSB 23
86 #define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MASK 0x00800000
87 #define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_GET(x) (((x) & 0x00800000) >> 23)
88 #define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_SET(x) (((x) << 23) & 0x00800000)
89 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MSB 24
90 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_LSB 24
91 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MASK 0x01000000
92 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_GET(x) (((x) & 0x01000000) >> 24)
93 #define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_SET(x) (((x) << 24) & 0x01000000)
94 #define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MSB 28
95 #define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_LSB 28
96 #define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MASK 0x10000000
97 #define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_GET(x) (((x) & 0x10000000) >> 28)
98 #define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_SET(x) (((x) << 28) & 0x10000000)
99 #define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MSB 31
100 #define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_LSB 30
101 #define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MASK 0xc0000000
102 #define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_GET(x) (((x) & 0xc0000000) >> 30)
103 #define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_SET(x) (((x) << 30) & 0xc0000000)
105 /* macros for BB_gen_controls */
106 #define PHY_BB_GEN_CONTROLS_ADDRESS 0x00009804
107 #define PHY_BB_GEN_CONTROLS_OFFSET 0x00009804
108 #define PHY_BB_GEN_CONTROLS_TURBO_MSB 0
109 #define PHY_BB_GEN_CONTROLS_TURBO_LSB 0
110 #define PHY_BB_GEN_CONTROLS_TURBO_MASK 0x00000001
111 #define PHY_BB_GEN_CONTROLS_TURBO_GET(x) (((x) & 0x00000001) >> 0)
112 #define PHY_BB_GEN_CONTROLS_TURBO_SET(x) (((x) << 0) & 0x00000001)
113 #define PHY_BB_GEN_CONTROLS_CF_SHORT20_MSB 1
114 #define PHY_BB_GEN_CONTROLS_CF_SHORT20_LSB 1
115 #define PHY_BB_GEN_CONTROLS_CF_SHORT20_MASK 0x00000002
116 #define PHY_BB_GEN_CONTROLS_CF_SHORT20_GET(x) (((x) & 0x00000002) >> 1)
117 #define PHY_BB_GEN_CONTROLS_CF_SHORT20_SET(x) (((x) << 1) & 0x00000002)
118 #define PHY_BB_GEN_CONTROLS_DYN_20_40_MSB 2
119 #define PHY_BB_GEN_CONTROLS_DYN_20_40_LSB 2
120 #define PHY_BB_GEN_CONTROLS_DYN_20_40_MASK 0x00000004
121 #define PHY_BB_GEN_CONTROLS_DYN_20_40_GET(x) (((x) & 0x00000004) >> 2)
122 #define PHY_BB_GEN_CONTROLS_DYN_20_40_SET(x) (((x) << 2) & 0x00000004)
123 #define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_MSB 3
124 #define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_LSB 3
125 #define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_MASK 0x00000008
126 #define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_GET(x) (((x) & 0x00000008) >> 3)
127 #define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_SET(x) (((x) << 3) & 0x00000008)
128 #define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_MSB 4
129 #define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_LSB 4
130 #define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_MASK 0x00000010
131 #define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_GET(x) (((x) & 0x00000010) >> 4)
132 #define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_SET(x) (((x) << 4) & 0x00000010)
133 #define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_MSB 5
134 #define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_LSB 5
135 #define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_MASK 0x00000020
136 #define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_GET(x) (((x) & 0x00000020) >> 5)
137 #define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_SET(x) (((x) << 5) & 0x00000020)
138 #define PHY_BB_GEN_CONTROLS_HT_ENABLE_MSB 6
139 #define PHY_BB_GEN_CONTROLS_HT_ENABLE_LSB 6
140 #define PHY_BB_GEN_CONTROLS_HT_ENABLE_MASK 0x00000040
141 #define PHY_BB_GEN_CONTROLS_HT_ENABLE_GET(x) (((x) & 0x00000040) >> 6)
142 #define PHY_BB_GEN_CONTROLS_HT_ENABLE_SET(x) (((x) << 6) & 0x00000040)
143 #define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MSB 7
144 #define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_LSB 7
145 #define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MASK 0x00000080
146 #define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_GET(x) (((x) & 0x00000080) >> 7)
147 #define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_SET(x) (((x) << 7) & 0x00000080)
148 #define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_MSB 8
149 #define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_LSB 8
150 #define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_MASK 0x00000100
151 #define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_GET(x) (((x) & 0x00000100) >> 8)
152 #define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_SET(x) (((x) << 8) & 0x00000100)
153 #define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_MSB 9
154 #define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_LSB 9
155 #define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_MASK 0x00000200
156 #define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_GET(x) (((x) & 0x00000200) >> 9)
157 #define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_SET(x) (((x) << 9) & 0x00000200)
158 #define PHY_BB_GEN_CONTROLS_GF_ENABLE_MSB 10
159 #define PHY_BB_GEN_CONTROLS_GF_ENABLE_LSB 10
160 #define PHY_BB_GEN_CONTROLS_GF_ENABLE_MASK 0x00000400
161 #define PHY_BB_GEN_CONTROLS_GF_ENABLE_GET(x) (((x) & 0x00000400) >> 10)
162 #define PHY_BB_GEN_CONTROLS_GF_ENABLE_SET(x) (((x) << 10) & 0x00000400)
163 #define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_MSB 11
164 #define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_LSB 11
165 #define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_MASK 0x00000800
166 #define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_GET(x) (((x) & 0x00000800) >> 11)
167 #define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_SET(x) (((x) << 11) & 0x00000800)
169 /* macros for BB_test_controls_status */
170 #define PHY_BB_TEST_CONTROLS_STATUS_ADDRESS 0x00009808
171 #define PHY_BB_TEST_CONTROLS_STATUS_OFFSET 0x00009808
172 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MSB 0
173 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_LSB 0
174 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MASK 0x00000001
175 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_GET(x) (((x) & 0x00000001) >> 0)
176 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_SET(x) (((x) << 0) & 0x00000001)
177 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MSB 1
178 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_LSB 1
179 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MASK 0x00000002
180 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_GET(x) (((x) & 0x00000002) >> 1)
181 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_SET(x) (((x) << 1) & 0x00000002)
182 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MSB 4
183 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_LSB 2
184 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MASK 0x0000001c
185 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_GET(x) (((x) & 0x0000001c) >> 2)
186 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_SET(x) (((x) << 2) & 0x0000001c)
187 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MSB 6
188 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_LSB 5
189 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MASK 0x00000060
190 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_GET(x) (((x) & 0x00000060) >> 5)
191 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_SET(x) (((x) << 5) & 0x00000060)
192 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MSB 7
193 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_LSB 7
194 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MASK 0x00000080
195 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_GET(x) (((x) & 0x00000080) >> 7)
196 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_SET(x) (((x) << 7) & 0x00000080)
197 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MSB 8
198 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_LSB 8
199 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MASK 0x00000100
200 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_GET(x) (((x) & 0x00000100) >> 8)
201 #define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_SET(x) (((x) << 8) & 0x00000100)
202 #define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MSB 9
203 #define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_LSB 9
204 #define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MASK 0x00000200
205 #define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_GET(x) (((x) & 0x00000200) >> 9)
206 #define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_SET(x) (((x) << 9) & 0x00000200)
207 #define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MSB 13
208 #define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_LSB 10
209 #define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MASK 0x00003c00
210 #define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_GET(x) (((x) & 0x00003c00) >> 10)
211 #define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_SET(x) (((x) << 10) & 0x00003c00)
212 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MSB 14
213 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_LSB 14
214 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MASK 0x00004000
215 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_GET(x) (((x) & 0x00004000) >> 14)
216 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_SET(x) (((x) << 14) & 0x00004000)
217 #define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MSB 15
218 #define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_LSB 15
219 #define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MASK 0x00008000
220 #define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_GET(x) (((x) & 0x00008000) >> 15)
221 #define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_SET(x) (((x) << 15) & 0x00008000)
222 #define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MSB 18
223 #define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_LSB 16
224 #define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MASK 0x00070000
225 #define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_GET(x) (((x) & 0x00070000) >> 16)
226 #define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_SET(x) (((x) << 16) & 0x00070000)
227 #define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MSB 19
228 #define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_LSB 19
229 #define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MASK 0x00080000
230 #define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_GET(x) (((x) & 0x00080000) >> 19)
231 #define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_SET(x) (((x) << 19) & 0x00080000)
232 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MSB 23
233 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_LSB 23
234 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MASK 0x00800000
235 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_GET(x) (((x) & 0x00800000) >> 23)
236 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_SET(x) (((x) << 23) & 0x00800000)
237 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MSB 27
238 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_LSB 27
239 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MASK 0x08000000
240 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_GET(x) (((x) & 0x08000000) >> 27)
241 #define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_SET(x) (((x) << 27) & 0x08000000)
242 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MSB 28
243 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_LSB 28
244 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MASK 0x10000000
245 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_GET(x) (((x) & 0x10000000) >> 28)
246 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_SET(x) (((x) << 28) & 0x10000000)
247 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MSB 30
248 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_LSB 29
249 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MASK 0x60000000
250 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_GET(x) (((x) & 0x60000000) >> 29)
251 #define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_SET(x) (((x) << 29) & 0x60000000)
253 /* macros for BB_timing_controls_1 */
254 #define PHY_BB_TIMING_CONTROLS_1_ADDRESS 0x0000980c
255 #define PHY_BB_TIMING_CONTROLS_1_OFFSET 0x0000980c
256 #define PHY_BB_TIMING_CONTROLS_1_STE_THR_MSB 6
257 #define PHY_BB_TIMING_CONTROLS_1_STE_THR_LSB 0
258 #define PHY_BB_TIMING_CONTROLS_1_STE_THR_MASK 0x0000007f
259 #define PHY_BB_TIMING_CONTROLS_1_STE_THR_GET(x) (((x) & 0x0000007f) >> 0)
260 #define PHY_BB_TIMING_CONTROLS_1_STE_THR_SET(x) (((x) << 0) & 0x0000007f)
261 #define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MSB 12
262 #define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_LSB 7
263 #define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MASK 0x00001f80
264 #define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_GET(x) (((x) & 0x00001f80) >> 7)
265 #define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_SET(x) (((x) << 7) & 0x00001f80)
266 #define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_MSB 16
267 #define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_LSB 13
268 #define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_MASK 0x0001e000
269 #define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_GET(x) (((x) & 0x0001e000) >> 13)
270 #define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_SET(x) (((x) << 13) & 0x0001e000)
271 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_MSB 17
272 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_LSB 17
273 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_MASK 0x00020000
274 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_GET(x) (((x) & 0x00020000) >> 17)
275 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_SET(x) (((x) << 17) & 0x00020000)
276 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MSB 19
277 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_LSB 18
278 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MASK 0x000c0000
279 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_GET(x) (((x) & 0x000c0000) >> 18)
280 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_SET(x) (((x) << 18) & 0x000c0000)
281 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MSB 21
282 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_LSB 20
283 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MASK 0x00300000
284 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_GET(x) (((x) & 0x00300000) >> 20)
285 #define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_SET(x) (((x) << 20) & 0x00300000)
286 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MSB 22
287 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_LSB 22
288 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MASK 0x00400000
289 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_GET(x) (((x) & 0x00400000) >> 22)
290 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_SET(x) (((x) << 22) & 0x00400000)
291 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MSB 23
292 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_LSB 23
293 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MASK 0x00800000
294 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_GET(x) (((x) & 0x00800000) >> 23)
295 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_SET(x) (((x) << 23) & 0x00800000)
296 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MSB 24
297 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_LSB 24
298 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MASK 0x01000000
299 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_GET(x) (((x) & 0x01000000) >> 24)
300 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_SET(x) (((x) << 24) & 0x01000000)
301 #define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MSB 26
302 #define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_LSB 25
303 #define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MASK 0x06000000
304 #define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_GET(x) (((x) & 0x06000000) >> 25)
305 #define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_SET(x) (((x) << 25) & 0x06000000)
306 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MSB 27
307 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_LSB 27
308 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MASK 0x08000000
309 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_GET(x) (((x) & 0x08000000) >> 27)
310 #define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_SET(x) (((x) << 27) & 0x08000000)
311 #define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MSB 28
312 #define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_LSB 28
313 #define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MASK 0x10000000
314 #define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_GET(x) (((x) & 0x10000000) >> 28)
315 #define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_SET(x) (((x) << 28) & 0x10000000)
316 #define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MSB 30
317 #define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_LSB 29
318 #define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MASK 0x60000000
319 #define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_GET(x) (((x) & 0x60000000) >> 29)
320 #define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_SET(x) (((x) << 29) & 0x60000000)
321 #define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MSB 31
322 #define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_LSB 31
323 #define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MASK 0x80000000
324 #define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_GET(x) (((x) & 0x80000000) >> 31)
325 #define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_SET(x) (((x) << 31) & 0x80000000)
327 /* macros for BB_timing_controls_2 */
328 #define PHY_BB_TIMING_CONTROLS_2_ADDRESS 0x00009810
329 #define PHY_BB_TIMING_CONTROLS_2_OFFSET 0x00009810
330 #define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MSB 11
331 #define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_LSB 0
332 #define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MASK 0x00000fff
333 #define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_GET(x) (((x) & 0x00000fff) >> 0)
334 #define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_SET(x) (((x) << 0) & 0x00000fff)
335 #define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MSB 12
336 #define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_LSB 12
337 #define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MASK 0x00001000
338 #define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_GET(x) (((x) & 0x00001000) >> 12)
339 #define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_SET(x) (((x) << 12) & 0x00001000)
340 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MSB 13
341 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_LSB 13
342 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MASK 0x00002000
343 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_GET(x) (((x) & 0x00002000) >> 13)
344 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_SET(x) (((x) << 13) & 0x00002000)
345 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_MSB 14
346 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_LSB 14
347 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_MASK 0x00004000
348 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_GET(x) (((x) & 0x00004000) >> 14)
349 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_SET(x) (((x) << 14) & 0x00004000)
350 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MSB 15
351 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_LSB 15
352 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MASK 0x00008000
353 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_GET(x) (((x) & 0x00008000) >> 15)
354 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_SET(x) (((x) << 15) & 0x00008000)
355 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MSB 22
356 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_LSB 16
357 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MASK 0x007f0000
358 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_GET(x) (((x) & 0x007f0000) >> 16)
359 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_SET(x) (((x) << 16) & 0x007f0000)
360 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MSB 26
361 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_LSB 24
362 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MASK 0x07000000
363 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_GET(x) (((x) & 0x07000000) >> 24)
364 #define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_SET(x) (((x) << 24) & 0x07000000)
365 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MSB 27
366 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_LSB 27
367 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MASK 0x08000000
368 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_GET(x) (((x) & 0x08000000) >> 27)
369 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_SET(x) (((x) << 27) & 0x08000000)
370 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MSB 28
371 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_LSB 28
372 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MASK 0x10000000
373 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_GET(x) (((x) & 0x10000000) >> 28)
374 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_SET(x) (((x) << 28) & 0x10000000)
375 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MSB 29
376 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_LSB 29
377 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MASK 0x20000000
378 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_GET(x) (((x) & 0x20000000) >> 29)
379 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_SET(x) (((x) << 29) & 0x20000000)
380 #define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MSB 30
381 #define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_LSB 30
382 #define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MASK 0x40000000
383 #define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_GET(x) (((x) & 0x40000000) >> 30)
384 #define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_SET(x) (((x) << 30) & 0x40000000)
385 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MSB 31
386 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_LSB 31
387 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MASK 0x80000000
388 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_GET(x) (((x) & 0x80000000) >> 31)
389 #define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_SET(x) (((x) << 31) & 0x80000000)
391 /* macros for BB_timing_controls_3 */
392 #define PHY_BB_TIMING_CONTROLS_3_ADDRESS 0x00009814
393 #define PHY_BB_TIMING_CONTROLS_3_OFFSET 0x00009814
394 #define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MSB 7
395 #define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_LSB 0
396 #define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MASK 0x000000ff
397 #define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_GET(x) (((x) & 0x000000ff) >> 0)
398 #define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_SET(x) (((x) << 0) & 0x000000ff)
399 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MSB 8
400 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_LSB 8
401 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MASK 0x00000100
402 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_GET(x) (((x) & 0x00000100) >> 8)
403 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_SET(x) (((x) << 8) & 0x00000100)
404 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MSB 9
405 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_LSB 9
406 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MASK 0x00000200
407 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_GET(x) (((x) & 0x00000200) >> 9)
408 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_SET(x) (((x) << 9) & 0x00000200)
409 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MSB 10
410 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_LSB 10
411 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MASK 0x00000400
412 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_GET(x) (((x) & 0x00000400) >> 10)
413 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_SET(x) (((x) << 10) & 0x00000400)
414 #define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MSB 11
415 #define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_LSB 11
416 #define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MASK 0x00000800
417 #define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_GET(x) (((x) & 0x00000800) >> 11)
418 #define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_SET(x) (((x) << 11) & 0x00000800)
419 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MSB 12
420 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_LSB 12
421 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MASK 0x00001000
422 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_GET(x) (((x) & 0x00001000) >> 12)
423 #define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_SET(x) (((x) << 12) & 0x00001000)
424 #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MSB 16
425 #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_LSB 13
426 #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MASK 0x0001e000
427 #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_GET(x) (((x) & 0x0001e000) >> 13)
428 #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_SET(x) (((x) << 13) & 0x0001e000)
429 #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MSB 31
430 #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_LSB 17
431 #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MASK 0xfffe0000
432 #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_GET(x) (((x) & 0xfffe0000) >> 17)
433 #define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_SET(x) (((x) << 17) & 0xfffe0000)
435 /* macros for BB_D2_chip_id */
436 #define PHY_BB_D2_CHIP_ID_ADDRESS 0x00009818
437 #define PHY_BB_D2_CHIP_ID_OFFSET 0x00009818
438 #define PHY_BB_D2_CHIP_ID_OLD_ID_MSB 7
439 #define PHY_BB_D2_CHIP_ID_OLD_ID_LSB 0
440 #define PHY_BB_D2_CHIP_ID_OLD_ID_MASK 0x000000ff
441 #define PHY_BB_D2_CHIP_ID_OLD_ID_GET(x) (((x) & 0x000000ff) >> 0)
442 #define PHY_BB_D2_CHIP_ID_ID_MSB 31
443 #define PHY_BB_D2_CHIP_ID_ID_LSB 8
444 #define PHY_BB_D2_CHIP_ID_ID_MASK 0xffffff00
445 #define PHY_BB_D2_CHIP_ID_ID_GET(x) (((x) & 0xffffff00) >> 8)
447 /* macros for BB_active */
448 #define PHY_BB_ACTIVE_ADDRESS 0x0000981c
449 #define PHY_BB_ACTIVE_OFFSET 0x0000981c
450 #define PHY_BB_ACTIVE_CF_ACTIVE_MSB 0
451 #define PHY_BB_ACTIVE_CF_ACTIVE_LSB 0
452 #define PHY_BB_ACTIVE_CF_ACTIVE_MASK 0x00000001
453 #define PHY_BB_ACTIVE_CF_ACTIVE_GET(x) (((x) & 0x00000001) >> 0)
454 #define PHY_BB_ACTIVE_CF_ACTIVE_SET(x) (((x) << 0) & 0x00000001)
456 /* macros for BB_tx_timing_1 */
457 #define PHY_BB_TX_TIMING_1_ADDRESS 0x00009820
458 #define PHY_BB_TX_TIMING_1_OFFSET 0x00009820
459 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MSB 7
460 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_LSB 0
461 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MASK 0x000000ff
462 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_GET(x) (((x) & 0x000000ff) >> 0)
463 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_SET(x) (((x) << 0) & 0x000000ff)
464 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MSB 15
465 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_LSB 8
466 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MASK 0x0000ff00
467 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_GET(x) (((x) & 0x0000ff00) >> 8)
468 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_SET(x) (((x) << 8) & 0x0000ff00)
469 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MSB 23
470 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_LSB 16
471 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MASK 0x00ff0000
472 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_GET(x) (((x) & 0x00ff0000) >> 16)
473 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_SET(x) (((x) << 16) & 0x00ff0000)
474 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MSB 31
475 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_LSB 24
476 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MASK 0xff000000
477 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_GET(x) (((x) & 0xff000000) >> 24)
478 #define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_SET(x) (((x) << 24) & 0xff000000)
480 /* macros for BB_tx_timing_2 */
481 #define PHY_BB_TX_TIMING_2_ADDRESS 0x00009824
482 #define PHY_BB_TX_TIMING_2_OFFSET 0x00009824
483 #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MSB 7
484 #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_LSB 0
485 #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MASK 0x000000ff
486 #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_GET(x) (((x) & 0x000000ff) >> 0)
487 #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_SET(x) (((x) << 0) & 0x000000ff)
488 #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MSB 15
489 #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_LSB 8
490 #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MASK 0x0000ff00
491 #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_GET(x) (((x) & 0x0000ff00) >> 8)
492 #define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_SET(x) (((x) << 8) & 0x0000ff00)
493 #define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MSB 23
494 #define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_LSB 16
495 #define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MASK 0x00ff0000
496 #define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_GET(x) (((x) & 0x00ff0000) >> 16)
497 #define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_SET(x) (((x) << 16) & 0x00ff0000)
498 #define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MSB 31
499 #define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_LSB 24
500 #define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MASK 0xff000000
501 #define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_GET(x) (((x) & 0xff000000) >> 24)
502 #define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_SET(x) (((x) << 24) & 0xff000000)
504 /* macros for BB_tx_timing_3 */
505 #define PHY_BB_TX_TIMING_3_ADDRESS 0x00009828
506 #define PHY_BB_TX_TIMING_3_OFFSET 0x00009828
507 #define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MSB 7
508 #define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_LSB 0
509 #define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MASK 0x000000ff
510 #define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_GET(x) (((x) & 0x000000ff) >> 0)
511 #define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_SET(x) (((x) << 0) & 0x000000ff)
512 #define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MSB 15
513 #define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_LSB 8
514 #define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MASK 0x0000ff00
515 #define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_GET(x) (((x) & 0x0000ff00) >> 8)
516 #define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_SET(x) (((x) << 8) & 0x0000ff00)
517 #define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MSB 23
518 #define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_LSB 16
519 #define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MASK 0x00ff0000
520 #define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_GET(x) (((x) & 0x00ff0000) >> 16)
521 #define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_SET(x) (((x) << 16) & 0x00ff0000)
522 #define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MSB 31
523 #define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_LSB 24
524 #define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MASK 0xff000000
525 #define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_GET(x) (((x) & 0xff000000) >> 24)
526 #define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_SET(x) (((x) << 24) & 0xff000000)
528 /* macros for BB_addac_parallel_control */
529 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ADDRESS 0x0000982c
530 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFFSET 0x0000982c
531 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MSB 12
532 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_LSB 12
533 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MASK 0x00001000
534 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_GET(x) (((x) & 0x00001000) >> 12)
535 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_SET(x) (((x) << 12) & 0x00001000)
536 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MSB 13
537 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_LSB 13
538 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MASK 0x00002000
539 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_GET(x) (((x) & 0x00002000) >> 13)
540 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_SET(x) (((x) << 13) & 0x00002000)
541 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MSB 15
542 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_LSB 15
543 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MASK 0x00008000
544 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_GET(x) (((x) & 0x00008000) >> 15)
545 #define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_SET(x) (((x) << 15) & 0x00008000)
546 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MSB 28
547 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_LSB 28
548 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MASK 0x10000000
549 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_GET(x) (((x) & 0x10000000) >> 28)
550 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_SET(x) (((x) << 28) & 0x10000000)
551 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MSB 29
552 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_LSB 29
553 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MASK 0x20000000
554 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_GET(x) (((x) & 0x20000000) >> 29)
555 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_SET(x) (((x) << 29) & 0x20000000)
556 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MSB 31
557 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_LSB 31
558 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MASK 0x80000000
559 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_GET(x) (((x) & 0x80000000) >> 31)
560 #define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_SET(x) (((x) << 31) & 0x80000000)
562 /* macros for BB_xpa_timing_control */
563 #define PHY_BB_XPA_TIMING_CONTROL_ADDRESS 0x00009834
564 #define PHY_BB_XPA_TIMING_CONTROL_OFFSET 0x00009834
565 #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MSB 7
566 #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_LSB 0
567 #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MASK 0x000000ff
568 #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_GET(x) (((x) & 0x000000ff) >> 0)
569 #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_SET(x) (((x) << 0) & 0x000000ff)
570 #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MSB 15
571 #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_LSB 8
572 #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MASK 0x0000ff00
573 #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_GET(x) (((x) & 0x0000ff00) >> 8)
574 #define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_SET(x) (((x) << 8) & 0x0000ff00)
575 #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MSB 23
576 #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_LSB 16
577 #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MASK 0x00ff0000
578 #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_GET(x) (((x) & 0x00ff0000) >> 16)
579 #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_SET(x) (((x) << 16) & 0x00ff0000)
580 #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MSB 31
581 #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_LSB 24
582 #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MASK 0xff000000
583 #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_GET(x) (((x) & 0xff000000) >> 24)
584 #define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_SET(x) (((x) << 24) & 0xff000000)
586 /* macros for BB_misc_pa_control */
587 #define PHY_BB_MISC_PA_CONTROL_ADDRESS 0x00009838
588 #define PHY_BB_MISC_PA_CONTROL_OFFSET 0x00009838
589 #define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MSB 0
590 #define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_LSB 0
591 #define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MASK 0x00000001
592 #define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_GET(x) (((x) & 0x00000001) >> 0)
593 #define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_SET(x) (((x) << 0) & 0x00000001)
594 #define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MSB 1
595 #define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_LSB 1
596 #define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MASK 0x00000002
597 #define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_GET(x) (((x) & 0x00000002) >> 1)
598 #define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_SET(x) (((x) << 1) & 0x00000002)
599 #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MSB 2
600 #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_LSB 2
601 #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MASK 0x00000004
602 #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_GET(x) (((x) & 0x00000004) >> 2)
603 #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_SET(x) (((x) << 2) & 0x00000004)
604 #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MSB 3
605 #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_LSB 3
606 #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MASK 0x00000008
607 #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_GET(x) (((x) & 0x00000008) >> 3)
608 #define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_SET(x) (((x) << 3) & 0x00000008)
610 /* macros for BB_tstdac_constant */
611 #define PHY_BB_TSTDAC_CONSTANT_ADDRESS 0x0000983c
612 #define PHY_BB_TSTDAC_CONSTANT_OFFSET 0x0000983c
613 #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MSB 10
614 #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_LSB 0
615 #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MASK 0x000007ff
616 #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_GET(x) (((x) & 0x000007ff) >> 0)
617 #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_SET(x) (((x) << 0) & 0x000007ff)
618 #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MSB 21
619 #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_LSB 11
620 #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MASK 0x003ff800
621 #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_GET(x) (((x) & 0x003ff800) >> 11)
622 #define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_SET(x) (((x) << 11) & 0x003ff800)
624 /* macros for BB_find_signal_low */
625 #define PHY_BB_FIND_SIGNAL_LOW_ADDRESS 0x00009840
626 #define PHY_BB_FIND_SIGNAL_LOW_OFFSET 0x00009840
627 #define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MSB 5
628 #define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_LSB 0
629 #define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MASK 0x0000003f
630 #define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_GET(x) (((x) & 0x0000003f) >> 0)
631 #define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_SET(x) (((x) << 0) & 0x0000003f)
632 #define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MSB 11
633 #define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_LSB 6
634 #define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MASK 0x00000fc0
635 #define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_GET(x) (((x) & 0x00000fc0) >> 6)
636 #define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_SET(x) (((x) << 6) & 0x00000fc0)
637 #define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MSB 19
638 #define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_LSB 12
639 #define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MASK 0x000ff000
640 #define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_GET(x) (((x) & 0x000ff000) >> 12)
641 #define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_SET(x) (((x) << 12) & 0x000ff000)
642 #define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MSB 23
643 #define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_LSB 20
644 #define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MASK 0x00f00000
645 #define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_GET(x) (((x) & 0x00f00000) >> 20)
646 #define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_SET(x) (((x) << 20) & 0x00f00000)
647 #define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MSB 30
648 #define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_LSB 24
649 #define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MASK 0x7f000000
650 #define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_GET(x) (((x) & 0x7f000000) >> 24)
651 #define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_SET(x) (((x) << 24) & 0x7f000000)
653 /* macros for BB_settling_time */
654 #define PHY_BB_SETTLING_TIME_ADDRESS 0x00009844
655 #define PHY_BB_SETTLING_TIME_OFFSET 0x00009844
656 #define PHY_BB_SETTLING_TIME_AGC_SETTLING_MSB 6
657 #define PHY_BB_SETTLING_TIME_AGC_SETTLING_LSB 0
658 #define PHY_BB_SETTLING_TIME_AGC_SETTLING_MASK 0x0000007f
659 #define PHY_BB_SETTLING_TIME_AGC_SETTLING_GET(x) (((x) & 0x0000007f) >> 0)
660 #define PHY_BB_SETTLING_TIME_AGC_SETTLING_SET(x) (((x) << 0) & 0x0000007f)
661 #define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_MSB 13
662 #define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_LSB 7
663 #define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_MASK 0x00003f80
664 #define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_GET(x) (((x) & 0x00003f80) >> 7)
665 #define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_SET(x) (((x) << 7) & 0x00003f80)
666 #define PHY_BB_SETTLING_TIME_ADCSAT_THRL_MSB 19
667 #define PHY_BB_SETTLING_TIME_ADCSAT_THRL_LSB 14
668 #define PHY_BB_SETTLING_TIME_ADCSAT_THRL_MASK 0x000fc000
669 #define PHY_BB_SETTLING_TIME_ADCSAT_THRL_GET(x) (((x) & 0x000fc000) >> 14)
670 #define PHY_BB_SETTLING_TIME_ADCSAT_THRL_SET(x) (((x) << 14) & 0x000fc000)
671 #define PHY_BB_SETTLING_TIME_ADCSAT_THRH_MSB 25
672 #define PHY_BB_SETTLING_TIME_ADCSAT_THRH_LSB 20
673 #define PHY_BB_SETTLING_TIME_ADCSAT_THRH_MASK 0x03f00000
674 #define PHY_BB_SETTLING_TIME_ADCSAT_THRH_GET(x) (((x) & 0x03f00000) >> 20)
675 #define PHY_BB_SETTLING_TIME_ADCSAT_THRH_SET(x) (((x) << 20) & 0x03f00000)
676 #define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_MSB 29
677 #define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_LSB 26
678 #define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_MASK 0x3c000000
679 #define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_GET(x) (((x) & 0x3c000000) >> 26)
680 #define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_SET(x) (((x) << 26) & 0x3c000000)
682 /* macros for BB_gain_force_max_gains_b0 */
683 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ADDRESS 0x00009848
684 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_OFFSET 0x00009848
685 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_MSB 13
686 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_LSB 7
687 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_MASK 0x00003f80
688 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_GET(x) (((x) & 0x00003f80) >> 7)
689 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_SET(x) (((x) << 7) & 0x00003f80)
690 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_MSB 20
691 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_LSB 14
692 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_MASK 0x001fc000
693 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_GET(x) (((x) & 0x001fc000) >> 14)
694 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_SET(x) (((x) << 14) & 0x001fc000)
695 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_MSB 21
696 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_LSB 21
697 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_MASK 0x00200000
698 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_GET(x) (((x) & 0x00200000) >> 21)
699 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_SET(x) (((x) << 21) & 0x00200000)
700 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_MSB 31
701 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_LSB 31
702 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_MASK 0x80000000
703 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_GET(x) (((x) & 0x80000000) >> 31)
704 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_SET(x) (((x) << 31) & 0x80000000)
706 /* macros for BB_gains_min_offsets_b0 */
707 #define PHY_BB_GAINS_MIN_OFFSETS_B0_ADDRESS 0x0000984c
708 #define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSET 0x0000984c
709 #define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_MSB 6
710 #define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_LSB 0
711 #define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_MASK 0x0000007f
712 #define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_GET(x) (((x) & 0x0000007f) >> 0)
713 #define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_SET(x) (((x) << 0) & 0x0000007f)
714 #define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_MSB 11
715 #define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_LSB 7
716 #define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_MASK 0x00000f80
717 #define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_GET(x) (((x) & 0x00000f80) >> 7)
718 #define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_SET(x) (((x) << 7) & 0x00000f80)
719 #define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_MSB 16
720 #define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_LSB 12
721 #define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_MASK 0x0001f000
722 #define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_GET(x) (((x) & 0x0001f000) >> 12)
723 #define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_SET(x) (((x) << 12) & 0x0001f000)
724 #define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_MSB 24
725 #define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_LSB 17
726 #define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_MASK 0x01fe0000
727 #define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_GET(x) (((x) & 0x01fe0000) >> 17)
728 #define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_SET(x) (((x) << 17) & 0x01fe0000)
729 #define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_MSB 25
730 #define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_LSB 25
731 #define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_MASK 0x02000000
732 #define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_GET(x) (((x) & 0x02000000) >> 25)
733 #define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_SET(x) (((x) << 25) & 0x02000000)
734 #define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_MSB 26
735 #define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_LSB 26
736 #define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_MASK 0x04000000
737 #define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_GET(x) (((x) & 0x04000000) >> 26)
738 #define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_SET(x) (((x) << 26) & 0x04000000)
740 /* macros for BB_desired_sigsize */
741 #define PHY_BB_DESIRED_SIGSIZE_ADDRESS 0x00009850
742 #define PHY_BB_DESIRED_SIGSIZE_OFFSET 0x00009850
743 #define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_MSB 7
744 #define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_LSB 0
745 #define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_MASK 0x000000ff
746 #define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_GET(x) (((x) & 0x000000ff) >> 0)
747 #define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_SET(x) (((x) << 0) & 0x000000ff)
748 #define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_MSB 27
749 #define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_LSB 20
750 #define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_MASK 0x0ff00000
751 #define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_GET(x) (((x) & 0x0ff00000) >> 20)
752 #define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_SET(x) (((x) << 20) & 0x0ff00000)
753 #define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_MSB 29
754 #define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_LSB 28
755 #define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_MASK 0x30000000
756 #define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_GET(x) (((x) & 0x30000000) >> 28)
757 #define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_SET(x) (((x) << 28) & 0x30000000)
758 #define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_MSB 30
759 #define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_LSB 30
760 #define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_MASK 0x40000000
761 #define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_GET(x) (((x) & 0x40000000) >> 30)
762 #define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_SET(x) (((x) << 30) & 0x40000000)
763 #define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_MSB 31
764 #define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_LSB 31
765 #define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_MASK 0x80000000
766 #define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_GET(x) (((x) & 0x80000000) >> 31)
767 #define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_SET(x) (((x) << 31) & 0x80000000)
769 /* macros for BB_timing_control_3a */
770 #define PHY_BB_TIMING_CONTROL_3A_ADDRESS 0x00009854
771 #define PHY_BB_TIMING_CONTROL_3A_OFFSET 0x00009854
772 #define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_MSB 6
773 #define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_LSB 0
774 #define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_MASK 0x0000007f
775 #define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_GET(x) (((x) & 0x0000007f) >> 0)
776 #define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_SET(x) (((x) << 0) & 0x0000007f)
778 /* macros for BB_find_signal */
779 #define PHY_BB_FIND_SIGNAL_ADDRESS 0x00009858
780 #define PHY_BB_FIND_SIGNAL_OFFSET 0x00009858
781 #define PHY_BB_FIND_SIGNAL_RELSTEP_MSB 5
782 #define PHY_BB_FIND_SIGNAL_RELSTEP_LSB 0
783 #define PHY_BB_FIND_SIGNAL_RELSTEP_MASK 0x0000003f
784 #define PHY_BB_FIND_SIGNAL_RELSTEP_GET(x) (((x) & 0x0000003f) >> 0)
785 #define PHY_BB_FIND_SIGNAL_RELSTEP_SET(x) (((x) << 0) & 0x0000003f)
786 #define PHY_BB_FIND_SIGNAL_RELPWR_MSB 11
787 #define PHY_BB_FIND_SIGNAL_RELPWR_LSB 6
788 #define PHY_BB_FIND_SIGNAL_RELPWR_MASK 0x00000fc0
789 #define PHY_BB_FIND_SIGNAL_RELPWR_GET(x) (((x) & 0x00000fc0) >> 6)
790 #define PHY_BB_FIND_SIGNAL_RELPWR_SET(x) (((x) << 6) & 0x00000fc0)
791 #define PHY_BB_FIND_SIGNAL_FIRSTEP_MSB 17
792 #define PHY_BB_FIND_SIGNAL_FIRSTEP_LSB 12
793 #define PHY_BB_FIND_SIGNAL_FIRSTEP_MASK 0x0003f000
794 #define PHY_BB_FIND_SIGNAL_FIRSTEP_GET(x) (((x) & 0x0003f000) >> 12)
795 #define PHY_BB_FIND_SIGNAL_FIRSTEP_SET(x) (((x) << 12) & 0x0003f000)
796 #define PHY_BB_FIND_SIGNAL_FIRPWR_MSB 25
797 #define PHY_BB_FIND_SIGNAL_FIRPWR_LSB 18
798 #define PHY_BB_FIND_SIGNAL_FIRPWR_MASK 0x03fc0000
799 #define PHY_BB_FIND_SIGNAL_FIRPWR_GET(x) (((x) & 0x03fc0000) >> 18)
800 #define PHY_BB_FIND_SIGNAL_FIRPWR_SET(x) (((x) << 18) & 0x03fc0000)
801 #define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_MSB 31
802 #define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_LSB 26
803 #define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_MASK 0xfc000000
804 #define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_GET(x) (((x) & 0xfc000000) >> 26)
805 #define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_SET(x) (((x) << 26) & 0xfc000000)
807 /* macros for BB_agc */
808 #define PHY_BB_AGC_ADDRESS 0x0000985c
809 #define PHY_BB_AGC_OFFSET 0x0000985c
810 #define PHY_BB_AGC_COARSEPWR_CONST_MSB 6
811 #define PHY_BB_AGC_COARSEPWR_CONST_LSB 0
812 #define PHY_BB_AGC_COARSEPWR_CONST_MASK 0x0000007f
813 #define PHY_BB_AGC_COARSEPWR_CONST_GET(x) (((x) & 0x0000007f) >> 0)
814 #define PHY_BB_AGC_COARSEPWR_CONST_SET(x) (((x) << 0) & 0x0000007f)
815 #define PHY_BB_AGC_COARSE_LOW_MSB 14
816 #define PHY_BB_AGC_COARSE_LOW_LSB 7
817 #define PHY_BB_AGC_COARSE_LOW_MASK 0x00007f80
818 #define PHY_BB_AGC_COARSE_LOW_GET(x) (((x) & 0x00007f80) >> 7)
819 #define PHY_BB_AGC_COARSE_LOW_SET(x) (((x) << 7) & 0x00007f80)
820 #define PHY_BB_AGC_COARSE_HIGH_MSB 21
821 #define PHY_BB_AGC_COARSE_HIGH_LSB 15
822 #define PHY_BB_AGC_COARSE_HIGH_MASK 0x003f8000
823 #define PHY_BB_AGC_COARSE_HIGH_GET(x) (((x) & 0x003f8000) >> 15)
824 #define PHY_BB_AGC_COARSE_HIGH_SET(x) (((x) << 15) & 0x003f8000)
825 #define PHY_BB_AGC_QUICK_DROP_MSB 29
826 #define PHY_BB_AGC_QUICK_DROP_LSB 22
827 #define PHY_BB_AGC_QUICK_DROP_MASK 0x3fc00000
828 #define PHY_BB_AGC_QUICK_DROP_GET(x) (((x) & 0x3fc00000) >> 22)
829 #define PHY_BB_AGC_QUICK_DROP_SET(x) (((x) << 22) & 0x3fc00000)
830 #define PHY_BB_AGC_RSSI_OUT_SELECT_MSB 31
831 #define PHY_BB_AGC_RSSI_OUT_SELECT_LSB 30
832 #define PHY_BB_AGC_RSSI_OUT_SELECT_MASK 0xc0000000
833 #define PHY_BB_AGC_RSSI_OUT_SELECT_GET(x) (((x) & 0xc0000000) >> 30)
834 #define PHY_BB_AGC_RSSI_OUT_SELECT_SET(x) (((x) << 30) & 0xc0000000)
836 /* macros for BB_agc_control */
837 #define PHY_BB_AGC_CONTROL_ADDRESS 0x00009860
838 #define PHY_BB_AGC_CONTROL_OFFSET 0x00009860
839 #define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MSB 0
840 #define PHY_BB_AGC_CONTROL_DO_CALIBRATE_LSB 0
841 #define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MASK 0x00000001
842 #define PHY_BB_AGC_CONTROL_DO_CALIBRATE_GET(x) (((x) & 0x00000001) >> 0)
843 #define PHY_BB_AGC_CONTROL_DO_CALIBRATE_SET(x) (((x) << 0) & 0x00000001)
844 #define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MSB 1
845 #define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_LSB 1
846 #define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MASK 0x00000002
847 #define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_GET(x) (((x) & 0x00000002) >> 1)
848 #define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_SET(x) (((x) << 1) & 0x00000002)
849 #define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MSB 5
850 #define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_LSB 3
851 #define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MASK 0x00000038
852 #define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_GET(x) (((x) & 0x00000038) >> 3)
853 #define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_SET(x) (((x) << 3) & 0x00000038)
854 #define PHY_BB_AGC_CONTROL_YCOK_MAX_MSB 9
855 #define PHY_BB_AGC_CONTROL_YCOK_MAX_LSB 6
856 #define PHY_BB_AGC_CONTROL_YCOK_MAX_MASK 0x000003c0
857 #define PHY_BB_AGC_CONTROL_YCOK_MAX_GET(x) (((x) & 0x000003c0) >> 6)
858 #define PHY_BB_AGC_CONTROL_YCOK_MAX_SET(x) (((x) << 6) & 0x000003c0)
859 #define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MSB 10
860 #define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_LSB 10
861 #define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MASK 0x00000400
862 #define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_GET(x) (((x) & 0x00000400) >> 10)
863 #define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_SET(x) (((x) << 10) & 0x00000400)
864 #define PHY_BB_AGC_CONTROL_CAL_ENABLE_MSB 11
865 #define PHY_BB_AGC_CONTROL_CAL_ENABLE_LSB 11
866 #define PHY_BB_AGC_CONTROL_CAL_ENABLE_MASK 0x00000800
867 #define PHY_BB_AGC_CONTROL_CAL_ENABLE_GET(x) (((x) & 0x00000800) >> 11)
868 #define PHY_BB_AGC_CONTROL_CAL_ENABLE_SET(x) (((x) << 11) & 0x00000800)
869 #define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_MSB 12
870 #define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_LSB 12
871 #define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_MASK 0x00001000
872 #define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_GET(x) (((x) & 0x00001000) >> 12)
873 #define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_SET(x) (((x) << 12) & 0x00001000)
874 #define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_MSB 13
875 #define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_LSB 13
876 #define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_MASK 0x00002000
877 #define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_GET(x) (((x) & 0x00002000) >> 13)
878 #define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_SET(x) (((x) << 13) & 0x00002000)
879 #define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MSB 15
880 #define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_LSB 15
881 #define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MASK 0x00008000
882 #define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_GET(x) (((x) & 0x00008000) >> 15)
883 #define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_SET(x) (((x) << 15) & 0x00008000)
884 #define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MSB 16
885 #define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_LSB 16
886 #define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MASK 0x00010000
887 #define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_GET(x) (((x) & 0x00010000) >> 16)
888 #define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_SET(x) (((x) << 16) & 0x00010000)
889 #define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MSB 17
890 #define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_LSB 17
891 #define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MASK 0x00020000
892 #define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_GET(x) (((x) & 0x00020000) >> 17)
893 #define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_SET(x) (((x) << 17) & 0x00020000)
894 #define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MSB 18
895 #define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_LSB 18
896 #define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MASK 0x00040000
897 #define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_GET(x) (((x) & 0x00040000) >> 18)
898 #define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_SET(x) (((x) << 18) & 0x00040000)
899 #define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MSB 19
900 #define PHY_BB_AGC_CONTROL_CLC_SUCCESS_LSB 19
901 #define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MASK 0x00080000
902 #define PHY_BB_AGC_CONTROL_CLC_SUCCESS_GET(x) (((x) & 0x00080000) >> 19)
903 #define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MSB 20
904 #define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_LSB 20
905 #define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MASK 0x00100000
906 #define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_GET(x) (((x) & 0x00100000) >> 20)
907 #define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_SET(x) (((x) << 20) & 0x00100000)
909 /* macros for BB_cca_b0 */
910 #define PHY_BB_CCA_B0_ADDRESS 0x00009864
911 #define PHY_BB_CCA_B0_OFFSET 0x00009864
912 #define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_MSB 8
913 #define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_LSB 0
914 #define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_MASK 0x000001ff
915 #define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_GET(x) (((x) & 0x000001ff) >> 0)
916 #define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_SET(x) (((x) << 0) & 0x000001ff)
917 #define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_MSB 11
918 #define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_LSB 9
919 #define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_MASK 0x00000e00
920 #define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_GET(x) (((x) & 0x00000e00) >> 9)
921 #define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_SET(x) (((x) << 9) & 0x00000e00)
922 #define PHY_BB_CCA_B0_CF_THRESH62_MSB 19
923 #define PHY_BB_CCA_B0_CF_THRESH62_LSB 12
924 #define PHY_BB_CCA_B0_CF_THRESH62_MASK 0x000ff000
925 #define PHY_BB_CCA_B0_CF_THRESH62_GET(x) (((x) & 0x000ff000) >> 12)
926 #define PHY_BB_CCA_B0_CF_THRESH62_SET(x) (((x) << 12) & 0x000ff000)
927 #define PHY_BB_CCA_B0_MINCCAPWR_0_MSB 28
928 #define PHY_BB_CCA_B0_MINCCAPWR_0_LSB 20
929 #define PHY_BB_CCA_B0_MINCCAPWR_0_MASK 0x1ff00000
930 #define PHY_BB_CCA_B0_MINCCAPWR_0_GET(x) (((x) & 0x1ff00000) >> 20)
932 /* macros for BB_sfcorr */
933 #define PHY_BB_SFCORR_ADDRESS 0x00009868
934 #define PHY_BB_SFCORR_OFFSET 0x00009868
935 #define PHY_BB_SFCORR_M2COUNT_THR_MSB 4
936 #define PHY_BB_SFCORR_M2COUNT_THR_LSB 0
937 #define PHY_BB_SFCORR_M2COUNT_THR_MASK 0x0000001f
938 #define PHY_BB_SFCORR_M2COUNT_THR_GET(x) (((x) & 0x0000001f) >> 0)
939 #define PHY_BB_SFCORR_M2COUNT_THR_SET(x) (((x) << 0) & 0x0000001f)
940 #define PHY_BB_SFCORR_ADCSAT_THRESH_MSB 10
941 #define PHY_BB_SFCORR_ADCSAT_THRESH_LSB 5
942 #define PHY_BB_SFCORR_ADCSAT_THRESH_MASK 0x000007e0
943 #define PHY_BB_SFCORR_ADCSAT_THRESH_GET(x) (((x) & 0x000007e0) >> 5)
944 #define PHY_BB_SFCORR_ADCSAT_THRESH_SET(x) (((x) << 5) & 0x000007e0)
945 #define PHY_BB_SFCORR_ADCSAT_ICOUNT_MSB 16
946 #define PHY_BB_SFCORR_ADCSAT_ICOUNT_LSB 11
947 #define PHY_BB_SFCORR_ADCSAT_ICOUNT_MASK 0x0001f800
948 #define PHY_BB_SFCORR_ADCSAT_ICOUNT_GET(x) (((x) & 0x0001f800) >> 11)
949 #define PHY_BB_SFCORR_ADCSAT_ICOUNT_SET(x) (((x) << 11) & 0x0001f800)
950 #define PHY_BB_SFCORR_M1_THRES_MSB 23
951 #define PHY_BB_SFCORR_M1_THRES_LSB 17
952 #define PHY_BB_SFCORR_M1_THRES_MASK 0x00fe0000
953 #define PHY_BB_SFCORR_M1_THRES_GET(x) (((x) & 0x00fe0000) >> 17)
954 #define PHY_BB_SFCORR_M1_THRES_SET(x) (((x) << 17) & 0x00fe0000)
955 #define PHY_BB_SFCORR_M2_THRES_MSB 30
956 #define PHY_BB_SFCORR_M2_THRES_LSB 24
957 #define PHY_BB_SFCORR_M2_THRES_MASK 0x7f000000
958 #define PHY_BB_SFCORR_M2_THRES_GET(x) (((x) & 0x7f000000) >> 24)
959 #define PHY_BB_SFCORR_M2_THRES_SET(x) (((x) << 24) & 0x7f000000)
961 /* macros for BB_self_corr_low */
962 #define PHY_BB_SELF_CORR_LOW_ADDRESS 0x0000986c
963 #define PHY_BB_SELF_CORR_LOW_OFFSET 0x0000986c
964 #define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MSB 0
965 #define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_LSB 0
966 #define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MASK 0x00000001
967 #define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_GET(x) (((x) & 0x00000001) >> 0)
968 #define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_SET(x) (((x) << 0) & 0x00000001)
969 #define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MSB 7
970 #define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_LSB 1
971 #define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MASK 0x000000fe
972 #define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_GET(x) (((x) & 0x000000fe) >> 1)
973 #define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_SET(x) (((x) << 1) & 0x000000fe)
974 #define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MSB 13
975 #define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_LSB 8
976 #define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MASK 0x00003f00
977 #define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_GET(x) (((x) & 0x00003f00) >> 8)
978 #define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_SET(x) (((x) << 8) & 0x00003f00)
979 #define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MSB 20
980 #define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_LSB 14
981 #define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MASK 0x001fc000
982 #define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_GET(x) (((x) & 0x001fc000) >> 14)
983 #define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_SET(x) (((x) << 14) & 0x001fc000)
984 #define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MSB 27
985 #define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_LSB 21
986 #define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MASK 0x0fe00000
987 #define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_GET(x) (((x) & 0x0fe00000) >> 21)
988 #define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_SET(x) (((x) << 21) & 0x0fe00000)
990 /* macros for BB_synth_control */
991 #define PHY_BB_SYNTH_CONTROL_ADDRESS 0x00009874
992 #define PHY_BB_SYNTH_CONTROL_OFFSET 0x00009874
993 #define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MSB 16
994 #define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_LSB 0
995 #define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MASK 0x0001ffff
996 #define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_GET(x) (((x) & 0x0001ffff) >> 0)
997 #define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_SET(x) (((x) << 0) & 0x0001ffff)
998 #define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MSB 25
999 #define PHY_BB_SYNTH_CONTROL_RFCHANNEL_LSB 17
1000 #define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MASK 0x03fe0000
1001 #define PHY_BB_SYNTH_CONTROL_RFCHANNEL_GET(x) (((x) & 0x03fe0000) >> 17)
1002 #define PHY_BB_SYNTH_CONTROL_RFCHANNEL_SET(x) (((x) << 17) & 0x03fe0000)
1003 #define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MSB 27
1004 #define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_LSB 26
1005 #define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MASK 0x0c000000
1006 #define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_GET(x) (((x) & 0x0c000000) >> 26)
1007 #define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_SET(x) (((x) << 26) & 0x0c000000)
1008 #define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MSB 28
1009 #define PHY_BB_SYNTH_CONTROL_RFFRACMODE_LSB 28
1010 #define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MASK 0x10000000
1011 #define PHY_BB_SYNTH_CONTROL_RFFRACMODE_GET(x) (((x) & 0x10000000) >> 28)
1012 #define PHY_BB_SYNTH_CONTROL_RFFRACMODE_SET(x) (((x) << 28) & 0x10000000)
1013 #define PHY_BB_SYNTH_CONTROL_RFBMODE_MSB 29
1014 #define PHY_BB_SYNTH_CONTROL_RFBMODE_LSB 29
1015 #define PHY_BB_SYNTH_CONTROL_RFBMODE_MASK 0x20000000
1016 #define PHY_BB_SYNTH_CONTROL_RFBMODE_GET(x) (((x) & 0x20000000) >> 29)
1017 #define PHY_BB_SYNTH_CONTROL_RFBMODE_SET(x) (((x) << 29) & 0x20000000)
1018 #define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MSB 30
1019 #define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_LSB 30
1020 #define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MASK 0x40000000
1021 #define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_GET(x) (((x) & 0x40000000) >> 30)
1022 #define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_SET(x) (((x) << 30) & 0x40000000)
1024 /* macros for BB_addac_clk_select */
1025 #define PHY_BB_ADDAC_CLK_SELECT_ADDRESS 0x00009878
1026 #define PHY_BB_ADDAC_CLK_SELECT_OFFSET 0x00009878
1027 #define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MSB 3
1028 #define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_LSB 2
1029 #define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MASK 0x0000000c
1030 #define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_GET(x) (((x) & 0x0000000c) >> 2)
1031 #define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_SET(x) (((x) << 2) & 0x0000000c)
1032 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_MSB 5
1033 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_LSB 4
1034 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_MASK 0x00000030
1035 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_GET(x) (((x) & 0x00000030) >> 4)
1036 #define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_SET(x) (((x) << 4) & 0x00000030)
1038 /* macros for BB_pll_cntl */
1039 #define PHY_BB_PLL_CNTL_ADDRESS 0x0000987c
1040 #define PHY_BB_PLL_CNTL_OFFSET 0x0000987c
1041 #define PHY_BB_PLL_CNTL_BB_PLL_DIV_MSB 9
1042 #define PHY_BB_PLL_CNTL_BB_PLL_DIV_LSB 0
1043 #define PHY_BB_PLL_CNTL_BB_PLL_DIV_MASK 0x000003ff
1044 #define PHY_BB_PLL_CNTL_BB_PLL_DIV_GET(x) (((x) & 0x000003ff) >> 0)
1045 #define PHY_BB_PLL_CNTL_BB_PLL_DIV_SET(x) (((x) << 0) & 0x000003ff)
1046 #define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MSB 13
1047 #define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_LSB 10
1048 #define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MASK 0x00003c00
1049 #define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_GET(x) (((x) & 0x00003c00) >> 10)
1050 #define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_SET(x) (((x) << 10) & 0x00003c00)
1051 #define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MSB 15
1052 #define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_LSB 14
1053 #define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MASK 0x0000c000
1054 #define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_GET(x) (((x) & 0x0000c000) >> 14)
1055 #define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_SET(x) (((x) << 14) & 0x0000c000)
1056 #define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MSB 16
1057 #define PHY_BB_PLL_CNTL_BB_PLLBYPASS_LSB 16
1058 #define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MASK 0x00010000
1059 #define PHY_BB_PLL_CNTL_BB_PLLBYPASS_GET(x) (((x) & 0x00010000) >> 16)
1060 #define PHY_BB_PLL_CNTL_BB_PLLBYPASS_SET(x) (((x) << 16) & 0x00010000)
1061 #define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MSB 27
1062 #define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_LSB 17
1063 #define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MASK 0x0ffe0000
1064 #define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_GET(x) (((x) & 0x0ffe0000) >> 17)
1065 #define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_SET(x) (((x) << 17) & 0x0ffe0000)
1067 /* macros for BB_vit_spur_mask_A */
1068 #define PHY_BB_VIT_SPUR_MASK_A_ADDRESS 0x00009900
1069 #define PHY_BB_VIT_SPUR_MASK_A_OFFSET 0x00009900
1070 #define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_MSB 9
1071 #define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_LSB 0
1072 #define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_MASK 0x000003ff
1073 #define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_GET(x) (((x) & 0x000003ff) >> 0)
1074 #define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_SET(x) (((x) << 0) & 0x000003ff)
1075 #define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_MSB 16
1076 #define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_LSB 10
1077 #define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_MASK 0x0001fc00
1078 #define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_GET(x) (((x) & 0x0001fc00) >> 10)
1079 #define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_SET(x) (((x) << 10) & 0x0001fc00)
1081 /* macros for BB_vit_spur_mask_B */
1082 #define PHY_BB_VIT_SPUR_MASK_B_ADDRESS 0x00009904
1083 #define PHY_BB_VIT_SPUR_MASK_B_OFFSET 0x00009904
1084 #define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_MSB 9
1085 #define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_LSB 0
1086 #define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_MASK 0x000003ff
1087 #define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_GET(x) (((x) & 0x000003ff) >> 0)
1088 #define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_SET(x) (((x) << 0) & 0x000003ff)
1089 #define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_MSB 16
1090 #define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_LSB 10
1091 #define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_MASK 0x0001fc00
1092 #define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_GET(x) (((x) & 0x0001fc00) >> 10)
1093 #define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_SET(x) (((x) << 10) & 0x0001fc00)
1095 /* macros for BB_pilot_spur_mask */
1096 #define PHY_BB_PILOT_SPUR_MASK_ADDRESS 0x00009908
1097 #define PHY_BB_PILOT_SPUR_MASK_OFFSET 0x00009908
1098 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_MSB 4
1099 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_LSB 0
1100 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_MASK 0x0000001f
1101 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_GET(x) (((x) & 0x0000001f) >> 0)
1102 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_SET(x) (((x) << 0) & 0x0000001f)
1103 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_MSB 11
1104 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_LSB 5
1105 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_MASK 0x00000fe0
1106 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_GET(x) (((x) & 0x00000fe0) >> 5)
1107 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_SET(x) (((x) << 5) & 0x00000fe0)
1108 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_MSB 16
1109 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_LSB 12
1110 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_MASK 0x0001f000
1111 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_GET(x) (((x) & 0x0001f000) >> 12)
1112 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_SET(x) (((x) << 12) & 0x0001f000)
1113 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_MSB 23
1114 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_LSB 17
1115 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_MASK 0x00fe0000
1116 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_GET(x) (((x) & 0x00fe0000) >> 17)
1117 #define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_SET(x) (((x) << 17) & 0x00fe0000)
1119 /* macros for BB_chan_spur_mask */
1120 #define PHY_BB_CHAN_SPUR_MASK_ADDRESS 0x0000990c
1121 #define PHY_BB_CHAN_SPUR_MASK_OFFSET 0x0000990c
1122 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_MSB 4
1123 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_LSB 0
1124 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_MASK 0x0000001f
1125 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_GET(x) (((x) & 0x0000001f) >> 0)
1126 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_SET(x) (((x) << 0) & 0x0000001f)
1127 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_MSB 11
1128 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_LSB 5
1129 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_MASK 0x00000fe0
1130 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_GET(x) (((x) & 0x00000fe0) >> 5)
1131 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_SET(x) (((x) << 5) & 0x00000fe0)
1132 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_MSB 16
1133 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_LSB 12
1134 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_MASK 0x0001f000
1135 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_GET(x) (((x) & 0x0001f000) >> 12)
1136 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_SET(x) (((x) << 12) & 0x0001f000)
1137 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_MSB 23
1138 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_LSB 17
1139 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_MASK 0x00fe0000
1140 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_GET(x) (((x) & 0x00fe0000) >> 17)
1141 #define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_SET(x) (((x) << 17) & 0x00fe0000)
1143 /* macros for BB_spectral_scan */
1144 #define PHY_BB_SPECTRAL_SCAN_ADDRESS 0x00009910
1145 #define PHY_BB_SPECTRAL_SCAN_OFFSET 0x00009910
1146 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MSB 0
1147 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_LSB 0
1148 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MASK 0x00000001
1149 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_GET(x) (((x) & 0x00000001) >> 0)
1150 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_SET(x) (((x) << 0) & 0x00000001)
1151 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MSB 1
1152 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_LSB 1
1153 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MASK 0x00000002
1154 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_GET(x) (((x) & 0x00000002) >> 1)
1155 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_SET(x) (((x) << 1) & 0x00000002)
1156 #define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_MSB 2
1157 #define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_LSB 2
1158 #define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_MASK 0x00000004
1159 #define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_GET(x) (((x) & 0x00000004) >> 2)
1160 #define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_SET(x) (((x) << 2) & 0x00000004)
1161 #define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_MSB 3
1162 #define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_LSB 3
1163 #define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_MASK 0x00000008
1164 #define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_GET(x) (((x) & 0x00000008) >> 3)
1165 #define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_SET(x) (((x) << 3) & 0x00000008)
1166 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_MSB 7
1167 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_LSB 4
1168 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_MASK 0x000000f0
1169 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_GET(x) (((x) & 0x000000f0) >> 4)
1170 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_SET(x) (((x) << 4) & 0x000000f0)
1171 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MSB 15
1172 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_LSB 8
1173 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MASK 0x0000ff00
1174 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_GET(x) (((x) & 0x0000ff00) >> 8)
1175 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_SET(x) (((x) << 8) & 0x0000ff00)
1176 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MSB 27
1177 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_LSB 16
1178 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MASK 0x0fff0000
1179 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_GET(x) (((x) & 0x0fff0000) >> 16)
1180 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_SET(x) (((x) << 16) & 0x0fff0000)
1181 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_MSB 28
1182 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_LSB 28
1183 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_MASK 0x10000000
1184 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_GET(x) (((x) & 0x10000000) >> 28)
1185 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_SET(x) (((x) << 28) & 0x10000000)
1186 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MSB 29
1187 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_LSB 29
1188 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MASK 0x20000000
1189 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_GET(x) (((x) & 0x20000000) >> 29)
1190 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_SET(x) (((x) << 29) & 0x20000000)
1191 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_MSB 30
1192 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_LSB 30
1193 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_MASK 0x40000000
1194 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_GET(x) (((x) & 0x40000000) >> 30)
1195 #define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_SET(x) (((x) << 30) & 0x40000000)
1197 /* macros for BB_analog_power_on_time */
1198 #define PHY_BB_ANALOG_POWER_ON_TIME_ADDRESS 0x00009914
1199 #define PHY_BB_ANALOG_POWER_ON_TIME_OFFSET 0x00009914
1200 #define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MSB 13
1201 #define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_LSB 0
1202 #define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MASK 0x00003fff
1203 #define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_GET(x) (((x) & 0x00003fff) >> 0)
1204 #define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_SET(x) (((x) << 0) & 0x00003fff)
1206 /* macros for BB_search_start_delay */
1207 #define PHY_BB_SEARCH_START_DELAY_ADDRESS 0x00009918
1208 #define PHY_BB_SEARCH_START_DELAY_OFFSET 0x00009918
1209 #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_MSB 11
1210 #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_LSB 0
1211 #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_MASK 0x00000fff
1212 #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_GET(x) (((x) & 0x00000fff) >> 0)
1213 #define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SET(x) (((x) << 0) & 0x00000fff)
1214 #define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_MSB 12
1215 #define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_LSB 12
1216 #define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_MASK 0x00001000
1217 #define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_GET(x) (((x) & 0x00001000) >> 12)
1218 #define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_SET(x) (((x) << 12) & 0x00001000)
1219 #define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_MSB 13
1220 #define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_LSB 13
1221 #define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_MASK 0x00002000
1222 #define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_GET(x) (((x) & 0x00002000) >> 13)
1223 #define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_SET(x) (((x) << 13) & 0x00002000)
1225 /* macros for BB_max_rx_length */
1226 #define PHY_BB_MAX_RX_LENGTH_ADDRESS 0x0000991c
1227 #define PHY_BB_MAX_RX_LENGTH_OFFSET 0x0000991c
1228 #define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MSB 11
1229 #define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_LSB 0
1230 #define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MASK 0x00000fff
1231 #define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_GET(x) (((x) & 0x00000fff) >> 0)
1232 #define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_SET(x) (((x) << 0) & 0x00000fff)
1233 #define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MSB 29
1234 #define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_LSB 12
1235 #define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MASK 0x3ffff000
1236 #define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_GET(x) (((x) & 0x3ffff000) >> 12)
1237 #define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_SET(x) (((x) << 12) & 0x3ffff000)
1239 /* macros for BB_timing_control_4 */
1240 #define PHY_BB_TIMING_CONTROL_4_ADDRESS 0x00009920
1241 #define PHY_BB_TIMING_CONTROL_4_OFFSET 0x00009920
1242 #define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MSB 15
1243 #define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_LSB 12
1244 #define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MASK 0x0000f000
1245 #define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_GET(x) (((x) & 0x0000f000) >> 12)
1246 #define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_SET(x) (((x) << 12) & 0x0000f000)
1247 #define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MSB 16
1248 #define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_LSB 16
1249 #define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MASK 0x00010000
1250 #define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_GET(x) (((x) & 0x00010000) >> 16)
1251 #define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_SET(x) (((x) << 16) & 0x00010000)
1252 #define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MSB 20
1253 #define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_LSB 17
1254 #define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MASK 0x001e0000
1255 #define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_GET(x) (((x) & 0x001e0000) >> 17)
1256 #define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_SET(x) (((x) << 17) & 0x001e0000)
1257 #define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MSB 27
1258 #define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_LSB 21
1259 #define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MASK 0x0fe00000
1260 #define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_GET(x) (((x) & 0x0fe00000) >> 21)
1261 #define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_SET(x) (((x) << 21) & 0x0fe00000)
1262 #define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MSB 28
1263 #define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_LSB 28
1264 #define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MASK 0x10000000
1265 #define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_GET(x) (((x) & 0x10000000) >> 28)
1266 #define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_SET(x) (((x) << 28) & 0x10000000)
1267 #define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MSB 29
1268 #define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_LSB 29
1269 #define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MASK 0x20000000
1270 #define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_GET(x) (((x) & 0x20000000) >> 29)
1271 #define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_SET(x) (((x) << 29) & 0x20000000)
1272 #define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_MSB 30
1273 #define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_LSB 30
1274 #define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_MASK 0x40000000
1275 #define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_GET(x) (((x) & 0x40000000) >> 30)
1276 #define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_SET(x) (((x) << 30) & 0x40000000)
1277 #define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MSB 31
1278 #define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_LSB 31
1279 #define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MASK 0x80000000
1280 #define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_GET(x) (((x) & 0x80000000) >> 31)
1281 #define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_SET(x) (((x) << 31) & 0x80000000)
1283 /* macros for BB_timing_control_5 */
1284 #define PHY_BB_TIMING_CONTROL_5_ADDRESS 0x00009924
1285 #define PHY_BB_TIMING_CONTROL_5_OFFSET 0x00009924
1286 #define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MSB 0
1287 #define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_LSB 0
1288 #define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MASK 0x00000001
1289 #define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_GET(x) (((x) & 0x00000001) >> 0)
1290 #define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_SET(x) (((x) << 0) & 0x00000001)
1291 #define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MSB 7
1292 #define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_LSB 1
1293 #define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MASK 0x000000fe
1294 #define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_GET(x) (((x) & 0x000000fe) >> 1)
1295 #define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_SET(x) (((x) << 1) & 0x000000fe)
1296 #define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MSB 15
1297 #define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_LSB 15
1298 #define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MASK 0x00008000
1299 #define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_GET(x) (((x) & 0x00008000) >> 15)
1300 #define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_SET(x) (((x) << 15) & 0x00008000)
1301 #define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MSB 22
1302 #define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_LSB 16
1303 #define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MASK 0x007f0000
1304 #define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_GET(x) (((x) & 0x007f0000) >> 16)
1305 #define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_SET(x) (((x) << 16) & 0x007f0000)
1306 #define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MSB 29
1307 #define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_LSB 23
1308 #define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MASK 0x3f800000
1309 #define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_GET(x) (((x) & 0x3f800000) >> 23)
1310 #define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_SET(x) (((x) << 23) & 0x3f800000)
1311 #define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_MSB 30
1312 #define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_LSB 30
1313 #define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_MASK 0x40000000
1314 #define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_GET(x) (((x) & 0x40000000) >> 30)
1315 #define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_SET(x) (((x) << 30) & 0x40000000)
1316 #define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_MSB 31
1317 #define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_LSB 31
1318 #define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_MASK 0x80000000
1319 #define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_GET(x) (((x) & 0x80000000) >> 31)
1320 #define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_SET(x) (((x) << 31) & 0x80000000)
1322 /* macros for BB_phyonly_warm_reset */
1323 #define PHY_BB_PHYONLY_WARM_RESET_ADDRESS 0x00009928
1324 #define PHY_BB_PHYONLY_WARM_RESET_OFFSET 0x00009928
1325 #define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_MSB 0
1326 #define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_LSB 0
1327 #define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_MASK 0x00000001
1328 #define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_GET(x) (((x) & 0x00000001) >> 0)
1329 #define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_SET(x) (((x) << 0) & 0x00000001)
1331 /* macros for BB_phyonly_control */
1332 #define PHY_BB_PHYONLY_CONTROL_ADDRESS 0x0000992c
1333 #define PHY_BB_PHYONLY_CONTROL_OFFSET 0x0000992c
1334 #define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MSB 0
1335 #define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_LSB 0
1336 #define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MASK 0x00000001
1337 #define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_GET(x) (((x) & 0x00000001) >> 0)
1338 #define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_SET(x) (((x) << 0) & 0x00000001)
1339 #define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MSB 1
1340 #define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_LSB 1
1341 #define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MASK 0x00000002
1342 #define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_GET(x) (((x) & 0x00000002) >> 1)
1343 #define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_SET(x) (((x) << 1) & 0x00000002)
1344 #define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_MSB 2
1345 #define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_LSB 2
1346 #define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_MASK 0x00000004
1347 #define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_GET(x) (((x) & 0x00000004) >> 2)
1348 #define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_SET(x) (((x) << 2) & 0x00000004)
1349 #define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MSB 3
1350 #define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_LSB 3
1351 #define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MASK 0x00000008
1352 #define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_GET(x) (((x) & 0x00000008) >> 3)
1353 #define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_SET(x) (((x) << 3) & 0x00000008)
1354 #define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MSB 4
1355 #define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_LSB 4
1356 #define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MASK 0x00000010
1357 #define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_GET(x) (((x) & 0x00000010) >> 4)
1358 #define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_SET(x) (((x) << 4) & 0x00000010)
1359 #define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MSB 5
1360 #define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_LSB 5
1361 #define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MASK 0x00000020
1362 #define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_GET(x) (((x) & 0x00000020) >> 5)
1363 #define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_SET(x) (((x) << 5) & 0x00000020)
1364 #define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MSB 6
1365 #define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_LSB 6
1366 #define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MASK 0x00000040
1367 #define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_GET(x) (((x) & 0x00000040) >> 6)
1368 #define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_SET(x) (((x) << 6) & 0x00000040)
1369 #define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MSB 7
1370 #define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_LSB 7
1371 #define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MASK 0x00000080
1372 #define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_GET(x) (((x) & 0x00000080) >> 7)
1373 #define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_SET(x) (((x) << 7) & 0x00000080)
1375 /* macros for BB_powertx_rate1 */
1376 #define PHY_BB_POWERTX_RATE1_ADDRESS 0x00009934
1377 #define PHY_BB_POWERTX_RATE1_OFFSET 0x00009934
1378 #define PHY_BB_POWERTX_RATE1_POWERTX_0_MSB 5
1379 #define PHY_BB_POWERTX_RATE1_POWERTX_0_LSB 0
1380 #define PHY_BB_POWERTX_RATE1_POWERTX_0_MASK 0x0000003f
1381 #define PHY_BB_POWERTX_RATE1_POWERTX_0_GET(x) (((x) & 0x0000003f) >> 0)
1382 #define PHY_BB_POWERTX_RATE1_POWERTX_0_SET(x) (((x) << 0) & 0x0000003f)
1383 #define PHY_BB_POWERTX_RATE1_POWERTX_1_MSB 13
1384 #define PHY_BB_POWERTX_RATE1_POWERTX_1_LSB 8
1385 #define PHY_BB_POWERTX_RATE1_POWERTX_1_MASK 0x00003f00
1386 #define PHY_BB_POWERTX_RATE1_POWERTX_1_GET(x) (((x) & 0x00003f00) >> 8)
1387 #define PHY_BB_POWERTX_RATE1_POWERTX_1_SET(x) (((x) << 8) & 0x00003f00)
1388 #define PHY_BB_POWERTX_RATE1_POWERTX_2_MSB 21
1389 #define PHY_BB_POWERTX_RATE1_POWERTX_2_LSB 16
1390 #define PHY_BB_POWERTX_RATE1_POWERTX_2_MASK 0x003f0000
1391 #define PHY_BB_POWERTX_RATE1_POWERTX_2_GET(x) (((x) & 0x003f0000) >> 16)
1392 #define PHY_BB_POWERTX_RATE1_POWERTX_2_SET(x) (((x) << 16) & 0x003f0000)
1393 #define PHY_BB_POWERTX_RATE1_POWERTX_3_MSB 29
1394 #define PHY_BB_POWERTX_RATE1_POWERTX_3_LSB 24
1395 #define PHY_BB_POWERTX_RATE1_POWERTX_3_MASK 0x3f000000
1396 #define PHY_BB_POWERTX_RATE1_POWERTX_3_GET(x) (((x) & 0x3f000000) >> 24)
1397 #define PHY_BB_POWERTX_RATE1_POWERTX_3_SET(x) (((x) << 24) & 0x3f000000)
1399 /* macros for BB_powertx_rate2 */
1400 #define PHY_BB_POWERTX_RATE2_ADDRESS 0x00009938
1401 #define PHY_BB_POWERTX_RATE2_OFFSET 0x00009938
1402 #define PHY_BB_POWERTX_RATE2_POWERTX_4_MSB 5
1403 #define PHY_BB_POWERTX_RATE2_POWERTX_4_LSB 0
1404 #define PHY_BB_POWERTX_RATE2_POWERTX_4_MASK 0x0000003f
1405 #define PHY_BB_POWERTX_RATE2_POWERTX_4_GET(x) (((x) & 0x0000003f) >> 0)
1406 #define PHY_BB_POWERTX_RATE2_POWERTX_4_SET(x) (((x) << 0) & 0x0000003f)
1407 #define PHY_BB_POWERTX_RATE2_POWERTX_5_MSB 13
1408 #define PHY_BB_POWERTX_RATE2_POWERTX_5_LSB 8
1409 #define PHY_BB_POWERTX_RATE2_POWERTX_5_MASK 0x00003f00
1410 #define PHY_BB_POWERTX_RATE2_POWERTX_5_GET(x) (((x) & 0x00003f00) >> 8)
1411 #define PHY_BB_POWERTX_RATE2_POWERTX_5_SET(x) (((x) << 8) & 0x00003f00)
1412 #define PHY_BB_POWERTX_RATE2_POWERTX_6_MSB 21
1413 #define PHY_BB_POWERTX_RATE2_POWERTX_6_LSB 16
1414 #define PHY_BB_POWERTX_RATE2_POWERTX_6_MASK 0x003f0000
1415 #define PHY_BB_POWERTX_RATE2_POWERTX_6_GET(x) (((x) & 0x003f0000) >> 16)
1416 #define PHY_BB_POWERTX_RATE2_POWERTX_6_SET(x) (((x) << 16) & 0x003f0000)
1417 #define PHY_BB_POWERTX_RATE2_POWERTX_7_MSB 29
1418 #define PHY_BB_POWERTX_RATE2_POWERTX_7_LSB 24
1419 #define PHY_BB_POWERTX_RATE2_POWERTX_7_MASK 0x3f000000
1420 #define PHY_BB_POWERTX_RATE2_POWERTX_7_GET(x) (((x) & 0x3f000000) >> 24)
1421 #define PHY_BB_POWERTX_RATE2_POWERTX_7_SET(x) (((x) << 24) & 0x3f000000)
1423 /* macros for BB_powertx_max */
1424 #define PHY_BB_POWERTX_MAX_ADDRESS 0x0000993c
1425 #define PHY_BB_POWERTX_MAX_OFFSET 0x0000993c
1426 #define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_MSB 6
1427 #define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_LSB 6
1428 #define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_MASK 0x00000040
1429 #define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_GET(x) (((x) & 0x00000040) >> 6)
1430 #define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_SET(x) (((x) << 6) & 0x00000040)
1432 /* macros for BB_extension_radar */
1433 #define PHY_BB_EXTENSION_RADAR_ADDRESS 0x00009940
1434 #define PHY_BB_EXTENSION_RADAR_OFFSET 0x00009940
1435 #define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_MSB 13
1436 #define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_LSB 8
1437 #define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_MASK 0x00003f00
1438 #define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_GET(x) (((x) & 0x00003f00) >> 8)
1439 #define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_SET(x) (((x) << 8) & 0x00003f00)
1440 #define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_MSB 14
1441 #define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_LSB 14
1442 #define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_MASK 0x00004000
1443 #define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_GET(x) (((x) & 0x00004000) >> 14)
1444 #define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_SET(x) (((x) << 14) & 0x00004000)
1445 #define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_MSB 22
1446 #define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_LSB 15
1447 #define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_MASK 0x007f8000
1448 #define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_GET(x) (((x) & 0x007f8000) >> 15)
1449 #define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_SET(x) (((x) << 15) & 0x007f8000)
1450 #define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MSB 30
1451 #define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_LSB 23
1452 #define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MASK 0x7f800000
1453 #define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_GET(x) (((x) & 0x7f800000) >> 23)
1454 #define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_SET(x) (((x) << 23) & 0x7f800000)
1455 #define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_MSB 31
1456 #define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_LSB 31
1457 #define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_MASK 0x80000000
1458 #define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_GET(x) (((x) & 0x80000000) >> 31)
1459 #define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_SET(x) (((x) << 31) & 0x80000000)
1461 /* macros for BB_frame_control */
1462 #define PHY_BB_FRAME_CONTROL_ADDRESS 0x00009944
1463 #define PHY_BB_FRAME_CONTROL_OFFSET 0x00009944
1464 #define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MSB 1
1465 #define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_LSB 0
1466 #define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MASK 0x00000003
1467 #define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_GET(x) (((x) & 0x00000003) >> 0)
1468 #define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_SET(x) (((x) << 0) & 0x00000003)
1469 #define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_MSB 2
1470 #define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_LSB 2
1471 #define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_MASK 0x00000004
1472 #define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_GET(x) (((x) & 0x00000004) >> 2)
1473 #define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_SET(x) (((x) << 2) & 0x00000004)
1474 #define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MSB 5
1475 #define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_LSB 3
1476 #define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MASK 0x00000038
1477 #define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_GET(x) (((x) & 0x00000038) >> 3)
1478 #define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_SET(x) (((x) << 3) & 0x00000038)
1479 #define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MSB 7
1480 #define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_LSB 6
1481 #define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MASK 0x000000c0
1482 #define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_GET(x) (((x) & 0x000000c0) >> 6)
1483 #define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_SET(x) (((x) << 6) & 0x000000c0)
1484 #define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MSB 15
1485 #define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_LSB 8
1486 #define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MASK 0x0000ff00
1487 #define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_GET(x) (((x) & 0x0000ff00) >> 8)
1488 #define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_SET(x) (((x) << 8) & 0x0000ff00)
1489 #define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MSB 16
1490 #define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_LSB 16
1491 #define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MASK 0x00010000
1492 #define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_GET(x) (((x) & 0x00010000) >> 16)
1493 #define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_SET(x) (((x) << 16) & 0x00010000)
1494 #define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MSB 17
1495 #define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_LSB 17
1496 #define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MASK 0x00020000
1497 #define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_GET(x) (((x) & 0x00020000) >> 17)
1498 #define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_SET(x) (((x) << 17) & 0x00020000)
1499 #define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MSB 18
1500 #define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_LSB 18
1501 #define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MASK 0x00040000
1502 #define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_GET(x) (((x) & 0x00040000) >> 18)
1503 #define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_SET(x) (((x) << 18) & 0x00040000)
1504 #define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_MSB 19
1505 #define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_LSB 19
1506 #define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_MASK 0x00080000
1507 #define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_GET(x) (((x) & 0x00080000) >> 19)
1508 #define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_SET(x) (((x) << 19) & 0x00080000)
1509 #define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MSB 20
1510 #define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_LSB 20
1511 #define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MASK 0x00100000
1512 #define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_GET(x) (((x) & 0x00100000) >> 20)
1513 #define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_SET(x) (((x) << 20) & 0x00100000)
1514 #define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MSB 21
1515 #define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_LSB 21
1516 #define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MASK 0x00200000
1517 #define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_GET(x) (((x) & 0x00200000) >> 21)
1518 #define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_SET(x) (((x) << 21) & 0x00200000)
1519 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MSB 22
1520 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_LSB 22
1521 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MASK 0x00400000
1522 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_GET(x) (((x) & 0x00400000) >> 22)
1523 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_SET(x) (((x) << 22) & 0x00400000)
1524 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MSB 23
1525 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_LSB 23
1526 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MASK 0x00800000
1527 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_GET(x) (((x) & 0x00800000) >> 23)
1528 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_SET(x) (((x) << 23) & 0x00800000)
1529 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MSB 24
1530 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_LSB 24
1531 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MASK 0x01000000
1532 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_GET(x) (((x) & 0x01000000) >> 24)
1533 #define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_SET(x) (((x) << 24) & 0x01000000)
1534 #define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MSB 25
1535 #define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_LSB 25
1536 #define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MASK 0x02000000
1537 #define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_GET(x) (((x) & 0x02000000) >> 25)
1538 #define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_SET(x) (((x) << 25) & 0x02000000)
1539 #define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MSB 26
1540 #define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_LSB 26
1541 #define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MASK 0x04000000
1542 #define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_GET(x) (((x) & 0x04000000) >> 26)
1543 #define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_SET(x) (((x) << 26) & 0x04000000)
1544 #define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MSB 27
1545 #define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_LSB 27
1546 #define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MASK 0x08000000
1547 #define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_GET(x) (((x) & 0x08000000) >> 27)
1548 #define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_SET(x) (((x) << 27) & 0x08000000)
1549 #define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_MSB 28
1550 #define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_LSB 28
1551 #define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_MASK 0x10000000
1552 #define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_GET(x) (((x) & 0x10000000) >> 28)
1553 #define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_SET(x) (((x) << 28) & 0x10000000)
1554 #define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MSB 29
1555 #define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_LSB 29
1556 #define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MASK 0x20000000
1557 #define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_GET(x) (((x) & 0x20000000) >> 29)
1558 #define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_SET(x) (((x) << 29) & 0x20000000)
1559 #define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MSB 30
1560 #define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_LSB 30
1561 #define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MASK 0x40000000
1562 #define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_GET(x) (((x) & 0x40000000) >> 30)
1563 #define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_SET(x) (((x) << 30) & 0x40000000)
1564 #define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MSB 31
1565 #define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_LSB 31
1566 #define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MASK 0x80000000
1567 #define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_GET(x) (((x) & 0x80000000) >> 31)
1568 #define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_SET(x) (((x) << 31) & 0x80000000)
1570 /* macros for BB_timing_control_6 */
1571 #define PHY_BB_TIMING_CONTROL_6_ADDRESS 0x00009948
1572 #define PHY_BB_TIMING_CONTROL_6_OFFSET 0x00009948
1573 #define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MSB 7
1574 #define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_LSB 0
1575 #define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MASK 0x000000ff
1576 #define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_GET(x) (((x) & 0x000000ff) >> 0)
1577 #define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_SET(x) (((x) << 0) & 0x000000ff)
1578 #define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MSB 14
1579 #define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_LSB 8
1580 #define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MASK 0x00007f00
1581 #define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_GET(x) (((x) & 0x00007f00) >> 8)
1582 #define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_SET(x) (((x) << 8) & 0x00007f00)
1583 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MSB 20
1584 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_LSB 15
1585 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MASK 0x001f8000
1586 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_GET(x) (((x) & 0x001f8000) >> 15)
1587 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_SET(x) (((x) << 15) & 0x001f8000)
1588 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MSB 27
1589 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_LSB 21
1590 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MASK 0x0fe00000
1591 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_GET(x) (((x) & 0x0fe00000) >> 21)
1592 #define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_SET(x) (((x) << 21) & 0x0fe00000)
1593 #define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_MSB 31
1594 #define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_LSB 28
1595 #define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_MASK 0xf0000000
1596 #define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_GET(x) (((x) & 0xf0000000) >> 28)
1597 #define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_SET(x) (((x) << 28) & 0xf0000000)
1599 /* macros for BB_spur_mask_controls */
1600 #define PHY_BB_SPUR_MASK_CONTROLS_ADDRESS 0x0000994c
1601 #define PHY_BB_SPUR_MASK_CONTROLS_OFFSET 0x0000994c
1602 #define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MSB 7
1603 #define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_LSB 0
1604 #define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MASK 0x000000ff
1605 #define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_GET(x) (((x) & 0x000000ff) >> 0)
1606 #define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_SET(x) (((x) << 0) & 0x000000ff)
1607 #define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MSB 8
1608 #define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_LSB 8
1609 #define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MASK 0x00000100
1610 #define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_GET(x) (((x) & 0x00000100) >> 8)
1611 #define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_SET(x) (((x) << 8) & 0x00000100)
1612 #define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MSB 17
1613 #define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_LSB 17
1614 #define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MASK 0x00020000
1615 #define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_GET(x) (((x) & 0x00020000) >> 17)
1616 #define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_SET(x) (((x) << 17) & 0x00020000)
1617 #define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MSB 25
1618 #define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_LSB 18
1619 #define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MASK 0x03fc0000
1620 #define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_GET(x) (((x) & 0x03fc0000) >> 18)
1621 #define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_SET(x) (((x) << 18) & 0x03fc0000)
1623 /* macros for BB_rx_iq_corr_b0 */
1624 #define PHY_BB_RX_IQ_CORR_B0_ADDRESS 0x00009950
1625 #define PHY_BB_RX_IQ_CORR_B0_OFFSET 0x00009950
1626 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_MSB 6
1627 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_LSB 0
1628 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_MASK 0x0000007f
1629 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_GET(x) (((x) & 0x0000007f) >> 0)
1630 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_SET(x) (((x) << 0) & 0x0000007f)
1631 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_MSB 13
1632 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_LSB 7
1633 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_MASK 0x00003f80
1634 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_GET(x) (((x) & 0x00003f80) >> 7)
1635 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_SET(x) (((x) << 7) & 0x00003f80)
1636 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MSB 14
1637 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_LSB 14
1638 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MASK 0x00004000
1639 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_GET(x) (((x) & 0x00004000) >> 14)
1640 #define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_SET(x) (((x) << 14) & 0x00004000)
1641 #define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MSB 21
1642 #define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_LSB 15
1643 #define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MASK 0x003f8000
1644 #define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_GET(x) (((x) & 0x003f8000) >> 15)
1645 #define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_SET(x) (((x) << 15) & 0x003f8000)
1646 #define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MSB 28
1647 #define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_LSB 22
1648 #define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MASK 0x1fc00000
1649 #define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_GET(x) (((x) & 0x1fc00000) >> 22)
1650 #define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_SET(x) (((x) << 22) & 0x1fc00000)
1651 #define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_MSB 29
1652 #define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_LSB 29
1653 #define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_MASK 0x20000000
1654 #define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_GET(x) (((x) & 0x20000000) >> 29)
1655 #define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_SET(x) (((x) << 29) & 0x20000000)
1657 /* macros for BB_radar_detection */
1658 #define PHY_BB_RADAR_DETECTION_ADDRESS 0x00009954
1659 #define PHY_BB_RADAR_DETECTION_OFFSET 0x00009954
1660 #define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MSB 0
1661 #define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_LSB 0
1662 #define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MASK 0x00000001
1663 #define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_GET(x) (((x) & 0x00000001) >> 0)
1664 #define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_SET(x) (((x) << 0) & 0x00000001)
1665 #define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_MSB 5
1666 #define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_LSB 1
1667 #define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_MASK 0x0000003e
1668 #define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_GET(x) (((x) & 0x0000003e) >> 1)
1669 #define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_SET(x) (((x) << 1) & 0x0000003e)
1670 #define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MSB 11
1671 #define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_LSB 6
1672 #define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MASK 0x00000fc0
1673 #define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_GET(x) (((x) & 0x00000fc0) >> 6)
1674 #define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_SET(x) (((x) << 6) & 0x00000fc0)
1675 #define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MSB 17
1676 #define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_LSB 12
1677 #define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MASK 0x0003f000
1678 #define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_GET(x) (((x) & 0x0003f000) >> 12)
1679 #define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_SET(x) (((x) << 12) & 0x0003f000)
1680 #define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_MSB 23
1681 #define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_LSB 18
1682 #define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_MASK 0x00fc0000
1683 #define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_GET(x) (((x) & 0x00fc0000) >> 18)
1684 #define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_SET(x) (((x) << 18) & 0x00fc0000)
1685 #define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MSB 30
1686 #define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_LSB 24
1687 #define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MASK 0x7f000000
1688 #define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_GET(x) (((x) & 0x7f000000) >> 24)
1689 #define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_SET(x) (((x) << 24) & 0x7f000000)
1690 #define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_MSB 31
1691 #define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_LSB 31
1692 #define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_MASK 0x80000000
1693 #define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_GET(x) (((x) & 0x80000000) >> 31)
1694 #define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_SET(x) (((x) << 31) & 0x80000000)
1696 /* macros for BB_radar_detection_2 */
1697 #define PHY_BB_RADAR_DETECTION_2_ADDRESS 0x00009958
1698 #define PHY_BB_RADAR_DETECTION_2_OFFSET 0x00009958
1699 #define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_MSB 7
1700 #define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_LSB 0
1701 #define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_MASK 0x000000ff
1702 #define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_GET(x) (((x) & 0x000000ff) >> 0)
1703 #define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_SET(x) (((x) << 0) & 0x000000ff)
1704 #define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MSB 12
1705 #define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_LSB 8
1706 #define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MASK 0x00001f00
1707 #define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_GET(x) (((x) & 0x00001f00) >> 8)
1708 #define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_SET(x) (((x) << 8) & 0x00001f00)
1709 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MSB 13
1710 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_LSB 13
1711 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MASK 0x00002000
1712 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_GET(x) (((x) & 0x00002000) >> 13)
1713 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_SET(x) (((x) << 13) & 0x00002000)
1714 #define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_MSB 14
1715 #define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_LSB 14
1716 #define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_MASK 0x00004000
1717 #define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_GET(x) (((x) & 0x00004000) >> 14)
1718 #define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_SET(x) (((x) << 14) & 0x00004000)
1719 #define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_MSB 15
1720 #define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_LSB 15
1721 #define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_MASK 0x00008000
1722 #define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_GET(x) (((x) & 0x00008000) >> 15)
1723 #define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_SET(x) (((x) << 15) & 0x00008000)
1724 #define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_MSB 21
1725 #define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_LSB 16
1726 #define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_MASK 0x003f0000
1727 #define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_GET(x) (((x) & 0x003f0000) >> 16)
1728 #define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_SET(x) (((x) << 16) & 0x003f0000)
1729 #define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_MSB 22
1730 #define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_LSB 22
1731 #define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_MASK 0x00400000
1732 #define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_GET(x) (((x) & 0x00400000) >> 22)
1733 #define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_SET(x) (((x) << 22) & 0x00400000)
1734 #define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_MSB 23
1735 #define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_LSB 23
1736 #define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_MASK 0x00800000
1737 #define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_GET(x) (((x) & 0x00800000) >> 23)
1738 #define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_SET(x) (((x) << 23) & 0x00800000)
1739 #define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_MSB 26
1740 #define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_LSB 24
1741 #define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_MASK 0x07000000
1742 #define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_GET(x) (((x) & 0x07000000) >> 24)
1743 #define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_SET(x) (((x) << 24) & 0x07000000)
1744 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MSB 27
1745 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_LSB 27
1746 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MASK 0x08000000
1747 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_GET(x) (((x) & 0x08000000) >> 27)
1748 #define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_SET(x) (((x) << 27) & 0x08000000)
1750 /* macros for BB_tx_phase_ramp_b0 */
1751 #define PHY_BB_TX_PHASE_RAMP_B0_ADDRESS 0x0000995c
1752 #define PHY_BB_TX_PHASE_RAMP_B0_OFFSET 0x0000995c
1753 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MSB 0
1754 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_LSB 0
1755 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MASK 0x00000001
1756 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_GET(x) (((x) & 0x00000001) >> 0)
1757 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_SET(x) (((x) << 0) & 0x00000001)
1758 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MSB 6
1759 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_LSB 1
1760 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MASK 0x0000007e
1761 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_GET(x) (((x) & 0x0000007e) >> 1)
1762 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_SET(x) (((x) << 1) & 0x0000007e)
1763 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MSB 16
1764 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_LSB 7
1765 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MASK 0x0001ff80
1766 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_GET(x) (((x) & 0x0001ff80) >> 7)
1767 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_SET(x) (((x) << 7) & 0x0001ff80)
1768 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MSB 24
1769 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_LSB 17
1770 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MASK 0x01fe0000
1771 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_GET(x) (((x) & 0x01fe0000) >> 17)
1772 #define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_SET(x) (((x) << 17) & 0x01fe0000)
1774 /* macros for BB_switch_table_chn_b0 */
1775 #define PHY_BB_SWITCH_TABLE_CHN_B0_ADDRESS 0x00009960
1776 #define PHY_BB_SWITCH_TABLE_CHN_B0_OFFSET 0x00009960
1777 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MSB 1
1778 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_LSB 0
1779 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MASK 0x00000003
1780 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_GET(x) (((x) & 0x00000003) >> 0)
1781 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_SET(x) (((x) << 0) & 0x00000003)
1782 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MSB 3
1783 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_LSB 2
1784 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MASK 0x0000000c
1785 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_GET(x) (((x) & 0x0000000c) >> 2)
1786 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_SET(x) (((x) << 2) & 0x0000000c)
1787 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MSB 5
1788 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_LSB 4
1789 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MASK 0x00000030
1790 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_GET(x) (((x) & 0x00000030) >> 4)
1791 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_SET(x) (((x) << 4) & 0x00000030)
1792 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MSB 7
1793 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_LSB 6
1794 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MASK 0x000000c0
1795 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_GET(x) (((x) & 0x000000c0) >> 6)
1796 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_SET(x) (((x) << 6) & 0x000000c0)
1797 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MSB 9
1798 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_LSB 8
1799 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MASK 0x00000300
1800 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_GET(x) (((x) & 0x00000300) >> 8)
1801 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_SET(x) (((x) << 8) & 0x00000300)
1802 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MSB 11
1803 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_LSB 10
1804 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MASK 0x00000c00
1805 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_GET(x) (((x) & 0x00000c00) >> 10)
1806 #define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_SET(x) (((x) << 10) & 0x00000c00)
1808 /* macros for BB_switch_table_com1 */
1809 #define PHY_BB_SWITCH_TABLE_COM1_ADDRESS 0x00009964
1810 #define PHY_BB_SWITCH_TABLE_COM1_OFFSET 0x00009964
1811 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MSB 3
1812 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_LSB 0
1813 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MASK 0x0000000f
1814 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_GET(x) (((x) & 0x0000000f) >> 0)
1815 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_SET(x) (((x) << 0) & 0x0000000f)
1816 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MSB 7
1817 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_LSB 4
1818 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MASK 0x000000f0
1819 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_GET(x) (((x) & 0x000000f0) >> 4)
1820 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_SET(x) (((x) << 4) & 0x000000f0)
1821 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MSB 11
1822 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_LSB 8
1823 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MASK 0x00000f00
1824 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_GET(x) (((x) & 0x00000f00) >> 8)
1825 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_SET(x) (((x) << 8) & 0x00000f00)
1826 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MSB 15
1827 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_LSB 12
1828 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MASK 0x0000f000
1829 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_GET(x) (((x) & 0x0000f000) >> 12)
1830 #define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_SET(x) (((x) << 12) & 0x0000f000)
1832 /* macros for BB_cca_ctrl_2_b0 */
1833 #define PHY_BB_CCA_CTRL_2_B0_ADDRESS 0x00009968
1834 #define PHY_BB_CCA_CTRL_2_B0_OFFSET 0x00009968
1835 #define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_MSB 8
1836 #define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_LSB 0
1837 #define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_MASK 0x000001ff
1838 #define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_GET(x) (((x) & 0x000001ff) >> 0)
1839 #define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_SET(x) (((x) << 0) & 0x000001ff)
1840 #define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_MSB 9
1841 #define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_LSB 9
1842 #define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_MASK 0x00000200
1843 #define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_GET(x) (((x) & 0x00000200) >> 9)
1844 #define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_SET(x) (((x) << 9) & 0x00000200)
1845 #define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_MSB 17
1846 #define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_LSB 10
1847 #define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_MASK 0x0003fc00
1848 #define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_GET(x) (((x) & 0x0003fc00) >> 10)
1849 #define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_SET(x) (((x) << 10) & 0x0003fc00)
1850 #define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_MSB 18
1851 #define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_LSB 18
1852 #define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_MASK 0x00040000
1853 #define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_GET(x) (((x) & 0x00040000) >> 18)
1854 #define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_SET(x) (((x) << 18) & 0x00040000)
1856 /* macros for BB_switch_table_com2 */
1857 #define PHY_BB_SWITCH_TABLE_COM2_ADDRESS 0x0000996c
1858 #define PHY_BB_SWITCH_TABLE_COM2_OFFSET 0x0000996c
1859 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_MSB 3
1860 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_LSB 0
1861 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_MASK 0x0000000f
1862 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_GET(x) (((x) & 0x0000000f) >> 0)
1863 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_SET(x) (((x) << 0) & 0x0000000f)
1864 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_MSB 7
1865 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_LSB 4
1866 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_MASK 0x000000f0
1867 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_GET(x) (((x) & 0x000000f0) >> 4)
1868 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_SET(x) (((x) << 4) & 0x000000f0)
1869 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_MSB 11
1870 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_LSB 8
1871 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_MASK 0x00000f00
1872 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_GET(x) (((x) & 0x00000f00) >> 8)
1873 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_SET(x) (((x) << 8) & 0x00000f00)
1874 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_MSB 15
1875 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_LSB 12
1876 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_MASK 0x0000f000
1877 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_GET(x) (((x) & 0x0000f000) >> 12)
1878 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_SET(x) (((x) << 12) & 0x0000f000)
1879 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_MSB 19
1880 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_LSB 16
1881 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_MASK 0x000f0000
1882 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_GET(x) (((x) & 0x000f0000) >> 16)
1883 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_SET(x) (((x) << 16) & 0x000f0000)
1884 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_MSB 23
1885 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_LSB 20
1886 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_MASK 0x00f00000
1887 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_GET(x) (((x) & 0x00f00000) >> 20)
1888 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_SET(x) (((x) << 20) & 0x00f00000)
1889 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_MSB 27
1890 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_LSB 24
1891 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_MASK 0x0f000000
1892 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_GET(x) (((x) & 0x0f000000) >> 24)
1893 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_SET(x) (((x) << 24) & 0x0f000000)
1894 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_MSB 31
1895 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_LSB 28
1896 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_MASK 0xf0000000
1897 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_GET(x) (((x) & 0xf0000000) >> 28)
1898 #define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_SET(x) (((x) << 28) & 0xf0000000)
1900 /* macros for BB_restart */
1901 #define PHY_BB_RESTART_ADDRESS 0x00009970
1902 #define PHY_BB_RESTART_OFFSET 0x00009970
1903 #define PHY_BB_RESTART_ENABLE_RESTART_MSB 0
1904 #define PHY_BB_RESTART_ENABLE_RESTART_LSB 0
1905 #define PHY_BB_RESTART_ENABLE_RESTART_MASK 0x00000001
1906 #define PHY_BB_RESTART_ENABLE_RESTART_GET(x) (((x) & 0x00000001) >> 0)
1907 #define PHY_BB_RESTART_ENABLE_RESTART_SET(x) (((x) << 0) & 0x00000001)
1908 #define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_MSB 5
1909 #define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_LSB 1
1910 #define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_MASK 0x0000003e
1911 #define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_GET(x) (((x) & 0x0000003e) >> 1)
1912 #define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_SET(x) (((x) << 1) & 0x0000003e)
1913 #define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_MSB 6
1914 #define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_LSB 6
1915 #define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_MASK 0x00000040
1916 #define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_GET(x) (((x) & 0x00000040) >> 6)
1917 #define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_SET(x) (((x) << 6) & 0x00000040)
1918 #define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_MSB 11
1919 #define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_LSB 7
1920 #define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_MASK 0x00000f80
1921 #define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_GET(x) (((x) & 0x00000f80) >> 7)
1922 #define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_SET(x) (((x) << 7) & 0x00000f80)
1923 #define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_MSB 17
1924 #define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_LSB 12
1925 #define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_MASK 0x0003f000
1926 #define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_GET(x) (((x) & 0x0003f000) >> 12)
1927 #define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_SET(x) (((x) << 12) & 0x0003f000)
1928 #define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_MSB 20
1929 #define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_LSB 18
1930 #define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_MASK 0x001c0000
1931 #define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_GET(x) (((x) & 0x001c0000) >> 18)
1932 #define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_SET(x) (((x) << 18) & 0x001c0000)
1933 #define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_MSB 21
1934 #define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_LSB 21
1935 #define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_MASK 0x00200000
1936 #define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_GET(x) (((x) & 0x00200000) >> 21)
1937 #define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_SET(x) (((x) << 21) & 0x00200000)
1938 #define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_MSB 28
1939 #define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_LSB 22
1940 #define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_MASK 0x1fc00000
1941 #define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_GET(x) (((x) & 0x1fc00000) >> 22)
1942 #define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_SET(x) (((x) << 22) & 0x1fc00000)
1943 #define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_MSB 29
1944 #define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_LSB 29
1945 #define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_MASK 0x20000000
1946 #define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_GET(x) (((x) & 0x20000000) >> 29)
1947 #define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_SET(x) (((x) << 29) & 0x20000000)
1948 #define PHY_BB_RESTART_DISABLE_DC_RESTART_MSB 30
1949 #define PHY_BB_RESTART_DISABLE_DC_RESTART_LSB 30
1950 #define PHY_BB_RESTART_DISABLE_DC_RESTART_MASK 0x40000000
1951 #define PHY_BB_RESTART_DISABLE_DC_RESTART_GET(x) (((x) & 0x40000000) >> 30)
1952 #define PHY_BB_RESTART_DISABLE_DC_RESTART_SET(x) (((x) << 30) & 0x40000000)
1953 #define PHY_BB_RESTART_RESTART_MODE_BW40_MSB 31
1954 #define PHY_BB_RESTART_RESTART_MODE_BW40_LSB 31
1955 #define PHY_BB_RESTART_RESTART_MODE_BW40_MASK 0x80000000
1956 #define PHY_BB_RESTART_RESTART_MODE_BW40_GET(x) (((x) & 0x80000000) >> 31)
1957 #define PHY_BB_RESTART_RESTART_MODE_BW40_SET(x) (((x) << 31) & 0x80000000)
1959 /* macros for BB_scrambler_seed */
1960 #define PHY_BB_SCRAMBLER_SEED_ADDRESS 0x00009978
1961 #define PHY_BB_SCRAMBLER_SEED_OFFSET 0x00009978
1962 #define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MSB 6
1963 #define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_LSB 0
1964 #define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MASK 0x0000007f
1965 #define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_GET(x) (((x) & 0x0000007f) >> 0)
1966 #define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_SET(x) (((x) << 0) & 0x0000007f)
1968 /* macros for BB_rfbus_request */
1969 #define PHY_BB_RFBUS_REQUEST_ADDRESS 0x0000997c
1970 #define PHY_BB_RFBUS_REQUEST_OFFSET 0x0000997c
1971 #define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MSB 0
1972 #define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_LSB 0
1973 #define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MASK 0x00000001
1974 #define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_GET(x) (((x) & 0x00000001) >> 0)
1975 #define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_SET(x) (((x) << 0) & 0x00000001)
1977 /* macros for BB_timing_control_11 */
1978 #define PHY_BB_TIMING_CONTROL_11_ADDRESS 0x000099a0
1979 #define PHY_BB_TIMING_CONTROL_11_OFFSET 0x000099a0
1980 #define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_MSB 19
1981 #define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_LSB 0
1982 #define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_MASK 0x000fffff
1983 #define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_GET(x) (((x) & 0x000fffff) >> 0)
1984 #define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_SET(x) (((x) << 0) & 0x000fffff)
1985 #define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MSB 29
1986 #define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_LSB 20
1987 #define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MASK 0x3ff00000
1988 #define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_GET(x) (((x) & 0x3ff00000) >> 20)
1989 #define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_SET(x) (((x) << 20) & 0x3ff00000)
1990 #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MSB 30
1991 #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_LSB 30
1992 #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MASK 0x40000000
1993 #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_GET(x) (((x) & 0x40000000) >> 30)
1994 #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_SET(x) (((x) << 30) & 0x40000000)
1995 #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MSB 31
1996 #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_LSB 31
1997 #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MASK 0x80000000
1998 #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_GET(x) (((x) & 0x80000000) >> 31)
1999 #define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_SET(x) (((x) << 31) & 0x80000000)
2001 /* macros for BB_multichain_enable */
2002 #define PHY_BB_MULTICHAIN_ENABLE_ADDRESS 0x000099a4
2003 #define PHY_BB_MULTICHAIN_ENABLE_OFFSET 0x000099a4
2004 #define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MSB 2
2005 #define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_LSB 0
2006 #define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK 0x00000007
2007 #define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_GET(x) (((x) & 0x00000007) >> 0)
2008 #define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_SET(x) (((x) << 0) & 0x00000007)
2010 /* macros for BB_multichain_control */
2011 #define PHY_BB_MULTICHAIN_CONTROL_ADDRESS 0x000099a8
2012 #define PHY_BB_MULTICHAIN_CONTROL_OFFSET 0x000099a8
2013 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MSB 0
2014 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_LSB 0
2015 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MASK 0x00000001
2016 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_GET(x) (((x) & 0x00000001) >> 0)
2017 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_SET(x) (((x) << 0) & 0x00000001)
2018 #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MSB 7
2019 #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_LSB 1
2020 #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MASK 0x000000fe
2021 #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_GET(x) (((x) & 0x000000fe) >> 1)
2022 #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_SET(x) (((x) << 1) & 0x000000fe)
2023 #define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MSB 8
2024 #define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_LSB 8
2025 #define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MASK 0x00000100
2026 #define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_GET(x) (((x) & 0x00000100) >> 8)
2027 #define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_SET(x) (((x) << 8) & 0x00000100)
2028 #define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MSB 9
2029 #define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_LSB 9
2030 #define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MASK 0x00000200
2031 #define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_GET(x) (((x) & 0x00000200) >> 9)
2032 #define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_SET(x) (((x) << 9) & 0x00000200)
2033 #define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MSB 20
2034 #define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_LSB 10
2035 #define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MASK 0x001ffc00
2036 #define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_GET(x) (((x) & 0x001ffc00) >> 10)
2037 #define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_SET(x) (((x) << 10) & 0x001ffc00)
2038 #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MSB 28
2039 #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_LSB 22
2040 #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MASK 0x1fc00000
2041 #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_GET(x) (((x) & 0x1fc00000) >> 22)
2042 #define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_SET(x) (((x) << 22) & 0x1fc00000)
2043 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MSB 29
2044 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_LSB 29
2045 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MASK 0x20000000
2046 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_GET(x) (((x) & 0x20000000) >> 29)
2047 #define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_SET(x) (((x) << 29) & 0x20000000)
2049 /* macros for BB_multichain_gain_ctrl */
2050 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ADDRESS 0x000099ac
2051 #define PHY_BB_MULTICHAIN_GAIN_CTRL_OFFSET 0x000099ac
2052 #define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_MSB 7
2053 #define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_LSB 0
2054 #define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_MASK 0x000000ff
2055 #define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_GET(x) (((x) & 0x000000ff) >> 0)
2056 #define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_SET(x) (((x) << 0) & 0x000000ff)
2057 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_MSB 8
2058 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_LSB 8
2059 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_MASK 0x00000100
2060 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_GET(x) (((x) & 0x00000100) >> 8)
2061 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_SET(x) (((x) << 8) & 0x00000100)
2062 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_MSB 14
2063 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_LSB 9
2064 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_MASK 0x00007e00
2065 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_GET(x) (((x) & 0x00007e00) >> 9)
2066 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_SET(x) (((x) << 9) & 0x00007e00)
2067 #define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_MSB 20
2068 #define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_LSB 15
2069 #define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_MASK 0x001f8000
2070 #define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_GET(x) (((x) & 0x001f8000) >> 15)
2071 #define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_SET(x) (((x) << 15) & 0x001f8000)
2072 #define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_MSB 21
2073 #define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_LSB 21
2074 #define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_MASK 0x00200000
2075 #define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_GET(x) (((x) & 0x00200000) >> 21)
2076 #define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_SET(x) (((x) << 21) & 0x00200000)
2077 #define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_MSB 22
2078 #define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_LSB 22
2079 #define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_MASK 0x00400000
2080 #define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_GET(x) (((x) & 0x00400000) >> 22)
2081 #define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_SET(x) (((x) << 22) & 0x00400000)
2082 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_MSB 23
2083 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_LSB 23
2084 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_MASK 0x00800000
2085 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_GET(x) (((x) & 0x00800000) >> 23)
2086 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_SET(x) (((x) << 23) & 0x00800000)
2087 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_MSB 24
2088 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_LSB 24
2089 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_MASK 0x01000000
2090 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_GET(x) (((x) & 0x01000000) >> 24)
2091 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_SET(x) (((x) << 24) & 0x01000000)
2092 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_MSB 26
2093 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_LSB 25
2094 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_MASK 0x06000000
2095 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_GET(x) (((x) & 0x06000000) >> 25)
2096 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_SET(x) (((x) << 25) & 0x06000000)
2097 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_MSB 28
2098 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_LSB 27
2099 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_MASK 0x18000000
2100 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_GET(x) (((x) & 0x18000000) >> 27)
2101 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_SET(x) (((x) << 27) & 0x18000000)
2102 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_MSB 29
2103 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_LSB 29
2104 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_MASK 0x20000000
2105 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_GET(x) (((x) & 0x20000000) >> 29)
2106 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_SET(x) (((x) << 29) & 0x20000000)
2107 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_MSB 30
2108 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_LSB 30
2109 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_MASK 0x40000000
2110 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_GET(x) (((x) & 0x40000000) >> 30)
2111 #define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_SET(x) (((x) << 30) & 0x40000000)
2113 /* macros for BB_adc_gain_dc_corr_b0 */
2114 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADDRESS 0x000099b4
2115 #define PHY_BB_ADC_GAIN_DC_CORR_B0_OFFSET 0x000099b4
2116 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MSB 5
2117 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_LSB 0
2118 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MASK 0x0000003f
2119 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_GET(x) (((x) & 0x0000003f) >> 0)
2120 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_SET(x) (((x) << 0) & 0x0000003f)
2121 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MSB 11
2122 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_LSB 6
2123 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MASK 0x00000fc0
2124 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_GET(x) (((x) & 0x00000fc0) >> 6)
2125 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_SET(x) (((x) << 6) & 0x00000fc0)
2126 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MSB 20
2127 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_LSB 12
2128 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MASK 0x001ff000
2129 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_GET(x) (((x) & 0x001ff000) >> 12)
2130 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_SET(x) (((x) << 12) & 0x001ff000)
2131 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MSB 29
2132 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_LSB 21
2133 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MASK 0x3fe00000
2134 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_GET(x) (((x) & 0x3fe00000) >> 21)
2135 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_SET(x) (((x) << 21) & 0x3fe00000)
2136 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_MSB 30
2137 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_LSB 30
2138 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_MASK 0x40000000
2139 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_GET(x) (((x) & 0x40000000) >> 30)
2140 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_SET(x) (((x) << 30) & 0x40000000)
2141 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_MSB 31
2142 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_LSB 31
2143 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_MASK 0x80000000
2144 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_GET(x) (((x) & 0x80000000) >> 31)
2145 #define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_SET(x) (((x) << 31) & 0x80000000)
2147 /* macros for BB_ext_chan_pwr_thr_1 */
2148 #define PHY_BB_EXT_CHAN_PWR_THR_1_ADDRESS 0x000099b8
2149 #define PHY_BB_EXT_CHAN_PWR_THR_1_OFFSET 0x000099b8
2150 #define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_MSB 7
2151 #define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_LSB 0
2152 #define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_MASK 0x000000ff
2153 #define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_GET(x) (((x) & 0x000000ff) >> 0)
2154 #define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_SET(x) (((x) << 0) & 0x000000ff)
2155 #define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_MSB 15
2156 #define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_LSB 8
2157 #define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_MASK 0x0000ff00
2158 #define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_GET(x) (((x) & 0x0000ff00) >> 8)
2159 #define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_SET(x) (((x) << 8) & 0x0000ff00)
2160 #define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_MSB 20
2161 #define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_LSB 16
2162 #define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_MASK 0x001f0000
2163 #define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_GET(x) (((x) & 0x001f0000) >> 16)
2164 #define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_SET(x) (((x) << 16) & 0x001f0000)
2165 #define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_MSB 26
2166 #define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_LSB 21
2167 #define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_MASK 0x07e00000
2168 #define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_GET(x) (((x) & 0x07e00000) >> 21)
2169 #define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_SET(x) (((x) << 21) & 0x07e00000)
2171 /* macros for BB_ext_chan_pwr_thr_2_b0 */
2172 #define PHY_BB_EXT_CHAN_PWR_THR_2_B0_ADDRESS 0x000099bc
2173 #define PHY_BB_EXT_CHAN_PWR_THR_2_B0_OFFSET 0x000099bc
2174 #define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_MSB 8
2175 #define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_LSB 0
2176 #define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_MASK 0x000001ff
2177 #define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_GET(x) (((x) & 0x000001ff) >> 0)
2178 #define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_SET(x) (((x) << 0) & 0x000001ff)
2179 #define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_MSB 15
2180 #define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_LSB 9
2181 #define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_MASK 0x0000fe00
2182 #define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_GET(x) (((x) & 0x0000fe00) >> 9)
2183 #define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_SET(x) (((x) << 9) & 0x0000fe00)
2184 #define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_MSB 24
2185 #define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_LSB 16
2186 #define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_MASK 0x01ff0000
2187 #define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_GET(x) (((x) & 0x01ff0000) >> 16)
2189 /* macros for BB_ext_chan_scorr_thr */
2190 #define PHY_BB_EXT_CHAN_SCORR_THR_ADDRESS 0x000099c0
2191 #define PHY_BB_EXT_CHAN_SCORR_THR_OFFSET 0x000099c0
2192 #define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_MSB 6
2193 #define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_LSB 0
2194 #define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_MASK 0x0000007f
2195 #define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_GET(x) (((x) & 0x0000007f) >> 0)
2196 #define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_SET(x) (((x) << 0) & 0x0000007f)
2197 #define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_MSB 13
2198 #define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_LSB 7
2199 #define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_MASK 0x00003f80
2200 #define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_GET(x) (((x) & 0x00003f80) >> 7)
2201 #define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_SET(x) (((x) << 7) & 0x00003f80)
2202 #define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_MSB 20
2203 #define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_LSB 14
2204 #define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_MASK 0x001fc000
2205 #define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_GET(x) (((x) & 0x001fc000) >> 14)
2206 #define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_SET(x) (((x) << 14) & 0x001fc000)
2207 #define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_MSB 27
2208 #define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_LSB 21
2209 #define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_MASK 0x0fe00000
2210 #define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_GET(x) (((x) & 0x0fe00000) >> 21)
2211 #define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_SET(x) (((x) << 21) & 0x0fe00000)
2212 #define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_MSB 28
2213 #define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_LSB 28
2214 #define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_MASK 0x10000000
2215 #define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_GET(x) (((x) & 0x10000000) >> 28)
2216 #define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_SET(x) (((x) << 28) & 0x10000000)
2218 /* macros for BB_ext_chan_detect_win */
2219 #define PHY_BB_EXT_CHAN_DETECT_WIN_ADDRESS 0x000099c4
2220 #define PHY_BB_EXT_CHAN_DETECT_WIN_OFFSET 0x000099c4
2221 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_MSB 3
2222 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LSB 0
2223 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_MASK 0x0000000f
2224 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_GET(x) (((x) & 0x0000000f) >> 0)
2225 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_SET(x) (((x) << 0) & 0x0000000f)
2226 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_MSB 7
2227 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_LSB 4
2228 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_MASK 0x000000f0
2229 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_GET(x) (((x) & 0x000000f0) >> 4)
2230 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_SET(x) (((x) << 4) & 0x000000f0)
2231 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_MSB 12
2232 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_LSB 8
2233 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_MASK 0x00001f00
2234 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_GET(x) (((x) & 0x00001f00) >> 8)
2235 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_SET(x) (((x) << 8) & 0x00001f00)
2236 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_MSB 15
2237 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_LSB 13
2238 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_MASK 0x0000e000
2239 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_GET(x) (((x) & 0x0000e000) >> 13)
2240 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_SET(x) (((x) << 13) & 0x0000e000)
2241 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_MSB 18
2242 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_LSB 16
2243 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_MASK 0x00070000
2244 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_GET(x) (((x) & 0x00070000) >> 16)
2245 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_SET(x) (((x) << 16) & 0x00070000)
2246 #define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_MSB 24
2247 #define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_LSB 19
2248 #define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_MASK 0x01f80000
2249 #define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_GET(x) (((x) & 0x01f80000) >> 19)
2250 #define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_SET(x) (((x) << 19) & 0x01f80000)
2251 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_MSB 28
2252 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_LSB 25
2253 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_MASK 0x1e000000
2254 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_GET(x) (((x) & 0x1e000000) >> 25)
2255 #define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_SET(x) (((x) << 25) & 0x1e000000)
2257 /* macros for BB_pwr_thr_20_40_det */
2258 #define PHY_BB_PWR_THR_20_40_DET_ADDRESS 0x000099c8
2259 #define PHY_BB_PWR_THR_20_40_DET_OFFSET 0x000099c8
2260 #define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_MSB 4
2261 #define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_LSB 0
2262 #define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_MASK 0x0000001f
2263 #define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_GET(x) (((x) & 0x0000001f) >> 0)
2264 #define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_SET(x) (((x) << 0) & 0x0000001f)
2265 #define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_MSB 10
2266 #define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_LSB 5
2267 #define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_MASK 0x000007e0
2268 #define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_GET(x) (((x) & 0x000007e0) >> 5)
2269 #define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_SET(x) (((x) << 5) & 0x000007e0)
2270 #define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_MSB 15
2271 #define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_LSB 11
2272 #define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_MASK 0x0000f800
2273 #define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_GET(x) (((x) & 0x0000f800) >> 11)
2274 #define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_SET(x) (((x) << 11) & 0x0000f800)
2275 #define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_MSB 23
2276 #define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_LSB 16
2277 #define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_MASK 0x00ff0000
2278 #define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_GET(x) (((x) & 0x00ff0000) >> 16)
2279 #define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_SET(x) (((x) << 16) & 0x00ff0000)
2280 #define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_MSB 28
2281 #define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_LSB 24
2282 #define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_MASK 0x1f000000
2283 #define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_GET(x) (((x) & 0x1f000000) >> 24)
2284 #define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_SET(x) (((x) << 24) & 0x1f000000)
2285 #define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_MSB 29
2286 #define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_LSB 29
2287 #define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_MASK 0x20000000
2288 #define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_GET(x) (((x) & 0x20000000) >> 29)
2289 #define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_SET(x) (((x) << 29) & 0x20000000)
2290 #define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_MSB 30
2291 #define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_LSB 30
2292 #define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_MASK 0x40000000
2293 #define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_GET(x) (((x) & 0x40000000) >> 30)
2294 #define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_SET(x) (((x) << 30) & 0x40000000)
2296 /* macros for BB_short_gi_delta_slope */
2297 #define PHY_BB_SHORT_GI_DELTA_SLOPE_ADDRESS 0x000099d0
2298 #define PHY_BB_SHORT_GI_DELTA_SLOPE_OFFSET 0x000099d0
2299 #define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_MSB 3
2300 #define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_LSB 0
2301 #define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_MASK 0x0000000f
2302 #define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_GET(x) (((x) & 0x0000000f) >> 0)
2303 #define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_SET(x) (((x) << 0) & 0x0000000f)
2304 #define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_MSB 18
2305 #define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_LSB 4
2306 #define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_MASK 0x0007fff0
2307 #define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_GET(x) (((x) & 0x0007fff0) >> 4)
2308 #define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_SET(x) (((x) << 4) & 0x0007fff0)
2310 /* macros for BB_chaninfo_ctrl */
2311 #define PHY_BB_CHANINFO_CTRL_ADDRESS 0x000099dc
2312 #define PHY_BB_CHANINFO_CTRL_OFFSET 0x000099dc
2313 #define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MSB 0
2314 #define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_LSB 0
2315 #define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MASK 0x00000001
2316 #define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_GET(x) (((x) & 0x00000001) >> 0)
2317 #define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_SET(x) (((x) << 0) & 0x00000001)
2318 #define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MSB 1
2319 #define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_LSB 1
2320 #define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MASK 0x00000002
2321 #define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_GET(x) (((x) & 0x00000002) >> 1)
2322 #define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_SET(x) (((x) << 1) & 0x00000002)
2324 /* macros for BB_heavy_clip_ctrl */
2325 #define PHY_BB_HEAVY_CLIP_CTRL_ADDRESS 0x000099e0
2326 #define PHY_BB_HEAVY_CLIP_CTRL_OFFSET 0x000099e0
2327 #define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_MSB 8
2328 #define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_LSB 0
2329 #define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_MASK 0x000001ff
2330 #define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_GET(x) (((x) & 0x000001ff) >> 0)
2331 #define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_SET(x) (((x) << 0) & 0x000001ff)
2332 #define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_MSB 9
2333 #define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_LSB 9
2334 #define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_MASK 0x00000200
2335 #define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_GET(x) (((x) & 0x00000200) >> 9)
2336 #define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_SET(x) (((x) << 9) & 0x00000200)
2338 /* macros for BB_heavy_clip_20 */
2339 #define PHY_BB_HEAVY_CLIP_20_ADDRESS 0x000099e4
2340 #define PHY_BB_HEAVY_CLIP_20_OFFSET 0x000099e4
2341 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_MSB 7
2342 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_LSB 0
2343 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_MASK 0x000000ff
2344 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_GET(x) (((x) & 0x000000ff) >> 0)
2345 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_SET(x) (((x) << 0) & 0x000000ff)
2346 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_MSB 15
2347 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_LSB 8
2348 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_MASK 0x0000ff00
2349 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_GET(x) (((x) & 0x0000ff00) >> 8)
2350 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_SET(x) (((x) << 8) & 0x0000ff00)
2351 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_MSB 23
2352 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_LSB 16
2353 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_MASK 0x00ff0000
2354 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_GET(x) (((x) & 0x00ff0000) >> 16)
2355 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_SET(x) (((x) << 16) & 0x00ff0000)
2356 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_MSB 31
2357 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_LSB 24
2358 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_MASK 0xff000000
2359 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_GET(x) (((x) & 0xff000000) >> 24)
2360 #define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_SET(x) (((x) << 24) & 0xff000000)
2362 /* macros for BB_heavy_clip_40 */
2363 #define PHY_BB_HEAVY_CLIP_40_ADDRESS 0x000099e8
2364 #define PHY_BB_HEAVY_CLIP_40_OFFSET 0x000099e8
2365 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_MSB 7
2366 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_LSB 0
2367 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_MASK 0x000000ff
2368 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_GET(x) (((x) & 0x000000ff) >> 0)
2369 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_SET(x) (((x) << 0) & 0x000000ff)
2370 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_MSB 15
2371 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_LSB 8
2372 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_MASK 0x0000ff00
2373 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_GET(x) (((x) & 0x0000ff00) >> 8)
2374 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_SET(x) (((x) << 8) & 0x0000ff00)
2375 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_MSB 23
2376 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_LSB 16
2377 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_MASK 0x00ff0000
2378 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_GET(x) (((x) & 0x00ff0000) >> 16)
2379 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_SET(x) (((x) << 16) & 0x00ff0000)
2380 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_MSB 31
2381 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_LSB 24
2382 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_MASK 0xff000000
2383 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_GET(x) (((x) & 0xff000000) >> 24)
2384 #define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_SET(x) (((x) << 24) & 0xff000000)
2386 /* macros for BB_rifs_srch */
2387 #define PHY_BB_RIFS_SRCH_ADDRESS 0x000099ec
2388 #define PHY_BB_RIFS_SRCH_OFFSET 0x000099ec
2389 #define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_MSB 7
2390 #define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_LSB 0
2391 #define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_MASK 0x000000ff
2392 #define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_GET(x) (((x) & 0x000000ff) >> 0)
2393 #define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_SET(x) (((x) << 0) & 0x000000ff)
2394 #define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_MSB 15
2395 #define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_LSB 8
2396 #define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_MASK 0x0000ff00
2397 #define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_GET(x) (((x) & 0x0000ff00) >> 8)
2398 #define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_SET(x) (((x) << 8) & 0x0000ff00)
2399 #define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_MSB 25
2400 #define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_LSB 16
2401 #define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_MASK 0x03ff0000
2402 #define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_GET(x) (((x) & 0x03ff0000) >> 16)
2403 #define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_SET(x) (((x) << 16) & 0x03ff0000)
2404 #define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_MSB 26
2405 #define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_LSB 26
2406 #define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_MASK 0x04000000
2407 #define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_GET(x) (((x) & 0x04000000) >> 26)
2408 #define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_SET(x) (((x) << 26) & 0x04000000)
2409 #define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_MSB 27
2410 #define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_LSB 27
2411 #define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_MASK 0x08000000
2412 #define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_GET(x) (((x) & 0x08000000) >> 27)
2413 #define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_SET(x) (((x) << 27) & 0x08000000)
2415 /* macros for BB_iq_adc_cal_mode */
2416 #define PHY_BB_IQ_ADC_CAL_MODE_ADDRESS 0x000099f0
2417 #define PHY_BB_IQ_ADC_CAL_MODE_OFFSET 0x000099f0
2418 #define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MSB 1
2419 #define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_LSB 0
2420 #define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MASK 0x00000003
2421 #define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_GET(x) (((x) & 0x00000003) >> 0)
2422 #define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_SET(x) (((x) << 0) & 0x00000003)
2423 #define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MSB 2
2424 #define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_LSB 2
2425 #define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MASK 0x00000004
2426 #define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_GET(x) (((x) & 0x00000004) >> 2)
2427 #define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_SET(x) (((x) << 2) & 0x00000004)
2429 /* macros for BB_per_chain_csd */
2430 #define PHY_BB_PER_CHAIN_CSD_ADDRESS 0x000099fc
2431 #define PHY_BB_PER_CHAIN_CSD_OFFSET 0x000099fc
2432 #define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_MSB 4
2433 #define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_LSB 0
2434 #define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_MASK 0x0000001f
2435 #define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_GET(x) (((x) & 0x0000001f) >> 0)
2436 #define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_SET(x) (((x) << 0) & 0x0000001f)
2437 #define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_MSB 9
2438 #define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_LSB 5
2439 #define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_MASK 0x000003e0
2440 #define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_GET(x) (((x) & 0x000003e0) >> 5)
2441 #define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_SET(x) (((x) << 5) & 0x000003e0)
2442 #define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_MSB 14
2443 #define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_LSB 10
2444 #define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_MASK 0x00007c00
2445 #define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_GET(x) (((x) & 0x00007c00) >> 10)
2446 #define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_SET(x) (((x) << 10) & 0x00007c00)
2448 /* macros for BB_rx_ocgain */
2449 #define PHY_BB_RX_OCGAIN_ADDRESS 0x00009a00
2450 #define PHY_BB_RX_OCGAIN_OFFSET 0x00009a00
2451 #define PHY_BB_RX_OCGAIN_GAIN_ENTRY_MSB 31
2452 #define PHY_BB_RX_OCGAIN_GAIN_ENTRY_LSB 0
2453 #define PHY_BB_RX_OCGAIN_GAIN_ENTRY_MASK 0xffffffff
2454 #define PHY_BB_RX_OCGAIN_GAIN_ENTRY_SET(x) (((x) << 0) & 0xffffffff)
2456 /* macros for BB_tx_crc */
2457 #define PHY_BB_TX_CRC_ADDRESS 0x00009c00
2458 #define PHY_BB_TX_CRC_OFFSET 0x00009c00
2459 #define PHY_BB_TX_CRC_TX_CRC_MSB 15
2460 #define PHY_BB_TX_CRC_TX_CRC_LSB 0
2461 #define PHY_BB_TX_CRC_TX_CRC_MASK 0x0000ffff
2462 #define PHY_BB_TX_CRC_TX_CRC_GET(x) (((x) & 0x0000ffff) >> 0)
2464 /* macros for BB_iq_adc_meas_0_b0 */
2465 #define PHY_BB_IQ_ADC_MEAS_0_B0_ADDRESS 0x00009c10
2466 #define PHY_BB_IQ_ADC_MEAS_0_B0_OFFSET 0x00009c10
2467 #define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MSB 31
2468 #define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_LSB 0
2469 #define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MASK 0xffffffff
2470 #define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_GET(x) (((x) & 0xffffffff) >> 0)
2472 /* macros for BB_iq_adc_meas_1_b0 */
2473 #define PHY_BB_IQ_ADC_MEAS_1_B0_ADDRESS 0x00009c14
2474 #define PHY_BB_IQ_ADC_MEAS_1_B0_OFFSET 0x00009c14
2475 #define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MSB 31
2476 #define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_LSB 0
2477 #define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MASK 0xffffffff
2478 #define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_GET(x) (((x) & 0xffffffff) >> 0)
2480 /* macros for BB_iq_adc_meas_2_b0 */
2481 #define PHY_BB_IQ_ADC_MEAS_2_B0_ADDRESS 0x00009c18
2482 #define PHY_BB_IQ_ADC_MEAS_2_B0_OFFSET 0x00009c18
2483 #define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MSB 31
2484 #define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_LSB 0
2485 #define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MASK 0xffffffff
2486 #define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_GET(x) (((x) & 0xffffffff) >> 0)
2488 /* macros for BB_iq_adc_meas_3_b0 */
2489 #define PHY_BB_IQ_ADC_MEAS_3_B0_ADDRESS 0x00009c1c
2490 #define PHY_BB_IQ_ADC_MEAS_3_B0_OFFSET 0x00009c1c
2491 #define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MSB 31
2492 #define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_LSB 0
2493 #define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MASK 0xffffffff
2494 #define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_GET(x) (((x) & 0xffffffff) >> 0)
2496 /* macros for BB_rfbus_grant */
2497 #define PHY_BB_RFBUS_GRANT_ADDRESS 0x00009c20
2498 #define PHY_BB_RFBUS_GRANT_OFFSET 0x00009c20
2499 #define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MSB 0
2500 #define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_LSB 0
2501 #define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MASK 0x00000001
2502 #define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_GET(x) (((x) & 0x00000001) >> 0)
2503 #define PHY_BB_RFBUS_GRANT_BT_ANT_MSB 1
2504 #define PHY_BB_RFBUS_GRANT_BT_ANT_LSB 1
2505 #define PHY_BB_RFBUS_GRANT_BT_ANT_MASK 0x00000002
2506 #define PHY_BB_RFBUS_GRANT_BT_ANT_GET(x) (((x) & 0x00000002) >> 1)
2508 /* macros for BB_tstadc */
2509 #define PHY_BB_TSTADC_ADDRESS 0x00009c24
2510 #define PHY_BB_TSTADC_OFFSET 0x00009c24
2511 #define PHY_BB_TSTADC_TSTADC_OUT_Q_MSB 9
2512 #define PHY_BB_TSTADC_TSTADC_OUT_Q_LSB 0
2513 #define PHY_BB_TSTADC_TSTADC_OUT_Q_MASK 0x000003ff
2514 #define PHY_BB_TSTADC_TSTADC_OUT_Q_GET(x) (((x) & 0x000003ff) >> 0)
2515 #define PHY_BB_TSTADC_TSTADC_OUT_I_MSB 19
2516 #define PHY_BB_TSTADC_TSTADC_OUT_I_LSB 10
2517 #define PHY_BB_TSTADC_TSTADC_OUT_I_MASK 0x000ffc00
2518 #define PHY_BB_TSTADC_TSTADC_OUT_I_GET(x) (((x) & 0x000ffc00) >> 10)
2520 /* macros for BB_tstdac */
2521 #define PHY_BB_TSTDAC_ADDRESS 0x00009c28
2522 #define PHY_BB_TSTDAC_OFFSET 0x00009c28
2523 #define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MSB 9
2524 #define PHY_BB_TSTDAC_TSTDAC_OUT_Q_LSB 0
2525 #define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MASK 0x000003ff
2526 #define PHY_BB_TSTDAC_TSTDAC_OUT_Q_GET(x) (((x) & 0x000003ff) >> 0)
2527 #define PHY_BB_TSTDAC_TSTDAC_OUT_I_MSB 19
2528 #define PHY_BB_TSTDAC_TSTDAC_OUT_I_LSB 10
2529 #define PHY_BB_TSTDAC_TSTDAC_OUT_I_MASK 0x000ffc00
2530 #define PHY_BB_TSTDAC_TSTDAC_OUT_I_GET(x) (((x) & 0x000ffc00) >> 10)
2532 /* macros for BB_illegal_tx_rate */
2533 #define PHY_BB_ILLEGAL_TX_RATE_ADDRESS 0x00009c30
2534 #define PHY_BB_ILLEGAL_TX_RATE_OFFSET 0x00009c30
2535 #define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_MSB 0
2536 #define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_LSB 0
2537 #define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_MASK 0x00000001
2538 #define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_GET(x) (((x) & 0x00000001) >> 0)
2540 /* macros for BB_spur_report_b0 */
2541 #define PHY_BB_SPUR_REPORT_B0_ADDRESS 0x00009c34
2542 #define PHY_BB_SPUR_REPORT_B0_OFFSET 0x00009c34
2543 #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MSB 7
2544 #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_LSB 0
2545 #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MASK 0x000000ff
2546 #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_GET(x) (((x) & 0x000000ff) >> 0)
2547 #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MSB 15
2548 #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_LSB 8
2549 #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MASK 0x0000ff00
2550 #define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_GET(x) (((x) & 0x0000ff00) >> 8)
2551 #define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MSB 31
2552 #define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_LSB 16
2553 #define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MASK 0xffff0000
2554 #define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_GET(x) (((x) & 0xffff0000) >> 16)
2556 /* macros for BB_channel_status */
2557 #define PHY_BB_CHANNEL_STATUS_ADDRESS 0x00009c38
2558 #define PHY_BB_CHANNEL_STATUS_OFFSET 0x00009c38
2559 #define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MSB 0
2560 #define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_LSB 0
2561 #define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MASK 0x00000001
2562 #define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_GET(x) (((x) & 0x00000001) >> 0)
2563 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MSB 1
2564 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_LSB 1
2565 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MASK 0x00000002
2566 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_GET(x) (((x) & 0x00000002) >> 1)
2567 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MSB 2
2568 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_LSB 2
2569 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MASK 0x00000004
2570 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_GET(x) (((x) & 0x00000004) >> 2)
2571 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MSB 3
2572 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_LSB 3
2573 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MASK 0x00000008
2574 #define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_GET(x) (((x) & 0x00000008) >> 3)
2575 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MSB 5
2576 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_LSB 4
2577 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MASK 0x00000030
2578 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_GET(x) (((x) & 0x00000030) >> 4)
2579 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MSB 7
2580 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_LSB 6
2581 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MASK 0x000000c0
2582 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_GET(x) (((x) & 0x000000c0) >> 6)
2583 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MSB 9
2584 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_LSB 8
2585 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MASK 0x00000300
2586 #define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_GET(x) (((x) & 0x00000300) >> 8)
2587 #define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MSB 13
2588 #define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_LSB 10
2589 #define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MASK 0x00003c00
2590 #define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_GET(x) (((x) & 0x00003c00) >> 10)
2591 #define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MSB 16
2592 #define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_LSB 14
2593 #define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MASK 0x0001c000
2594 #define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_GET(x) (((x) & 0x0001c000) >> 14)
2596 /* macros for BB_rssi_b0 */
2597 #define PHY_BB_RSSI_B0_ADDRESS 0x00009c3c
2598 #define PHY_BB_RSSI_B0_OFFSET 0x00009c3c
2599 #define PHY_BB_RSSI_B0_RSSI_0_MSB 7
2600 #define PHY_BB_RSSI_B0_RSSI_0_LSB 0
2601 #define PHY_BB_RSSI_B0_RSSI_0_MASK 0x000000ff
2602 #define PHY_BB_RSSI_B0_RSSI_0_GET(x) (((x) & 0x000000ff) >> 0)
2603 #define PHY_BB_RSSI_B0_RSSI_EXT_0_MSB 15
2604 #define PHY_BB_RSSI_B0_RSSI_EXT_0_LSB 8
2605 #define PHY_BB_RSSI_B0_RSSI_EXT_0_MASK 0x0000ff00
2606 #define PHY_BB_RSSI_B0_RSSI_EXT_0_GET(x) (((x) & 0x0000ff00) >> 8)
2608 /* macros for BB_spur_est_cck_report_b0 */
2609 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_ADDRESS 0x00009c40
2610 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_OFFSET 0x00009c40
2611 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_MSB 7
2612 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_LSB 0
2613 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_MASK 0x000000ff
2614 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_GET(x) (((x) & 0x000000ff) >> 0)
2615 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_MSB 15
2616 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_LSB 8
2617 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_MASK 0x0000ff00
2618 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_GET(x) (((x) & 0x0000ff00) >> 8)
2619 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_MSB 23
2620 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_LSB 16
2621 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_MASK 0x00ff0000
2622 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_GET(x) (((x) & 0x00ff0000) >> 16)
2623 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_MSB 31
2624 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_LSB 24
2625 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_MASK 0xff000000
2626 #define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_GET(x) (((x) & 0xff000000) >> 24)
2628 /* macros for BB_chan_info_noise_pwr */
2629 #define PHY_BB_CHAN_INFO_NOISE_PWR_ADDRESS 0x00009cac
2630 #define PHY_BB_CHAN_INFO_NOISE_PWR_OFFSET 0x00009cac
2631 #define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_MSB 11
2632 #define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_LSB 0
2633 #define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_MASK 0x00000fff
2634 #define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_GET(x) (((x) & 0x00000fff) >> 0)
2636 /* macros for BB_chan_info_gain_diff */
2637 #define PHY_BB_CHAN_INFO_GAIN_DIFF_ADDRESS 0x00009cb0
2638 #define PHY_BB_CHAN_INFO_GAIN_DIFF_OFFSET 0x00009cb0
2639 #define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_MSB 11
2640 #define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_LSB 0
2641 #define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_MASK 0x00000fff
2642 #define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_GET(x) (((x) & 0x00000fff) >> 0)
2644 /* macros for BB_chan_info_fine_timing */
2645 #define PHY_BB_CHAN_INFO_FINE_TIMING_ADDRESS 0x00009cb4
2646 #define PHY_BB_CHAN_INFO_FINE_TIMING_OFFSET 0x00009cb4
2647 #define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MSB 11
2648 #define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_LSB 0
2649 #define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MASK 0x00000fff
2650 #define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_GET(x) (((x) & 0x00000fff) >> 0)
2651 #define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MSB 21
2652 #define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_LSB 12
2653 #define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MASK 0x003ff000
2654 #define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_GET(x) (((x) & 0x003ff000) >> 12)
2656 /* macros for BB_chan_info_gain_b0 */
2657 #define PHY_BB_CHAN_INFO_GAIN_B0_ADDRESS 0x00009cb8
2658 #define PHY_BB_CHAN_INFO_GAIN_B0_OFFSET 0x00009cb8
2659 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MSB 7
2660 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_LSB 0
2661 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MASK 0x000000ff
2662 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_GET(x) (((x) & 0x000000ff) >> 0)
2663 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MSB 15
2664 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_LSB 8
2665 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MASK 0x0000ff00
2666 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_GET(x) (((x) & 0x0000ff00) >> 8)
2667 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MSB 16
2668 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_LSB 16
2669 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MASK 0x00010000
2670 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_GET(x) (((x) & 0x00010000) >> 16)
2671 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MSB 17
2672 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_LSB 17
2673 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MASK 0x00020000
2674 #define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_GET(x) (((x) & 0x00020000) >> 17)
2676 /* macros for BB_chan_info_chan_tab_b0 */
2677 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_ADDRESS 0x00009cbc
2678 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_OFFSET 0x00009cbc
2679 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_MSB 5
2680 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_LSB 0
2681 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_MASK 0x0000003f
2682 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_GET(x) (((x) & 0x0000003f) >> 0)
2683 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_MSB 11
2684 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_LSB 6
2685 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_MASK 0x00000fc0
2686 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_GET(x) (((x) & 0x00000fc0) >> 6)
2687 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_MSB 15
2688 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_LSB 12
2689 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_MASK 0x0000f000
2690 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_GET(x) (((x) & 0x0000f000) >> 12)
2691 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_MSB 21
2692 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_LSB 16
2693 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_MASK 0x003f0000
2694 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_GET(x) (((x) & 0x003f0000) >> 16)
2695 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_MSB 27
2696 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_LSB 22
2697 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_MASK 0x0fc00000
2698 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_GET(x) (((x) & 0x0fc00000) >> 22)
2699 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_MSB 31
2700 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_LSB 28
2701 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_MASK 0xf0000000
2702 #define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_GET(x) (((x) & 0xf0000000) >> 28)
2704 /* macros for BB_paprd_am2am_mask */
2705 #define PHY_BB_PAPRD_AM2AM_MASK_ADDRESS 0x00009de4
2706 #define PHY_BB_PAPRD_AM2AM_MASK_OFFSET 0x00009de4
2707 #define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MSB 24
2708 #define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_LSB 0
2709 #define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MASK 0x01ffffff
2710 #define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_GET(x) (((x) & 0x01ffffff) >> 0)
2711 #define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_SET(x) (((x) << 0) & 0x01ffffff)
2713 /* macros for BB_paprd_am2pm_mask */
2714 #define PHY_BB_PAPRD_AM2PM_MASK_ADDRESS 0x00009de8
2715 #define PHY_BB_PAPRD_AM2PM_MASK_OFFSET 0x00009de8
2716 #define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MSB 24
2717 #define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_LSB 0
2718 #define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MASK 0x01ffffff
2719 #define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_GET(x) (((x) & 0x01ffffff) >> 0)
2720 #define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_SET(x) (((x) << 0) & 0x01ffffff)
2722 /* macros for BB_paprd_ht40_mask */
2723 #define PHY_BB_PAPRD_HT40_MASK_ADDRESS 0x00009dec
2724 #define PHY_BB_PAPRD_HT40_MASK_OFFSET 0x00009dec
2725 #define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MSB 24
2726 #define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_LSB 0
2727 #define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MASK 0x01ffffff
2728 #define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_GET(x) (((x) & 0x01ffffff) >> 0)
2729 #define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_SET(x) (((x) << 0) & 0x01ffffff)
2731 /* macros for BB_paprd_ctrl0 */
2732 #define PHY_BB_PAPRD_CTRL0_ADDRESS 0x00009df0
2733 #define PHY_BB_PAPRD_CTRL0_OFFSET 0x00009df0
2734 #define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_MSB 0
2735 #define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_LSB 0
2736 #define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_MASK 0x00000001
2737 #define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_GET(x) (((x) & 0x00000001) >> 0)
2738 #define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_SET(x) (((x) << 0) & 0x00000001)
2739 #define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_MSB 1
2740 #define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_LSB 1
2741 #define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_MASK 0x00000002
2742 #define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_GET(x) (((x) & 0x00000002) >> 1)
2743 #define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_SET(x) (((x) << 1) & 0x00000002)
2744 #define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_MSB 26
2745 #define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_LSB 2
2746 #define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_MASK 0x07fffffc
2747 #define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_GET(x) (((x) & 0x07fffffc) >> 2)
2748 #define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_SET(x) (((x) << 2) & 0x07fffffc)
2749 #define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_MSB 31
2750 #define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_LSB 27
2751 #define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_MASK 0xf8000000
2752 #define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_GET(x) (((x) & 0xf8000000) >> 27)
2753 #define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_SET(x) (((x) << 27) & 0xf8000000)
2755 /* macros for BB_paprd_ctrl1 */
2756 #define PHY_BB_PAPRD_CTRL1_ADDRESS 0x00009df4
2757 #define PHY_BB_PAPRD_CTRL1_OFFSET 0x00009df4
2758 #define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_MSB 0
2759 #define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_LSB 0
2760 #define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_MASK 0x00000001
2761 #define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_GET(x) (((x) & 0x00000001) >> 0)
2762 #define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_SET(x) (((x) << 0) & 0x00000001)
2763 #define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_MSB 1
2764 #define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_LSB 1
2765 #define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_MASK 0x00000002
2766 #define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_GET(x) (((x) & 0x00000002) >> 1)
2767 #define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_SET(x) (((x) << 1) & 0x00000002)
2768 #define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_MSB 2
2769 #define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_LSB 2
2770 #define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_MASK 0x00000004
2771 #define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_GET(x) (((x) & 0x00000004) >> 2)
2772 #define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_SET(x) (((x) << 2) & 0x00000004)
2773 #define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_MSB 8
2774 #define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_LSB 3
2775 #define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_MASK 0x000001f8
2776 #define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_GET(x) (((x) & 0x000001f8) >> 3)
2777 #define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_SET(x) (((x) << 3) & 0x000001f8)
2778 #define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_MSB 16
2779 #define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_LSB 9
2780 #define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_MASK 0x0001fe00
2781 #define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_GET(x) (((x) & 0x0001fe00) >> 9)
2782 #define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_SET(x) (((x) << 9) & 0x0001fe00)
2783 #define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_MSB 26
2784 #define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_LSB 17
2785 #define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_MASK 0x07fe0000
2786 #define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_GET(x) (((x) & 0x07fe0000) >> 17)
2787 #define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_SET(x) (((x) << 17) & 0x07fe0000)
2788 #define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_MSB 27
2789 #define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_LSB 27
2790 #define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_MASK 0x08000000
2791 #define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_GET(x) (((x) & 0x08000000) >> 27)
2792 #define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_SET(x) (((x) << 27) & 0x08000000)
2794 /* macros for BB_pa_gain123 */
2795 #define PHY_BB_PA_GAIN123_ADDRESS 0x00009df8
2796 #define PHY_BB_PA_GAIN123_OFFSET 0x00009df8
2797 #define PHY_BB_PA_GAIN123_PA_GAIN1_MSB 9
2798 #define PHY_BB_PA_GAIN123_PA_GAIN1_LSB 0
2799 #define PHY_BB_PA_GAIN123_PA_GAIN1_MASK 0x000003ff
2800 #define PHY_BB_PA_GAIN123_PA_GAIN1_GET(x) (((x) & 0x000003ff) >> 0)
2801 #define PHY_BB_PA_GAIN123_PA_GAIN1_SET(x) (((x) << 0) & 0x000003ff)
2802 #define PHY_BB_PA_GAIN123_PA_GAIN2_MSB 19
2803 #define PHY_BB_PA_GAIN123_PA_GAIN2_LSB 10
2804 #define PHY_BB_PA_GAIN123_PA_GAIN2_MASK 0x000ffc00
2805 #define PHY_BB_PA_GAIN123_PA_GAIN2_GET(x) (((x) & 0x000ffc00) >> 10)
2806 #define PHY_BB_PA_GAIN123_PA_GAIN2_SET(x) (((x) << 10) & 0x000ffc00)
2807 #define PHY_BB_PA_GAIN123_PA_GAIN3_MSB 29
2808 #define PHY_BB_PA_GAIN123_PA_GAIN3_LSB 20
2809 #define PHY_BB_PA_GAIN123_PA_GAIN3_MASK 0x3ff00000
2810 #define PHY_BB_PA_GAIN123_PA_GAIN3_GET(x) (((x) & 0x3ff00000) >> 20)
2811 #define PHY_BB_PA_GAIN123_PA_GAIN3_SET(x) (((x) << 20) & 0x3ff00000)
2813 /* macros for BB_pa_gain45 */
2814 #define PHY_BB_PA_GAIN45_ADDRESS 0x00009dfc
2815 #define PHY_BB_PA_GAIN45_OFFSET 0x00009dfc
2816 #define PHY_BB_PA_GAIN45_PA_GAIN4_MSB 9
2817 #define PHY_BB_PA_GAIN45_PA_GAIN4_LSB 0
2818 #define PHY_BB_PA_GAIN45_PA_GAIN4_MASK 0x000003ff
2819 #define PHY_BB_PA_GAIN45_PA_GAIN4_GET(x) (((x) & 0x000003ff) >> 0)
2820 #define PHY_BB_PA_GAIN45_PA_GAIN4_SET(x) (((x) << 0) & 0x000003ff)
2821 #define PHY_BB_PA_GAIN45_PA_GAIN5_MSB 19
2822 #define PHY_BB_PA_GAIN45_PA_GAIN5_LSB 10
2823 #define PHY_BB_PA_GAIN45_PA_GAIN5_MASK 0x000ffc00
2824 #define PHY_BB_PA_GAIN45_PA_GAIN5_GET(x) (((x) & 0x000ffc00) >> 10)
2825 #define PHY_BB_PA_GAIN45_PA_GAIN5_SET(x) (((x) << 10) & 0x000ffc00)
2826 #define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_MSB 24
2827 #define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_LSB 20
2828 #define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_MASK 0x01f00000
2829 #define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_GET(x) (((x) & 0x01f00000) >> 20)
2830 #define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_SET(x) (((x) << 20) & 0x01f00000)
2832 /* macros for BB_paprd_pre_post_scale_0 */
2833 #define PHY_BB_PAPRD_PRE_POST_SCALE_0_ADDRESS 0x00009e00
2834 #define PHY_BB_PAPRD_PRE_POST_SCALE_0_OFFSET 0x00009e00
2835 #define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_MSB 17
2836 #define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_LSB 0
2837 #define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_MASK 0x0003ffff
2838 #define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_GET(x) (((x) & 0x0003ffff) >> 0)
2839 #define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_SET(x) (((x) << 0) & 0x0003ffff)
2841 /* macros for BB_paprd_pre_post_scale_1 */
2842 #define PHY_BB_PAPRD_PRE_POST_SCALE_1_ADDRESS 0x00009e04
2843 #define PHY_BB_PAPRD_PRE_POST_SCALE_1_OFFSET 0x00009e04
2844 #define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_MSB 17
2845 #define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_LSB 0
2846 #define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_MASK 0x0003ffff
2847 #define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_GET(x) (((x) & 0x0003ffff) >> 0)
2848 #define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_SET(x) (((x) << 0) & 0x0003ffff)
2850 /* macros for BB_paprd_pre_post_scale_2 */
2851 #define PHY_BB_PAPRD_PRE_POST_SCALE_2_ADDRESS 0x00009e08
2852 #define PHY_BB_PAPRD_PRE_POST_SCALE_2_OFFSET 0x00009e08
2853 #define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_MSB 17
2854 #define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_LSB 0
2855 #define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_MASK 0x0003ffff
2856 #define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_GET(x) (((x) & 0x0003ffff) >> 0)
2857 #define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_SET(x) (((x) << 0) & 0x0003ffff)
2859 /* macros for BB_paprd_pre_post_scale_3 */
2860 #define PHY_BB_PAPRD_PRE_POST_SCALE_3_ADDRESS 0x00009e0c
2861 #define PHY_BB_PAPRD_PRE_POST_SCALE_3_OFFSET 0x00009e0c
2862 #define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_MSB 17
2863 #define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_LSB 0
2864 #define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_MASK 0x0003ffff
2865 #define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_GET(x) (((x) & 0x0003ffff) >> 0)
2866 #define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_SET(x) (((x) << 0) & 0x0003ffff)
2868 /* macros for BB_paprd_pre_post_scale_4 */
2869 #define PHY_BB_PAPRD_PRE_POST_SCALE_4_ADDRESS 0x00009e10
2870 #define PHY_BB_PAPRD_PRE_POST_SCALE_4_OFFSET 0x00009e10
2871 #define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_MSB 17
2872 #define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_LSB 0
2873 #define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_MASK 0x0003ffff
2874 #define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_GET(x) (((x) & 0x0003ffff) >> 0)
2875 #define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_SET(x) (((x) << 0) & 0x0003ffff)
2877 /* macros for BB_paprd_pre_post_scale_5 */
2878 #define PHY_BB_PAPRD_PRE_POST_SCALE_5_ADDRESS 0x00009e14
2879 #define PHY_BB_PAPRD_PRE_POST_SCALE_5_OFFSET 0x00009e14
2880 #define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_MSB 17
2881 #define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_LSB 0
2882 #define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_MASK 0x0003ffff
2883 #define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_GET(x) (((x) & 0x0003ffff) >> 0)
2884 #define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_SET(x) (((x) << 0) & 0x0003ffff)
2886 /* macros for BB_paprd_pre_post_scale_6 */
2887 #define PHY_BB_PAPRD_PRE_POST_SCALE_6_ADDRESS 0x00009e18
2888 #define PHY_BB_PAPRD_PRE_POST_SCALE_6_OFFSET 0x00009e18
2889 #define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_MSB 17
2890 #define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_LSB 0
2891 #define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_MASK 0x0003ffff
2892 #define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_GET(x) (((x) & 0x0003ffff) >> 0)
2893 #define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_SET(x) (((x) << 0) & 0x0003ffff)
2895 /* macros for BB_paprd_pre_post_scale_7 */
2896 #define PHY_BB_PAPRD_PRE_POST_SCALE_7_ADDRESS 0x00009e1c
2897 #define PHY_BB_PAPRD_PRE_POST_SCALE_7_OFFSET 0x00009e1c
2898 #define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_MSB 17
2899 #define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_LSB 0
2900 #define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_MASK 0x0003ffff
2901 #define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_GET(x) (((x) & 0x0003ffff) >> 0)
2902 #define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_SET(x) (((x) << 0) & 0x0003ffff)
2904 /* macros for BB_paprd_mem_tab */
2905 #define PHY_BB_PAPRD_MEM_TAB_ADDRESS 0x00009e20
2906 #define PHY_BB_PAPRD_MEM_TAB_OFFSET 0x00009e20
2907 #define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_MSB 21
2908 #define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_LSB 0
2909 #define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_MASK 0x003fffff
2910 #define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_GET(x) (((x) & 0x003fffff) >> 0)
2911 #define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_SET(x) (((x) << 0) & 0x003fffff)
2913 /* macros for BB_peak_det_ctrl_1 */
2914 #define PHY_BB_PEAK_DET_CTRL_1_ADDRESS 0x0000a000
2915 #define PHY_BB_PEAK_DET_CTRL_1_OFFSET 0x0000a000
2916 #define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_MSB 0
2917 #define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_LSB 0
2918 #define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_MASK 0x00000001
2919 #define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_GET(x) (((x) & 0x00000001) >> 0)
2920 #define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_SET(x) (((x) << 0) & 0x00000001)
2921 #define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_MSB 1
2922 #define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_LSB 1
2923 #define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_MASK 0x00000002
2924 #define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_GET(x) (((x) & 0x00000002) >> 1)
2925 #define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_SET(x) (((x) << 1) & 0x00000002)
2926 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_MSB 7
2927 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_LSB 2
2928 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_MASK 0x000000fc
2929 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_GET(x) (((x) & 0x000000fc) >> 2)
2930 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_SET(x) (((x) << 2) & 0x000000fc)
2931 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_MSB 12
2932 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_LSB 8
2933 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_MASK 0x00001f00
2934 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_GET(x) (((x) & 0x00001f00) >> 8)
2935 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_SET(x) (((x) << 8) & 0x00001f00)
2936 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_MSB 17
2937 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_LSB 13
2938 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_MASK 0x0003e000
2939 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_GET(x) (((x) & 0x0003e000) >> 13)
2940 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_SET(x) (((x) << 13) & 0x0003e000)
2941 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_MSB 22
2942 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_LSB 18
2943 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_MASK 0x007c0000
2944 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_GET(x) (((x) & 0x007c0000) >> 18)
2945 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_SET(x) (((x) << 18) & 0x007c0000)
2946 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_MSB 29
2947 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_LSB 23
2948 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_MASK 0x3f800000
2949 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_GET(x) (((x) & 0x3f800000) >> 23)
2950 #define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_SET(x) (((x) << 23) & 0x3f800000)
2951 #define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_MSB 30
2952 #define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_LSB 30
2953 #define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_MASK 0x40000000
2954 #define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_GET(x) (((x) & 0x40000000) >> 30)
2955 #define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_SET(x) (((x) << 30) & 0x40000000)
2956 #define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_MSB 31
2957 #define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_LSB 31
2958 #define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_MASK 0x80000000
2959 #define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_GET(x) (((x) & 0x80000000) >> 31)
2960 #define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_SET(x) (((x) << 31) & 0x80000000)
2962 /* macros for BB_peak_det_ctrl_2 */
2963 #define PHY_BB_PEAK_DET_CTRL_2_ADDRESS 0x0000a004
2964 #define PHY_BB_PEAK_DET_CTRL_2_OFFSET 0x0000a004
2965 #define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_MSB 9
2966 #define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_LSB 0
2967 #define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_MASK 0x000003ff
2968 #define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_GET(x) (((x) & 0x000003ff) >> 0)
2969 #define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_SET(x) (((x) << 0) & 0x000003ff)
2970 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_MSB 14
2971 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_LSB 10
2972 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_MASK 0x00007c00
2973 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_GET(x) (((x) & 0x00007c00) >> 10)
2974 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_SET(x) (((x) << 10) & 0x00007c00)
2975 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_MSB 19
2976 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_LSB 15
2977 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_MASK 0x000f8000
2978 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_GET(x) (((x) & 0x000f8000) >> 15)
2979 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_SET(x) (((x) << 15) & 0x000f8000)
2980 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_MSB 24
2981 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_LSB 20
2982 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_MASK 0x01f00000
2983 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_GET(x) (((x) & 0x01f00000) >> 20)
2984 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_SET(x) (((x) << 20) & 0x01f00000)
2985 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_MSB 29
2986 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_LSB 25
2987 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_MASK 0x3e000000
2988 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_GET(x) (((x) & 0x3e000000) >> 25)
2989 #define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_SET(x) (((x) << 25) & 0x3e000000)
2991 /* macros for BB_rx_gain_bounds_1 */
2992 #define PHY_BB_RX_GAIN_BOUNDS_1_ADDRESS 0x0000a008
2993 #define PHY_BB_RX_GAIN_BOUNDS_1_OFFSET 0x0000a008
2994 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_MSB 7
2995 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_LSB 0
2996 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_MASK 0x000000ff
2997 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_GET(x) (((x) & 0x000000ff) >> 0)
2998 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_SET(x) (((x) << 0) & 0x000000ff)
2999 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_MSB 15
3000 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_LSB 8
3001 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_MASK 0x0000ff00
3002 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_GET(x) (((x) & 0x0000ff00) >> 8)
3003 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_SET(x) (((x) << 8) & 0x0000ff00)
3004 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_MSB 23
3005 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_LSB 16
3006 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_MASK 0x00ff0000
3007 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_GET(x) (((x) & 0x00ff0000) >> 16)
3008 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_SET(x) (((x) << 16) & 0x00ff0000)
3009 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_MSB 24
3010 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_LSB 24
3011 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_MASK 0x01000000
3012 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_GET(x) (((x) & 0x01000000) >> 24)
3013 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_SET(x) (((x) << 24) & 0x01000000)
3014 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_MSB 25
3015 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_LSB 25
3016 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_MASK 0x02000000
3017 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_GET(x) (((x) & 0x02000000) >> 25)
3018 #define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_SET(x) (((x) << 25) & 0x02000000)
3020 /* macros for BB_rx_gain_bounds_2 */
3021 #define PHY_BB_RX_GAIN_BOUNDS_2_ADDRESS 0x0000a00c
3022 #define PHY_BB_RX_GAIN_BOUNDS_2_OFFSET 0x0000a00c
3023 #define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_MSB 7
3024 #define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_LSB 0
3025 #define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_MASK 0x000000ff
3026 #define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_GET(x) (((x) & 0x000000ff) >> 0)
3027 #define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_SET(x) (((x) << 0) & 0x000000ff)
3028 #define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_MSB 15
3029 #define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_LSB 8
3030 #define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_MASK 0x0000ff00
3031 #define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_GET(x) (((x) & 0x0000ff00) >> 8)
3032 #define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_SET(x) (((x) << 8) & 0x0000ff00)
3033 #define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_MSB 23
3034 #define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_LSB 16
3035 #define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_MASK 0x00ff0000
3036 #define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_GET(x) (((x) & 0x00ff0000) >> 16)
3037 #define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_SET(x) (((x) << 16) & 0x00ff0000)
3038 #define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_MSB 31
3039 #define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_LSB 24
3040 #define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_MASK 0xff000000
3041 #define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_GET(x) (((x) & 0xff000000) >> 24)
3042 #define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_SET(x) (((x) << 24) & 0xff000000)
3044 /* macros for BB_peak_det_cal_ctrl */
3045 #define PHY_BB_PEAK_DET_CAL_CTRL_ADDRESS 0x0000a010
3046 #define PHY_BB_PEAK_DET_CAL_CTRL_OFFSET 0x0000a010
3047 #define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_MSB 5
3048 #define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_LSB 0
3049 #define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_MASK 0x0000003f
3050 #define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_GET(x) (((x) & 0x0000003f) >> 0)
3051 #define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_SET(x) (((x) << 0) & 0x0000003f)
3052 #define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_MSB 11
3053 #define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_LSB 6
3054 #define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_MASK 0x00000fc0
3055 #define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_GET(x) (((x) & 0x00000fc0) >> 6)
3056 #define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_SET(x) (((x) << 6) & 0x00000fc0)
3057 #define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_MSB 13
3058 #define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_LSB 12
3059 #define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_MASK 0x00003000
3060 #define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_GET(x) (((x) & 0x00003000) >> 12)
3061 #define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_SET(x) (((x) << 12) & 0x00003000)
3063 /* macros for BB_agc_dig_dc_ctrl */
3064 #define PHY_BB_AGC_DIG_DC_CTRL_ADDRESS 0x0000a014
3065 #define PHY_BB_AGC_DIG_DC_CTRL_OFFSET 0x0000a014
3066 #define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_MSB 0
3067 #define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_LSB 0
3068 #define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_MASK 0x00000001
3069 #define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_GET(x) (((x) & 0x00000001) >> 0)
3070 #define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_SET(x) (((x) << 0) & 0x00000001)
3071 #define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_MSB 3
3072 #define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_LSB 1
3073 #define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_MASK 0x0000000e
3074 #define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_GET(x) (((x) & 0x0000000e) >> 1)
3075 #define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_SET(x) (((x) << 1) & 0x0000000e)
3076 #define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_MSB 9
3077 #define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_LSB 4
3078 #define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_MASK 0x000003f0
3079 #define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_GET(x) (((x) & 0x000003f0) >> 4)
3080 #define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_SET(x) (((x) << 4) & 0x000003f0)
3081 #define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_MSB 31
3082 #define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_LSB 16
3083 #define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_MASK 0xffff0000
3084 #define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_GET(x) (((x) & 0xffff0000) >> 16)
3085 #define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_SET(x) (((x) << 16) & 0xffff0000)
3087 /* macros for BB_agc_dig_dc_status_i_b0 */
3088 #define PHY_BB_AGC_DIG_DC_STATUS_I_B0_ADDRESS 0x0000a018
3089 #define PHY_BB_AGC_DIG_DC_STATUS_I_B0_OFFSET 0x0000a018
3090 #define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_MSB 8
3091 #define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_LSB 0
3092 #define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_MASK 0x000001ff
3093 #define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_GET(x) (((x) & 0x000001ff) >> 0)
3094 #define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_MSB 17
3095 #define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_LSB 9
3096 #define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_MASK 0x0003fe00
3097 #define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_GET(x) (((x) & 0x0003fe00) >> 9)
3098 #define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_MSB 26
3099 #define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_LSB 18
3100 #define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_MASK 0x07fc0000
3101 #define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_GET(x) (((x) & 0x07fc0000) >> 18)
3103 /* macros for BB_agc_dig_dc_status_q_b0 */
3104 #define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_ADDRESS 0x0000a01c
3105 #define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_OFFSET 0x0000a01c
3106 #define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_MSB 8
3107 #define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_LSB 0
3108 #define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_MASK 0x000001ff
3109 #define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_GET(x) (((x) & 0x000001ff) >> 0)
3110 #define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_MSB 17
3111 #define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_LSB 9
3112 #define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_MASK 0x0003fe00
3113 #define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_GET(x) (((x) & 0x0003fe00) >> 9)
3114 #define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_MSB 26
3115 #define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_LSB 18
3116 #define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_MASK 0x07fc0000
3117 #define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_GET(x) (((x) & 0x07fc0000) >> 18)
3119 /* macros for BB_bbb_txfir_0 */
3120 #define PHY_BB_BBB_TXFIR_0_ADDRESS 0x0000a1f4
3121 #define PHY_BB_BBB_TXFIR_0_OFFSET 0x0000a1f4
3122 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MSB 3
3123 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_LSB 0
3124 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MASK 0x0000000f
3125 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_GET(x) (((x) & 0x0000000f) >> 0)
3126 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_SET(x) (((x) << 0) & 0x0000000f)
3127 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MSB 11
3128 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_LSB 8
3129 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MASK 0x00000f00
3130 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_GET(x) (((x) & 0x00000f00) >> 8)
3131 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_SET(x) (((x) << 8) & 0x00000f00)
3132 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MSB 20
3133 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_LSB 16
3134 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MASK 0x001f0000
3135 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_GET(x) (((x) & 0x001f0000) >> 16)
3136 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_SET(x) (((x) << 16) & 0x001f0000)
3137 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MSB 28
3138 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_LSB 24
3139 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MASK 0x1f000000
3140 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_GET(x) (((x) & 0x1f000000) >> 24)
3141 #define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_SET(x) (((x) << 24) & 0x1f000000)
3143 /* macros for BB_bbb_txfir_1 */
3144 #define PHY_BB_BBB_TXFIR_1_ADDRESS 0x0000a1f8
3145 #define PHY_BB_BBB_TXFIR_1_OFFSET 0x0000a1f8
3146 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MSB 5
3147 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_LSB 0
3148 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MASK 0x0000003f
3149 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_GET(x) (((x) & 0x0000003f) >> 0)
3150 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_SET(x) (((x) << 0) & 0x0000003f)
3151 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MSB 13
3152 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_LSB 8
3153 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MASK 0x00003f00
3154 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_GET(x) (((x) & 0x00003f00) >> 8)
3155 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_SET(x) (((x) << 8) & 0x00003f00)
3156 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MSB 22
3157 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_LSB 16
3158 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MASK 0x007f0000
3159 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_GET(x) (((x) & 0x007f0000) >> 16)
3160 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_SET(x) (((x) << 16) & 0x007f0000)
3161 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MSB 30
3162 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_LSB 24
3163 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MASK 0x7f000000
3164 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_GET(x) (((x) & 0x7f000000) >> 24)
3165 #define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_SET(x) (((x) << 24) & 0x7f000000)
3167 /* macros for BB_bbb_txfir_2 */
3168 #define PHY_BB_BBB_TXFIR_2_ADDRESS 0x0000a1fc
3169 #define PHY_BB_BBB_TXFIR_2_OFFSET 0x0000a1fc
3170 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MSB 7
3171 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_LSB 0
3172 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MASK 0x000000ff
3173 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_GET(x) (((x) & 0x000000ff) >> 0)
3174 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_SET(x) (((x) << 0) & 0x000000ff)
3175 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MSB 15
3176 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_LSB 8
3177 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MASK 0x0000ff00
3178 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_GET(x) (((x) & 0x0000ff00) >> 8)
3179 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_SET(x) (((x) << 8) & 0x0000ff00)
3180 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MSB 23
3181 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_LSB 16
3182 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MASK 0x00ff0000
3183 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_GET(x) (((x) & 0x00ff0000) >> 16)
3184 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_SET(x) (((x) << 16) & 0x00ff0000)
3185 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MSB 31
3186 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_LSB 24
3187 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MASK 0xff000000
3188 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_GET(x) (((x) & 0xff000000) >> 24)
3189 #define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_SET(x) (((x) << 24) & 0xff000000)
3191 /* macros for BB_modes_select */
3192 #define PHY_BB_MODES_SELECT_ADDRESS 0x0000a200
3193 #define PHY_BB_MODES_SELECT_OFFSET 0x0000a200
3194 #define PHY_BB_MODES_SELECT_CCK_MODE_MSB 0
3195 #define PHY_BB_MODES_SELECT_CCK_MODE_LSB 0
3196 #define PHY_BB_MODES_SELECT_CCK_MODE_MASK 0x00000001
3197 #define PHY_BB_MODES_SELECT_CCK_MODE_GET(x) (((x) & 0x00000001) >> 0)
3198 #define PHY_BB_MODES_SELECT_CCK_MODE_SET(x) (((x) << 0) & 0x00000001)
3199 #define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MSB 2
3200 #define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_LSB 2
3201 #define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MASK 0x00000004
3202 #define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_GET(x) (((x) & 0x00000004) >> 2)
3203 #define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_SET(x) (((x) << 2) & 0x00000004)
3204 #define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MSB 5
3205 #define PHY_BB_MODES_SELECT_HALF_RATE_MODE_LSB 5
3206 #define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MASK 0x00000020
3207 #define PHY_BB_MODES_SELECT_HALF_RATE_MODE_GET(x) (((x) & 0x00000020) >> 5)
3208 #define PHY_BB_MODES_SELECT_HALF_RATE_MODE_SET(x) (((x) << 5) & 0x00000020)
3209 #define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MSB 6
3210 #define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_LSB 6
3211 #define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MASK 0x00000040
3212 #define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_GET(x) (((x) & 0x00000040) >> 6)
3213 #define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_SET(x) (((x) << 6) & 0x00000040)
3214 #define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MSB 7
3215 #define PHY_BB_MODES_SELECT_MAC_CLK_MODE_LSB 7
3216 #define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MASK 0x00000080
3217 #define PHY_BB_MODES_SELECT_MAC_CLK_MODE_GET(x) (((x) & 0x00000080) >> 7)
3218 #define PHY_BB_MODES_SELECT_MAC_CLK_MODE_SET(x) (((x) << 7) & 0x00000080)
3219 #define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MSB 8
3220 #define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_LSB 8
3221 #define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MASK 0x00000100
3222 #define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_GET(x) (((x) & 0x00000100) >> 8)
3223 #define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_SET(x) (((x) << 8) & 0x00000100)
3225 /* macros for BB_bbb_tx_ctrl */
3226 #define PHY_BB_BBB_TX_CTRL_ADDRESS 0x0000a204
3227 #define PHY_BB_BBB_TX_CTRL_OFFSET 0x0000a204
3228 #define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MSB 0
3229 #define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_LSB 0
3230 #define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MASK 0x00000001
3231 #define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_GET(x) (((x) & 0x00000001) >> 0)
3232 #define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_SET(x) (((x) << 0) & 0x00000001)
3233 #define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MSB 1
3234 #define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_LSB 1
3235 #define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MASK 0x00000002
3236 #define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_GET(x) (((x) & 0x00000002) >> 1)
3237 #define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_SET(x) (((x) << 1) & 0x00000002)
3238 #define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MSB 3
3239 #define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_LSB 2
3240 #define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MASK 0x0000000c
3241 #define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_GET(x) (((x) & 0x0000000c) >> 2)
3242 #define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_SET(x) (((x) << 2) & 0x0000000c)
3243 #define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MSB 4
3244 #define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_LSB 4
3245 #define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MASK 0x00000010
3246 #define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_GET(x) (((x) & 0x00000010) >> 4)
3247 #define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_SET(x) (((x) << 4) & 0x00000010)
3248 #define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MSB 5
3249 #define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_LSB 5
3250 #define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MASK 0x00000020
3251 #define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_GET(x) (((x) & 0x00000020) >> 5)
3252 #define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_SET(x) (((x) << 5) & 0x00000020)
3253 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MSB 8
3254 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_LSB 6
3255 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MASK 0x000001c0
3256 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_GET(x) (((x) & 0x000001c0) >> 6)
3257 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_SET(x) (((x) << 6) & 0x000001c0)
3258 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MSB 11
3259 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_LSB 9
3260 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MASK 0x00000e00
3261 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_GET(x) (((x) & 0x00000e00) >> 9)
3262 #define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_SET(x) (((x) << 9) & 0x00000e00)
3264 /* macros for BB_bbb_sig_detect */
3265 #define PHY_BB_BBB_SIG_DETECT_ADDRESS 0x0000a208
3266 #define PHY_BB_BBB_SIG_DETECT_OFFSET 0x0000a208
3267 #define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_MSB 5
3268 #define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_LSB 0
3269 #define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_MASK 0x0000003f
3270 #define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_GET(x) (((x) & 0x0000003f) >> 0)
3271 #define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_SET(x) (((x) << 0) & 0x0000003f)
3272 #define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_MSB 12
3273 #define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_LSB 6
3274 #define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_MASK 0x00001fc0
3275 #define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_GET(x) (((x) & 0x00001fc0) >> 6)
3276 #define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_SET(x) (((x) << 6) & 0x00001fc0)
3277 #define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_MSB 13
3278 #define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_LSB 13
3279 #define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_MASK 0x00002000
3280 #define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_GET(x) (((x) & 0x00002000) >> 13)
3281 #define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_SET(x) (((x) << 13) & 0x00002000)
3282 #define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_MSB 14
3283 #define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_LSB 14
3284 #define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_MASK 0x00004000
3285 #define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_GET(x) (((x) & 0x00004000) >> 14)
3286 #define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_SET(x) (((x) << 14) & 0x00004000)
3287 #define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_MSB 15
3288 #define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_LSB 15
3289 #define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_MASK 0x00008000
3290 #define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_GET(x) (((x) & 0x00008000) >> 15)
3291 #define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_SET(x) (((x) << 15) & 0x00008000)
3292 #define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_MSB 16
3293 #define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_LSB 16
3294 #define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_MASK 0x00010000
3295 #define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_GET(x) (((x) & 0x00010000) >> 16)
3296 #define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_SET(x) (((x) << 16) & 0x00010000)
3297 #define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_MSB 17
3298 #define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_LSB 17
3299 #define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_MASK 0x00020000
3300 #define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_GET(x) (((x) & 0x00020000) >> 17)
3301 #define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_SET(x) (((x) << 17) & 0x00020000)
3302 #define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_MSB 18
3303 #define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_LSB 18
3304 #define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_MASK 0x00040000
3305 #define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_GET(x) (((x) & 0x00040000) >> 18)
3306 #define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_SET(x) (((x) << 18) & 0x00040000)
3307 #define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_MSB 19
3308 #define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_LSB 19
3309 #define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_MASK 0x00080000
3310 #define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_GET(x) (((x) & 0x00080000) >> 19)
3311 #define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_SET(x) (((x) << 19) & 0x00080000)
3312 #define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_MSB 20
3313 #define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_LSB 20
3314 #define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_MASK 0x00100000
3315 #define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_GET(x) (((x) & 0x00100000) >> 20)
3316 #define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_SET(x) (((x) << 20) & 0x00100000)
3317 #define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_MSB 21
3318 #define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_LSB 21
3319 #define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_MASK 0x00200000
3320 #define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_GET(x) (((x) & 0x00200000) >> 21)
3321 #define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_SET(x) (((x) << 21) & 0x00200000)
3322 #define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_MSB 22
3323 #define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_LSB 22
3324 #define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_MASK 0x00400000
3325 #define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_GET(x) (((x) & 0x00400000) >> 22)
3326 #define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_SET(x) (((x) << 22) & 0x00400000)
3327 #define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_MSB 31
3328 #define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_LSB 31
3329 #define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_MASK 0x80000000
3330 #define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_GET(x) (((x) & 0x80000000) >> 31)
3331 #define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_SET(x) (((x) << 31) & 0x80000000)
3333 /* macros for BB_ext_atten_switch_ctl_b0 */
3334 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_ADDRESS 0x0000a20c
3335 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_OFFSET 0x0000a20c
3336 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_MSB 5
3337 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_LSB 0
3338 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_MASK 0x0000003f
3339 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_GET(x) (((x) & 0x0000003f) >> 0)
3340 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_SET(x) (((x) << 0) & 0x0000003f)
3341 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_MSB 11
3342 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_LSB 6
3343 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_MASK 0x00000fc0
3344 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_GET(x) (((x) & 0x00000fc0) >> 6)
3345 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_SET(x) (((x) << 6) & 0x00000fc0)
3346 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_MSB 16
3347 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_LSB 12
3348 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_MASK 0x0001f000
3349 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_GET(x) (((x) & 0x0001f000) >> 12)
3350 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_SET(x) (((x) << 12) & 0x0001f000)
3351 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_MSB 21
3352 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_LSB 17
3353 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_MASK 0x003e0000
3354 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_GET(x) (((x) & 0x003e0000) >> 17)
3355 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_SET(x) (((x) << 17) & 0x003e0000)
3357 /* macros for BB_bbb_rx_ctrl_1 */
3358 #define PHY_BB_BBB_RX_CTRL_1_ADDRESS 0x0000a210
3359 #define PHY_BB_BBB_RX_CTRL_1_OFFSET 0x0000a210
3360 #define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_MSB 2
3361 #define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_LSB 0
3362 #define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_MASK 0x00000007
3363 #define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_GET(x) (((x) & 0x00000007) >> 0)
3364 #define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_SET(x) (((x) << 0) & 0x00000007)
3365 #define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_MSB 7
3366 #define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_LSB 3
3367 #define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_MASK 0x000000f8
3368 #define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_GET(x) (((x) & 0x000000f8) >> 3)
3369 #define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_SET(x) (((x) << 3) & 0x000000f8)
3370 #define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_MSB 10
3371 #define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_LSB 8
3372 #define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_MASK 0x00000700
3373 #define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_GET(x) (((x) & 0x00000700) >> 8)
3374 #define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_SET(x) (((x) << 8) & 0x00000700)
3375 #define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_MSB 15
3376 #define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_LSB 11
3377 #define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_MASK 0x0000f800
3378 #define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_GET(x) (((x) & 0x0000f800) >> 11)
3379 #define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_SET(x) (((x) << 11) & 0x0000f800)
3380 #define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_MSB 20
3381 #define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_LSB 16
3382 #define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_MASK 0x001f0000
3383 #define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_GET(x) (((x) & 0x001f0000) >> 16)
3384 #define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_SET(x) (((x) << 16) & 0x001f0000)
3385 #define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_MSB 23
3386 #define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_LSB 21
3387 #define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_MASK 0x00e00000
3388 #define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_GET(x) (((x) & 0x00e00000) >> 21)
3389 #define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_SET(x) (((x) << 21) & 0x00e00000)
3390 #define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_MSB 30
3391 #define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_LSB 24
3392 #define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_MASK 0x7f000000
3393 #define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_GET(x) (((x) & 0x7f000000) >> 24)
3394 #define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_SET(x) (((x) << 24) & 0x7f000000)
3395 #define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_MSB 31
3396 #define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_LSB 31
3397 #define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_MASK 0x80000000
3398 #define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_GET(x) (((x) & 0x80000000) >> 31)
3399 #define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_SET(x) (((x) << 31) & 0x80000000)
3401 /* macros for BB_bbb_rx_ctrl_2 */
3402 #define PHY_BB_BBB_RX_CTRL_2_ADDRESS 0x0000a214
3403 #define PHY_BB_BBB_RX_CTRL_2_OFFSET 0x0000a214
3404 #define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_MSB 5
3405 #define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_LSB 0
3406 #define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_MASK 0x0000003f
3407 #define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_GET(x) (((x) & 0x0000003f) >> 0)
3408 #define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_SET(x) (((x) << 0) & 0x0000003f)
3409 #define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_MSB 11
3410 #define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_LSB 6
3411 #define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_MASK 0x00000fc0
3412 #define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_GET(x) (((x) & 0x00000fc0) >> 6)
3413 #define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_SET(x) (((x) << 6) & 0x00000fc0)
3414 #define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_MSB 16
3415 #define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_LSB 12
3416 #define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_MASK 0x0001f000
3417 #define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_GET(x) (((x) & 0x0001f000) >> 12)
3418 #define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_SET(x) (((x) << 12) & 0x0001f000)
3419 #define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_MSB 21
3420 #define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_LSB 17
3421 #define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_MASK 0x003e0000
3422 #define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_GET(x) (((x) & 0x003e0000) >> 17)
3423 #define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_SET(x) (((x) << 17) & 0x003e0000)
3424 #define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_MSB 25
3425 #define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_LSB 22
3426 #define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_MASK 0x03c00000
3427 #define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_GET(x) (((x) & 0x03c00000) >> 22)
3428 #define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_SET(x) (((x) << 22) & 0x03c00000)
3429 #define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_MSB 31
3430 #define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_LSB 26
3431 #define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_MASK 0xfc000000
3432 #define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_GET(x) (((x) & 0xfc000000) >> 26)
3433 #define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_SET(x) (((x) << 26) & 0xfc000000)
3435 /* macros for BB_bbb_rx_ctrl_3 */
3436 #define PHY_BB_BBB_RX_CTRL_3_ADDRESS 0x0000a218
3437 #define PHY_BB_BBB_RX_CTRL_3_OFFSET 0x0000a218
3438 #define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_MSB 7
3439 #define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_LSB 0
3440 #define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_MASK 0x000000ff
3441 #define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_GET(x) (((x) & 0x000000ff) >> 0)
3442 #define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_SET(x) (((x) << 0) & 0x000000ff)
3443 #define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_MSB 15
3444 #define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_LSB 8
3445 #define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_MASK 0x0000ff00
3446 #define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_GET(x) (((x) & 0x0000ff00) >> 8)
3447 #define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_SET(x) (((x) << 8) & 0x0000ff00)
3448 #define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_MSB 23
3449 #define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_LSB 16
3450 #define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_MASK 0x00ff0000
3451 #define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_GET(x) (((x) & 0x00ff0000) >> 16)
3452 #define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_SET(x) (((x) << 16) & 0x00ff0000)
3454 /* macros for BB_bbb_rx_ctrl_4 */
3455 #define PHY_BB_BBB_RX_CTRL_4_ADDRESS 0x0000a21c
3456 #define PHY_BB_BBB_RX_CTRL_4_OFFSET 0x0000a21c
3457 #define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_MSB 3
3458 #define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_LSB 0
3459 #define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_MASK 0x0000000f
3460 #define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_GET(x) (((x) & 0x0000000f) >> 0)
3461 #define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_SET(x) (((x) << 0) & 0x0000000f)
3462 #define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_MSB 15
3463 #define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_LSB 4
3464 #define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_MASK 0x0000fff0
3465 #define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_GET(x) (((x) & 0x0000fff0) >> 4)
3466 #define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_SET(x) (((x) << 4) & 0x0000fff0)
3467 #define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_MSB 16
3468 #define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_LSB 16
3469 #define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_MASK 0x00010000
3470 #define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_GET(x) (((x) & 0x00010000) >> 16)
3471 #define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_SET(x) (((x) << 16) & 0x00010000)
3472 #define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_MSB 17
3473 #define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_LSB 17
3474 #define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_MASK 0x00020000
3475 #define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_GET(x) (((x) & 0x00020000) >> 17)
3476 #define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_SET(x) (((x) << 17) & 0x00020000)
3477 #define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_MSB 18
3478 #define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_LSB 18
3479 #define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_MASK 0x00040000
3480 #define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_GET(x) (((x) & 0x00040000) >> 18)
3481 #define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_SET(x) (((x) << 18) & 0x00040000)
3482 #define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_MSB 24
3483 #define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_LSB 19
3484 #define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_MASK 0x01f80000
3485 #define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_GET(x) (((x) & 0x01f80000) >> 19)
3486 #define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_SET(x) (((x) << 19) & 0x01f80000)
3487 #define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_MSB 30
3488 #define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_LSB 25
3489 #define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_MASK 0x7e000000
3490 #define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_GET(x) (((x) & 0x7e000000) >> 25)
3491 #define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_SET(x) (((x) << 25) & 0x7e000000)
3493 /* macros for BB_bbb_rx_ctrl_5 */
3494 #define PHY_BB_BBB_RX_CTRL_5_ADDRESS 0x0000a220
3495 #define PHY_BB_BBB_RX_CTRL_5_OFFSET 0x0000a220
3496 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_MSB 4
3497 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_LSB 0
3498 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_MASK 0x0000001f
3499 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_GET(x) (((x) & 0x0000001f) >> 0)
3500 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_SET(x) (((x) << 0) & 0x0000001f)
3501 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_MSB 9
3502 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_LSB 5
3503 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_MASK 0x000003e0
3504 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_GET(x) (((x) & 0x000003e0) >> 5)
3505 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_SET(x) (((x) << 5) & 0x000003e0)
3506 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_MSB 15
3507 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_LSB 10
3508 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_MASK 0x0000fc00
3509 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_GET(x) (((x) & 0x0000fc00) >> 10)
3510 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_SET(x) (((x) << 10) & 0x0000fc00)
3511 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_MSB 20
3512 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_LSB 16
3513 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_MASK 0x001f0000
3514 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_GET(x) (((x) & 0x001f0000) >> 16)
3515 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_SET(x) (((x) << 16) & 0x001f0000)
3516 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_MSB 26
3517 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_LSB 21
3518 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_MASK 0x07e00000
3519 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_GET(x) (((x) & 0x07e00000) >> 21)
3520 #define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_SET(x) (((x) << 21) & 0x07e00000)
3522 /* macros for BB_bbb_rx_ctrl_6 */
3523 #define PHY_BB_BBB_RX_CTRL_6_ADDRESS 0x0000a224
3524 #define PHY_BB_BBB_RX_CTRL_6_OFFSET 0x0000a224
3525 #define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_MSB 9
3526 #define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_LSB 0
3527 #define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_MASK 0x000003ff
3528 #define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_GET(x) (((x) & 0x000003ff) >> 0)
3529 #define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_SET(x) (((x) << 0) & 0x000003ff)
3530 #define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_MSB 10
3531 #define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_LSB 10
3532 #define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_MASK 0x00000400
3533 #define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_GET(x) (((x) & 0x00000400) >> 10)
3534 #define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_SET(x) (((x) << 10) & 0x00000400)
3535 #define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_MSB 20
3536 #define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_LSB 11
3537 #define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_MASK 0x001ff800
3538 #define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_GET(x) (((x) & 0x001ff800) >> 11)
3539 #define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_SET(x) (((x) << 11) & 0x001ff800)
3541 /* macros for BB_bbb_dagc_ctrl */
3542 #define PHY_BB_BBB_DAGC_CTRL_ADDRESS 0x0000a228
3543 #define PHY_BB_BBB_DAGC_CTRL_OFFSET 0x0000a228
3544 #define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_MSB 0
3545 #define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_LSB 0
3546 #define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_MASK 0x00000001
3547 #define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_GET(x) (((x) & 0x00000001) >> 0)
3548 #define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_SET(x) (((x) << 0) & 0x00000001)
3549 #define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_MSB 8
3550 #define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_LSB 1
3551 #define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_MASK 0x000001fe
3552 #define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_GET(x) (((x) & 0x000001fe) >> 1)
3553 #define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_SET(x) (((x) << 1) & 0x000001fe)
3554 #define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_MSB 9
3555 #define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_LSB 9
3556 #define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_MASK 0x00000200
3557 #define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_GET(x) (((x) & 0x00000200) >> 9)
3558 #define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_SET(x) (((x) << 9) & 0x00000200)
3559 #define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_MSB 16
3560 #define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_LSB 10
3561 #define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_MASK 0x0001fc00
3562 #define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_GET(x) (((x) & 0x0001fc00) >> 10)
3563 #define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_SET(x) (((x) << 10) & 0x0001fc00)
3564 #define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_MSB 17
3565 #define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_LSB 17
3566 #define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_MASK 0x00020000
3567 #define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_GET(x) (((x) & 0x00020000) >> 17)
3568 #define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_SET(x) (((x) << 17) & 0x00020000)
3569 #define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_MSB 23
3570 #define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_LSB 18
3571 #define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_MASK 0x00fc0000
3572 #define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_GET(x) (((x) & 0x00fc0000) >> 18)
3573 #define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_SET(x) (((x) << 18) & 0x00fc0000)
3574 #define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_MSB 27
3575 #define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_LSB 24
3576 #define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_MASK 0x0f000000
3577 #define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_GET(x) (((x) & 0x0f000000) >> 24)
3578 #define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_SET(x) (((x) << 24) & 0x0f000000)
3580 /* macros for BB_force_clken_cck */
3581 #define PHY_BB_FORCE_CLKEN_CCK_ADDRESS 0x0000a22c
3582 #define PHY_BB_FORCE_CLKEN_CCK_OFFSET 0x0000a22c
3583 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_MSB 0
3584 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_LSB 0
3585 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_MASK 0x00000001
3586 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_GET(x) (((x) & 0x00000001) >> 0)
3587 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_SET(x) (((x) << 0) & 0x00000001)
3588 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_MSB 1
3589 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_LSB 1
3590 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_MASK 0x00000002
3591 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_GET(x) (((x) & 0x00000002) >> 1)
3592 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_SET(x) (((x) << 1) & 0x00000002)
3593 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_MSB 2
3594 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_LSB 2
3595 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_MASK 0x00000004
3596 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_GET(x) (((x) & 0x00000004) >> 2)
3597 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_SET(x) (((x) << 2) & 0x00000004)
3598 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_MSB 3
3599 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_LSB 3
3600 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_MASK 0x00000008
3601 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_GET(x) (((x) & 0x00000008) >> 3)
3602 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_SET(x) (((x) << 3) & 0x00000008)
3603 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_MSB 4
3604 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_LSB 4
3605 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_MASK 0x00000010
3606 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_GET(x) (((x) & 0x00000010) >> 4)
3607 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_SET(x) (((x) << 4) & 0x00000010)
3608 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_MSB 5
3609 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_LSB 5
3610 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_MASK 0x00000020
3611 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_GET(x) (((x) & 0x00000020) >> 5)
3612 #define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_SET(x) (((x) << 5) & 0x00000020)
3614 /* macros for BB_rx_clear_delay */
3615 #define PHY_BB_RX_CLEAR_DELAY_ADDRESS 0x0000a230
3616 #define PHY_BB_RX_CLEAR_DELAY_OFFSET 0x0000a230
3617 #define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_MSB 9
3618 #define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_LSB 0
3619 #define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_MASK 0x000003ff
3620 #define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_GET(x) (((x) & 0x000003ff) >> 0)
3621 #define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_SET(x) (((x) << 0) & 0x000003ff)
3623 /* macros for BB_powertx_rate3 */
3624 #define PHY_BB_POWERTX_RATE3_ADDRESS 0x0000a234
3625 #define PHY_BB_POWERTX_RATE3_OFFSET 0x0000a234
3626 #define PHY_BB_POWERTX_RATE3_POWERTX_1L_MSB 5
3627 #define PHY_BB_POWERTX_RATE3_POWERTX_1L_LSB 0
3628 #define PHY_BB_POWERTX_RATE3_POWERTX_1L_MASK 0x0000003f
3629 #define PHY_BB_POWERTX_RATE3_POWERTX_1L_GET(x) (((x) & 0x0000003f) >> 0)
3630 #define PHY_BB_POWERTX_RATE3_POWERTX_1L_SET(x) (((x) << 0) & 0x0000003f)
3631 #define PHY_BB_POWERTX_RATE3_POWERTX_2L_MSB 21
3632 #define PHY_BB_POWERTX_RATE3_POWERTX_2L_LSB 16
3633 #define PHY_BB_POWERTX_RATE3_POWERTX_2L_MASK 0x003f0000
3634 #define PHY_BB_POWERTX_RATE3_POWERTX_2L_GET(x) (((x) & 0x003f0000) >> 16)
3635 #define PHY_BB_POWERTX_RATE3_POWERTX_2L_SET(x) (((x) << 16) & 0x003f0000)
3636 #define PHY_BB_POWERTX_RATE3_POWERTX_2S_MSB 29
3637 #define PHY_BB_POWERTX_RATE3_POWERTX_2S_LSB 24
3638 #define PHY_BB_POWERTX_RATE3_POWERTX_2S_MASK 0x3f000000
3639 #define PHY_BB_POWERTX_RATE3_POWERTX_2S_GET(x) (((x) & 0x3f000000) >> 24)
3640 #define PHY_BB_POWERTX_RATE3_POWERTX_2S_SET(x) (((x) << 24) & 0x3f000000)
3642 /* macros for BB_powertx_rate4 */
3643 #define PHY_BB_POWERTX_RATE4_ADDRESS 0x0000a238
3644 #define PHY_BB_POWERTX_RATE4_OFFSET 0x0000a238
3645 #define PHY_BB_POWERTX_RATE4_POWERTX_55L_MSB 5
3646 #define PHY_BB_POWERTX_RATE4_POWERTX_55L_LSB 0
3647 #define PHY_BB_POWERTX_RATE4_POWERTX_55L_MASK 0x0000003f
3648 #define PHY_BB_POWERTX_RATE4_POWERTX_55L_GET(x) (((x) & 0x0000003f) >> 0)
3649 #define PHY_BB_POWERTX_RATE4_POWERTX_55L_SET(x) (((x) << 0) & 0x0000003f)
3650 #define PHY_BB_POWERTX_RATE4_POWERTX_55S_MSB 13
3651 #define PHY_BB_POWERTX_RATE4_POWERTX_55S_LSB 8
3652 #define PHY_BB_POWERTX_RATE4_POWERTX_55S_MASK 0x00003f00
3653 #define PHY_BB_POWERTX_RATE4_POWERTX_55S_GET(x) (((x) & 0x00003f00) >> 8)
3654 #define PHY_BB_POWERTX_RATE4_POWERTX_55S_SET(x) (((x) << 8) & 0x00003f00)
3655 #define PHY_BB_POWERTX_RATE4_POWERTX_11L_MSB 21
3656 #define PHY_BB_POWERTX_RATE4_POWERTX_11L_LSB 16
3657 #define PHY_BB_POWERTX_RATE4_POWERTX_11L_MASK 0x003f0000
3658 #define PHY_BB_POWERTX_RATE4_POWERTX_11L_GET(x) (((x) & 0x003f0000) >> 16)
3659 #define PHY_BB_POWERTX_RATE4_POWERTX_11L_SET(x) (((x) << 16) & 0x003f0000)
3660 #define PHY_BB_POWERTX_RATE4_POWERTX_11S_MSB 29
3661 #define PHY_BB_POWERTX_RATE4_POWERTX_11S_LSB 24
3662 #define PHY_BB_POWERTX_RATE4_POWERTX_11S_MASK 0x3f000000
3663 #define PHY_BB_POWERTX_RATE4_POWERTX_11S_GET(x) (((x) & 0x3f000000) >> 24)
3664 #define PHY_BB_POWERTX_RATE4_POWERTX_11S_SET(x) (((x) << 24) & 0x3f000000)
3666 /* macros for BB_cck_spur_mit */
3667 #define PHY_BB_CCK_SPUR_MIT_ADDRESS 0x0000a240
3668 #define PHY_BB_CCK_SPUR_MIT_OFFSET 0x0000a240
3669 #define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_MSB 0
3670 #define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_LSB 0
3671 #define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_MASK 0x00000001
3672 #define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_GET(x) (((x) & 0x00000001) >> 0)
3673 #define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_SET(x) (((x) << 0) & 0x00000001)
3674 #define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_MSB 8
3675 #define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_LSB 1
3676 #define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_MASK 0x000001fe
3677 #define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_GET(x) (((x) & 0x000001fe) >> 1)
3678 #define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_SET(x) (((x) << 1) & 0x000001fe)
3679 #define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_MSB 28
3680 #define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_LSB 9
3681 #define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_MASK 0x1ffffe00
3682 #define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_GET(x) (((x) & 0x1ffffe00) >> 9)
3683 #define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_SET(x) (((x) << 9) & 0x1ffffe00)
3684 #define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_MSB 30
3685 #define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_LSB 29
3686 #define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_MASK 0x60000000
3687 #define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_GET(x) (((x) & 0x60000000) >> 29)
3688 #define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_SET(x) (((x) << 29) & 0x60000000)
3690 /* macros for BB_panic_watchdog_status */
3691 #define PHY_BB_PANIC_WATCHDOG_STATUS_ADDRESS 0x0000a244
3692 #define PHY_BB_PANIC_WATCHDOG_STATUS_OFFSET 0x0000a244
3693 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_MSB 2
3694 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_LSB 0
3695 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_MASK 0x00000007
3696 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_GET(x) (((x) & 0x00000007) >> 0)
3697 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_SET(x) (((x) << 0) & 0x00000007)
3698 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_MSB 3
3699 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_LSB 3
3700 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_MASK 0x00000008
3701 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_GET(x) (((x) & 0x00000008) >> 3)
3702 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_SET(x) (((x) << 3) & 0x00000008)
3703 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_MSB 7
3704 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_LSB 4
3705 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_MASK 0x000000f0
3706 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_GET(x) (((x) & 0x000000f0) >> 4)
3707 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_SET(x) (((x) << 4) & 0x000000f0)
3708 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_MSB 11
3709 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_LSB 8
3710 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_MASK 0x00000f00
3711 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_GET(x) (((x) & 0x00000f00) >> 8)
3712 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_SET(x) (((x) << 8) & 0x00000f00)
3713 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_MSB 15
3714 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_LSB 12
3715 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_MASK 0x0000f000
3716 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_GET(x) (((x) & 0x0000f000) >> 12)
3717 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_SET(x) (((x) << 12) & 0x0000f000)
3718 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_MSB 19
3719 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_LSB 16
3720 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_MASK 0x000f0000
3721 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_GET(x) (((x) & 0x000f0000) >> 16)
3722 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_SET(x) (((x) << 16) & 0x000f0000)
3723 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_MSB 23
3724 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_LSB 20
3725 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_MASK 0x00f00000
3726 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_GET(x) (((x) & 0x00f00000) >> 20)
3727 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_SET(x) (((x) << 20) & 0x00f00000)
3728 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_MSB 27
3729 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_LSB 24
3730 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_MASK 0x0f000000
3731 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_GET(x) (((x) & 0x0f000000) >> 24)
3732 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_SET(x) (((x) << 24) & 0x0f000000)
3733 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_MSB 31
3734 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_LSB 28
3735 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_MASK 0xf0000000
3736 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_GET(x) (((x) & 0xf0000000) >> 28)
3737 #define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_SET(x) (((x) << 28) & 0xf0000000)
3739 /* macros for BB_panic_watchdog_ctrl_1 */
3740 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_ADDRESS 0x0000a248
3741 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_OFFSET 0x0000a248
3742 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_MSB 0
3743 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_LSB 0
3744 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_MASK 0x00000001
3745 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_GET(x) (((x) & 0x00000001) >> 0)
3746 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_SET(x) (((x) << 0) & 0x00000001)
3747 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_MSB 1
3748 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_LSB 1
3749 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_MASK 0x00000002
3750 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_GET(x) (((x) & 0x00000002) >> 1)
3751 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_SET(x) (((x) << 1) & 0x00000002)
3752 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_MSB 15
3753 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_LSB 2
3754 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_MASK 0x0000fffc
3755 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_GET(x) (((x) & 0x0000fffc) >> 2)
3756 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_SET(x) (((x) << 2) & 0x0000fffc)
3757 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_MSB 31
3758 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_LSB 16
3759 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_MASK 0xffff0000
3760 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_GET(x) (((x) & 0xffff0000) >> 16)
3761 #define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_SET(x) (((x) << 16) & 0xffff0000)
3763 /* macros for BB_panic_watchdog_ctrl_2 */
3764 #define PHY_BB_PANIC_WATCHDOG_CTRL_2_ADDRESS 0x0000a24c
3765 #define PHY_BB_PANIC_WATCHDOG_CTRL_2_OFFSET 0x0000a24c
3766 #define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MSB 0
3767 #define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_LSB 0
3768 #define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MASK 0x00000001
3769 #define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_GET(x) (((x) & 0x00000001) >> 0)
3770 #define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_SET(x) (((x) << 0) & 0x00000001)
3771 #define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_MSB 1
3772 #define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_LSB 1
3773 #define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_MASK 0x00000002
3774 #define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_GET(x) (((x) & 0x00000002) >> 1)
3775 #define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_SET(x) (((x) << 1) & 0x00000002)
3776 #define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_MSB 2
3777 #define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_LSB 2
3778 #define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_MASK 0x00000004
3779 #define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_GET(x) (((x) & 0x00000004) >> 2)
3780 #define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_SET(x) (((x) << 2) & 0x00000004)
3782 /* macros for BB_iqcorr_ctrl_cck */
3783 #define PHY_BB_IQCORR_CTRL_CCK_ADDRESS 0x0000a250
3784 #define PHY_BB_IQCORR_CTRL_CCK_OFFSET 0x0000a250
3785 #define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_MSB 4
3786 #define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_LSB 0
3787 #define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_MASK 0x0000001f
3788 #define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_GET(x) (((x) & 0x0000001f) >> 0)
3789 #define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_SET(x) (((x) << 0) & 0x0000001f)
3790 #define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_MSB 10
3791 #define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_LSB 5
3792 #define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_MASK 0x000007e0
3793 #define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_GET(x) (((x) & 0x000007e0) >> 5)
3794 #define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_SET(x) (((x) << 5) & 0x000007e0)
3795 #define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_MSB 11
3796 #define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_LSB 11
3797 #define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_MASK 0x00000800
3798 #define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_GET(x) (((x) & 0x00000800) >> 11)
3799 #define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_SET(x) (((x) << 11) & 0x00000800)
3800 #define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_MSB 13
3801 #define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_LSB 12
3802 #define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_MASK 0x00003000
3803 #define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_GET(x) (((x) & 0x00003000) >> 12)
3804 #define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_SET(x) (((x) << 12) & 0x00003000)
3805 #define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_MSB 15
3806 #define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_LSB 14
3807 #define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_MASK 0x0000c000
3808 #define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_GET(x) (((x) & 0x0000c000) >> 14)
3809 #define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_SET(x) (((x) << 14) & 0x0000c000)
3810 #define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_MSB 20
3811 #define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_LSB 16
3812 #define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_MASK 0x001f0000
3813 #define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_GET(x) (((x) & 0x001f0000) >> 16)
3814 #define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_SET(x) (((x) << 16) & 0x001f0000)
3815 #define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_MSB 21
3816 #define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_LSB 21
3817 #define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_MASK 0x00200000
3818 #define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_GET(x) (((x) & 0x00200000) >> 21)
3819 #define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_SET(x) (((x) << 21) & 0x00200000)
3821 /* macros for BB_bluetooth_cntl */
3822 #define PHY_BB_BLUETOOTH_CNTL_ADDRESS 0x0000a254
3823 #define PHY_BB_BLUETOOTH_CNTL_OFFSET 0x0000a254
3824 #define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MSB 0
3825 #define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_LSB 0
3826 #define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MASK 0x00000001
3827 #define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_GET(x) (((x) & 0x00000001) >> 0)
3828 #define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_SET(x) (((x) << 0) & 0x00000001)
3829 #define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MSB 1
3830 #define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_LSB 1
3831 #define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MASK 0x00000002
3832 #define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_GET(x) (((x) & 0x00000002) >> 1)
3833 #define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_SET(x) (((x) << 1) & 0x00000002)
3835 /* macros for BB_tpc_1 */
3836 #define PHY_BB_TPC_1_ADDRESS 0x0000a258
3837 #define PHY_BB_TPC_1_OFFSET 0x0000a258
3838 #define PHY_BB_TPC_1_FORCE_DAC_GAIN_MSB 0
3839 #define PHY_BB_TPC_1_FORCE_DAC_GAIN_LSB 0
3840 #define PHY_BB_TPC_1_FORCE_DAC_GAIN_MASK 0x00000001
3841 #define PHY_BB_TPC_1_FORCE_DAC_GAIN_GET(x) (((x) & 0x00000001) >> 0)
3842 #define PHY_BB_TPC_1_FORCE_DAC_GAIN_SET(x) (((x) << 0) & 0x00000001)
3843 #define PHY_BB_TPC_1_FORCED_DAC_GAIN_MSB 5
3844 #define PHY_BB_TPC_1_FORCED_DAC_GAIN_LSB 1
3845 #define PHY_BB_TPC_1_FORCED_DAC_GAIN_MASK 0x0000003e
3846 #define PHY_BB_TPC_1_FORCED_DAC_GAIN_GET(x) (((x) & 0x0000003e) >> 1)
3847 #define PHY_BB_TPC_1_FORCED_DAC_GAIN_SET(x) (((x) << 1) & 0x0000003e)
3848 #define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_MSB 13
3849 #define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_LSB 6
3850 #define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_MASK 0x00003fc0
3851 #define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_GET(x) (((x) & 0x00003fc0) >> 6)
3852 #define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_SET(x) (((x) << 6) & 0x00003fc0)
3853 #define PHY_BB_TPC_1_NUM_PD_GAIN_MSB 15
3854 #define PHY_BB_TPC_1_NUM_PD_GAIN_LSB 14
3855 #define PHY_BB_TPC_1_NUM_PD_GAIN_MASK 0x0000c000
3856 #define PHY_BB_TPC_1_NUM_PD_GAIN_GET(x) (((x) & 0x0000c000) >> 14)
3857 #define PHY_BB_TPC_1_NUM_PD_GAIN_SET(x) (((x) << 14) & 0x0000c000)
3858 #define PHY_BB_TPC_1_PD_GAIN_SETTING1_MSB 17
3859 #define PHY_BB_TPC_1_PD_GAIN_SETTING1_LSB 16
3860 #define PHY_BB_TPC_1_PD_GAIN_SETTING1_MASK 0x00030000
3861 #define PHY_BB_TPC_1_PD_GAIN_SETTING1_GET(x) (((x) & 0x00030000) >> 16)
3862 #define PHY_BB_TPC_1_PD_GAIN_SETTING1_SET(x) (((x) << 16) & 0x00030000)
3863 #define PHY_BB_TPC_1_PD_GAIN_SETTING2_MSB 19
3864 #define PHY_BB_TPC_1_PD_GAIN_SETTING2_LSB 18
3865 #define PHY_BB_TPC_1_PD_GAIN_SETTING2_MASK 0x000c0000
3866 #define PHY_BB_TPC_1_PD_GAIN_SETTING2_GET(x) (((x) & 0x000c0000) >> 18)
3867 #define PHY_BB_TPC_1_PD_GAIN_SETTING2_SET(x) (((x) << 18) & 0x000c0000)
3868 #define PHY_BB_TPC_1_PD_GAIN_SETTING3_MSB 21
3869 #define PHY_BB_TPC_1_PD_GAIN_SETTING3_LSB 20
3870 #define PHY_BB_TPC_1_PD_GAIN_SETTING3_MASK 0x00300000
3871 #define PHY_BB_TPC_1_PD_GAIN_SETTING3_GET(x) (((x) & 0x00300000) >> 20)
3872 #define PHY_BB_TPC_1_PD_GAIN_SETTING3_SET(x) (((x) << 20) & 0x00300000)
3873 #define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_MSB 22
3874 #define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_LSB 22
3875 #define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_MASK 0x00400000
3876 #define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_GET(x) (((x) & 0x00400000) >> 22)
3877 #define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_SET(x) (((x) << 22) & 0x00400000)
3878 #define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_MSB 28
3879 #define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_LSB 23
3880 #define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_MASK 0x1f800000
3881 #define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_GET(x) (((x) & 0x1f800000) >> 23)
3882 #define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_SET(x) (((x) << 23) & 0x1f800000)
3883 #define PHY_BB_TPC_1_FORCE_PDADC_GAIN_MSB 29
3884 #define PHY_BB_TPC_1_FORCE_PDADC_GAIN_LSB 29
3885 #define PHY_BB_TPC_1_FORCE_PDADC_GAIN_MASK 0x20000000
3886 #define PHY_BB_TPC_1_FORCE_PDADC_GAIN_GET(x) (((x) & 0x20000000) >> 29)
3887 #define PHY_BB_TPC_1_FORCE_PDADC_GAIN_SET(x) (((x) << 29) & 0x20000000)
3888 #define PHY_BB_TPC_1_FORCED_PDADC_GAIN_MSB 31
3889 #define PHY_BB_TPC_1_FORCED_PDADC_GAIN_LSB 30
3890 #define PHY_BB_TPC_1_FORCED_PDADC_GAIN_MASK 0xc0000000
3891 #define PHY_BB_TPC_1_FORCED_PDADC_GAIN_GET(x) (((x) & 0xc0000000) >> 30)
3892 #define PHY_BB_TPC_1_FORCED_PDADC_GAIN_SET(x) (((x) << 30) & 0xc0000000)
3894 /* macros for BB_tpc_2 */
3895 #define PHY_BB_TPC_2_ADDRESS 0x0000a25c
3896 #define PHY_BB_TPC_2_OFFSET 0x0000a25c
3897 #define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MSB 7
3898 #define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_LSB 0
3899 #define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MASK 0x000000ff
3900 #define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_GET(x) (((x) & 0x000000ff) >> 0)
3901 #define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_SET(x) (((x) << 0) & 0x000000ff)
3902 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MSB 15
3903 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_LSB 8
3904 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MASK 0x0000ff00
3905 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_GET(x) (((x) & 0x0000ff00) >> 8)
3906 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_SET(x) (((x) << 8) & 0x0000ff00)
3907 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MSB 23
3908 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_LSB 16
3909 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MASK 0x00ff0000
3910 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_GET(x) (((x) & 0x00ff0000) >> 16)
3911 #define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_SET(x) (((x) << 16) & 0x00ff0000)
3913 /* macros for BB_tpc_3 */
3914 #define PHY_BB_TPC_3_ADDRESS 0x0000a260
3915 #define PHY_BB_TPC_3_OFFSET 0x0000a260
3916 #define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MSB 7
3917 #define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_LSB 0
3918 #define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MASK 0x000000ff
3919 #define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_GET(x) (((x) & 0x000000ff) >> 0)
3920 #define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_SET(x) (((x) << 0) & 0x000000ff)
3921 #define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MSB 15
3922 #define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_LSB 8
3923 #define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MASK 0x0000ff00
3924 #define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_GET(x) (((x) & 0x0000ff00) >> 8)
3925 #define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_SET(x) (((x) << 8) & 0x0000ff00)
3926 #define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_MSB 18
3927 #define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_LSB 16
3928 #define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_MASK 0x00070000
3929 #define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_GET(x) (((x) & 0x00070000) >> 16)
3930 #define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_SET(x) (((x) << 16) & 0x00070000)
3931 #define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_MSB 21
3932 #define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_LSB 19
3933 #define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_MASK 0x00380000
3934 #define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_GET(x) (((x) & 0x00380000) >> 19)
3935 #define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_SET(x) (((x) << 19) & 0x00380000)
3936 #define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MSB 24
3937 #define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_LSB 22
3938 #define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MASK 0x01c00000
3939 #define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_GET(x) (((x) & 0x01c00000) >> 22)
3940 #define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_SET(x) (((x) << 22) & 0x01c00000)
3941 #define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MSB 27
3942 #define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_LSB 25
3943 #define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MASK 0x0e000000
3944 #define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_GET(x) (((x) & 0x0e000000) >> 25)
3945 #define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_SET(x) (((x) << 25) & 0x0e000000)
3946 #define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MSB 31
3947 #define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_LSB 31
3948 #define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MASK 0x80000000
3949 #define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_GET(x) (((x) & 0x80000000) >> 31)
3950 #define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_SET(x) (((x) << 31) & 0x80000000)
3952 /* macros for BB_tpc_4_b0 */
3953 #define PHY_BB_TPC_4_B0_ADDRESS 0x0000a264
3954 #define PHY_BB_TPC_4_B0_OFFSET 0x0000a264
3955 #define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_MSB 0
3956 #define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_LSB 0
3957 #define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_MASK 0x00000001
3958 #define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_GET(x) (((x) & 0x00000001) >> 0)
3959 #define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_MSB 8
3960 #define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_LSB 1
3961 #define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_MASK 0x000001fe
3962 #define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_GET(x) (((x) & 0x000001fe) >> 1)
3963 #define PHY_BB_TPC_4_B0_DAC_GAIN_0_MSB 13
3964 #define PHY_BB_TPC_4_B0_DAC_GAIN_0_LSB 9
3965 #define PHY_BB_TPC_4_B0_DAC_GAIN_0_MASK 0x00003e00
3966 #define PHY_BB_TPC_4_B0_DAC_GAIN_0_GET(x) (((x) & 0x00003e00) >> 9)
3967 #define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_MSB 19
3968 #define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_LSB 14
3969 #define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_MASK 0x000fc000
3970 #define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_GET(x) (((x) & 0x000fc000) >> 14)
3971 #define PHY_BB_TPC_4_B0_RATE_SENT_0_MSB 24
3972 #define PHY_BB_TPC_4_B0_RATE_SENT_0_LSB 20
3973 #define PHY_BB_TPC_4_B0_RATE_SENT_0_MASK 0x01f00000
3974 #define PHY_BB_TPC_4_B0_RATE_SENT_0_GET(x) (((x) & 0x01f00000) >> 20)
3975 #define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_MSB 30
3976 #define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_LSB 25
3977 #define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_MASK 0x7e000000
3978 #define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_GET(x) (((x) & 0x7e000000) >> 25)
3979 #define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_SET(x) (((x) << 25) & 0x7e000000)
3981 /* macros for BB_analog_swap */
3982 #define PHY_BB_ANALOG_SWAP_ADDRESS 0x0000a268
3983 #define PHY_BB_ANALOG_SWAP_OFFSET 0x0000a268
3984 #define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MSB 2
3985 #define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_LSB 0
3986 #define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MASK 0x00000007
3987 #define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_GET(x) (((x) & 0x00000007) >> 0)
3988 #define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_SET(x) (((x) << 0) & 0x00000007)
3989 #define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MSB 5
3990 #define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_LSB 3
3991 #define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MASK 0x00000038
3992 #define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_GET(x) (((x) & 0x00000038) >> 3)
3993 #define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_SET(x) (((x) << 3) & 0x00000038)
3994 #define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MSB 6
3995 #define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_LSB 6
3996 #define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MASK 0x00000040
3997 #define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_GET(x) (((x) & 0x00000040) >> 6)
3998 #define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_SET(x) (((x) << 6) & 0x00000040)
3999 #define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MSB 7
4000 #define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_LSB 7
4001 #define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MASK 0x00000080
4002 #define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_GET(x) (((x) & 0x00000080) >> 7)
4003 #define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_SET(x) (((x) << 7) & 0x00000080)
4004 #define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MSB 8
4005 #define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_LSB 8
4006 #define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MASK 0x00000100
4007 #define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_GET(x) (((x) & 0x00000100) >> 8)
4008 #define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_SET(x) (((x) << 8) & 0x00000100)
4010 /* macros for BB_tpc_5_b0 */
4011 #define PHY_BB_TPC_5_B0_ADDRESS 0x0000a26c
4012 #define PHY_BB_TPC_5_B0_OFFSET 0x0000a26c
4013 #define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_MSB 3
4014 #define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_LSB 0
4015 #define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_MASK 0x0000000f
4016 #define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_GET(x) (((x) & 0x0000000f) >> 0)
4017 #define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_SET(x) (((x) << 0) & 0x0000000f)
4018 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_MSB 9
4019 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_LSB 4
4020 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_MASK 0x000003f0
4021 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_GET(x) (((x) & 0x000003f0) >> 4)
4022 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_SET(x) (((x) << 4) & 0x000003f0)
4023 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_MSB 15
4024 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_LSB 10
4025 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_MASK 0x0000fc00
4026 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_GET(x) (((x) & 0x0000fc00) >> 10)
4027 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_SET(x) (((x) << 10) & 0x0000fc00)
4028 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_MSB 21
4029 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_LSB 16
4030 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_MASK 0x003f0000
4031 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_GET(x) (((x) & 0x003f0000) >> 16)
4032 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_SET(x) (((x) << 16) & 0x003f0000)
4033 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_MSB 27
4034 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_LSB 22
4035 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_MASK 0x0fc00000
4036 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_GET(x) (((x) & 0x0fc00000) >> 22)
4037 #define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_SET(x) (((x) << 22) & 0x0fc00000)
4039 /* macros for BB_tpc_6_b0 */
4040 #define PHY_BB_TPC_6_B0_ADDRESS 0x0000a270
4041 #define PHY_BB_TPC_6_B0_OFFSET 0x0000a270
4042 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_MSB 5
4043 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_LSB 0
4044 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_MASK 0x0000003f
4045 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_GET(x) (((x) & 0x0000003f) >> 0)
4046 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_SET(x) (((x) << 0) & 0x0000003f)
4047 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_MSB 11
4048 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_LSB 6
4049 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_MASK 0x00000fc0
4050 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_GET(x) (((x) & 0x00000fc0) >> 6)
4051 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_SET(x) (((x) << 6) & 0x00000fc0)
4052 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_MSB 17
4053 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_LSB 12
4054 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_MASK 0x0003f000
4055 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_GET(x) (((x) & 0x0003f000) >> 12)
4056 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_SET(x) (((x) << 12) & 0x0003f000)
4057 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_MSB 23
4058 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_LSB 18
4059 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_MASK 0x00fc0000
4060 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_GET(x) (((x) & 0x00fc0000) >> 18)
4061 #define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_SET(x) (((x) << 18) & 0x00fc0000)
4062 #define PHY_BB_TPC_6_B0_ERROR_EST_MODE_MSB 25
4063 #define PHY_BB_TPC_6_B0_ERROR_EST_MODE_LSB 24
4064 #define PHY_BB_TPC_6_B0_ERROR_EST_MODE_MASK 0x03000000
4065 #define PHY_BB_TPC_6_B0_ERROR_EST_MODE_GET(x) (((x) & 0x03000000) >> 24)
4066 #define PHY_BB_TPC_6_B0_ERROR_EST_MODE_SET(x) (((x) << 24) & 0x03000000)
4067 #define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_MSB 28
4068 #define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_LSB 26
4069 #define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_MASK 0x1c000000
4070 #define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_GET(x) (((x) & 0x1c000000) >> 26)
4071 #define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_SET(x) (((x) << 26) & 0x1c000000)
4073 /* macros for BB_tpc_7 */
4074 #define PHY_BB_TPC_7_ADDRESS 0x0000a274
4075 #define PHY_BB_TPC_7_OFFSET 0x0000a274
4076 #define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MSB 5
4077 #define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_LSB 0
4078 #define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MASK 0x0000003f
4079 #define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_GET(x) (((x) & 0x0000003f) >> 0)
4080 #define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_SET(x) (((x) << 0) & 0x0000003f)
4081 #define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_MSB 11
4082 #define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_LSB 6
4083 #define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_MASK 0x00000fc0
4084 #define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_GET(x) (((x) & 0x00000fc0) >> 6)
4085 #define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_SET(x) (((x) << 6) & 0x00000fc0)
4086 #define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MSB 12
4087 #define PHY_BB_TPC_7_EN_CL_GAIN_MOD_LSB 12
4088 #define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MASK 0x00001000
4089 #define PHY_BB_TPC_7_EN_CL_GAIN_MOD_GET(x) (((x) & 0x00001000) >> 12)
4090 #define PHY_BB_TPC_7_EN_CL_GAIN_MOD_SET(x) (((x) << 12) & 0x00001000)
4091 #define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MSB 13
4092 #define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_LSB 13
4093 #define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MASK 0x00002000
4094 #define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_GET(x) (((x) & 0x00002000) >> 13)
4095 #define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_SET(x) (((x) << 13) & 0x00002000)
4096 #define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MSB 14
4097 #define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_LSB 14
4098 #define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MASK 0x00004000
4099 #define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_GET(x) (((x) & 0x00004000) >> 14)
4100 #define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_SET(x) (((x) << 14) & 0x00004000)
4101 #define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MSB 15
4102 #define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_LSB 15
4103 #define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MASK 0x00008000
4104 #define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_GET(x) (((x) & 0x00008000) >> 15)
4105 #define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_SET(x) (((x) << 15) & 0x00008000)
4107 /* macros for BB_tpc_8 */
4108 #define PHY_BB_TPC_8_ADDRESS 0x0000a278
4109 #define PHY_BB_TPC_8_OFFSET 0x0000a278
4110 #define PHY_BB_TPC_8_DESIRED_SCALE_0_MSB 4
4111 #define PHY_BB_TPC_8_DESIRED_SCALE_0_LSB 0
4112 #define PHY_BB_TPC_8_DESIRED_SCALE_0_MASK 0x0000001f
4113 #define PHY_BB_TPC_8_DESIRED_SCALE_0_GET(x) (((x) & 0x0000001f) >> 0)
4114 #define PHY_BB_TPC_8_DESIRED_SCALE_0_SET(x) (((x) << 0) & 0x0000001f)
4115 #define PHY_BB_TPC_8_DESIRED_SCALE_1_MSB 9
4116 #define PHY_BB_TPC_8_DESIRED_SCALE_1_LSB 5
4117 #define PHY_BB_TPC_8_DESIRED_SCALE_1_MASK 0x000003e0
4118 #define PHY_BB_TPC_8_DESIRED_SCALE_1_GET(x) (((x) & 0x000003e0) >> 5)
4119 #define PHY_BB_TPC_8_DESIRED_SCALE_1_SET(x) (((x) << 5) & 0x000003e0)
4120 #define PHY_BB_TPC_8_DESIRED_SCALE_2_MSB 14
4121 #define PHY_BB_TPC_8_DESIRED_SCALE_2_LSB 10
4122 #define PHY_BB_TPC_8_DESIRED_SCALE_2_MASK 0x00007c00
4123 #define PHY_BB_TPC_8_DESIRED_SCALE_2_GET(x) (((x) & 0x00007c00) >> 10)
4124 #define PHY_BB_TPC_8_DESIRED_SCALE_2_SET(x) (((x) << 10) & 0x00007c00)
4125 #define PHY_BB_TPC_8_DESIRED_SCALE_3_MSB 19
4126 #define PHY_BB_TPC_8_DESIRED_SCALE_3_LSB 15
4127 #define PHY_BB_TPC_8_DESIRED_SCALE_3_MASK 0x000f8000
4128 #define PHY_BB_TPC_8_DESIRED_SCALE_3_GET(x) (((x) & 0x000f8000) >> 15)
4129 #define PHY_BB_TPC_8_DESIRED_SCALE_3_SET(x) (((x) << 15) & 0x000f8000)
4130 #define PHY_BB_TPC_8_DESIRED_SCALE_4_MSB 24
4131 #define PHY_BB_TPC_8_DESIRED_SCALE_4_LSB 20
4132 #define PHY_BB_TPC_8_DESIRED_SCALE_4_MASK 0x01f00000
4133 #define PHY_BB_TPC_8_DESIRED_SCALE_4_GET(x) (((x) & 0x01f00000) >> 20)
4134 #define PHY_BB_TPC_8_DESIRED_SCALE_4_SET(x) (((x) << 20) & 0x01f00000)
4135 #define PHY_BB_TPC_8_DESIRED_SCALE_5_MSB 29
4136 #define PHY_BB_TPC_8_DESIRED_SCALE_5_LSB 25
4137 #define PHY_BB_TPC_8_DESIRED_SCALE_5_MASK 0x3e000000
4138 #define PHY_BB_TPC_8_DESIRED_SCALE_5_GET(x) (((x) & 0x3e000000) >> 25)
4139 #define PHY_BB_TPC_8_DESIRED_SCALE_5_SET(x) (((x) << 25) & 0x3e000000)
4141 /* macros for BB_tpc_9 */
4142 #define PHY_BB_TPC_9_ADDRESS 0x0000a27c
4143 #define PHY_BB_TPC_9_OFFSET 0x0000a27c
4144 #define PHY_BB_TPC_9_DESIRED_SCALE_6_MSB 4
4145 #define PHY_BB_TPC_9_DESIRED_SCALE_6_LSB 0
4146 #define PHY_BB_TPC_9_DESIRED_SCALE_6_MASK 0x0000001f
4147 #define PHY_BB_TPC_9_DESIRED_SCALE_6_GET(x) (((x) & 0x0000001f) >> 0)
4148 #define PHY_BB_TPC_9_DESIRED_SCALE_6_SET(x) (((x) << 0) & 0x0000001f)
4149 #define PHY_BB_TPC_9_DESIRED_SCALE_7_MSB 9
4150 #define PHY_BB_TPC_9_DESIRED_SCALE_7_LSB 5
4151 #define PHY_BB_TPC_9_DESIRED_SCALE_7_MASK 0x000003e0
4152 #define PHY_BB_TPC_9_DESIRED_SCALE_7_GET(x) (((x) & 0x000003e0) >> 5)
4153 #define PHY_BB_TPC_9_DESIRED_SCALE_7_SET(x) (((x) << 5) & 0x000003e0)
4154 #define PHY_BB_TPC_9_DESIRED_SCALE_CCK_MSB 14
4155 #define PHY_BB_TPC_9_DESIRED_SCALE_CCK_LSB 10
4156 #define PHY_BB_TPC_9_DESIRED_SCALE_CCK_MASK 0x00007c00
4157 #define PHY_BB_TPC_9_DESIRED_SCALE_CCK_GET(x) (((x) & 0x00007c00) >> 10)
4158 #define PHY_BB_TPC_9_DESIRED_SCALE_CCK_SET(x) (((x) << 10) & 0x00007c00)
4159 #define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_MSB 20
4160 #define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_LSB 20
4161 #define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_MASK 0x00100000
4162 #define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_GET(x) (((x) & 0x00100000) >> 20)
4163 #define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_SET(x) (((x) << 20) & 0x00100000)
4164 #define PHY_BB_TPC_9_PD_DC_OFFSET_THR_MSB 26
4165 #define PHY_BB_TPC_9_PD_DC_OFFSET_THR_LSB 21
4166 #define PHY_BB_TPC_9_PD_DC_OFFSET_THR_MASK 0x07e00000
4167 #define PHY_BB_TPC_9_PD_DC_OFFSET_THR_GET(x) (((x) & 0x07e00000) >> 21)
4168 #define PHY_BB_TPC_9_PD_DC_OFFSET_THR_SET(x) (((x) << 21) & 0x07e00000)
4169 #define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MSB 30
4170 #define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_LSB 27
4171 #define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MASK 0x78000000
4172 #define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_GET(x) (((x) & 0x78000000) >> 27)
4173 #define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_SET(x) (((x) << 27) & 0x78000000)
4174 #define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_MSB 31
4175 #define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_LSB 31
4176 #define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_MASK 0x80000000
4177 #define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_GET(x) (((x) & 0x80000000) >> 31)
4178 #define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_SET(x) (((x) << 31) & 0x80000000)
4180 /* macros for BB_pdadc_tab_b0 */
4181 #define PHY_BB_PDADC_TAB_B0_ADDRESS 0x0000a280
4182 #define PHY_BB_PDADC_TAB_B0_OFFSET 0x0000a280
4183 #define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_MSB 31
4184 #define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_LSB 0
4185 #define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_MASK 0xffffffff
4186 #define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_SET(x) (((x) << 0) & 0xffffffff)
4188 /* macros for BB_cl_tab_b0 */
4189 #define PHY_BB_CL_TAB_B0_ADDRESS 0x0000a300
4190 #define PHY_BB_CL_TAB_B0_OFFSET 0x0000a300
4191 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MSB 4
4192 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_LSB 0
4193 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MASK 0x0000001f
4194 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_GET(x) (((x) & 0x0000001f) >> 0)
4195 #define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_SET(x) (((x) << 0) & 0x0000001f)
4196 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MSB 15
4197 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_LSB 5
4198 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MASK 0x0000ffe0
4199 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_GET(x) (((x) & 0x0000ffe0) >> 5)
4200 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_SET(x) (((x) << 5) & 0x0000ffe0)
4201 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MSB 26
4202 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_LSB 16
4203 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MASK 0x07ff0000
4204 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_GET(x) (((x) & 0x07ff0000) >> 16)
4205 #define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_SET(x) (((x) << 16) & 0x07ff0000)
4206 #define PHY_BB_CL_TAB_B0_BB_GAIN_MSB 30
4207 #define PHY_BB_CL_TAB_B0_BB_GAIN_LSB 27
4208 #define PHY_BB_CL_TAB_B0_BB_GAIN_MASK 0x78000000
4209 #define PHY_BB_CL_TAB_B0_BB_GAIN_GET(x) (((x) & 0x78000000) >> 27)
4210 #define PHY_BB_CL_TAB_B0_BB_GAIN_SET(x) (((x) << 27) & 0x78000000)
4212 /* macros for BB_cl_map_0_b0 */
4213 #define PHY_BB_CL_MAP_0_B0_ADDRESS 0x0000a340
4214 #define PHY_BB_CL_MAP_0_B0_OFFSET 0x0000a340
4215 #define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MSB 31
4216 #define PHY_BB_CL_MAP_0_B0_CL_MAP_0_LSB 0
4217 #define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MASK 0xffffffff
4218 #define PHY_BB_CL_MAP_0_B0_CL_MAP_0_GET(x) (((x) & 0xffffffff) >> 0)
4219 #define PHY_BB_CL_MAP_0_B0_CL_MAP_0_SET(x) (((x) << 0) & 0xffffffff)
4221 /* macros for BB_cl_map_1_b0 */
4222 #define PHY_BB_CL_MAP_1_B0_ADDRESS 0x0000a344
4223 #define PHY_BB_CL_MAP_1_B0_OFFSET 0x0000a344
4224 #define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MSB 31
4225 #define PHY_BB_CL_MAP_1_B0_CL_MAP_1_LSB 0
4226 #define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MASK 0xffffffff
4227 #define PHY_BB_CL_MAP_1_B0_CL_MAP_1_GET(x) (((x) & 0xffffffff) >> 0)
4228 #define PHY_BB_CL_MAP_1_B0_CL_MAP_1_SET(x) (((x) << 0) & 0xffffffff)
4230 /* macros for BB_cl_map_2_b0 */
4231 #define PHY_BB_CL_MAP_2_B0_ADDRESS 0x0000a348
4232 #define PHY_BB_CL_MAP_2_B0_OFFSET 0x0000a348
4233 #define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MSB 31
4234 #define PHY_BB_CL_MAP_2_B0_CL_MAP_2_LSB 0
4235 #define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MASK 0xffffffff
4236 #define PHY_BB_CL_MAP_2_B0_CL_MAP_2_GET(x) (((x) & 0xffffffff) >> 0)
4237 #define PHY_BB_CL_MAP_2_B0_CL_MAP_2_SET(x) (((x) << 0) & 0xffffffff)
4239 /* macros for BB_cl_map_3_b0 */
4240 #define PHY_BB_CL_MAP_3_B0_ADDRESS 0x0000a34c
4241 #define PHY_BB_CL_MAP_3_B0_OFFSET 0x0000a34c
4242 #define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MSB 31
4243 #define PHY_BB_CL_MAP_3_B0_CL_MAP_3_LSB 0
4244 #define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MASK 0xffffffff
4245 #define PHY_BB_CL_MAP_3_B0_CL_MAP_3_GET(x) (((x) & 0xffffffff) >> 0)
4246 #define PHY_BB_CL_MAP_3_B0_CL_MAP_3_SET(x) (((x) << 0) & 0xffffffff)
4248 /* macros for BB_cl_cal_ctrl */
4249 #define PHY_BB_CL_CAL_CTRL_ADDRESS 0x0000a358
4250 #define PHY_BB_CL_CAL_CTRL_OFFSET 0x0000a358
4251 #define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MSB 0
4252 #define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_LSB 0
4253 #define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MASK 0x00000001
4254 #define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_GET(x) (((x) & 0x00000001) >> 0)
4255 #define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_SET(x) (((x) << 0) & 0x00000001)
4256 #define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MSB 1
4257 #define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_LSB 1
4258 #define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MASK 0x00000002
4259 #define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_GET(x) (((x) & 0x00000002) >> 1)
4260 #define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_SET(x) (((x) << 1) & 0x00000002)
4261 #define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MSB 3
4262 #define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_LSB 2
4263 #define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MASK 0x0000000c
4264 #define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_GET(x) (((x) & 0x0000000c) >> 2)
4265 #define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_SET(x) (((x) << 2) & 0x0000000c)
4266 #define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MSB 7
4267 #define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_LSB 4
4268 #define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MASK 0x000000f0
4269 #define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_GET(x) (((x) & 0x000000f0) >> 4)
4270 #define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_SET(x) (((x) << 4) & 0x000000f0)
4271 #define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MSB 15
4272 #define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_LSB 8
4273 #define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MASK 0x0000ff00
4274 #define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_GET(x) (((x) & 0x0000ff00) >> 8)
4275 #define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_SET(x) (((x) << 8) & 0x0000ff00)
4276 #define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MSB 21
4277 #define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_LSB 16
4278 #define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MASK 0x003f0000
4279 #define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_GET(x) (((x) & 0x003f0000) >> 16)
4280 #define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_SET(x) (((x) << 16) & 0x003f0000)
4281 #define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MSB 29
4282 #define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_LSB 22
4283 #define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MASK 0x3fc00000
4284 #define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_GET(x) (((x) & 0x3fc00000) >> 22)
4285 #define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_SET(x) (((x) << 22) & 0x3fc00000)
4286 #define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MSB 30
4287 #define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_LSB 30
4288 #define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MASK 0x40000000
4289 #define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_GET(x) (((x) & 0x40000000) >> 30)
4290 #define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_SET(x) (((x) << 30) & 0x40000000)
4291 #define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MSB 31
4292 #define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_LSB 31
4293 #define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MASK 0x80000000
4294 #define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_GET(x) (((x) & 0x80000000) >> 31)
4295 #define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_SET(x) (((x) << 31) & 0x80000000)
4297 /* macros for BB_cl_map_pal_0_b0 */
4298 #define PHY_BB_CL_MAP_PAL_0_B0_ADDRESS 0x0000a35c
4299 #define PHY_BB_CL_MAP_PAL_0_B0_OFFSET 0x0000a35c
4300 #define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_MSB 31
4301 #define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_LSB 0
4302 #define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_MASK 0xffffffff
4303 #define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_GET(x) (((x) & 0xffffffff) >> 0)
4304 #define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_SET(x) (((x) << 0) & 0xffffffff)
4306 /* macros for BB_cl_map_pal_1_b0 */
4307 #define PHY_BB_CL_MAP_PAL_1_B0_ADDRESS 0x0000a360
4308 #define PHY_BB_CL_MAP_PAL_1_B0_OFFSET 0x0000a360
4309 #define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_MSB 31
4310 #define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_LSB 0
4311 #define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_MASK 0xffffffff
4312 #define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_GET(x) (((x) & 0xffffffff) >> 0)
4313 #define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_SET(x) (((x) << 0) & 0xffffffff)
4315 /* macros for BB_cl_map_pal_2_b0 */
4316 #define PHY_BB_CL_MAP_PAL_2_B0_ADDRESS 0x0000a364
4317 #define PHY_BB_CL_MAP_PAL_2_B0_OFFSET 0x0000a364
4318 #define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_MSB 31
4319 #define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_LSB 0
4320 #define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_MASK 0xffffffff
4321 #define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_GET(x) (((x) & 0xffffffff) >> 0)
4322 #define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_SET(x) (((x) << 0) & 0xffffffff)
4324 /* macros for BB_cl_map_pal_3_b0 */
4325 #define PHY_BB_CL_MAP_PAL_3_B0_ADDRESS 0x0000a368
4326 #define PHY_BB_CL_MAP_PAL_3_B0_OFFSET 0x0000a368
4327 #define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_MSB 31
4328 #define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_LSB 0
4329 #define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_MASK 0xffffffff
4330 #define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_GET(x) (((x) & 0xffffffff) >> 0)
4331 #define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_SET(x) (((x) << 0) & 0xffffffff)
4333 /* macros for BB_rifs */
4334 #define PHY_BB_RIFS_ADDRESS 0x0000a388
4335 #define PHY_BB_RIFS_OFFSET 0x0000a388
4336 #define PHY_BB_RIFS_DISABLE_FCC_FIX_MSB 25
4337 #define PHY_BB_RIFS_DISABLE_FCC_FIX_LSB 25
4338 #define PHY_BB_RIFS_DISABLE_FCC_FIX_MASK 0x02000000
4339 #define PHY_BB_RIFS_DISABLE_FCC_FIX_GET(x) (((x) & 0x02000000) >> 25)
4340 #define PHY_BB_RIFS_DISABLE_FCC_FIX_SET(x) (((x) << 25) & 0x02000000)
4341 #define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MSB 26
4342 #define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_LSB 26
4343 #define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MASK 0x04000000
4344 #define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_GET(x) (((x) & 0x04000000) >> 26)
4345 #define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_SET(x) (((x) << 26) & 0x04000000)
4346 #define PHY_BB_RIFS_DISABLE_FCC_FIX2_MSB 27
4347 #define PHY_BB_RIFS_DISABLE_FCC_FIX2_LSB 27
4348 #define PHY_BB_RIFS_DISABLE_FCC_FIX2_MASK 0x08000000
4349 #define PHY_BB_RIFS_DISABLE_FCC_FIX2_GET(x) (((x) & 0x08000000) >> 27)
4350 #define PHY_BB_RIFS_DISABLE_FCC_FIX2_SET(x) (((x) << 27) & 0x08000000)
4351 #define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_MSB 28
4352 #define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_LSB 28
4353 #define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_MASK 0x10000000
4354 #define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_GET(x) (((x) & 0x10000000) >> 28)
4355 #define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_SET(x) (((x) << 28) & 0x10000000)
4356 #define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_MSB 29
4357 #define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_LSB 29
4358 #define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_MASK 0x20000000
4359 #define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_GET(x) (((x) & 0x20000000) >> 29)
4360 #define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_SET(x) (((x) << 29) & 0x20000000)
4361 #define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_MSB 30
4362 #define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_LSB 30
4363 #define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_MASK 0x40000000
4364 #define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_GET(x) (((x) & 0x40000000) >> 30)
4365 #define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_SET(x) (((x) << 30) & 0x40000000)
4367 /* macros for BB_powertx_rate5 */
4368 #define PHY_BB_POWERTX_RATE5_ADDRESS 0x0000a38c
4369 #define PHY_BB_POWERTX_RATE5_OFFSET 0x0000a38c
4370 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_MSB 5
4371 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_LSB 0
4372 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_MASK 0x0000003f
4373 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_GET(x) (((x) & 0x0000003f) >> 0)
4374 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_SET(x) (((x) << 0) & 0x0000003f)
4375 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_MSB 13
4376 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_LSB 8
4377 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_MASK 0x00003f00
4378 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_GET(x) (((x) & 0x00003f00) >> 8)
4379 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_SET(x) (((x) << 8) & 0x00003f00)
4380 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_MSB 21
4381 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_LSB 16
4382 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_MASK 0x003f0000
4383 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_GET(x) (((x) & 0x003f0000) >> 16)
4384 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_SET(x) (((x) << 16) & 0x003f0000)
4385 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_MSB 29
4386 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_LSB 24
4387 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_MASK 0x3f000000
4388 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_GET(x) (((x) & 0x3f000000) >> 24)
4389 #define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_SET(x) (((x) << 24) & 0x3f000000)
4391 /* macros for BB_powertx_rate6 */
4392 #define PHY_BB_POWERTX_RATE6_ADDRESS 0x0000a390
4393 #define PHY_BB_POWERTX_RATE6_OFFSET 0x0000a390
4394 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_MSB 5
4395 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_LSB 0
4396 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_MASK 0x0000003f
4397 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_GET(x) (((x) & 0x0000003f) >> 0)
4398 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_SET(x) (((x) << 0) & 0x0000003f)
4399 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_MSB 13
4400 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_LSB 8
4401 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_MASK 0x00003f00
4402 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_GET(x) (((x) & 0x00003f00) >> 8)
4403 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_SET(x) (((x) << 8) & 0x00003f00)
4404 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_MSB 21
4405 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_LSB 16
4406 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_MASK 0x003f0000
4407 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_GET(x) (((x) & 0x003f0000) >> 16)
4408 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_SET(x) (((x) << 16) & 0x003f0000)
4409 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_MSB 29
4410 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_LSB 24
4411 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_MASK 0x3f000000
4412 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_GET(x) (((x) & 0x3f000000) >> 24)
4413 #define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_SET(x) (((x) << 24) & 0x3f000000)
4415 /* macros for BB_tpc_10 */
4416 #define PHY_BB_TPC_10_ADDRESS 0x0000a394
4417 #define PHY_BB_TPC_10_OFFSET 0x0000a394
4418 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_MSB 4
4419 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_LSB 0
4420 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_MASK 0x0000001f
4421 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_GET(x) (((x) & 0x0000001f) >> 0)
4422 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_SET(x) (((x) << 0) & 0x0000001f)
4423 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_MSB 9
4424 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_LSB 5
4425 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_MASK 0x000003e0
4426 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_GET(x) (((x) & 0x000003e0) >> 5)
4427 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_SET(x) (((x) << 5) & 0x000003e0)
4428 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_MSB 14
4429 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_LSB 10
4430 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_MASK 0x00007c00
4431 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_GET(x) (((x) & 0x00007c00) >> 10)
4432 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_SET(x) (((x) << 10) & 0x00007c00)
4433 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_MSB 19
4434 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_LSB 15
4435 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_MASK 0x000f8000
4436 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_GET(x) (((x) & 0x000f8000) >> 15)
4437 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_SET(x) (((x) << 15) & 0x000f8000)
4438 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_MSB 24
4439 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_LSB 20
4440 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_MASK 0x01f00000
4441 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_GET(x) (((x) & 0x01f00000) >> 20)
4442 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_SET(x) (((x) << 20) & 0x01f00000)
4443 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_MSB 29
4444 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_LSB 25
4445 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_MASK 0x3e000000
4446 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_GET(x) (((x) & 0x3e000000) >> 25)
4447 #define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_SET(x) (((x) << 25) & 0x3e000000)
4449 /* macros for BB_tpc_11_b0 */
4450 #define PHY_BB_TPC_11_B0_ADDRESS 0x0000a398
4451 #define PHY_BB_TPC_11_B0_OFFSET 0x0000a398
4452 #define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_MSB 4
4453 #define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_LSB 0
4454 #define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_MASK 0x0000001f
4455 #define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_GET(x) (((x) & 0x0000001f) >> 0)
4456 #define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_SET(x) (((x) << 0) & 0x0000001f)
4457 #define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_MSB 9
4458 #define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_LSB 5
4459 #define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_MASK 0x000003e0
4460 #define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_GET(x) (((x) & 0x000003e0) >> 5)
4461 #define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_SET(x) (((x) << 5) & 0x000003e0)
4462 #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MSB 23
4463 #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB 16
4464 #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MASK 0x00ff0000
4465 #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_GET(x) (((x) & 0x00ff0000) >> 16)
4466 #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_SET(x) (((x) << 16) & 0x00ff0000)
4467 #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_MSB 31
4468 #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_LSB 24
4469 #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_MASK 0xff000000
4470 #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_GET(x) (((x) & 0xff000000) >> 24)
4471 #define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_SET(x) (((x) << 24) & 0xff000000)
4473 /* macros for BB_cal_chain_mask */
4474 #define PHY_BB_CAL_CHAIN_MASK_ADDRESS 0x0000a39c
4475 #define PHY_BB_CAL_CHAIN_MASK_OFFSET 0x0000a39c
4476 #define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MSB 2
4477 #define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_LSB 0
4478 #define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MASK 0x00000007
4479 #define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_GET(x) (((x) & 0x00000007) >> 0)
4480 #define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_SET(x) (((x) << 0) & 0x00000007)
4482 /* macros for BB_powertx_sub */
4483 #define PHY_BB_POWERTX_SUB_ADDRESS 0x0000a3bc
4484 #define PHY_BB_POWERTX_SUB_OFFSET 0x0000a3bc
4485 #define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_MSB 5
4486 #define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_LSB 0
4487 #define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_MASK 0x0000003f
4488 #define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_GET(x) (((x) & 0x0000003f) >> 0)
4489 #define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_SET(x) (((x) << 0) & 0x0000003f)
4491 /* macros for BB_powertx_rate7 */
4492 #define PHY_BB_POWERTX_RATE7_ADDRESS 0x0000a3c0
4493 #define PHY_BB_POWERTX_RATE7_OFFSET 0x0000a3c0
4494 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_MSB 5
4495 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_LSB 0
4496 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_MASK 0x0000003f
4497 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_GET(x) (((x) & 0x0000003f) >> 0)
4498 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_SET(x) (((x) << 0) & 0x0000003f)
4499 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_MSB 13
4500 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_LSB 8
4501 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_MASK 0x00003f00
4502 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_GET(x) (((x) & 0x00003f00) >> 8)
4503 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_SET(x) (((x) << 8) & 0x00003f00)
4504 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_MSB 21
4505 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_LSB 16
4506 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_MASK 0x003f0000
4507 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_GET(x) (((x) & 0x003f0000) >> 16)
4508 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_SET(x) (((x) << 16) & 0x003f0000)
4509 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_MSB 29
4510 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_LSB 24
4511 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_MASK 0x3f000000
4512 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_GET(x) (((x) & 0x3f000000) >> 24)
4513 #define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_SET(x) (((x) << 24) & 0x3f000000)
4515 /* macros for BB_powertx_rate8 */
4516 #define PHY_BB_POWERTX_RATE8_ADDRESS 0x0000a3c4
4517 #define PHY_BB_POWERTX_RATE8_OFFSET 0x0000a3c4
4518 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_MSB 5
4519 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_LSB 0
4520 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_MASK 0x0000003f
4521 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_GET(x) (((x) & 0x0000003f) >> 0)
4522 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_SET(x) (((x) << 0) & 0x0000003f)
4523 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_MSB 13
4524 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_LSB 8
4525 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_MASK 0x00003f00
4526 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_GET(x) (((x) & 0x00003f00) >> 8)
4527 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_SET(x) (((x) << 8) & 0x00003f00)
4528 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_MSB 21
4529 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_LSB 16
4530 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_MASK 0x003f0000
4531 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_GET(x) (((x) & 0x003f0000) >> 16)
4532 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_SET(x) (((x) << 16) & 0x003f0000)
4533 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_MSB 29
4534 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_LSB 24
4535 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_MASK 0x3f000000
4536 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_GET(x) (((x) & 0x3f000000) >> 24)
4537 #define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_SET(x) (((x) << 24) & 0x3f000000)
4539 /* macros for BB_powertx_rate9 */
4540 #define PHY_BB_POWERTX_RATE9_ADDRESS 0x0000a3c8
4541 #define PHY_BB_POWERTX_RATE9_OFFSET 0x0000a3c8
4542 #define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_MSB 5
4543 #define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_LSB 0
4544 #define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_MASK 0x0000003f
4545 #define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_GET(x) (((x) & 0x0000003f) >> 0)
4546 #define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_SET(x) (((x) << 0) & 0x0000003f)
4547 #define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_MSB 13
4548 #define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_LSB 8
4549 #define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_MASK 0x00003f00
4550 #define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_GET(x) (((x) & 0x00003f00) >> 8)
4551 #define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_SET(x) (((x) << 8) & 0x00003f00)
4552 #define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_MSB 21
4553 #define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_LSB 16
4554 #define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_MASK 0x003f0000
4555 #define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_GET(x) (((x) & 0x003f0000) >> 16)
4556 #define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_SET(x) (((x) << 16) & 0x003f0000)
4557 #define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_MSB 29
4558 #define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_LSB 24
4559 #define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_MASK 0x3f000000
4560 #define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_GET(x) (((x) & 0x3f000000) >> 24)
4561 #define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_SET(x) (((x) << 24) & 0x3f000000)
4563 /* macros for BB_powertx_rate10 */
4564 #define PHY_BB_POWERTX_RATE10_ADDRESS 0x0000a3cc
4565 #define PHY_BB_POWERTX_RATE10_OFFSET 0x0000a3cc
4566 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_MSB 5
4567 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_LSB 0
4568 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_MASK 0x0000003f
4569 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_GET(x) (((x) & 0x0000003f) >> 0)
4570 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_SET(x) (((x) << 0) & 0x0000003f)
4571 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_MSB 13
4572 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_LSB 8
4573 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_MASK 0x00003f00
4574 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_GET(x) (((x) & 0x00003f00) >> 8)
4575 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_SET(x) (((x) << 8) & 0x00003f00)
4576 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_MSB 21
4577 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_LSB 16
4578 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_MASK 0x003f0000
4579 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_GET(x) (((x) & 0x003f0000) >> 16)
4580 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_SET(x) (((x) << 16) & 0x003f0000)
4581 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_MSB 29
4582 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_LSB 24
4583 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_MASK 0x3f000000
4584 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_GET(x) (((x) & 0x3f000000) >> 24)
4585 #define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_SET(x) (((x) << 24) & 0x3f000000)
4587 /* macros for BB_powertx_rate11 */
4588 #define PHY_BB_POWERTX_RATE11_ADDRESS 0x0000a3d0
4589 #define PHY_BB_POWERTX_RATE11_OFFSET 0x0000a3d0
4590 #define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_MSB 5
4591 #define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_LSB 0
4592 #define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_MASK 0x0000003f
4593 #define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_GET(x) (((x) & 0x0000003f) >> 0)
4594 #define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_SET(x) (((x) << 0) & 0x0000003f)
4595 #define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_MSB 13
4596 #define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_LSB 8
4597 #define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_MASK 0x00003f00
4598 #define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_GET(x) (((x) & 0x00003f00) >> 8)
4599 #define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_SET(x) (((x) << 8) & 0x00003f00)
4600 #define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_MSB 21
4601 #define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_LSB 16
4602 #define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_MASK 0x003f0000
4603 #define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_GET(x) (((x) & 0x003f0000) >> 16)
4604 #define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_SET(x) (((x) << 16) & 0x003f0000)
4605 #define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_MSB 29
4606 #define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_LSB 24
4607 #define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_MASK 0x3f000000
4608 #define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_GET(x) (((x) & 0x3f000000) >> 24)
4609 #define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_SET(x) (((x) << 24) & 0x3f000000)
4611 /* macros for BB_powertx_rate12 */
4612 #define PHY_BB_POWERTX_RATE12_ADDRESS 0x0000a3d4
4613 #define PHY_BB_POWERTX_RATE12_OFFSET 0x0000a3d4
4614 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_MSB 5
4615 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_LSB 0
4616 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_MASK 0x0000003f
4617 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_GET(x) (((x) & 0x0000003f) >> 0)
4618 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_SET(x) (((x) << 0) & 0x0000003f)
4619 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_MSB 13
4620 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_LSB 8
4621 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_MASK 0x00003f00
4622 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_GET(x) (((x) & 0x00003f00) >> 8)
4623 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_SET(x) (((x) << 8) & 0x00003f00)
4624 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_MSB 21
4625 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_LSB 16
4626 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_MASK 0x003f0000
4627 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_GET(x) (((x) & 0x003f0000) >> 16)
4628 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_SET(x) (((x) << 16) & 0x003f0000)
4629 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_MSB 29
4630 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_LSB 24
4631 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_MASK 0x3f000000
4632 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_GET(x) (((x) & 0x3f000000) >> 24)
4633 #define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_SET(x) (((x) << 24) & 0x3f000000)
4635 /* macros for BB_force_analog */
4636 #define PHY_BB_FORCE_ANALOG_ADDRESS 0x0000a3d8
4637 #define PHY_BB_FORCE_ANALOG_OFFSET 0x0000a3d8
4638 #define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MSB 0
4639 #define PHY_BB_FORCE_ANALOG_FORCE_XPAON_LSB 0
4640 #define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MASK 0x00000001
4641 #define PHY_BB_FORCE_ANALOG_FORCE_XPAON_GET(x) (((x) & 0x00000001) >> 0)
4642 #define PHY_BB_FORCE_ANALOG_FORCE_XPAON_SET(x) (((x) << 0) & 0x00000001)
4643 #define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MSB 3
4644 #define PHY_BB_FORCE_ANALOG_FORCED_XPAON_LSB 1
4645 #define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MASK 0x0000000e
4646 #define PHY_BB_FORCE_ANALOG_FORCED_XPAON_GET(x) (((x) & 0x0000000e) >> 1)
4647 #define PHY_BB_FORCE_ANALOG_FORCED_XPAON_SET(x) (((x) << 1) & 0x0000000e)
4648 #define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_MSB 4
4649 #define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_LSB 4
4650 #define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_MASK 0x00000010
4651 #define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_GET(x) (((x) & 0x00000010) >> 4)
4652 #define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_SET(x) (((x) << 4) & 0x00000010)
4653 #define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_MSB 7
4654 #define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_LSB 5
4655 #define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_MASK 0x000000e0
4656 #define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_GET(x) (((x) & 0x000000e0) >> 5)
4657 #define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_SET(x) (((x) << 5) & 0x000000e0)
4659 /* macros for BB_tpc_12 */
4660 #define PHY_BB_TPC_12_ADDRESS 0x0000a3dc
4661 #define PHY_BB_TPC_12_OFFSET 0x0000a3dc
4662 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_MSB 4
4663 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_LSB 0
4664 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_MASK 0x0000001f
4665 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_GET(x) (((x) & 0x0000001f) >> 0)
4666 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_SET(x) (((x) << 0) & 0x0000001f)
4667 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_MSB 9
4668 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_LSB 5
4669 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_MASK 0x000003e0
4670 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_GET(x) (((x) & 0x000003e0) >> 5)
4671 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_SET(x) (((x) << 5) & 0x000003e0)
4672 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_MSB 14
4673 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_LSB 10
4674 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_MASK 0x00007c00
4675 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_GET(x) (((x) & 0x00007c00) >> 10)
4676 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_SET(x) (((x) << 10) & 0x00007c00)
4677 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_MSB 19
4678 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_LSB 15
4679 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_MASK 0x000f8000
4680 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_GET(x) (((x) & 0x000f8000) >> 15)
4681 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_SET(x) (((x) << 15) & 0x000f8000)
4682 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_MSB 24
4683 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_LSB 20
4684 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_MASK 0x01f00000
4685 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_GET(x) (((x) & 0x01f00000) >> 20)
4686 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_SET(x) (((x) << 20) & 0x01f00000)
4687 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_MSB 29
4688 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_LSB 25
4689 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_MASK 0x3e000000
4690 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_GET(x) (((x) & 0x3e000000) >> 25)
4691 #define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_SET(x) (((x) << 25) & 0x3e000000)
4693 /* macros for BB_tpc_13 */
4694 #define PHY_BB_TPC_13_ADDRESS 0x0000a3e0
4695 #define PHY_BB_TPC_13_OFFSET 0x0000a3e0
4696 #define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_MSB 4
4697 #define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_LSB 0
4698 #define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_MASK 0x0000001f
4699 #define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_GET(x) (((x) & 0x0000001f) >> 0)
4700 #define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_SET(x) (((x) << 0) & 0x0000001f)
4701 #define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_MSB 9
4702 #define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_LSB 5
4703 #define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_MASK 0x000003e0
4704 #define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_GET(x) (((x) & 0x000003e0) >> 5)
4705 #define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_SET(x) (((x) << 5) & 0x000003e0)
4707 /* macros for BB_tpc_14 */
4708 #define PHY_BB_TPC_14_ADDRESS 0x0000a3e4
4709 #define PHY_BB_TPC_14_OFFSET 0x0000a3e4
4710 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_MSB 4
4711 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_LSB 0
4712 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_MASK 0x0000001f
4713 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_GET(x) (((x) & 0x0000001f) >> 0)
4714 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_SET(x) (((x) << 0) & 0x0000001f)
4715 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_MSB 9
4716 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_LSB 5
4717 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_MASK 0x000003e0
4718 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_GET(x) (((x) & 0x000003e0) >> 5)
4719 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_SET(x) (((x) << 5) & 0x000003e0)
4720 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_MSB 14
4721 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_LSB 10
4722 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_MASK 0x00007c00
4723 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_GET(x) (((x) & 0x00007c00) >> 10)
4724 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_SET(x) (((x) << 10) & 0x00007c00)
4725 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_MSB 19
4726 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_LSB 15
4727 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_MASK 0x000f8000
4728 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_GET(x) (((x) & 0x000f8000) >> 15)
4729 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_SET(x) (((x) << 15) & 0x000f8000)
4730 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_MSB 24
4731 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_LSB 20
4732 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_MASK 0x01f00000
4733 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_GET(x) (((x) & 0x01f00000) >> 20)
4734 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_SET(x) (((x) << 20) & 0x01f00000)
4735 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_MSB 29
4736 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_LSB 25
4737 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_MASK 0x3e000000
4738 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_GET(x) (((x) & 0x3e000000) >> 25)
4739 #define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_SET(x) (((x) << 25) & 0x3e000000)
4741 /* macros for BB_tpc_15 */
4742 #define PHY_BB_TPC_15_ADDRESS 0x0000a3e8
4743 #define PHY_BB_TPC_15_OFFSET 0x0000a3e8
4744 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_MSB 4
4745 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_LSB 0
4746 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_MASK 0x0000001f
4747 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_GET(x) (((x) & 0x0000001f) >> 0)
4748 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_SET(x) (((x) << 0) & 0x0000001f)
4749 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_MSB 9
4750 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_LSB 5
4751 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_MASK 0x000003e0
4752 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_GET(x) (((x) & 0x000003e0) >> 5)
4753 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_SET(x) (((x) << 5) & 0x000003e0)
4754 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_MSB 14
4755 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_LSB 10
4756 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_MASK 0x00007c00
4757 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_GET(x) (((x) & 0x00007c00) >> 10)
4758 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_SET(x) (((x) << 10) & 0x00007c00)
4759 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_MSB 19
4760 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_LSB 15
4761 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_MASK 0x000f8000
4762 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_GET(x) (((x) & 0x000f8000) >> 15)
4763 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_SET(x) (((x) << 15) & 0x000f8000)
4764 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_MSB 24
4765 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_LSB 20
4766 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_MASK 0x01f00000
4767 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_GET(x) (((x) & 0x01f00000) >> 20)
4768 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_SET(x) (((x) << 20) & 0x01f00000)
4769 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_MSB 29
4770 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_LSB 25
4771 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_MASK 0x3e000000
4772 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_GET(x) (((x) & 0x3e000000) >> 25)
4773 #define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_SET(x) (((x) << 25) & 0x3e000000)
4775 /* macros for BB_tpc_16 */
4776 #define PHY_BB_TPC_16_ADDRESS 0x0000a3ec
4777 #define PHY_BB_TPC_16_OFFSET 0x0000a3ec
4778 #define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_MSB 13
4779 #define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_LSB 8
4780 #define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_MASK 0x00003f00
4781 #define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_GET(x) (((x) & 0x00003f00) >> 8)
4782 #define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_SET(x) (((x) << 8) & 0x00003f00)
4783 #define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_MSB 21
4784 #define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_LSB 16
4785 #define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_MASK 0x003f0000
4786 #define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_GET(x) (((x) & 0x003f0000) >> 16)
4787 #define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_SET(x) (((x) << 16) & 0x003f0000)
4788 #define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_MSB 29
4789 #define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_LSB 24
4790 #define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_MASK 0x3f000000
4791 #define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_GET(x) (((x) & 0x3f000000) >> 24)
4792 #define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_SET(x) (((x) << 24) & 0x3f000000)
4794 /* macros for BB_tpc_17 */
4795 #define PHY_BB_TPC_17_ADDRESS 0x0000a3f0
4796 #define PHY_BB_TPC_17_OFFSET 0x0000a3f0
4797 #define PHY_BB_TPC_17_ENABLE_PAL_MSB 0
4798 #define PHY_BB_TPC_17_ENABLE_PAL_LSB 0
4799 #define PHY_BB_TPC_17_ENABLE_PAL_MASK 0x00000001
4800 #define PHY_BB_TPC_17_ENABLE_PAL_GET(x) (((x) & 0x00000001) >> 0)
4801 #define PHY_BB_TPC_17_ENABLE_PAL_SET(x) (((x) << 0) & 0x00000001)
4802 #define PHY_BB_TPC_17_ENABLE_PAL_CCK_MSB 1
4803 #define PHY_BB_TPC_17_ENABLE_PAL_CCK_LSB 1
4804 #define PHY_BB_TPC_17_ENABLE_PAL_CCK_MASK 0x00000002
4805 #define PHY_BB_TPC_17_ENABLE_PAL_CCK_GET(x) (((x) & 0x00000002) >> 1)
4806 #define PHY_BB_TPC_17_ENABLE_PAL_CCK_SET(x) (((x) << 1) & 0x00000002)
4807 #define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_MSB 2
4808 #define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_LSB 2
4809 #define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_MASK 0x00000004
4810 #define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_GET(x) (((x) & 0x00000004) >> 2)
4811 #define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_SET(x) (((x) << 2) & 0x00000004)
4812 #define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_MSB 3
4813 #define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_LSB 3
4814 #define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_MASK 0x00000008
4815 #define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_GET(x) (((x) & 0x00000008) >> 3)
4816 #define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_SET(x) (((x) << 3) & 0x00000008)
4817 #define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_MSB 9
4818 #define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_LSB 4
4819 #define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_MASK 0x000003f0
4820 #define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_GET(x) (((x) & 0x000003f0) >> 4)
4821 #define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_SET(x) (((x) << 4) & 0x000003f0)
4822 #define PHY_BB_TPC_17_FORCE_PAL_LOCKED_MSB 10
4823 #define PHY_BB_TPC_17_FORCE_PAL_LOCKED_LSB 10
4824 #define PHY_BB_TPC_17_FORCE_PAL_LOCKED_MASK 0x00000400
4825 #define PHY_BB_TPC_17_FORCE_PAL_LOCKED_GET(x) (((x) & 0x00000400) >> 10)
4826 #define PHY_BB_TPC_17_FORCE_PAL_LOCKED_SET(x) (((x) << 10) & 0x00000400)
4827 #define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_MSB 16
4828 #define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_LSB 11
4829 #define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_MASK 0x0001f800
4830 #define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_GET(x) (((x) & 0x0001f800) >> 11)
4831 #define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_SET(x) (((x) << 11) & 0x0001f800)
4833 /* macros for BB_tpc_18 */
4834 #define PHY_BB_TPC_18_ADDRESS 0x0000a3f4
4835 #define PHY_BB_TPC_18_OFFSET 0x0000a3f4
4836 #define PHY_BB_TPC_18_THERM_CAL_VALUE_MSB 7
4837 #define PHY_BB_TPC_18_THERM_CAL_VALUE_LSB 0
4838 #define PHY_BB_TPC_18_THERM_CAL_VALUE_MASK 0x000000ff
4839 #define PHY_BB_TPC_18_THERM_CAL_VALUE_GET(x) (((x) & 0x000000ff) >> 0)
4840 #define PHY_BB_TPC_18_THERM_CAL_VALUE_SET(x) (((x) << 0) & 0x000000ff)
4841 #define PHY_BB_TPC_18_VOLT_CAL_VALUE_MSB 15
4842 #define PHY_BB_TPC_18_VOLT_CAL_VALUE_LSB 8
4843 #define PHY_BB_TPC_18_VOLT_CAL_VALUE_MASK 0x0000ff00
4844 #define PHY_BB_TPC_18_VOLT_CAL_VALUE_GET(x) (((x) & 0x0000ff00) >> 8)
4845 #define PHY_BB_TPC_18_VOLT_CAL_VALUE_SET(x) (((x) << 8) & 0x0000ff00)
4846 #define PHY_BB_TPC_18_USE_LEGACY_TPC_MSB 16
4847 #define PHY_BB_TPC_18_USE_LEGACY_TPC_LSB 16
4848 #define PHY_BB_TPC_18_USE_LEGACY_TPC_MASK 0x00010000
4849 #define PHY_BB_TPC_18_USE_LEGACY_TPC_GET(x) (((x) & 0x00010000) >> 16)
4850 #define PHY_BB_TPC_18_USE_LEGACY_TPC_SET(x) (((x) << 16) & 0x00010000)
4852 /* macros for BB_tpc_19 */
4853 #define PHY_BB_TPC_19_ADDRESS 0x0000a3f8
4854 #define PHY_BB_TPC_19_OFFSET 0x0000a3f8
4855 #define PHY_BB_TPC_19_ALPHA_THERM_MSB 7
4856 #define PHY_BB_TPC_19_ALPHA_THERM_LSB 0
4857 #define PHY_BB_TPC_19_ALPHA_THERM_MASK 0x000000ff
4858 #define PHY_BB_TPC_19_ALPHA_THERM_GET(x) (((x) & 0x000000ff) >> 0)
4859 #define PHY_BB_TPC_19_ALPHA_THERM_SET(x) (((x) << 0) & 0x000000ff)
4860 #define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_MSB 15
4861 #define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_LSB 8
4862 #define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_MASK 0x0000ff00
4863 #define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_GET(x) (((x) & 0x0000ff00) >> 8)
4864 #define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_SET(x) (((x) << 8) & 0x0000ff00)
4865 #define PHY_BB_TPC_19_ALPHA_VOLT_MSB 20
4866 #define PHY_BB_TPC_19_ALPHA_VOLT_LSB 16
4867 #define PHY_BB_TPC_19_ALPHA_VOLT_MASK 0x001f0000
4868 #define PHY_BB_TPC_19_ALPHA_VOLT_GET(x) (((x) & 0x001f0000) >> 16)
4869 #define PHY_BB_TPC_19_ALPHA_VOLT_SET(x) (((x) << 16) & 0x001f0000)
4870 #define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_MSB 25
4871 #define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_LSB 21
4872 #define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_MASK 0x03e00000
4873 #define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_GET(x) (((x) & 0x03e00000) >> 21)
4874 #define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_SET(x) (((x) << 21) & 0x03e00000)
4876 /* macros for BB_tpc_20 */
4877 #define PHY_BB_TPC_20_ADDRESS 0x0000a3fc
4878 #define PHY_BB_TPC_20_OFFSET 0x0000a3fc
4879 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_MSB 0
4880 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_LSB 0
4881 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_MASK 0x00000001
4882 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_GET(x) (((x) & 0x00000001) >> 0)
4883 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_SET(x) (((x) << 0) & 0x00000001)
4884 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_MSB 1
4885 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_LSB 1
4886 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_MASK 0x00000002
4887 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_GET(x) (((x) & 0x00000002) >> 1)
4888 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_SET(x) (((x) << 1) & 0x00000002)
4889 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_MSB 2
4890 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_LSB 2
4891 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_MASK 0x00000004
4892 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_GET(x) (((x) & 0x00000004) >> 2)
4893 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_SET(x) (((x) << 2) & 0x00000004)
4894 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_MSB 3
4895 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_LSB 3
4896 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_MASK 0x00000008
4897 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_GET(x) (((x) & 0x00000008) >> 3)
4898 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_SET(x) (((x) << 3) & 0x00000008)
4899 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_MSB 4
4900 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_LSB 4
4901 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_MASK 0x00000010
4902 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_GET(x) (((x) & 0x00000010) >> 4)
4903 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_SET(x) (((x) << 4) & 0x00000010)
4904 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_MSB 5
4905 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_LSB 5
4906 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_MASK 0x00000020
4907 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_GET(x) (((x) & 0x00000020) >> 5)
4908 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_SET(x) (((x) << 5) & 0x00000020)
4909 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_MSB 6
4910 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_LSB 6
4911 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_MASK 0x00000040
4912 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_GET(x) (((x) & 0x00000040) >> 6)
4913 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_SET(x) (((x) << 6) & 0x00000040)
4914 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_MSB 7
4915 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_LSB 7
4916 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_MASK 0x00000080
4917 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_GET(x) (((x) & 0x00000080) >> 7)
4918 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_SET(x) (((x) << 7) & 0x00000080)
4919 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_MSB 8
4920 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_LSB 8
4921 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_MASK 0x00000100
4922 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_GET(x) (((x) & 0x00000100) >> 8)
4923 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_SET(x) (((x) << 8) & 0x00000100)
4924 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_MSB 9
4925 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_LSB 9
4926 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_MASK 0x00000200
4927 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_GET(x) (((x) & 0x00000200) >> 9)
4928 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_SET(x) (((x) << 9) & 0x00000200)
4929 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_MSB 10
4930 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_LSB 10
4931 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_MASK 0x00000400
4932 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_GET(x) (((x) & 0x00000400) >> 10)
4933 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_SET(x) (((x) << 10) & 0x00000400)
4934 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_MSB 11
4935 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_LSB 11
4936 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_MASK 0x00000800
4937 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_GET(x) (((x) & 0x00000800) >> 11)
4938 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_SET(x) (((x) << 11) & 0x00000800)
4939 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_MSB 12
4940 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_LSB 12
4941 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_MASK 0x00001000
4942 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_GET(x) (((x) & 0x00001000) >> 12)
4943 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_SET(x) (((x) << 12) & 0x00001000)
4944 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_MSB 13
4945 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_LSB 13
4946 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_MASK 0x00002000
4947 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_GET(x) (((x) & 0x00002000) >> 13)
4948 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_SET(x) (((x) << 13) & 0x00002000)
4949 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_MSB 14
4950 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_LSB 14
4951 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_MASK 0x00004000
4952 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_GET(x) (((x) & 0x00004000) >> 14)
4953 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_SET(x) (((x) << 14) & 0x00004000)
4954 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_MSB 15
4955 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_LSB 15
4956 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_MASK 0x00008000
4957 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_GET(x) (((x) & 0x00008000) >> 15)
4958 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_SET(x) (((x) << 15) & 0x00008000)
4959 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_MSB 16
4960 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_LSB 16
4961 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_MASK 0x00010000
4962 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_GET(x) (((x) & 0x00010000) >> 16)
4963 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_SET(x) (((x) << 16) & 0x00010000)
4964 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_MSB 17
4965 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_LSB 17
4966 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_MASK 0x00020000
4967 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_GET(x) (((x) & 0x00020000) >> 17)
4968 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_SET(x) (((x) << 17) & 0x00020000)
4969 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_MSB 18
4970 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_LSB 18
4971 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_MASK 0x00040000
4972 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_GET(x) (((x) & 0x00040000) >> 18)
4973 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_SET(x) (((x) << 18) & 0x00040000)
4974 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_MSB 19
4975 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_LSB 19
4976 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_MASK 0x00080000
4977 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_GET(x) (((x) & 0x00080000) >> 19)
4978 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_SET(x) (((x) << 19) & 0x00080000)
4979 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_MSB 20
4980 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_LSB 20
4981 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_MASK 0x00100000
4982 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_GET(x) (((x) & 0x00100000) >> 20)
4983 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_SET(x) (((x) << 20) & 0x00100000)
4984 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_MSB 21
4985 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_LSB 21
4986 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_MASK 0x00200000
4987 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_GET(x) (((x) & 0x00200000) >> 21)
4988 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_SET(x) (((x) << 21) & 0x00200000)
4989 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_MSB 22
4990 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_LSB 22
4991 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_MASK 0x00400000
4992 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_GET(x) (((x) & 0x00400000) >> 22)
4993 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_SET(x) (((x) << 22) & 0x00400000)
4994 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_MSB 23
4995 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_LSB 23
4996 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_MASK 0x00800000
4997 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_GET(x) (((x) & 0x00800000) >> 23)
4998 #define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_SET(x) (((x) << 23) & 0x00800000)
5000 /* macros for BB_tx_gain_tab_1 */
5001 #define PHY_BB_TX_GAIN_TAB_1_ADDRESS 0x0000a400
5002 #define PHY_BB_TX_GAIN_TAB_1_OFFSET 0x0000a400
5003 #define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_MSB 31
5004 #define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_LSB 0
5005 #define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_MASK 0xffffffff
5006 #define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_GET(x) (((x) & 0xffffffff) >> 0)
5007 #define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_SET(x) (((x) << 0) & 0xffffffff)
5009 /* macros for BB_tx_gain_tab_2 */
5010 #define PHY_BB_TX_GAIN_TAB_2_ADDRESS 0x0000a404
5011 #define PHY_BB_TX_GAIN_TAB_2_OFFSET 0x0000a404
5012 #define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_MSB 31
5013 #define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_LSB 0
5014 #define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_MASK 0xffffffff
5015 #define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_GET(x) (((x) & 0xffffffff) >> 0)
5016 #define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_SET(x) (((x) << 0) & 0xffffffff)
5018 /* macros for BB_tx_gain_tab_3 */
5019 #define PHY_BB_TX_GAIN_TAB_3_ADDRESS 0x0000a408
5020 #define PHY_BB_TX_GAIN_TAB_3_OFFSET 0x0000a408
5021 #define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_MSB 31
5022 #define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_LSB 0
5023 #define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_MASK 0xffffffff
5024 #define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_GET(x) (((x) & 0xffffffff) >> 0)
5025 #define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_SET(x) (((x) << 0) & 0xffffffff)
5027 /* macros for BB_tx_gain_tab_4 */
5028 #define PHY_BB_TX_GAIN_TAB_4_ADDRESS 0x0000a40c
5029 #define PHY_BB_TX_GAIN_TAB_4_OFFSET 0x0000a40c
5030 #define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_MSB 31
5031 #define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_LSB 0
5032 #define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_MASK 0xffffffff
5033 #define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_GET(x) (((x) & 0xffffffff) >> 0)
5034 #define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_SET(x) (((x) << 0) & 0xffffffff)
5036 /* macros for BB_tx_gain_tab_5 */
5037 #define PHY_BB_TX_GAIN_TAB_5_ADDRESS 0x0000a410
5038 #define PHY_BB_TX_GAIN_TAB_5_OFFSET 0x0000a410
5039 #define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_MSB 31
5040 #define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_LSB 0
5041 #define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_MASK 0xffffffff
5042 #define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_GET(x) (((x) & 0xffffffff) >> 0)
5043 #define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_SET(x) (((x) << 0) & 0xffffffff)
5045 /* macros for BB_tx_gain_tab_6 */
5046 #define PHY_BB_TX_GAIN_TAB_6_ADDRESS 0x0000a414
5047 #define PHY_BB_TX_GAIN_TAB_6_OFFSET 0x0000a414
5048 #define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_MSB 31
5049 #define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_LSB 0
5050 #define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_MASK 0xffffffff
5051 #define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_GET(x) (((x) & 0xffffffff) >> 0)
5052 #define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_SET(x) (((x) << 0) & 0xffffffff)
5054 /* macros for BB_tx_gain_tab_7 */
5055 #define PHY_BB_TX_GAIN_TAB_7_ADDRESS 0x0000a418
5056 #define PHY_BB_TX_GAIN_TAB_7_OFFSET 0x0000a418
5057 #define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_MSB 31
5058 #define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_LSB 0
5059 #define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_MASK 0xffffffff
5060 #define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_GET(x) (((x) & 0xffffffff) >> 0)
5061 #define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_SET(x) (((x) << 0) & 0xffffffff)
5063 /* macros for BB_tx_gain_tab_8 */
5064 #define PHY_BB_TX_GAIN_TAB_8_ADDRESS 0x0000a41c
5065 #define PHY_BB_TX_GAIN_TAB_8_OFFSET 0x0000a41c
5066 #define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_MSB 31
5067 #define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_LSB 0
5068 #define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_MASK 0xffffffff
5069 #define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_GET(x) (((x) & 0xffffffff) >> 0)
5070 #define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_SET(x) (((x) << 0) & 0xffffffff)
5072 /* macros for BB_tx_gain_tab_9 */
5073 #define PHY_BB_TX_GAIN_TAB_9_ADDRESS 0x0000a420
5074 #define PHY_BB_TX_GAIN_TAB_9_OFFSET 0x0000a420
5075 #define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_MSB 31
5076 #define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_LSB 0
5077 #define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_MASK 0xffffffff
5078 #define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_GET(x) (((x) & 0xffffffff) >> 0)
5079 #define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_SET(x) (((x) << 0) & 0xffffffff)
5081 /* macros for BB_tx_gain_tab_10 */
5082 #define PHY_BB_TX_GAIN_TAB_10_ADDRESS 0x0000a424
5083 #define PHY_BB_TX_GAIN_TAB_10_OFFSET 0x0000a424
5084 #define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_MSB 31
5085 #define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_LSB 0
5086 #define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_MASK 0xffffffff
5087 #define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_GET(x) (((x) & 0xffffffff) >> 0)
5088 #define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_SET(x) (((x) << 0) & 0xffffffff)
5090 /* macros for BB_tx_gain_tab_11 */
5091 #define PHY_BB_TX_GAIN_TAB_11_ADDRESS 0x0000a428
5092 #define PHY_BB_TX_GAIN_TAB_11_OFFSET 0x0000a428
5093 #define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_MSB 31
5094 #define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_LSB 0
5095 #define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_MASK 0xffffffff
5096 #define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_GET(x) (((x) & 0xffffffff) >> 0)
5097 #define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_SET(x) (((x) << 0) & 0xffffffff)
5099 /* macros for BB_tx_gain_tab_12 */
5100 #define PHY_BB_TX_GAIN_TAB_12_ADDRESS 0x0000a42c
5101 #define PHY_BB_TX_GAIN_TAB_12_OFFSET 0x0000a42c
5102 #define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_MSB 31
5103 #define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_LSB 0
5104 #define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_MASK 0xffffffff
5105 #define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_GET(x) (((x) & 0xffffffff) >> 0)
5106 #define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_SET(x) (((x) << 0) & 0xffffffff)
5108 /* macros for BB_tx_gain_tab_13 */
5109 #define PHY_BB_TX_GAIN_TAB_13_ADDRESS 0x0000a430
5110 #define PHY_BB_TX_GAIN_TAB_13_OFFSET 0x0000a430
5111 #define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_MSB 31
5112 #define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_LSB 0
5113 #define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_MASK 0xffffffff
5114 #define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_GET(x) (((x) & 0xffffffff) >> 0)
5115 #define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_SET(x) (((x) << 0) & 0xffffffff)
5117 /* macros for BB_tx_gain_tab_14 */
5118 #define PHY_BB_TX_GAIN_TAB_14_ADDRESS 0x0000a434
5119 #define PHY_BB_TX_GAIN_TAB_14_OFFSET 0x0000a434
5120 #define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_MSB 31
5121 #define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_LSB 0
5122 #define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_MASK 0xffffffff
5123 #define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_GET(x) (((x) & 0xffffffff) >> 0)
5124 #define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_SET(x) (((x) << 0) & 0xffffffff)
5126 /* macros for BB_tx_gain_tab_15 */
5127 #define PHY_BB_TX_GAIN_TAB_15_ADDRESS 0x0000a438
5128 #define PHY_BB_TX_GAIN_TAB_15_OFFSET 0x0000a438
5129 #define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_MSB 31
5130 #define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_LSB 0
5131 #define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_MASK 0xffffffff
5132 #define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_GET(x) (((x) & 0xffffffff) >> 0)
5133 #define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_SET(x) (((x) << 0) & 0xffffffff)
5135 /* macros for BB_tx_gain_tab_16 */
5136 #define PHY_BB_TX_GAIN_TAB_16_ADDRESS 0x0000a43c
5137 #define PHY_BB_TX_GAIN_TAB_16_OFFSET 0x0000a43c
5138 #define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_MSB 31
5139 #define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_LSB 0
5140 #define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_MASK 0xffffffff
5141 #define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_GET(x) (((x) & 0xffffffff) >> 0)
5142 #define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_SET(x) (((x) << 0) & 0xffffffff)
5144 /* macros for BB_tx_gain_tab_17 */
5145 #define PHY_BB_TX_GAIN_TAB_17_ADDRESS 0x0000a440
5146 #define PHY_BB_TX_GAIN_TAB_17_OFFSET 0x0000a440
5147 #define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_MSB 31
5148 #define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_LSB 0
5149 #define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_MASK 0xffffffff
5150 #define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_GET(x) (((x) & 0xffffffff) >> 0)
5151 #define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_SET(x) (((x) << 0) & 0xffffffff)
5153 /* macros for BB_tx_gain_tab_18 */
5154 #define PHY_BB_TX_GAIN_TAB_18_ADDRESS 0x0000a444
5155 #define PHY_BB_TX_GAIN_TAB_18_OFFSET 0x0000a444
5156 #define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_MSB 31
5157 #define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_LSB 0
5158 #define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_MASK 0xffffffff
5159 #define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_GET(x) (((x) & 0xffffffff) >> 0)
5160 #define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_SET(x) (((x) << 0) & 0xffffffff)
5162 /* macros for BB_tx_gain_tab_19 */
5163 #define PHY_BB_TX_GAIN_TAB_19_ADDRESS 0x0000a448
5164 #define PHY_BB_TX_GAIN_TAB_19_OFFSET 0x0000a448
5165 #define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_MSB 31
5166 #define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_LSB 0
5167 #define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_MASK 0xffffffff
5168 #define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_GET(x) (((x) & 0xffffffff) >> 0)
5169 #define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_SET(x) (((x) << 0) & 0xffffffff)
5171 /* macros for BB_tx_gain_tab_20 */
5172 #define PHY_BB_TX_GAIN_TAB_20_ADDRESS 0x0000a44c
5173 #define PHY_BB_TX_GAIN_TAB_20_OFFSET 0x0000a44c
5174 #define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_MSB 31
5175 #define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_LSB 0
5176 #define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_MASK 0xffffffff
5177 #define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_GET(x) (((x) & 0xffffffff) >> 0)
5178 #define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_SET(x) (((x) << 0) & 0xffffffff)
5180 /* macros for BB_tx_gain_tab_21 */
5181 #define PHY_BB_TX_GAIN_TAB_21_ADDRESS 0x0000a450
5182 #define PHY_BB_TX_GAIN_TAB_21_OFFSET 0x0000a450
5183 #define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_MSB 31
5184 #define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_LSB 0
5185 #define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_MASK 0xffffffff
5186 #define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_GET(x) (((x) & 0xffffffff) >> 0)
5187 #define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_SET(x) (((x) << 0) & 0xffffffff)
5189 /* macros for BB_tx_gain_tab_22 */
5190 #define PHY_BB_TX_GAIN_TAB_22_ADDRESS 0x0000a454
5191 #define PHY_BB_TX_GAIN_TAB_22_OFFSET 0x0000a454
5192 #define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_MSB 31
5193 #define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_LSB 0
5194 #define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_MASK 0xffffffff
5195 #define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_GET(x) (((x) & 0xffffffff) >> 0)
5196 #define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_SET(x) (((x) << 0) & 0xffffffff)
5198 /* macros for BB_tx_gain_tab_23 */
5199 #define PHY_BB_TX_GAIN_TAB_23_ADDRESS 0x0000a458
5200 #define PHY_BB_TX_GAIN_TAB_23_OFFSET 0x0000a458
5201 #define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_MSB 31
5202 #define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_LSB 0
5203 #define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_MASK 0xffffffff
5204 #define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_GET(x) (((x) & 0xffffffff) >> 0)
5205 #define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_SET(x) (((x) << 0) & 0xffffffff)
5207 /* macros for BB_tx_gain_tab_24 */
5208 #define PHY_BB_TX_GAIN_TAB_24_ADDRESS 0x0000a45c
5209 #define PHY_BB_TX_GAIN_TAB_24_OFFSET 0x0000a45c
5210 #define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_MSB 31
5211 #define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_LSB 0
5212 #define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_MASK 0xffffffff
5213 #define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_GET(x) (((x) & 0xffffffff) >> 0)
5214 #define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_SET(x) (((x) << 0) & 0xffffffff)
5216 /* macros for BB_tx_gain_tab_25 */
5217 #define PHY_BB_TX_GAIN_TAB_25_ADDRESS 0x0000a460
5218 #define PHY_BB_TX_GAIN_TAB_25_OFFSET 0x0000a460
5219 #define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_MSB 31
5220 #define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_LSB 0
5221 #define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_MASK 0xffffffff
5222 #define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_GET(x) (((x) & 0xffffffff) >> 0)
5223 #define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_SET(x) (((x) << 0) & 0xffffffff)
5225 /* macros for BB_tx_gain_tab_26 */
5226 #define PHY_BB_TX_GAIN_TAB_26_ADDRESS 0x0000a464
5227 #define PHY_BB_TX_GAIN_TAB_26_OFFSET 0x0000a464
5228 #define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_MSB 31
5229 #define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_LSB 0
5230 #define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_MASK 0xffffffff
5231 #define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_GET(x) (((x) & 0xffffffff) >> 0)
5232 #define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_SET(x) (((x) << 0) & 0xffffffff)
5234 /* macros for BB_tx_gain_tab_27 */
5235 #define PHY_BB_TX_GAIN_TAB_27_ADDRESS 0x0000a468
5236 #define PHY_BB_TX_GAIN_TAB_27_OFFSET 0x0000a468
5237 #define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_MSB 31
5238 #define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_LSB 0
5239 #define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_MASK 0xffffffff
5240 #define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_GET(x) (((x) & 0xffffffff) >> 0)
5241 #define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_SET(x) (((x) << 0) & 0xffffffff)
5243 /* macros for BB_tx_gain_tab_28 */
5244 #define PHY_BB_TX_GAIN_TAB_28_ADDRESS 0x0000a46c
5245 #define PHY_BB_TX_GAIN_TAB_28_OFFSET 0x0000a46c
5246 #define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_MSB 31
5247 #define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_LSB 0
5248 #define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_MASK 0xffffffff
5249 #define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_GET(x) (((x) & 0xffffffff) >> 0)
5250 #define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_SET(x) (((x) << 0) & 0xffffffff)
5252 /* macros for BB_tx_gain_tab_29 */
5253 #define PHY_BB_TX_GAIN_TAB_29_ADDRESS 0x0000a470
5254 #define PHY_BB_TX_GAIN_TAB_29_OFFSET 0x0000a470
5255 #define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_MSB 31
5256 #define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_LSB 0
5257 #define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_MASK 0xffffffff
5258 #define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_GET(x) (((x) & 0xffffffff) >> 0)
5259 #define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_SET(x) (((x) << 0) & 0xffffffff)
5261 /* macros for BB_tx_gain_tab_30 */
5262 #define PHY_BB_TX_GAIN_TAB_30_ADDRESS 0x0000a474
5263 #define PHY_BB_TX_GAIN_TAB_30_OFFSET 0x0000a474
5264 #define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_MSB 31
5265 #define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_LSB 0
5266 #define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_MASK 0xffffffff
5267 #define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_GET(x) (((x) & 0xffffffff) >> 0)
5268 #define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_SET(x) (((x) << 0) & 0xffffffff)
5270 /* macros for BB_tx_gain_tab_31 */
5271 #define PHY_BB_TX_GAIN_TAB_31_ADDRESS 0x0000a478
5272 #define PHY_BB_TX_GAIN_TAB_31_OFFSET 0x0000a478
5273 #define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_MSB 31
5274 #define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_LSB 0
5275 #define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_MASK 0xffffffff
5276 #define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_GET(x) (((x) & 0xffffffff) >> 0)
5277 #define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_SET(x) (((x) << 0) & 0xffffffff)
5279 /* macros for BB_tx_gain_tab_32 */
5280 #define PHY_BB_TX_GAIN_TAB_32_ADDRESS 0x0000a47c
5281 #define PHY_BB_TX_GAIN_TAB_32_OFFSET 0x0000a47c
5282 #define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_MSB 31
5283 #define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_LSB 0
5284 #define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_MASK 0xffffffff
5285 #define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_GET(x) (((x) & 0xffffffff) >> 0)
5286 #define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_SET(x) (((x) << 0) & 0xffffffff)
5288 /* macros for BB_tx_gain_tab_pal_1 */
5289 #define PHY_BB_TX_GAIN_TAB_PAL_1_ADDRESS 0x0000a480
5290 #define PHY_BB_TX_GAIN_TAB_PAL_1_OFFSET 0x0000a480
5291 #define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_MSB 31
5292 #define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_LSB 0
5293 #define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_MASK 0xffffffff
5294 #define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5295 #define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5297 /* macros for BB_tx_gain_tab_pal_2 */
5298 #define PHY_BB_TX_GAIN_TAB_PAL_2_ADDRESS 0x0000a484
5299 #define PHY_BB_TX_GAIN_TAB_PAL_2_OFFSET 0x0000a484
5300 #define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_MSB 31
5301 #define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_LSB 0
5302 #define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_MASK 0xffffffff
5303 #define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5304 #define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5306 /* macros for BB_tx_gain_tab_pal_3 */
5307 #define PHY_BB_TX_GAIN_TAB_PAL_3_ADDRESS 0x0000a488
5308 #define PHY_BB_TX_GAIN_TAB_PAL_3_OFFSET 0x0000a488
5309 #define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_MSB 31
5310 #define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_LSB 0
5311 #define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_MASK 0xffffffff
5312 #define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5313 #define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5315 /* macros for BB_tx_gain_tab_pal_4 */
5316 #define PHY_BB_TX_GAIN_TAB_PAL_4_ADDRESS 0x0000a48c
5317 #define PHY_BB_TX_GAIN_TAB_PAL_4_OFFSET 0x0000a48c
5318 #define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_MSB 31
5319 #define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_LSB 0
5320 #define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_MASK 0xffffffff
5321 #define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5322 #define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5324 /* macros for BB_tx_gain_tab_pal_5 */
5325 #define PHY_BB_TX_GAIN_TAB_PAL_5_ADDRESS 0x0000a490
5326 #define PHY_BB_TX_GAIN_TAB_PAL_5_OFFSET 0x0000a490
5327 #define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_MSB 31
5328 #define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_LSB 0
5329 #define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_MASK 0xffffffff
5330 #define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5331 #define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5333 /* macros for BB_tx_gain_tab_pal_6 */
5334 #define PHY_BB_TX_GAIN_TAB_PAL_6_ADDRESS 0x0000a494
5335 #define PHY_BB_TX_GAIN_TAB_PAL_6_OFFSET 0x0000a494
5336 #define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_MSB 31
5337 #define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_LSB 0
5338 #define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_MASK 0xffffffff
5339 #define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5340 #define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5342 /* macros for BB_tx_gain_tab_pal_7 */
5343 #define PHY_BB_TX_GAIN_TAB_PAL_7_ADDRESS 0x0000a498
5344 #define PHY_BB_TX_GAIN_TAB_PAL_7_OFFSET 0x0000a498
5345 #define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_MSB 31
5346 #define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_LSB 0
5347 #define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_MASK 0xffffffff
5348 #define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5349 #define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5351 /* macros for BB_tx_gain_tab_pal_8 */
5352 #define PHY_BB_TX_GAIN_TAB_PAL_8_ADDRESS 0x0000a49c
5353 #define PHY_BB_TX_GAIN_TAB_PAL_8_OFFSET 0x0000a49c
5354 #define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_MSB 31
5355 #define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_LSB 0
5356 #define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_MASK 0xffffffff
5357 #define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5358 #define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5360 /* macros for BB_tx_gain_tab_pal_9 */
5361 #define PHY_BB_TX_GAIN_TAB_PAL_9_ADDRESS 0x0000a4a0
5362 #define PHY_BB_TX_GAIN_TAB_PAL_9_OFFSET 0x0000a4a0
5363 #define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_MSB 31
5364 #define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_LSB 0
5365 #define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_MASK 0xffffffff
5366 #define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5367 #define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5369 /* macros for BB_tx_gain_tab_pal_10 */
5370 #define PHY_BB_TX_GAIN_TAB_PAL_10_ADDRESS 0x0000a4a4
5371 #define PHY_BB_TX_GAIN_TAB_PAL_10_OFFSET 0x0000a4a4
5372 #define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_MSB 31
5373 #define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_LSB 0
5374 #define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_MASK 0xffffffff
5375 #define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5376 #define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5378 /* macros for BB_tx_gain_tab_pal_11 */
5379 #define PHY_BB_TX_GAIN_TAB_PAL_11_ADDRESS 0x0000a4a8
5380 #define PHY_BB_TX_GAIN_TAB_PAL_11_OFFSET 0x0000a4a8
5381 #define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_MSB 31
5382 #define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_LSB 0
5383 #define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_MASK 0xffffffff
5384 #define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5385 #define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5387 /* macros for BB_tx_gain_tab_pal_12 */
5388 #define PHY_BB_TX_GAIN_TAB_PAL_12_ADDRESS 0x0000a4ac
5389 #define PHY_BB_TX_GAIN_TAB_PAL_12_OFFSET 0x0000a4ac
5390 #define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_MSB 31
5391 #define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_LSB 0
5392 #define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_MASK 0xffffffff
5393 #define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5394 #define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5396 /* macros for BB_tx_gain_tab_pal_13 */
5397 #define PHY_BB_TX_GAIN_TAB_PAL_13_ADDRESS 0x0000a4b0
5398 #define PHY_BB_TX_GAIN_TAB_PAL_13_OFFSET 0x0000a4b0
5399 #define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_MSB 31
5400 #define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_LSB 0
5401 #define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_MASK 0xffffffff
5402 #define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5403 #define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5405 /* macros for BB_tx_gain_tab_pal_14 */
5406 #define PHY_BB_TX_GAIN_TAB_PAL_14_ADDRESS 0x0000a4b4
5407 #define PHY_BB_TX_GAIN_TAB_PAL_14_OFFSET 0x0000a4b4
5408 #define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_MSB 31
5409 #define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_LSB 0
5410 #define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_MASK 0xffffffff
5411 #define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5412 #define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5414 /* macros for BB_tx_gain_tab_pal_15 */
5415 #define PHY_BB_TX_GAIN_TAB_PAL_15_ADDRESS 0x0000a4b8
5416 #define PHY_BB_TX_GAIN_TAB_PAL_15_OFFSET 0x0000a4b8
5417 #define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_MSB 31
5418 #define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_LSB 0
5419 #define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_MASK 0xffffffff
5420 #define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5421 #define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5423 /* macros for BB_tx_gain_tab_pal_16 */
5424 #define PHY_BB_TX_GAIN_TAB_PAL_16_ADDRESS 0x0000a4bc
5425 #define PHY_BB_TX_GAIN_TAB_PAL_16_OFFSET 0x0000a4bc
5426 #define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_MSB 31
5427 #define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_LSB 0
5428 #define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_MASK 0xffffffff
5429 #define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5430 #define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5432 /* macros for BB_tx_gain_tab_pal_17 */
5433 #define PHY_BB_TX_GAIN_TAB_PAL_17_ADDRESS 0x0000a4c0
5434 #define PHY_BB_TX_GAIN_TAB_PAL_17_OFFSET 0x0000a4c0
5435 #define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_MSB 31
5436 #define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_LSB 0
5437 #define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_MASK 0xffffffff
5438 #define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5439 #define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5441 /* macros for BB_tx_gain_tab_pal_18 */
5442 #define PHY_BB_TX_GAIN_TAB_PAL_18_ADDRESS 0x0000a4c4
5443 #define PHY_BB_TX_GAIN_TAB_PAL_18_OFFSET 0x0000a4c4
5444 #define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_MSB 31
5445 #define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_LSB 0
5446 #define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_MASK 0xffffffff
5447 #define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5448 #define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5450 /* macros for BB_tx_gain_tab_pal_19 */
5451 #define PHY_BB_TX_GAIN_TAB_PAL_19_ADDRESS 0x0000a4c8
5452 #define PHY_BB_TX_GAIN_TAB_PAL_19_OFFSET 0x0000a4c8
5453 #define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_MSB 31
5454 #define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_LSB 0
5455 #define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_MASK 0xffffffff
5456 #define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5457 #define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5459 /* macros for BB_tx_gain_tab_pal_20 */
5460 #define PHY_BB_TX_GAIN_TAB_PAL_20_ADDRESS 0x0000a4cc
5461 #define PHY_BB_TX_GAIN_TAB_PAL_20_OFFSET 0x0000a4cc
5462 #define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_MSB 31
5463 #define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_LSB 0
5464 #define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_MASK 0xffffffff
5465 #define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5466 #define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5468 /* macros for BB_tx_gain_tab_pal_21 */
5469 #define PHY_BB_TX_GAIN_TAB_PAL_21_ADDRESS 0x0000a4d0
5470 #define PHY_BB_TX_GAIN_TAB_PAL_21_OFFSET 0x0000a4d0
5471 #define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_MSB 31
5472 #define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_LSB 0
5473 #define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_MASK 0xffffffff
5474 #define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5475 #define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5477 /* macros for BB_tx_gain_tab_pal_22 */
5478 #define PHY_BB_TX_GAIN_TAB_PAL_22_ADDRESS 0x0000a4d4
5479 #define PHY_BB_TX_GAIN_TAB_PAL_22_OFFSET 0x0000a4d4
5480 #define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_MSB 31
5481 #define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_LSB 0
5482 #define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_MASK 0xffffffff
5483 #define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5484 #define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5486 /* macros for BB_tx_gain_tab_pal_23 */
5487 #define PHY_BB_TX_GAIN_TAB_PAL_23_ADDRESS 0x0000a4d8
5488 #define PHY_BB_TX_GAIN_TAB_PAL_23_OFFSET 0x0000a4d8
5489 #define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_MSB 31
5490 #define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_LSB 0
5491 #define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_MASK 0xffffffff
5492 #define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5493 #define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5495 /* macros for BB_tx_gain_tab_pal_24 */
5496 #define PHY_BB_TX_GAIN_TAB_PAL_24_ADDRESS 0x0000a4dc
5497 #define PHY_BB_TX_GAIN_TAB_PAL_24_OFFSET 0x0000a4dc
5498 #define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_MSB 31
5499 #define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_LSB 0
5500 #define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_MASK 0xffffffff
5501 #define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5502 #define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5504 /* macros for BB_tx_gain_tab_pal_25 */
5505 #define PHY_BB_TX_GAIN_TAB_PAL_25_ADDRESS 0x0000a4e0
5506 #define PHY_BB_TX_GAIN_TAB_PAL_25_OFFSET 0x0000a4e0
5507 #define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_MSB 31
5508 #define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_LSB 0
5509 #define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_MASK 0xffffffff
5510 #define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5511 #define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5513 /* macros for BB_tx_gain_tab_pal_26 */
5514 #define PHY_BB_TX_GAIN_TAB_PAL_26_ADDRESS 0x0000a4e4
5515 #define PHY_BB_TX_GAIN_TAB_PAL_26_OFFSET 0x0000a4e4
5516 #define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_MSB 31
5517 #define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_LSB 0
5518 #define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_MASK 0xffffffff
5519 #define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5520 #define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5522 /* macros for BB_tx_gain_tab_pal_27 */
5523 #define PHY_BB_TX_GAIN_TAB_PAL_27_ADDRESS 0x0000a4e8
5524 #define PHY_BB_TX_GAIN_TAB_PAL_27_OFFSET 0x0000a4e8
5525 #define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_MSB 31
5526 #define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_LSB 0
5527 #define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_MASK 0xffffffff
5528 #define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5529 #define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5531 /* macros for BB_tx_gain_tab_pal_28 */
5532 #define PHY_BB_TX_GAIN_TAB_PAL_28_ADDRESS 0x0000a4ec
5533 #define PHY_BB_TX_GAIN_TAB_PAL_28_OFFSET 0x0000a4ec
5534 #define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_MSB 31
5535 #define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_LSB 0
5536 #define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_MASK 0xffffffff
5537 #define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5538 #define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5540 /* macros for BB_tx_gain_tab_pal_29 */
5541 #define PHY_BB_TX_GAIN_TAB_PAL_29_ADDRESS 0x0000a4f0
5542 #define PHY_BB_TX_GAIN_TAB_PAL_29_OFFSET 0x0000a4f0
5543 #define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_MSB 31
5544 #define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_LSB 0
5545 #define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_MASK 0xffffffff
5546 #define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5547 #define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5549 /* macros for BB_tx_gain_tab_pal_30 */
5550 #define PHY_BB_TX_GAIN_TAB_PAL_30_ADDRESS 0x0000a4f4
5551 #define PHY_BB_TX_GAIN_TAB_PAL_30_OFFSET 0x0000a4f4
5552 #define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_MSB 31
5553 #define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_LSB 0
5554 #define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_MASK 0xffffffff
5555 #define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5556 #define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5558 /* macros for BB_tx_gain_tab_pal_31 */
5559 #define PHY_BB_TX_GAIN_TAB_PAL_31_ADDRESS 0x0000a4f8
5560 #define PHY_BB_TX_GAIN_TAB_PAL_31_OFFSET 0x0000a4f8
5561 #define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_MSB 31
5562 #define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_LSB 0
5563 #define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_MASK 0xffffffff
5564 #define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5565 #define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5567 /* macros for BB_tx_gain_tab_pal_32 */
5568 #define PHY_BB_TX_GAIN_TAB_PAL_32_ADDRESS 0x0000a4fc
5569 #define PHY_BB_TX_GAIN_TAB_PAL_32_OFFSET 0x0000a4fc
5570 #define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_MSB 31
5571 #define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_LSB 0
5572 #define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_MASK 0xffffffff
5573 #define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
5574 #define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
5576 /* macros for BB_caltx_gain_set_0 */
5577 #define PHY_BB_CALTX_GAIN_SET_0_ADDRESS 0x0000a518
5578 #define PHY_BB_CALTX_GAIN_SET_0_OFFSET 0x0000a518
5579 #define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_MSB 13
5580 #define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_LSB 0
5581 #define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_MASK 0x00003fff
5582 #define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_GET(x) (((x) & 0x00003fff) >> 0)
5583 #define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_SET(x) (((x) << 0) & 0x00003fff)
5584 #define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_MSB 27
5585 #define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_LSB 14
5586 #define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_MASK 0x0fffc000
5587 #define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_GET(x) (((x) & 0x0fffc000) >> 14)
5588 #define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_SET(x) (((x) << 14) & 0x0fffc000)
5590 /* macros for BB_caltx_gain_set_2 */
5591 #define PHY_BB_CALTX_GAIN_SET_2_ADDRESS 0x0000a51c
5592 #define PHY_BB_CALTX_GAIN_SET_2_OFFSET 0x0000a51c
5593 #define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_MSB 13
5594 #define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_LSB 0
5595 #define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_MASK 0x00003fff
5596 #define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_GET(x) (((x) & 0x00003fff) >> 0)
5597 #define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_SET(x) (((x) << 0) & 0x00003fff)
5598 #define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_MSB 27
5599 #define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_LSB 14
5600 #define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_MASK 0x0fffc000
5601 #define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_GET(x) (((x) & 0x0fffc000) >> 14)
5602 #define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_SET(x) (((x) << 14) & 0x0fffc000)
5604 /* macros for BB_caltx_gain_set_4 */
5605 #define PHY_BB_CALTX_GAIN_SET_4_ADDRESS 0x0000a520
5606 #define PHY_BB_CALTX_GAIN_SET_4_OFFSET 0x0000a520
5607 #define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_MSB 13
5608 #define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_LSB 0
5609 #define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_MASK 0x00003fff
5610 #define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_GET(x) (((x) & 0x00003fff) >> 0)
5611 #define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_SET(x) (((x) << 0) & 0x00003fff)
5612 #define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_MSB 27
5613 #define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_LSB 14
5614 #define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_MASK 0x0fffc000
5615 #define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_GET(x) (((x) & 0x0fffc000) >> 14)
5616 #define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_SET(x) (((x) << 14) & 0x0fffc000)
5618 /* macros for BB_caltx_gain_set_6 */
5619 #define PHY_BB_CALTX_GAIN_SET_6_ADDRESS 0x0000a524
5620 #define PHY_BB_CALTX_GAIN_SET_6_OFFSET 0x0000a524
5621 #define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_MSB 13
5622 #define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_LSB 0
5623 #define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_MASK 0x00003fff
5624 #define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_GET(x) (((x) & 0x00003fff) >> 0)
5625 #define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_SET(x) (((x) << 0) & 0x00003fff)
5626 #define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_MSB 27
5627 #define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_LSB 14
5628 #define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_MASK 0x0fffc000
5629 #define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_GET(x) (((x) & 0x0fffc000) >> 14)
5630 #define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_SET(x) (((x) << 14) & 0x0fffc000)
5632 /* macros for BB_caltx_gain_set_8 */
5633 #define PHY_BB_CALTX_GAIN_SET_8_ADDRESS 0x0000a528
5634 #define PHY_BB_CALTX_GAIN_SET_8_OFFSET 0x0000a528
5635 #define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_MSB 13
5636 #define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_LSB 0
5637 #define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_MASK 0x00003fff
5638 #define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_GET(x) (((x) & 0x00003fff) >> 0)
5639 #define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_SET(x) (((x) << 0) & 0x00003fff)
5640 #define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_MSB 27
5641 #define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_LSB 14
5642 #define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_MASK 0x0fffc000
5643 #define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_GET(x) (((x) & 0x0fffc000) >> 14)
5644 #define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_SET(x) (((x) << 14) & 0x0fffc000)
5646 /* macros for BB_caltx_gain_set_10 */
5647 #define PHY_BB_CALTX_GAIN_SET_10_ADDRESS 0x0000a52c
5648 #define PHY_BB_CALTX_GAIN_SET_10_OFFSET 0x0000a52c
5649 #define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_MSB 13
5650 #define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_LSB 0
5651 #define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_MASK 0x00003fff
5652 #define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_GET(x) (((x) & 0x00003fff) >> 0)
5653 #define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_SET(x) (((x) << 0) & 0x00003fff)
5654 #define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_MSB 27
5655 #define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_LSB 14
5656 #define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_MASK 0x0fffc000
5657 #define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_GET(x) (((x) & 0x0fffc000) >> 14)
5658 #define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_SET(x) (((x) << 14) & 0x0fffc000)
5660 /* macros for BB_caltx_gain_set_12 */
5661 #define PHY_BB_CALTX_GAIN_SET_12_ADDRESS 0x0000a530
5662 #define PHY_BB_CALTX_GAIN_SET_12_OFFSET 0x0000a530
5663 #define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_MSB 13
5664 #define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_LSB 0
5665 #define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_MASK 0x00003fff
5666 #define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_GET(x) (((x) & 0x00003fff) >> 0)
5667 #define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_SET(x) (((x) << 0) & 0x00003fff)
5668 #define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_MSB 27
5669 #define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_LSB 14
5670 #define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_MASK 0x0fffc000
5671 #define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_GET(x) (((x) & 0x0fffc000) >> 14)
5672 #define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_SET(x) (((x) << 14) & 0x0fffc000)
5674 /* macros for BB_caltx_gain_set_14 */
5675 #define PHY_BB_CALTX_GAIN_SET_14_ADDRESS 0x0000a534
5676 #define PHY_BB_CALTX_GAIN_SET_14_OFFSET 0x0000a534
5677 #define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_MSB 13
5678 #define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_LSB 0
5679 #define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_MASK 0x00003fff
5680 #define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_GET(x) (((x) & 0x00003fff) >> 0)
5681 #define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_SET(x) (((x) << 0) & 0x00003fff)
5682 #define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_MSB 27
5683 #define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_LSB 14
5684 #define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_MASK 0x0fffc000
5685 #define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_GET(x) (((x) & 0x0fffc000) >> 14)
5686 #define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_SET(x) (((x) << 14) & 0x0fffc000)
5688 /* macros for BB_caltx_gain_set_16 */
5689 #define PHY_BB_CALTX_GAIN_SET_16_ADDRESS 0x0000a538
5690 #define PHY_BB_CALTX_GAIN_SET_16_OFFSET 0x0000a538
5691 #define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_MSB 13
5692 #define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_LSB 0
5693 #define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_MASK 0x00003fff
5694 #define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_GET(x) (((x) & 0x00003fff) >> 0)
5695 #define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_SET(x) (((x) << 0) & 0x00003fff)
5696 #define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_MSB 27
5697 #define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_LSB 14
5698 #define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_MASK 0x0fffc000
5699 #define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_GET(x) (((x) & 0x0fffc000) >> 14)
5700 #define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_SET(x) (((x) << 14) & 0x0fffc000)
5702 /* macros for BB_caltx_gain_set_18 */
5703 #define PHY_BB_CALTX_GAIN_SET_18_ADDRESS 0x0000a53c
5704 #define PHY_BB_CALTX_GAIN_SET_18_OFFSET 0x0000a53c
5705 #define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_MSB 13
5706 #define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_LSB 0
5707 #define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_MASK 0x00003fff
5708 #define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_GET(x) (((x) & 0x00003fff) >> 0)
5709 #define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_SET(x) (((x) << 0) & 0x00003fff)
5710 #define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_MSB 27
5711 #define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_LSB 14
5712 #define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_MASK 0x0fffc000
5713 #define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_GET(x) (((x) & 0x0fffc000) >> 14)
5714 #define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_SET(x) (((x) << 14) & 0x0fffc000)
5716 /* macros for BB_caltx_gain_set_20 */
5717 #define PHY_BB_CALTX_GAIN_SET_20_ADDRESS 0x0000a540
5718 #define PHY_BB_CALTX_GAIN_SET_20_OFFSET 0x0000a540
5719 #define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_MSB 13
5720 #define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_LSB 0
5721 #define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_MASK 0x00003fff
5722 #define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_GET(x) (((x) & 0x00003fff) >> 0)
5723 #define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_SET(x) (((x) << 0) & 0x00003fff)
5724 #define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_MSB 27
5725 #define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_LSB 14
5726 #define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_MASK 0x0fffc000
5727 #define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_GET(x) (((x) & 0x0fffc000) >> 14)
5728 #define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_SET(x) (((x) << 14) & 0x0fffc000)
5730 /* macros for BB_caltx_gain_set_22 */
5731 #define PHY_BB_CALTX_GAIN_SET_22_ADDRESS 0x0000a544
5732 #define PHY_BB_CALTX_GAIN_SET_22_OFFSET 0x0000a544
5733 #define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_MSB 13
5734 #define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_LSB 0
5735 #define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_MASK 0x00003fff
5736 #define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_GET(x) (((x) & 0x00003fff) >> 0)
5737 #define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_SET(x) (((x) << 0) & 0x00003fff)
5738 #define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_MSB 27
5739 #define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_LSB 14
5740 #define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_MASK 0x0fffc000
5741 #define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_GET(x) (((x) & 0x0fffc000) >> 14)
5742 #define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_SET(x) (((x) << 14) & 0x0fffc000)
5744 /* macros for BB_caltx_gain_set_24 */
5745 #define PHY_BB_CALTX_GAIN_SET_24_ADDRESS 0x0000a548
5746 #define PHY_BB_CALTX_GAIN_SET_24_OFFSET 0x0000a548
5747 #define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_MSB 13
5748 #define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_LSB 0
5749 #define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_MASK 0x00003fff
5750 #define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_GET(x) (((x) & 0x00003fff) >> 0)
5751 #define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_SET(x) (((x) << 0) & 0x00003fff)
5752 #define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_MSB 27
5753 #define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_LSB 14
5754 #define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_MASK 0x0fffc000
5755 #define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_GET(x) (((x) & 0x0fffc000) >> 14)
5756 #define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_SET(x) (((x) << 14) & 0x0fffc000)
5758 /* macros for BB_caltx_gain_set_26 */
5759 #define PHY_BB_CALTX_GAIN_SET_26_ADDRESS 0x0000a54c
5760 #define PHY_BB_CALTX_GAIN_SET_26_OFFSET 0x0000a54c
5761 #define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_MSB 13
5762 #define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_LSB 0
5763 #define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_MASK 0x00003fff
5764 #define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_GET(x) (((x) & 0x00003fff) >> 0)
5765 #define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_SET(x) (((x) << 0) & 0x00003fff)
5766 #define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_MSB 27
5767 #define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_LSB 14
5768 #define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_MASK 0x0fffc000
5769 #define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_GET(x) (((x) & 0x0fffc000) >> 14)
5770 #define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_SET(x) (((x) << 14) & 0x0fffc000)
5772 /* macros for BB_caltx_gain_set_28 */
5773 #define PHY_BB_CALTX_GAIN_SET_28_ADDRESS 0x0000a550
5774 #define PHY_BB_CALTX_GAIN_SET_28_OFFSET 0x0000a550
5775 #define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_MSB 13
5776 #define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_LSB 0
5777 #define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_MASK 0x00003fff
5778 #define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_GET(x) (((x) & 0x00003fff) >> 0)
5779 #define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_SET(x) (((x) << 0) & 0x00003fff)
5780 #define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_MSB 27
5781 #define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_LSB 14
5782 #define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_MASK 0x0fffc000
5783 #define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_GET(x) (((x) & 0x0fffc000) >> 14)
5784 #define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_SET(x) (((x) << 14) & 0x0fffc000)
5786 /* macros for BB_caltx_gain_set_30 */
5787 #define PHY_BB_CALTX_GAIN_SET_30_ADDRESS 0x0000a554
5788 #define PHY_BB_CALTX_GAIN_SET_30_OFFSET 0x0000a554
5789 #define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_MSB 13
5790 #define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_LSB 0
5791 #define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_MASK 0x00003fff
5792 #define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_GET(x) (((x) & 0x00003fff) >> 0)
5793 #define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_SET(x) (((x) << 0) & 0x00003fff)
5794 #define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_MSB 27
5795 #define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_LSB 14
5796 #define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_MASK 0x0fffc000
5797 #define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_GET(x) (((x) & 0x0fffc000) >> 14)
5798 #define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_SET(x) (((x) << 14) & 0x0fffc000)
5800 /* macros for BB_txiqcal_meas_b0 */
5801 #define PHY_BB_TXIQCAL_MEAS_B0_ADDRESS 0x0000a558
5802 #define PHY_BB_TXIQCAL_MEAS_B0_OFFSET 0x0000a558
5803 #define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_MSB 11
5804 #define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_LSB 0
5805 #define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_MASK 0x00000fff
5806 #define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_GET(x) (((x) & 0x00000fff) >> 0)
5807 #define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_MSB 23
5808 #define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_LSB 12
5809 #define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_MASK 0x00fff000
5810 #define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_GET(x) (((x) & 0x00fff000) >> 12)
5812 /* macros for BB_txiqcal_start */
5813 #define PHY_BB_TXIQCAL_START_ADDRESS 0x0000a6d8
5814 #define PHY_BB_TXIQCAL_START_OFFSET 0x0000a6d8
5815 #define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_MSB 0
5816 #define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_LSB 0
5817 #define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_MASK 0x00000001
5818 #define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_GET(x) (((x) & 0x00000001) >> 0)
5819 #define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_SET(x) (((x) << 0) & 0x00000001)
5821 /* macros for BB_txiqcal_control_0 */
5822 #define PHY_BB_TXIQCAL_CONTROL_0_ADDRESS 0x0000a6dc
5823 #define PHY_BB_TXIQCAL_CONTROL_0_OFFSET 0x0000a6dc
5824 #define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_MSB 0
5825 #define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_LSB 0
5826 #define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_MASK 0x00000001
5827 #define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_GET(x) (((x) & 0x00000001) >> 0)
5828 #define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_SET(x) (((x) << 0) & 0x00000001)
5829 #define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MSB 6
5830 #define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_LSB 1
5831 #define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MASK 0x0000007e
5832 #define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_GET(x) (((x) & 0x0000007e) >> 1)
5833 #define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_SET(x) (((x) << 1) & 0x0000007e)
5834 #define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MSB 12
5835 #define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_LSB 7
5836 #define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MASK 0x00001f80
5837 #define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_GET(x) (((x) & 0x00001f80) >> 7)
5838 #define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_SET(x) (((x) << 7) & 0x00001f80)
5839 #define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MSB 18
5840 #define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_LSB 13
5841 #define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MASK 0x0007e000
5842 #define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_GET(x) (((x) & 0x0007e000) >> 13)
5843 #define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_SET(x) (((x) << 13) & 0x0007e000)
5844 #define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MSB 22
5845 #define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_LSB 19
5846 #define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MASK 0x00780000
5847 #define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_GET(x) (((x) & 0x00780000) >> 19)
5848 #define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_SET(x) (((x) << 19) & 0x00780000)
5849 #define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MSB 29
5850 #define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_LSB 23
5851 #define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MASK 0x3f800000
5852 #define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_GET(x) (((x) & 0x3f800000) >> 23)
5853 #define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_SET(x) (((x) << 23) & 0x3f800000)
5855 /* macros for BB_txiqcal_control_1 */
5856 #define PHY_BB_TXIQCAL_CONTROL_1_ADDRESS 0x0000a6e0
5857 #define PHY_BB_TXIQCAL_CONTROL_1_OFFSET 0x0000a6e0
5858 #define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MSB 5
5859 #define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_LSB 0
5860 #define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MASK 0x0000003f
5861 #define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_GET(x) (((x) & 0x0000003f) >> 0)
5862 #define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_SET(x) (((x) << 0) & 0x0000003f)
5863 #define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MSB 11
5864 #define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_LSB 6
5865 #define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MASK 0x00000fc0
5866 #define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_GET(x) (((x) & 0x00000fc0) >> 6)
5867 #define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_SET(x) (((x) << 6) & 0x00000fc0)
5868 #define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MSB 17
5869 #define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_LSB 12
5870 #define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MASK 0x0003f000
5871 #define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_GET(x) (((x) & 0x0003f000) >> 12)
5872 #define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_SET(x) (((x) << 12) & 0x0003f000)
5873 #define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MSB 24
5874 #define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_LSB 18
5875 #define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MASK 0x01fc0000
5876 #define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_GET(x) (((x) & 0x01fc0000) >> 18)
5877 #define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_SET(x) (((x) << 18) & 0x01fc0000)
5879 /* macros for BB_txiqcal_control_2 */
5880 #define PHY_BB_TXIQCAL_CONTROL_2_ADDRESS 0x0000a6e4
5881 #define PHY_BB_TXIQCAL_CONTROL_2_OFFSET 0x0000a6e4
5882 #define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_MSB 3
5883 #define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_LSB 0
5884 #define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_MASK 0x0000000f
5885 #define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_GET(x) (((x) & 0x0000000f) >> 0)
5886 #define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_SET(x) (((x) << 0) & 0x0000000f)
5887 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MSB 8
5888 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_LSB 4
5889 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MASK 0x000001f0
5890 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_GET(x) (((x) & 0x000001f0) >> 4)
5891 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_SET(x) (((x) << 4) & 0x000001f0)
5892 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MSB 13
5893 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_LSB 9
5894 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MASK 0x00003e00
5895 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_GET(x) (((x) & 0x00003e00) >> 9)
5896 #define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_SET(x) (((x) << 9) & 0x00003e00)
5898 /* macros for BB_txiqcal_control_3 */
5899 #define PHY_BB_TXIQCAL_CONTROL_3_ADDRESS 0x0000a6e8
5900 #define PHY_BB_TXIQCAL_CONTROL_3_OFFSET 0x0000a6e8
5901 #define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MSB 5
5902 #define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_LSB 0
5903 #define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MASK 0x0000003f
5904 #define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_GET(x) (((x) & 0x0000003f) >> 0)
5905 #define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_SET(x) (((x) << 0) & 0x0000003f)
5906 #define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MSB 11
5907 #define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_LSB 6
5908 #define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MASK 0x00000fc0
5909 #define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_GET(x) (((x) & 0x00000fc0) >> 6)
5910 #define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_SET(x) (((x) << 6) & 0x00000fc0)
5911 #define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MSB 21
5912 #define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_LSB 12
5913 #define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MASK 0x003ff000
5914 #define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_GET(x) (((x) & 0x003ff000) >> 12)
5915 #define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_SET(x) (((x) << 12) & 0x003ff000)
5916 #define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MSB 23
5917 #define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_LSB 22
5918 #define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MASK 0x00c00000
5919 #define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_GET(x) (((x) & 0x00c00000) >> 22)
5920 #define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_SET(x) (((x) << 22) & 0x00c00000)
5921 #define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_MSB 24
5922 #define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_LSB 24
5923 #define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_MASK 0x01000000
5924 #define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_GET(x) (((x) & 0x01000000) >> 24)
5925 #define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_SET(x) (((x) << 24) & 0x01000000)
5926 #define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_MSB 26
5927 #define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_LSB 25
5928 #define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_MASK 0x06000000
5929 #define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_GET(x) (((x) & 0x06000000) >> 25)
5930 #define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_SET(x) (((x) << 25) & 0x06000000)
5931 #define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_MSB 28
5932 #define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_LSB 27
5933 #define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_MASK 0x18000000
5934 #define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_GET(x) (((x) & 0x18000000) >> 27)
5935 #define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_SET(x) (((x) << 27) & 0x18000000)
5936 #define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MSB 30
5937 #define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_LSB 29
5938 #define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MASK 0x60000000
5939 #define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_GET(x) (((x) & 0x60000000) >> 29)
5940 #define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_SET(x) (((x) << 29) & 0x60000000)
5941 #define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MSB 31
5942 #define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_LSB 31
5943 #define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MASK 0x80000000
5944 #define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_GET(x) (((x) & 0x80000000) >> 31)
5945 #define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_SET(x) (((x) << 31) & 0x80000000)
5947 /* macros for BB_txiq_corr_coeff_01_b0 */
5948 #define PHY_BB_TXIQ_CORR_COEFF_01_B0_ADDRESS 0x0000a6ec
5949 #define PHY_BB_TXIQ_CORR_COEFF_01_B0_OFFSET 0x0000a6ec
5950 #define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_MSB 13
5951 #define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_LSB 0
5952 #define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_MASK 0x00003fff
5953 #define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_GET(x) (((x) & 0x00003fff) >> 0)
5954 #define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_SET(x) (((x) << 0) & 0x00003fff)
5955 #define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_MSB 27
5956 #define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_LSB 14
5957 #define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_MASK 0x0fffc000
5958 #define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_GET(x) (((x) & 0x0fffc000) >> 14)
5959 #define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_SET(x) (((x) << 14) & 0x0fffc000)
5961 /* macros for BB_txiq_corr_coeff_23_b0 */
5962 #define PHY_BB_TXIQ_CORR_COEFF_23_B0_ADDRESS 0x0000a6f0
5963 #define PHY_BB_TXIQ_CORR_COEFF_23_B0_OFFSET 0x0000a6f0
5964 #define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_MSB 13
5965 #define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_LSB 0
5966 #define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_MASK 0x00003fff
5967 #define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_GET(x) (((x) & 0x00003fff) >> 0)
5968 #define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_SET(x) (((x) << 0) & 0x00003fff)
5969 #define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_MSB 27
5970 #define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_LSB 14
5971 #define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_MASK 0x0fffc000
5972 #define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_GET(x) (((x) & 0x0fffc000) >> 14)
5973 #define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_SET(x) (((x) << 14) & 0x0fffc000)
5975 /* macros for BB_txiq_corr_coeff_45_b0 */
5976 #define PHY_BB_TXIQ_CORR_COEFF_45_B0_ADDRESS 0x0000a6f4
5977 #define PHY_BB_TXIQ_CORR_COEFF_45_B0_OFFSET 0x0000a6f4
5978 #define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_MSB 13
5979 #define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_LSB 0
5980 #define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_MASK 0x00003fff
5981 #define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_GET(x) (((x) & 0x00003fff) >> 0)
5982 #define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_SET(x) (((x) << 0) & 0x00003fff)
5983 #define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_MSB 27
5984 #define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_LSB 14
5985 #define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_MASK 0x0fffc000
5986 #define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_GET(x) (((x) & 0x0fffc000) >> 14)
5987 #define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_SET(x) (((x) << 14) & 0x0fffc000)
5989 /* macros for BB_txiq_corr_coeff_67_b0 */
5990 #define PHY_BB_TXIQ_CORR_COEFF_67_B0_ADDRESS 0x0000a6f8
5991 #define PHY_BB_TXIQ_CORR_COEFF_67_B0_OFFSET 0x0000a6f8
5992 #define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_MSB 13
5993 #define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_LSB 0
5994 #define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_MASK 0x00003fff
5995 #define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_GET(x) (((x) & 0x00003fff) >> 0)
5996 #define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_SET(x) (((x) << 0) & 0x00003fff)
5997 #define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_MSB 27
5998 #define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_LSB 14
5999 #define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_MASK 0x0fffc000
6000 #define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_GET(x) (((x) & 0x0fffc000) >> 14)
6001 #define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_SET(x) (((x) << 14) & 0x0fffc000)
6003 /* macros for BB_txiq_corr_coeff_89_b0 */
6004 #define PHY_BB_TXIQ_CORR_COEFF_89_B0_ADDRESS 0x0000a6fc
6005 #define PHY_BB_TXIQ_CORR_COEFF_89_B0_OFFSET 0x0000a6fc
6006 #define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_MSB 13
6007 #define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_LSB 0
6008 #define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_MASK 0x00003fff
6009 #define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_GET(x) (((x) & 0x00003fff) >> 0)
6010 #define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_SET(x) (((x) << 0) & 0x00003fff)
6011 #define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_MSB 27
6012 #define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_LSB 14
6013 #define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_MASK 0x0fffc000
6014 #define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_GET(x) (((x) & 0x0fffc000) >> 14)
6015 #define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_SET(x) (((x) << 14) & 0x0fffc000)
6017 /* macros for BB_txiq_corr_coeff_ab_b0 */
6018 #define PHY_BB_TXIQ_CORR_COEFF_AB_B0_ADDRESS 0x0000a700
6019 #define PHY_BB_TXIQ_CORR_COEFF_AB_B0_OFFSET 0x0000a700
6020 #define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_MSB 13
6021 #define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_LSB 0
6022 #define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_MASK 0x00003fff
6023 #define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_GET(x) (((x) & 0x00003fff) >> 0)
6024 #define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_SET(x) (((x) << 0) & 0x00003fff)
6025 #define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_MSB 27
6026 #define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_LSB 14
6027 #define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_MASK 0x0fffc000
6028 #define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_GET(x) (((x) & 0x0fffc000) >> 14)
6029 #define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_SET(x) (((x) << 14) & 0x0fffc000)
6031 /* macros for BB_txiq_corr_coeff_cd_b0 */
6032 #define PHY_BB_TXIQ_CORR_COEFF_CD_B0_ADDRESS 0x0000a704
6033 #define PHY_BB_TXIQ_CORR_COEFF_CD_B0_OFFSET 0x0000a704
6034 #define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_MSB 13
6035 #define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_LSB 0
6036 #define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_MASK 0x00003fff
6037 #define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_GET(x) (((x) & 0x00003fff) >> 0)
6038 #define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_SET(x) (((x) << 0) & 0x00003fff)
6039 #define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_MSB 27
6040 #define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_LSB 14
6041 #define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_MASK 0x0fffc000
6042 #define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_GET(x) (((x) & 0x0fffc000) >> 14)
6043 #define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_SET(x) (((x) << 14) & 0x0fffc000)
6045 /* macros for BB_txiq_corr_coeff_ef_b0 */
6046 #define PHY_BB_TXIQ_CORR_COEFF_EF_B0_ADDRESS 0x0000a708
6047 #define PHY_BB_TXIQ_CORR_COEFF_EF_B0_OFFSET 0x0000a708
6048 #define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_MSB 13
6049 #define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_LSB 0
6050 #define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_MASK 0x00003fff
6051 #define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_GET(x) (((x) & 0x00003fff) >> 0)
6052 #define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_SET(x) (((x) << 0) & 0x00003fff)
6053 #define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_MSB 27
6054 #define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_LSB 14
6055 #define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_MASK 0x0fffc000
6056 #define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_GET(x) (((x) & 0x0fffc000) >> 14)
6057 #define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_SET(x) (((x) << 14) & 0x0fffc000)
6059 /* macros for BB_cal_rxbb_gain_tbl_0 */
6060 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_ADDRESS 0x0000a70c
6061 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_OFFSET 0x0000a70c
6062 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MSB 5
6063 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_LSB 0
6064 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MASK 0x0000003f
6065 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_GET(x) (((x) & 0x0000003f) >> 0)
6066 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_SET(x) (((x) << 0) & 0x0000003f)
6067 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MSB 11
6068 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_LSB 6
6069 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MASK 0x00000fc0
6070 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_GET(x) (((x) & 0x00000fc0) >> 6)
6071 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_SET(x) (((x) << 6) & 0x00000fc0)
6072 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MSB 17
6073 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_LSB 12
6074 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MASK 0x0003f000
6075 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_GET(x) (((x) & 0x0003f000) >> 12)
6076 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_SET(x) (((x) << 12) & 0x0003f000)
6077 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MSB 23
6078 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_LSB 18
6079 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MASK 0x00fc0000
6080 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_GET(x) (((x) & 0x00fc0000) >> 18)
6081 #define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_SET(x) (((x) << 18) & 0x00fc0000)
6083 /* macros for BB_cal_rxbb_gain_tbl_4 */
6084 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_ADDRESS 0x0000a710
6085 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_OFFSET 0x0000a710
6086 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MSB 5
6087 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_LSB 0
6088 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MASK 0x0000003f
6089 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_GET(x) (((x) & 0x0000003f) >> 0)
6090 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_SET(x) (((x) << 0) & 0x0000003f)
6091 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MSB 11
6092 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_LSB 6
6093 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MASK 0x00000fc0
6094 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_GET(x) (((x) & 0x00000fc0) >> 6)
6095 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_SET(x) (((x) << 6) & 0x00000fc0)
6096 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MSB 17
6097 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_LSB 12
6098 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MASK 0x0003f000
6099 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_GET(x) (((x) & 0x0003f000) >> 12)
6100 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_SET(x) (((x) << 12) & 0x0003f000)
6101 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MSB 23
6102 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_LSB 18
6103 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MASK 0x00fc0000
6104 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_GET(x) (((x) & 0x00fc0000) >> 18)
6105 #define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_SET(x) (((x) << 18) & 0x00fc0000)
6107 /* macros for BB_cal_rxbb_gain_tbl_8 */
6108 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_ADDRESS 0x0000a714
6109 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_OFFSET 0x0000a714
6110 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MSB 5
6111 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_LSB 0
6112 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MASK 0x0000003f
6113 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_GET(x) (((x) & 0x0000003f) >> 0)
6114 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_SET(x) (((x) << 0) & 0x0000003f)
6115 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MSB 11
6116 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_LSB 6
6117 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MASK 0x00000fc0
6118 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_GET(x) (((x) & 0x00000fc0) >> 6)
6119 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_SET(x) (((x) << 6) & 0x00000fc0)
6120 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MSB 17
6121 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_LSB 12
6122 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MASK 0x0003f000
6123 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_GET(x) (((x) & 0x0003f000) >> 12)
6124 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_SET(x) (((x) << 12) & 0x0003f000)
6125 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MSB 23
6126 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_LSB 18
6127 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MASK 0x00fc0000
6128 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_GET(x) (((x) & 0x00fc0000) >> 18)
6129 #define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_SET(x) (((x) << 18) & 0x00fc0000)
6131 /* macros for BB_cal_rxbb_gain_tbl_12 */
6132 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_ADDRESS 0x0000a718
6133 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_OFFSET 0x0000a718
6134 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MSB 5
6135 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_LSB 0
6136 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MASK 0x0000003f
6137 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_GET(x) (((x) & 0x0000003f) >> 0)
6138 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_SET(x) (((x) << 0) & 0x0000003f)
6139 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MSB 11
6140 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_LSB 6
6141 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MASK 0x00000fc0
6142 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_GET(x) (((x) & 0x00000fc0) >> 6)
6143 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_SET(x) (((x) << 6) & 0x00000fc0)
6144 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MSB 17
6145 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_LSB 12
6146 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MASK 0x0003f000
6147 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_GET(x) (((x) & 0x0003f000) >> 12)
6148 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_SET(x) (((x) << 12) & 0x0003f000)
6149 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MSB 23
6150 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_LSB 18
6151 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MASK 0x00fc0000
6152 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_GET(x) (((x) & 0x00fc0000) >> 18)
6153 #define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_SET(x) (((x) << 18) & 0x00fc0000)
6155 /* macros for BB_cal_rxbb_gain_tbl_16 */
6156 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_ADDRESS 0x0000a71c
6157 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_OFFSET 0x0000a71c
6158 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MSB 5
6159 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_LSB 0
6160 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MASK 0x0000003f
6161 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_GET(x) (((x) & 0x0000003f) >> 0)
6162 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_SET(x) (((x) << 0) & 0x0000003f)
6163 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MSB 11
6164 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_LSB 6
6165 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MASK 0x00000fc0
6166 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_GET(x) (((x) & 0x00000fc0) >> 6)
6167 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_SET(x) (((x) << 6) & 0x00000fc0)
6168 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MSB 17
6169 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_LSB 12
6170 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MASK 0x0003f000
6171 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_GET(x) (((x) & 0x0003f000) >> 12)
6172 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_SET(x) (((x) << 12) & 0x0003f000)
6173 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MSB 23
6174 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_LSB 18
6175 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MASK 0x00fc0000
6176 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_GET(x) (((x) & 0x00fc0000) >> 18)
6177 #define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_SET(x) (((x) << 18) & 0x00fc0000)
6179 /* macros for BB_cal_rxbb_gain_tbl_20 */
6180 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_ADDRESS 0x0000a720
6181 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_OFFSET 0x0000a720
6182 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MSB 5
6183 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_LSB 0
6184 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MASK 0x0000003f
6185 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_GET(x) (((x) & 0x0000003f) >> 0)
6186 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_SET(x) (((x) << 0) & 0x0000003f)
6187 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MSB 11
6188 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_LSB 6
6189 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MASK 0x00000fc0
6190 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_GET(x) (((x) & 0x00000fc0) >> 6)
6191 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_SET(x) (((x) << 6) & 0x00000fc0)
6192 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MSB 17
6193 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_LSB 12
6194 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MASK 0x0003f000
6195 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_GET(x) (((x) & 0x0003f000) >> 12)
6196 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_SET(x) (((x) << 12) & 0x0003f000)
6197 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MSB 23
6198 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_LSB 18
6199 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MASK 0x00fc0000
6200 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_GET(x) (((x) & 0x00fc0000) >> 18)
6201 #define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_SET(x) (((x) << 18) & 0x00fc0000)
6203 /* macros for BB_cal_rxbb_gain_tbl_24 */
6204 #define PHY_BB_CAL_RXBB_GAIN_TBL_24_ADDRESS 0x0000a724
6205 #define PHY_BB_CAL_RXBB_GAIN_TBL_24_OFFSET 0x0000a724
6206 #define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MSB 5
6207 #define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_LSB 0
6208 #define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MASK 0x0000003f
6209 #define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_GET(x) (((x) & 0x0000003f) >> 0)
6210 #define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_SET(x) (((x) << 0) & 0x0000003f)
6212 /* macros for BB_txiqcal_status_b0 */
6213 #define PHY_BB_TXIQCAL_STATUS_B0_ADDRESS 0x0000a728
6214 #define PHY_BB_TXIQCAL_STATUS_B0_OFFSET 0x0000a728
6215 #define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MSB 0
6216 #define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_LSB 0
6217 #define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MASK 0x00000001
6218 #define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_GET(x) (((x) & 0x00000001) >> 0)
6219 #define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MSB 5
6220 #define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_LSB 1
6221 #define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MASK 0x0000003e
6222 #define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_GET(x) (((x) & 0x0000003e) >> 1)
6223 #define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MSB 11
6224 #define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_LSB 6
6225 #define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MASK 0x00000fc0
6226 #define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_GET(x) (((x) & 0x00000fc0) >> 6)
6227 #define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MSB 17
6228 #define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_LSB 12
6229 #define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MASK 0x0003f000
6230 #define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_GET(x) (((x) & 0x0003f000) >> 12)
6231 #define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MSB 24
6232 #define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_LSB 18
6233 #define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MASK 0x01fc0000
6234 #define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_GET(x) (((x) & 0x01fc0000) >> 18)
6236 /* macros for BB_paprd_trainer_cntl1 */
6237 #define PHY_BB_PAPRD_TRAINER_CNTL1_ADDRESS 0x0000a72c
6238 #define PHY_BB_PAPRD_TRAINER_CNTL1_OFFSET 0x0000a72c
6239 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MSB 0
6240 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_LSB 0
6241 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MASK 0x00000001
6242 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_GET(x) (((x) & 0x00000001) >> 0)
6243 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_SET(x) (((x) << 0) & 0x00000001)
6244 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MSB 7
6245 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_LSB 1
6246 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MASK 0x000000fe
6247 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_GET(x) (((x) & 0x000000fe) >> 1)
6248 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_SET(x) (((x) << 1) & 0x000000fe)
6249 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MSB 8
6250 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_LSB 8
6251 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MASK 0x00000100
6252 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_GET(x) (((x) & 0x00000100) >> 8)
6253 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_SET(x) (((x) << 8) & 0x00000100)
6254 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MSB 9
6255 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_LSB 9
6256 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MASK 0x00000200
6257 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_GET(x) (((x) & 0x00000200) >> 9)
6258 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_SET(x) (((x) << 9) & 0x00000200)
6259 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MSB 10
6260 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_LSB 10
6261 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MASK 0x00000400
6262 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_GET(x) (((x) & 0x00000400) >> 10)
6263 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_SET(x) (((x) << 10) & 0x00000400)
6264 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_MSB 11
6265 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_LSB 11
6266 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_MASK 0x00000800
6267 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_GET(x) (((x) & 0x00000800) >> 11)
6268 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_SET(x) (((x) << 11) & 0x00000800)
6269 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_MSB 18
6270 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_LSB 12
6271 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_MASK 0x0007f000
6272 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_GET(x) (((x) & 0x0007f000) >> 12)
6273 #define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_SET(x) (((x) << 12) & 0x0007f000)
6275 /* macros for BB_paprd_trainer_cntl2 */
6276 #define PHY_BB_PAPRD_TRAINER_CNTL2_ADDRESS 0x0000a730
6277 #define PHY_BB_PAPRD_TRAINER_CNTL2_OFFSET 0x0000a730
6278 #define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MSB 31
6279 #define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_LSB 0
6280 #define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MASK 0xffffffff
6281 #define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_GET(x) (((x) & 0xffffffff) >> 0)
6282 #define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_SET(x) (((x) << 0) & 0xffffffff)
6284 /* macros for BB_paprd_trainer_cntl3 */
6285 #define PHY_BB_PAPRD_TRAINER_CNTL3_ADDRESS 0x0000a734
6286 #define PHY_BB_PAPRD_TRAINER_CNTL3_OFFSET 0x0000a734
6287 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_MSB 5
6288 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_LSB 0
6289 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_MASK 0x0000003f
6290 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_GET(x) (((x) & 0x0000003f) >> 0)
6291 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_SET(x) (((x) << 0) & 0x0000003f)
6292 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MSB 11
6293 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_LSB 6
6294 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MASK 0x00000fc0
6295 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_GET(x) (((x) & 0x00000fc0) >> 6)
6296 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_SET(x) (((x) << 6) & 0x00000fc0)
6297 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MSB 16
6298 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_LSB 12
6299 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MASK 0x0001f000
6300 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_GET(x) (((x) & 0x0001f000) >> 12)
6301 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_SET(x) (((x) << 12) & 0x0001f000)
6302 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MSB 19
6303 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_LSB 17
6304 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MASK 0x000e0000
6305 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_GET(x) (((x) & 0x000e0000) >> 17)
6306 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_SET(x) (((x) << 17) & 0x000e0000)
6307 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MSB 23
6308 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_LSB 20
6309 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MASK 0x00f00000
6310 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_GET(x) (((x) & 0x00f00000) >> 20)
6311 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_SET(x) (((x) << 20) & 0x00f00000)
6312 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MSB 27
6313 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_LSB 24
6314 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MASK 0x0f000000
6315 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_GET(x) (((x) & 0x0f000000) >> 24)
6316 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_SET(x) (((x) << 24) & 0x0f000000)
6317 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MSB 28
6318 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_LSB 28
6319 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MASK 0x10000000
6320 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_GET(x) (((x) & 0x10000000) >> 28)
6321 #define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_SET(x) (((x) << 28) & 0x10000000)
6323 /* macros for BB_paprd_trainer_cntl4 */
6324 #define PHY_BB_PAPRD_TRAINER_CNTL4_ADDRESS 0x0000a738
6325 #define PHY_BB_PAPRD_TRAINER_CNTL4_OFFSET 0x0000a738
6326 #define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MSB 11
6327 #define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_LSB 0
6328 #define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MASK 0x00000fff
6329 #define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_GET(x) (((x) & 0x00000fff) >> 0)
6330 #define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_SET(x) (((x) << 0) & 0x00000fff)
6331 #define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MSB 15
6332 #define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_LSB 12
6333 #define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MASK 0x0000f000
6334 #define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_GET(x) (((x) & 0x0000f000) >> 12)
6335 #define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_SET(x) (((x) << 12) & 0x0000f000)
6336 #define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MSB 25
6337 #define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_LSB 16
6338 #define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MASK 0x03ff0000
6339 #define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_GET(x) (((x) & 0x03ff0000) >> 16)
6340 #define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_SET(x) (((x) << 16) & 0x03ff0000)
6342 /* macros for BB_paprd_trainer_stat1 */
6343 #define PHY_BB_PAPRD_TRAINER_STAT1_ADDRESS 0x0000a73c
6344 #define PHY_BB_PAPRD_TRAINER_STAT1_OFFSET 0x0000a73c
6345 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MSB 0
6346 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_LSB 0
6347 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MASK 0x00000001
6348 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_GET(x) (((x) & 0x00000001) >> 0)
6349 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_SET(x) (((x) << 0) & 0x00000001)
6350 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MSB 1
6351 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_LSB 1
6352 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MASK 0x00000002
6353 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_GET(x) (((x) & 0x00000002) >> 1)
6354 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MSB 2
6355 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_LSB 2
6356 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MASK 0x00000004
6357 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_GET(x) (((x) & 0x00000004) >> 2)
6358 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MSB 3
6359 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_LSB 3
6360 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MASK 0x00000008
6361 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_GET(x) (((x) & 0x00000008) >> 3)
6362 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MSB 8
6363 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_LSB 4
6364 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MASK 0x000001f0
6365 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_GET(x) (((x) & 0x000001f0) >> 4)
6366 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MSB 16
6367 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_LSB 9
6368 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MASK 0x0001fe00
6369 #define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_GET(x) (((x) & 0x0001fe00) >> 9)
6371 /* macros for BB_paprd_trainer_stat2 */
6372 #define PHY_BB_PAPRD_TRAINER_STAT2_ADDRESS 0x0000a740
6373 #define PHY_BB_PAPRD_TRAINER_STAT2_OFFSET 0x0000a740
6374 #define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MSB 15
6375 #define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_LSB 0
6376 #define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MASK 0x0000ffff
6377 #define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_GET(x) (((x) & 0x0000ffff) >> 0)
6378 #define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MSB 20
6379 #define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_LSB 16
6380 #define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MASK 0x001f0000
6381 #define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_GET(x) (((x) & 0x001f0000) >> 16)
6382 #define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MSB 22
6383 #define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_LSB 21
6384 #define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MASK 0x00600000
6385 #define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_GET(x) (((x) & 0x00600000) >> 21)
6387 /* macros for BB_paprd_trainer_stat3 */
6388 #define PHY_BB_PAPRD_TRAINER_STAT3_ADDRESS 0x0000a744
6389 #define PHY_BB_PAPRD_TRAINER_STAT3_OFFSET 0x0000a744
6390 #define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MSB 19
6391 #define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_LSB 0
6392 #define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MASK 0x000fffff
6393 #define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_GET(x) (((x) & 0x000fffff) >> 0)
6395 /* macros for BB_fcal_1 */
6396 #define PHY_BB_FCAL_1_ADDRESS 0x0000a7d8
6397 #define PHY_BB_FCAL_1_OFFSET 0x0000a7d8
6398 #define PHY_BB_FCAL_1_FLC_PB_FSTEP_MSB 9
6399 #define PHY_BB_FCAL_1_FLC_PB_FSTEP_LSB 0
6400 #define PHY_BB_FCAL_1_FLC_PB_FSTEP_MASK 0x000003ff
6401 #define PHY_BB_FCAL_1_FLC_PB_FSTEP_GET(x) (((x) & 0x000003ff) >> 0)
6402 #define PHY_BB_FCAL_1_FLC_PB_FSTEP_SET(x) (((x) << 0) & 0x000003ff)
6403 #define PHY_BB_FCAL_1_FLC_SB_FSTEP_MSB 19
6404 #define PHY_BB_FCAL_1_FLC_SB_FSTEP_LSB 10
6405 #define PHY_BB_FCAL_1_FLC_SB_FSTEP_MASK 0x000ffc00
6406 #define PHY_BB_FCAL_1_FLC_SB_FSTEP_GET(x) (((x) & 0x000ffc00) >> 10)
6407 #define PHY_BB_FCAL_1_FLC_SB_FSTEP_SET(x) (((x) << 10) & 0x000ffc00)
6408 #define PHY_BB_FCAL_1_FLC_PB_ATTEN_MSB 24
6409 #define PHY_BB_FCAL_1_FLC_PB_ATTEN_LSB 20
6410 #define PHY_BB_FCAL_1_FLC_PB_ATTEN_MASK 0x01f00000
6411 #define PHY_BB_FCAL_1_FLC_PB_ATTEN_GET(x) (((x) & 0x01f00000) >> 20)
6412 #define PHY_BB_FCAL_1_FLC_PB_ATTEN_SET(x) (((x) << 20) & 0x01f00000)
6413 #define PHY_BB_FCAL_1_FLC_SB_ATTEN_MSB 29
6414 #define PHY_BB_FCAL_1_FLC_SB_ATTEN_LSB 25
6415 #define PHY_BB_FCAL_1_FLC_SB_ATTEN_MASK 0x3e000000
6416 #define PHY_BB_FCAL_1_FLC_SB_ATTEN_GET(x) (((x) & 0x3e000000) >> 25)
6417 #define PHY_BB_FCAL_1_FLC_SB_ATTEN_SET(x) (((x) << 25) & 0x3e000000)
6419 /* macros for BB_fcal_2_b0 */
6420 #define PHY_BB_FCAL_2_B0_ADDRESS 0x0000a7dc
6421 #define PHY_BB_FCAL_2_B0_OFFSET 0x0000a7dc
6422 #define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MSB 2
6423 #define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_LSB 0
6424 #define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MASK 0x00000007
6425 #define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_GET(x) (((x) & 0x00000007) >> 0)
6426 #define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_SET(x) (((x) << 0) & 0x00000007)
6427 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MSB 7
6428 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_LSB 3
6429 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MASK 0x000000f8
6430 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_GET(x) (((x) & 0x000000f8) >> 3)
6431 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_SET(x) (((x) << 3) & 0x000000f8)
6432 #define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MSB 9
6433 #define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_LSB 8
6434 #define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MASK 0x00000300
6435 #define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_GET(x) (((x) & 0x00000300) >> 8)
6436 #define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_SET(x) (((x) << 8) & 0x00000300)
6437 #define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MSB 12
6438 #define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_LSB 10
6439 #define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MASK 0x00001c00
6440 #define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_GET(x) (((x) & 0x00001c00) >> 10)
6441 #define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_SET(x) (((x) << 10) & 0x00001c00)
6442 #define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MSB 14
6443 #define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_LSB 13
6444 #define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MASK 0x00006000
6445 #define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_GET(x) (((x) & 0x00006000) >> 13)
6446 #define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_SET(x) (((x) << 13) & 0x00006000)
6447 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MSB 15
6448 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_LSB 15
6449 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MASK 0x00008000
6450 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_GET(x) (((x) & 0x00008000) >> 15)
6451 #define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_SET(x) (((x) << 15) & 0x00008000)
6452 #define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MSB 18
6453 #define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_LSB 16
6454 #define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MASK 0x00070000
6455 #define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_GET(x) (((x) & 0x00070000) >> 16)
6456 #define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_SET(x) (((x) << 16) & 0x00070000)
6457 #define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MSB 24
6458 #define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_LSB 20
6459 #define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MASK 0x01f00000
6460 #define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_GET(x) (((x) & 0x01f00000) >> 20)
6462 /* macros for BB_radar_bw_filter */
6463 #define PHY_BB_RADAR_BW_FILTER_ADDRESS 0x0000a7e0
6464 #define PHY_BB_RADAR_BW_FILTER_OFFSET 0x0000a7e0
6465 #define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_MSB 0
6466 #define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_LSB 0
6467 #define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_MASK 0x00000001
6468 #define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_GET(x) (((x) & 0x00000001) >> 0)
6469 #define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_SET(x) (((x) << 0) & 0x00000001)
6470 #define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_MSB 1
6471 #define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_LSB 1
6472 #define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_MASK 0x00000002
6473 #define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_GET(x) (((x) & 0x00000002) >> 1)
6474 #define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_SET(x) (((x) << 1) & 0x00000002)
6475 #define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_MSB 3
6476 #define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_LSB 2
6477 #define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_MASK 0x0000000c
6478 #define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_GET(x) (((x) & 0x0000000c) >> 2)
6479 #define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_SET(x) (((x) << 2) & 0x0000000c)
6480 #define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_MSB 5
6481 #define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_LSB 4
6482 #define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_MASK 0x00000030
6483 #define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_GET(x) (((x) & 0x00000030) >> 4)
6484 #define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_SET(x) (((x) << 4) & 0x00000030)
6485 #define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_MSB 14
6486 #define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_LSB 8
6487 #define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_MASK 0x00007f00
6488 #define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_GET(x) (((x) & 0x00007f00) >> 8)
6489 #define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_SET(x) (((x) << 8) & 0x00007f00)
6490 #define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_MSB 20
6491 #define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_LSB 15
6492 #define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_MASK 0x001f8000
6493 #define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_GET(x) (((x) & 0x001f8000) >> 15)
6494 #define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_SET(x) (((x) << 15) & 0x001f8000)
6495 #define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_MSB 26
6496 #define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_LSB 21
6497 #define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_MASK 0x07e00000
6498 #define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_GET(x) (((x) & 0x07e00000) >> 21)
6499 #define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_SET(x) (((x) << 21) & 0x07e00000)
6501 /* macros for BB_dft_tone_ctrl_b0 */
6502 #define PHY_BB_DFT_TONE_CTRL_B0_ADDRESS 0x0000a7e4
6503 #define PHY_BB_DFT_TONE_CTRL_B0_OFFSET 0x0000a7e4
6504 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MSB 0
6505 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_LSB 0
6506 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MASK 0x00000001
6507 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_GET(x) (((x) & 0x00000001) >> 0)
6508 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_SET(x) (((x) << 0) & 0x00000001)
6509 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MSB 3
6510 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_LSB 2
6511 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MASK 0x0000000c
6512 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_GET(x) (((x) & 0x0000000c) >> 2)
6513 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_SET(x) (((x) << 2) & 0x0000000c)
6514 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MSB 12
6515 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_LSB 4
6516 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MASK 0x00001ff0
6517 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_GET(x) (((x) & 0x00001ff0) >> 4)
6518 #define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_SET(x) (((x) << 4) & 0x00001ff0)
6520 /* macros for BB_therm_adc_1 */
6521 #define PHY_BB_THERM_ADC_1_ADDRESS 0x0000a7e8
6522 #define PHY_BB_THERM_ADC_1_OFFSET 0x0000a7e8
6523 #define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_MSB 7
6524 #define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_LSB 0
6525 #define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_MASK 0x000000ff
6526 #define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_GET(x) (((x) & 0x000000ff) >> 0)
6527 #define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_SET(x) (((x) << 0) & 0x000000ff)
6528 #define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_MSB 15
6529 #define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_LSB 8
6530 #define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_MASK 0x0000ff00
6531 #define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_GET(x) (((x) & 0x0000ff00) >> 8)
6532 #define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_SET(x) (((x) << 8) & 0x0000ff00)
6533 #define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_MSB 23
6534 #define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_LSB 16
6535 #define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_MASK 0x00ff0000
6536 #define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_GET(x) (((x) & 0x00ff0000) >> 16)
6537 #define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_SET(x) (((x) << 16) & 0x00ff0000)
6538 #define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_MSB 25
6539 #define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_LSB 24
6540 #define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_MASK 0x03000000
6541 #define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_GET(x) (((x) & 0x03000000) >> 24)
6542 #define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_SET(x) (((x) << 24) & 0x03000000)
6543 #define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MSB 26
6544 #define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_LSB 26
6545 #define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MASK 0x04000000
6546 #define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_GET(x) (((x) & 0x04000000) >> 26)
6547 #define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_SET(x) (((x) << 26) & 0x04000000)
6548 #define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MSB 27
6549 #define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_LSB 27
6550 #define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MASK 0x08000000
6551 #define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_GET(x) (((x) & 0x08000000) >> 27)
6552 #define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_SET(x) (((x) << 27) & 0x08000000)
6554 /* macros for BB_therm_adc_2 */
6555 #define PHY_BB_THERM_ADC_2_ADDRESS 0x0000a7ec
6556 #define PHY_BB_THERM_ADC_2_OFFSET 0x0000a7ec
6557 #define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_MSB 11
6558 #define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_LSB 0
6559 #define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_MASK 0x00000fff
6560 #define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_GET(x) (((x) & 0x00000fff) >> 0)
6561 #define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_SET(x) (((x) << 0) & 0x00000fff)
6562 #define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_MSB 21
6563 #define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_LSB 12
6564 #define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_MASK 0x003ff000
6565 #define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_GET(x) (((x) & 0x003ff000) >> 12)
6566 #define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_SET(x) (((x) << 12) & 0x003ff000)
6567 #define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_MSB 31
6568 #define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_LSB 22
6569 #define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_MASK 0xffc00000
6570 #define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_GET(x) (((x) & 0xffc00000) >> 22)
6571 #define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_SET(x) (((x) << 22) & 0xffc00000)
6573 /* macros for BB_therm_adc_3 */
6574 #define PHY_BB_THERM_ADC_3_ADDRESS 0x0000a7f0
6575 #define PHY_BB_THERM_ADC_3_OFFSET 0x0000a7f0
6576 #define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_MSB 7
6577 #define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_LSB 0
6578 #define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_MASK 0x000000ff
6579 #define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_GET(x) (((x) & 0x000000ff) >> 0)
6580 #define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_SET(x) (((x) << 0) & 0x000000ff)
6581 #define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_MSB 16
6582 #define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_LSB 8
6583 #define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_MASK 0x0001ff00
6584 #define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_GET(x) (((x) & 0x0001ff00) >> 8)
6585 #define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_SET(x) (((x) << 8) & 0x0001ff00)
6586 #define PHY_BB_THERM_ADC_3_ADC_INTERVAL_MSB 29
6587 #define PHY_BB_THERM_ADC_3_ADC_INTERVAL_LSB 17
6588 #define PHY_BB_THERM_ADC_3_ADC_INTERVAL_MASK 0x3ffe0000
6589 #define PHY_BB_THERM_ADC_3_ADC_INTERVAL_GET(x) (((x) & 0x3ffe0000) >> 17)
6590 #define PHY_BB_THERM_ADC_3_ADC_INTERVAL_SET(x) (((x) << 17) & 0x3ffe0000)
6592 /* macros for BB_therm_adc_4 */
6593 #define PHY_BB_THERM_ADC_4_ADDRESS 0x0000a7f4
6594 #define PHY_BB_THERM_ADC_4_OFFSET 0x0000a7f4
6595 #define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_MSB 7
6596 #define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_LSB 0
6597 #define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_MASK 0x000000ff
6598 #define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_GET(x) (((x) & 0x000000ff) >> 0)
6599 #define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_MSB 15
6600 #define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_LSB 8
6601 #define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_MASK 0x0000ff00
6602 #define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_GET(x) (((x) & 0x0000ff00) >> 8)
6603 #define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_MSB 23
6604 #define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_LSB 16
6605 #define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_MASK 0x00ff0000
6606 #define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_GET(x) (((x) & 0x00ff0000) >> 16)
6608 /* macros for BB_tx_forced_gain */
6609 #define PHY_BB_TX_FORCED_GAIN_ADDRESS 0x0000a7f8
6610 #define PHY_BB_TX_FORCED_GAIN_OFFSET 0x0000a7f8
6611 #define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MSB 0
6612 #define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_LSB 0
6613 #define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MASK 0x00000001
6614 #define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_GET(x) (((x) & 0x00000001) >> 0)
6615 #define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_SET(x) (((x) << 0) & 0x00000001)
6616 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MSB 3
6617 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_LSB 1
6618 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MASK 0x0000000e
6619 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_GET(x) (((x) & 0x0000000e) >> 1)
6620 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_SET(x) (((x) << 1) & 0x0000000e)
6621 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MSB 5
6622 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_LSB 4
6623 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MASK 0x00000030
6624 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_GET(x) (((x) & 0x00000030) >> 4)
6625 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_SET(x) (((x) << 4) & 0x00000030)
6626 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MSB 9
6627 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_LSB 6
6628 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MASK 0x000003c0
6629 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_GET(x) (((x) & 0x000003c0) >> 6)
6630 #define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_SET(x) (((x) << 6) & 0x000003c0)
6631 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_MSB 13
6632 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_LSB 10
6633 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_MASK 0x00003c00
6634 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_GET(x) (((x) & 0x00003c00) >> 10)
6635 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_SET(x) (((x) << 10) & 0x00003c00)
6636 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_MSB 17
6637 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_LSB 14
6638 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_MASK 0x0003c000
6639 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_GET(x) (((x) & 0x0003c000) >> 14)
6640 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_SET(x) (((x) << 14) & 0x0003c000)
6641 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_MSB 21
6642 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_LSB 18
6643 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_MASK 0x003c0000
6644 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_GET(x) (((x) & 0x003c0000) >> 18)
6645 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_SET(x) (((x) << 18) & 0x003c0000)
6646 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_MSB 23
6647 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_LSB 22
6648 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_MASK 0x00c00000
6649 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_GET(x) (((x) & 0x00c00000) >> 22)
6650 #define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_SET(x) (((x) << 22) & 0x00c00000)
6651 #define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MSB 24
6652 #define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_LSB 24
6653 #define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MASK 0x01000000
6654 #define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_GET(x) (((x) & 0x01000000) >> 24)
6655 #define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_SET(x) (((x) << 24) & 0x01000000)
6657 /* macros for BB_eco_ctrl */
6658 #define PHY_BB_ECO_CTRL_ADDRESS 0x0000a7fc
6659 #define PHY_BB_ECO_CTRL_OFFSET 0x0000a7fc
6660 #define PHY_BB_ECO_CTRL_ECO_CTRL_MSB 7
6661 #define PHY_BB_ECO_CTRL_ECO_CTRL_LSB 0
6662 #define PHY_BB_ECO_CTRL_ECO_CTRL_MASK 0x000000ff
6663 #define PHY_BB_ECO_CTRL_ECO_CTRL_GET(x) (((x) & 0x000000ff) >> 0)
6664 #define PHY_BB_ECO_CTRL_ECO_CTRL_SET(x) (((x) << 0) & 0x000000ff)
6666 /* macros for BB_gain_force_max_gains_b1 */
6667 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_ADDRESS 0x0000a848
6668 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_OFFSET 0x0000a848
6669 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_MSB 13
6670 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_LSB 7
6671 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_MASK 0x00003f80
6672 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_GET(x) (((x) & 0x00003f80) >> 7)
6673 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_SET(x) (((x) << 7) & 0x00003f80)
6674 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_MSB 20
6675 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_LSB 14
6676 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_MASK 0x001fc000
6677 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_GET(x) (((x) & 0x001fc000) >> 14)
6678 #define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_SET(x) (((x) << 14) & 0x001fc000)
6680 /* macros for BB_gains_min_offsets_b1 */
6681 #define PHY_BB_GAINS_MIN_OFFSETS_B1_ADDRESS 0x0000a84c
6682 #define PHY_BB_GAINS_MIN_OFFSETS_B1_OFFSET 0x0000a84c
6683 #define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_MSB 24
6684 #define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_LSB 17
6685 #define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_MASK 0x01fe0000
6686 #define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_GET(x) (((x) & 0x01fe0000) >> 17)
6687 #define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_SET(x) (((x) << 17) & 0x01fe0000)
6688 #define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_MSB 25
6689 #define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_LSB 25
6690 #define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_MASK 0x02000000
6691 #define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_GET(x) (((x) & 0x02000000) >> 25)
6692 #define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_SET(x) (((x) << 25) & 0x02000000)
6693 #define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_MSB 26
6694 #define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_LSB 26
6695 #define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_MASK 0x04000000
6696 #define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_GET(x) (((x) & 0x04000000) >> 26)
6697 #define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_SET(x) (((x) << 26) & 0x04000000)
6699 /* macros for BB_rx_ocgain2 */
6700 #define PHY_BB_RX_OCGAIN2_ADDRESS 0x0000aa00
6701 #define PHY_BB_RX_OCGAIN2_OFFSET 0x0000aa00
6702 #define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_MSB 31
6703 #define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_LSB 0
6704 #define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_MASK 0xffffffff
6705 #define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_SET(x) (((x) << 0) & 0xffffffff)
6707 /* macros for BB_ext_atten_switch_ctl_b1 */
6708 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_ADDRESS 0x0000b20c
6709 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_OFFSET 0x0000b20c
6710 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_MSB 5
6711 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_LSB 0
6712 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_MASK 0x0000003f
6713 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_GET(x) (((x) & 0x0000003f) >> 0)
6714 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_SET(x) (((x) << 0) & 0x0000003f)
6715 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_MSB 11
6716 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_LSB 6
6717 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_MASK 0x00000fc0
6718 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_GET(x) (((x) & 0x00000fc0) >> 6)
6719 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_SET(x) (((x) << 6) & 0x00000fc0)
6720 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_MSB 16
6721 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_LSB 12
6722 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_MASK 0x0001f000
6723 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_GET(x) (((x) & 0x0001f000) >> 12)
6724 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_SET(x) (((x) << 12) & 0x0001f000)
6725 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_MSB 21
6726 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_LSB 17
6727 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_MASK 0x003e0000
6728 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_GET(x) (((x) & 0x003e0000) >> 17)
6729 #define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_SET(x) (((x) << 17) & 0x003e0000)
6732 #ifndef __ASSEMBLER__
6734 typedef struct bb_lc_reg_reg_s {
6735 volatile char pad__0[0x9800]; /* 0x0 - 0x9800 */
6736 volatile unsigned int BB_test_controls; /* 0x9800 - 0x9804 */
6737 volatile unsigned int BB_gen_controls; /* 0x9804 - 0x9808 */
6738 volatile unsigned int BB_test_controls_status; /* 0x9808 - 0x980c */
6739 volatile unsigned int BB_timing_controls_1; /* 0x980c - 0x9810 */
6740 volatile unsigned int BB_timing_controls_2; /* 0x9810 - 0x9814 */
6741 volatile unsigned int BB_timing_controls_3; /* 0x9814 - 0x9818 */
6742 volatile unsigned int BB_D2_chip_id; /* 0x9818 - 0x981c */
6743 volatile unsigned int BB_active; /* 0x981c - 0x9820 */
6744 volatile unsigned int BB_tx_timing_1; /* 0x9820 - 0x9824 */
6745 volatile unsigned int BB_tx_timing_2; /* 0x9824 - 0x9828 */
6746 volatile unsigned int BB_tx_timing_3; /* 0x9828 - 0x982c */
6747 volatile unsigned int BB_addac_parallel_control; /* 0x982c - 0x9830 */
6748 volatile char pad__1[0x4]; /* 0x9830 - 0x9834 */
6749 volatile unsigned int BB_xpa_timing_control; /* 0x9834 - 0x9838 */
6750 volatile unsigned int BB_misc_pa_control; /* 0x9838 - 0x983c */
6751 volatile unsigned int BB_tstdac_constant; /* 0x983c - 0x9840 */
6752 volatile unsigned int BB_find_signal_low; /* 0x9840 - 0x9844 */
6753 volatile unsigned int BB_settling_time; /* 0x9844 - 0x9848 */
6754 volatile unsigned int BB_gain_force_max_gains_b0; /* 0x9848 - 0x984c */
6755 volatile unsigned int BB_gains_min_offsets_b0; /* 0x984c - 0x9850 */
6756 volatile unsigned int BB_desired_sigsize; /* 0x9850 - 0x9854 */
6757 volatile unsigned int BB_timing_control_3a; /* 0x9854 - 0x9858 */
6758 volatile unsigned int BB_find_signal; /* 0x9858 - 0x985c */
6759 volatile unsigned int BB_agc; /* 0x985c - 0x9860 */
6760 volatile unsigned int BB_agc_control; /* 0x9860 - 0x9864 */
6761 volatile unsigned int BB_cca_b0; /* 0x9864 - 0x9868 */
6762 volatile unsigned int BB_sfcorr; /* 0x9868 - 0x986c */
6763 volatile unsigned int BB_self_corr_low; /* 0x986c - 0x9870 */
6764 volatile char pad__2[0x4]; /* 0x9870 - 0x9874 */
6765 volatile unsigned int BB_synth_control; /* 0x9874 - 0x9878 */
6766 volatile unsigned int BB_addac_clk_select; /* 0x9878 - 0x987c */
6767 volatile unsigned int BB_pll_cntl; /* 0x987c - 0x9880 */
6768 volatile char pad__3[0x80]; /* 0x9880 - 0x9900 */
6769 volatile unsigned int BB_vit_spur_mask_A; /* 0x9900 - 0x9904 */
6770 volatile unsigned int BB_vit_spur_mask_B; /* 0x9904 - 0x9908 */
6771 volatile unsigned int BB_pilot_spur_mask; /* 0x9908 - 0x990c */
6772 volatile unsigned int BB_chan_spur_mask; /* 0x990c - 0x9910 */
6773 volatile unsigned int BB_spectral_scan; /* 0x9910 - 0x9914 */
6774 volatile unsigned int BB_analog_power_on_time; /* 0x9914 - 0x9918 */
6775 volatile unsigned int BB_search_start_delay; /* 0x9918 - 0x991c */
6776 volatile unsigned int BB_max_rx_length; /* 0x991c - 0x9920 */
6777 volatile unsigned int BB_timing_control_4; /* 0x9920 - 0x9924 */
6778 volatile unsigned int BB_timing_control_5; /* 0x9924 - 0x9928 */
6779 volatile unsigned int BB_phyonly_warm_reset; /* 0x9928 - 0x992c */
6780 volatile unsigned int BB_phyonly_control; /* 0x992c - 0x9930 */
6781 volatile char pad__4[0x4]; /* 0x9930 - 0x9934 */
6782 volatile unsigned int BB_powertx_rate1; /* 0x9934 - 0x9938 */
6783 volatile unsigned int BB_powertx_rate2; /* 0x9938 - 0x993c */
6784 volatile unsigned int BB_powertx_max; /* 0x993c - 0x9940 */
6785 volatile unsigned int BB_extension_radar; /* 0x9940 - 0x9944 */
6786 volatile unsigned int BB_frame_control; /* 0x9944 - 0x9948 */
6787 volatile unsigned int BB_timing_control_6; /* 0x9948 - 0x994c */
6788 volatile unsigned int BB_spur_mask_controls; /* 0x994c - 0x9950 */
6789 volatile unsigned int BB_rx_iq_corr_b0; /* 0x9950 - 0x9954 */
6790 volatile unsigned int BB_radar_detection; /* 0x9954 - 0x9958 */
6791 volatile unsigned int BB_radar_detection_2; /* 0x9958 - 0x995c */
6792 volatile unsigned int BB_tx_phase_ramp_b0; /* 0x995c - 0x9960 */
6793 volatile unsigned int BB_switch_table_chn_b0; /* 0x9960 - 0x9964 */
6794 volatile unsigned int BB_switch_table_com1; /* 0x9964 - 0x9968 */
6795 volatile unsigned int BB_cca_ctrl_2_b0; /* 0x9968 - 0x996c */
6796 volatile unsigned int BB_switch_table_com2; /* 0x996c - 0x9970 */
6797 volatile unsigned int BB_restart; /* 0x9970 - 0x9974 */
6798 volatile char pad__5[0x4]; /* 0x9974 - 0x9978 */
6799 volatile unsigned int BB_scrambler_seed; /* 0x9978 - 0x997c */
6800 volatile unsigned int BB_rfbus_request; /* 0x997c - 0x9980 */
6801 volatile char pad__6[0x20]; /* 0x9980 - 0x99a0 */
6802 volatile unsigned int BB_timing_control_11; /* 0x99a0 - 0x99a4 */
6803 volatile unsigned int BB_multichain_enable; /* 0x99a4 - 0x99a8 */
6804 volatile unsigned int BB_multichain_control; /* 0x99a8 - 0x99ac */
6805 volatile unsigned int BB_multichain_gain_ctrl; /* 0x99ac - 0x99b0 */
6806 volatile char pad__7[0x4]; /* 0x99b0 - 0x99b4 */
6807 volatile unsigned int BB_adc_gain_dc_corr_b0; /* 0x99b4 - 0x99b8 */
6808 volatile unsigned int BB_ext_chan_pwr_thr_1; /* 0x99b8 - 0x99bc */
6809 volatile unsigned int BB_ext_chan_pwr_thr_2_b0; /* 0x99bc - 0x99c0 */
6810 volatile unsigned int BB_ext_chan_scorr_thr; /* 0x99c0 - 0x99c4 */
6811 volatile unsigned int BB_ext_chan_detect_win; /* 0x99c4 - 0x99c8 */
6812 volatile unsigned int BB_pwr_thr_20_40_det; /* 0x99c8 - 0x99cc */
6813 volatile char pad__8[0x4]; /* 0x99cc - 0x99d0 */
6814 volatile unsigned int BB_short_gi_delta_slope; /* 0x99d0 - 0x99d4 */
6815 volatile char pad__9[0x8]; /* 0x99d4 - 0x99dc */
6816 volatile unsigned int BB_chaninfo_ctrl; /* 0x99dc - 0x99e0 */
6817 volatile unsigned int BB_heavy_clip_ctrl; /* 0x99e0 - 0x99e4 */
6818 volatile unsigned int BB_heavy_clip_20; /* 0x99e4 - 0x99e8 */
6819 volatile unsigned int BB_heavy_clip_40; /* 0x99e8 - 0x99ec */
6820 volatile unsigned int BB_rifs_srch; /* 0x99ec - 0x99f0 */
6821 volatile unsigned int BB_iq_adc_cal_mode; /* 0x99f0 - 0x99f4 */
6822 volatile char pad__10[0x8]; /* 0x99f4 - 0x99fc */
6823 volatile unsigned int BB_per_chain_csd; /* 0x99fc - 0x9a00 */
6824 volatile unsigned int BB_rx_ocgain[128]; /* 0x9a00 - 0x9c00 */
6825 volatile unsigned int BB_tx_crc; /* 0x9c00 - 0x9c04 */
6826 volatile char pad__11[0xc]; /* 0x9c04 - 0x9c10 */
6827 volatile unsigned int BB_iq_adc_meas_0_b0; /* 0x9c10 - 0x9c14 */
6828 volatile unsigned int BB_iq_adc_meas_1_b0; /* 0x9c14 - 0x9c18 */
6829 volatile unsigned int BB_iq_adc_meas_2_b0; /* 0x9c18 - 0x9c1c */
6830 volatile unsigned int BB_iq_adc_meas_3_b0; /* 0x9c1c - 0x9c20 */
6831 volatile unsigned int BB_rfbus_grant; /* 0x9c20 - 0x9c24 */
6832 volatile unsigned int BB_tstadc; /* 0x9c24 - 0x9c28 */
6833 volatile unsigned int BB_tstdac; /* 0x9c28 - 0x9c2c */
6834 volatile char pad__12[0x4]; /* 0x9c2c - 0x9c30 */
6835 volatile unsigned int BB_illegal_tx_rate; /* 0x9c30 - 0x9c34 */
6836 volatile unsigned int BB_spur_report_b0; /* 0x9c34 - 0x9c38 */
6837 volatile unsigned int BB_channel_status; /* 0x9c38 - 0x9c3c */
6838 volatile unsigned int BB_rssi_b0; /* 0x9c3c - 0x9c40 */
6839 volatile unsigned int BB_spur_est_cck_report_b0; /* 0x9c40 - 0x9c44 */
6840 volatile char pad__13[0x68]; /* 0x9c44 - 0x9cac */
6841 volatile unsigned int BB_chan_info_noise_pwr; /* 0x9cac - 0x9cb0 */
6842 volatile unsigned int BB_chan_info_gain_diff; /* 0x9cb0 - 0x9cb4 */
6843 volatile unsigned int BB_chan_info_fine_timing; /* 0x9cb4 - 0x9cb8 */
6844 volatile unsigned int BB_chan_info_gain_b0; /* 0x9cb8 - 0x9cbc */
6845 volatile unsigned int BB_chan_info_chan_tab_b0[60]; /* 0x9cbc - 0x9dac */
6846 volatile char pad__14[0x38]; /* 0x9dac - 0x9de4 */
6847 volatile unsigned int BB_paprd_am2am_mask; /* 0x9de4 - 0x9de8 */
6848 volatile unsigned int BB_paprd_am2pm_mask; /* 0x9de8 - 0x9dec */
6849 volatile unsigned int BB_paprd_ht40_mask; /* 0x9dec - 0x9df0 */
6850 volatile unsigned int BB_paprd_ctrl0; /* 0x9df0 - 0x9df4 */
6851 volatile unsigned int BB_paprd_ctrl1; /* 0x9df4 - 0x9df8 */
6852 volatile unsigned int BB_pa_gain123; /* 0x9df8 - 0x9dfc */
6853 volatile unsigned int BB_pa_gain45; /* 0x9dfc - 0x9e00 */
6854 volatile unsigned int BB_paprd_pre_post_scale_0; /* 0x9e00 - 0x9e04 */
6855 volatile unsigned int BB_paprd_pre_post_scale_1; /* 0x9e04 - 0x9e08 */
6856 volatile unsigned int BB_paprd_pre_post_scale_2; /* 0x9e08 - 0x9e0c */
6857 volatile unsigned int BB_paprd_pre_post_scale_3; /* 0x9e0c - 0x9e10 */
6858 volatile unsigned int BB_paprd_pre_post_scale_4; /* 0x9e10 - 0x9e14 */
6859 volatile unsigned int BB_paprd_pre_post_scale_5; /* 0x9e14 - 0x9e18 */
6860 volatile unsigned int BB_paprd_pre_post_scale_6; /* 0x9e18 - 0x9e1c */
6861 volatile unsigned int BB_paprd_pre_post_scale_7; /* 0x9e1c - 0x9e20 */
6862 volatile unsigned int BB_paprd_mem_tab[120]; /* 0x9e20 - 0xa000 */
6863 volatile unsigned int BB_peak_det_ctrl_1; /* 0xa000 - 0xa004 */
6864 volatile unsigned int BB_peak_det_ctrl_2; /* 0xa004 - 0xa008 */
6865 volatile unsigned int BB_rx_gain_bounds_1; /* 0xa008 - 0xa00c */
6866 volatile unsigned int BB_rx_gain_bounds_2; /* 0xa00c - 0xa010 */
6867 volatile unsigned int BB_peak_det_cal_ctrl; /* 0xa010 - 0xa014 */
6868 volatile unsigned int BB_agc_dig_dc_ctrl; /* 0xa014 - 0xa018 */
6869 volatile unsigned int BB_agc_dig_dc_status_i_b0; /* 0xa018 - 0xa01c */
6870 volatile unsigned int BB_agc_dig_dc_status_q_b0; /* 0xa01c - 0xa020 */
6871 volatile char pad__15[0x1d4]; /* 0xa020 - 0xa1f4 */
6872 volatile unsigned int BB_bbb_txfir_0; /* 0xa1f4 - 0xa1f8 */
6873 volatile unsigned int BB_bbb_txfir_1; /* 0xa1f8 - 0xa1fc */
6874 volatile unsigned int BB_bbb_txfir_2; /* 0xa1fc - 0xa200 */
6875 volatile unsigned int BB_modes_select; /* 0xa200 - 0xa204 */
6876 volatile unsigned int BB_bbb_tx_ctrl; /* 0xa204 - 0xa208 */
6877 volatile unsigned int BB_bbb_sig_detect; /* 0xa208 - 0xa20c */
6878 volatile unsigned int BB_ext_atten_switch_ctl_b0; /* 0xa20c - 0xa210 */
6879 volatile unsigned int BB_bbb_rx_ctrl_1; /* 0xa210 - 0xa214 */
6880 volatile unsigned int BB_bbb_rx_ctrl_2; /* 0xa214 - 0xa218 */
6881 volatile unsigned int BB_bbb_rx_ctrl_3; /* 0xa218 - 0xa21c */
6882 volatile unsigned int BB_bbb_rx_ctrl_4; /* 0xa21c - 0xa220 */
6883 volatile unsigned int BB_bbb_rx_ctrl_5; /* 0xa220 - 0xa224 */
6884 volatile unsigned int BB_bbb_rx_ctrl_6; /* 0xa224 - 0xa228 */
6885 volatile unsigned int BB_bbb_dagc_ctrl; /* 0xa228 - 0xa22c */
6886 volatile unsigned int BB_force_clken_cck; /* 0xa22c - 0xa230 */
6887 volatile unsigned int BB_rx_clear_delay; /* 0xa230 - 0xa234 */
6888 volatile unsigned int BB_powertx_rate3; /* 0xa234 - 0xa238 */
6889 volatile unsigned int BB_powertx_rate4; /* 0xa238 - 0xa23c */
6890 volatile char pad__16[0x4]; /* 0xa23c - 0xa240 */
6891 volatile unsigned int BB_cck_spur_mit; /* 0xa240 - 0xa244 */
6892 volatile unsigned int BB_panic_watchdog_status; /* 0xa244 - 0xa248 */
6893 volatile unsigned int BB_panic_watchdog_ctrl_1; /* 0xa248 - 0xa24c */
6894 volatile unsigned int BB_panic_watchdog_ctrl_2; /* 0xa24c - 0xa250 */
6895 volatile unsigned int BB_iqcorr_ctrl_cck; /* 0xa250 - 0xa254 */
6896 volatile unsigned int BB_bluetooth_cntl; /* 0xa254 - 0xa258 */
6897 volatile unsigned int BB_tpc_1; /* 0xa258 - 0xa25c */
6898 volatile unsigned int BB_tpc_2; /* 0xa25c - 0xa260 */
6899 volatile unsigned int BB_tpc_3; /* 0xa260 - 0xa264 */
6900 volatile unsigned int BB_tpc_4_b0; /* 0xa264 - 0xa268 */
6901 volatile unsigned int BB_analog_swap; /* 0xa268 - 0xa26c */
6902 volatile unsigned int BB_tpc_5_b0; /* 0xa26c - 0xa270 */
6903 volatile unsigned int BB_tpc_6_b0; /* 0xa270 - 0xa274 */
6904 volatile unsigned int BB_tpc_7; /* 0xa274 - 0xa278 */
6905 volatile unsigned int BB_tpc_8; /* 0xa278 - 0xa27c */
6906 volatile unsigned int BB_tpc_9; /* 0xa27c - 0xa280 */
6907 volatile unsigned int BB_pdadc_tab_b0[32]; /* 0xa280 - 0xa300 */
6908 volatile unsigned int BB_cl_tab_b0[16]; /* 0xa300 - 0xa340 */
6909 volatile unsigned int BB_cl_map_0_b0; /* 0xa340 - 0xa344 */
6910 volatile unsigned int BB_cl_map_1_b0; /* 0xa344 - 0xa348 */
6911 volatile unsigned int BB_cl_map_2_b0; /* 0xa348 - 0xa34c */
6912 volatile unsigned int BB_cl_map_3_b0; /* 0xa34c - 0xa350 */
6913 volatile char pad__17[0x8]; /* 0xa350 - 0xa358 */
6914 volatile unsigned int BB_cl_cal_ctrl; /* 0xa358 - 0xa35c */
6915 volatile unsigned int BB_cl_map_pal_0_b0; /* 0xa35c - 0xa360 */
6916 volatile unsigned int BB_cl_map_pal_1_b0; /* 0xa360 - 0xa364 */
6917 volatile unsigned int BB_cl_map_pal_2_b0; /* 0xa364 - 0xa368 */
6918 volatile unsigned int BB_cl_map_pal_3_b0; /* 0xa368 - 0xa36c */
6919 volatile char pad__18[0x1c]; /* 0xa36c - 0xa388 */
6920 volatile unsigned int BB_rifs; /* 0xa388 - 0xa38c */
6921 volatile unsigned int BB_powertx_rate5; /* 0xa38c - 0xa390 */
6922 volatile unsigned int BB_powertx_rate6; /* 0xa390 - 0xa394 */
6923 volatile unsigned int BB_tpc_10; /* 0xa394 - 0xa398 */
6924 volatile unsigned int BB_tpc_11_b0; /* 0xa398 - 0xa39c */
6925 volatile unsigned int BB_cal_chain_mask; /* 0xa39c - 0xa3a0 */
6926 volatile char pad__19[0x1c]; /* 0xa3a0 - 0xa3bc */
6927 volatile unsigned int BB_powertx_sub; /* 0xa3bc - 0xa3c0 */
6928 volatile unsigned int BB_powertx_rate7; /* 0xa3c0 - 0xa3c4 */
6929 volatile unsigned int BB_powertx_rate8; /* 0xa3c4 - 0xa3c8 */
6930 volatile unsigned int BB_powertx_rate9; /* 0xa3c8 - 0xa3cc */
6931 volatile unsigned int BB_powertx_rate10; /* 0xa3cc - 0xa3d0 */
6932 volatile unsigned int BB_powertx_rate11; /* 0xa3d0 - 0xa3d4 */
6933 volatile unsigned int BB_powertx_rate12; /* 0xa3d4 - 0xa3d8 */
6934 volatile unsigned int BB_force_analog; /* 0xa3d8 - 0xa3dc */
6935 volatile unsigned int BB_tpc_12; /* 0xa3dc - 0xa3e0 */
6936 volatile unsigned int BB_tpc_13; /* 0xa3e0 - 0xa3e4 */
6937 volatile unsigned int BB_tpc_14; /* 0xa3e4 - 0xa3e8 */
6938 volatile unsigned int BB_tpc_15; /* 0xa3e8 - 0xa3ec */
6939 volatile unsigned int BB_tpc_16; /* 0xa3ec - 0xa3f0 */
6940 volatile unsigned int BB_tpc_17; /* 0xa3f0 - 0xa3f4 */
6941 volatile unsigned int BB_tpc_18; /* 0xa3f4 - 0xa3f8 */
6942 volatile unsigned int BB_tpc_19; /* 0xa3f8 - 0xa3fc */
6943 volatile unsigned int BB_tpc_20; /* 0xa3fc - 0xa400 */
6944 volatile unsigned int BB_tx_gain_tab_1; /* 0xa400 - 0xa404 */
6945 volatile unsigned int BB_tx_gain_tab_2; /* 0xa404 - 0xa408 */
6946 volatile unsigned int BB_tx_gain_tab_3; /* 0xa408 - 0xa40c */
6947 volatile unsigned int BB_tx_gain_tab_4; /* 0xa40c - 0xa410 */
6948 volatile unsigned int BB_tx_gain_tab_5; /* 0xa410 - 0xa414 */
6949 volatile unsigned int BB_tx_gain_tab_6; /* 0xa414 - 0xa418 */
6950 volatile unsigned int BB_tx_gain_tab_7; /* 0xa418 - 0xa41c */
6951 volatile unsigned int BB_tx_gain_tab_8; /* 0xa41c - 0xa420 */
6952 volatile unsigned int BB_tx_gain_tab_9; /* 0xa420 - 0xa424 */
6953 volatile unsigned int BB_tx_gain_tab_10; /* 0xa424 - 0xa428 */
6954 volatile unsigned int BB_tx_gain_tab_11; /* 0xa428 - 0xa42c */
6955 volatile unsigned int BB_tx_gain_tab_12; /* 0xa42c - 0xa430 */
6956 volatile unsigned int BB_tx_gain_tab_13; /* 0xa430 - 0xa434 */
6957 volatile unsigned int BB_tx_gain_tab_14; /* 0xa434 - 0xa438 */
6958 volatile unsigned int BB_tx_gain_tab_15; /* 0xa438 - 0xa43c */
6959 volatile unsigned int BB_tx_gain_tab_16; /* 0xa43c - 0xa440 */
6960 volatile unsigned int BB_tx_gain_tab_17; /* 0xa440 - 0xa444 */
6961 volatile unsigned int BB_tx_gain_tab_18; /* 0xa444 - 0xa448 */
6962 volatile unsigned int BB_tx_gain_tab_19; /* 0xa448 - 0xa44c */
6963 volatile unsigned int BB_tx_gain_tab_20; /* 0xa44c - 0xa450 */
6964 volatile unsigned int BB_tx_gain_tab_21; /* 0xa450 - 0xa454 */
6965 volatile unsigned int BB_tx_gain_tab_22; /* 0xa454 - 0xa458 */
6966 volatile unsigned int BB_tx_gain_tab_23; /* 0xa458 - 0xa45c */
6967 volatile unsigned int BB_tx_gain_tab_24; /* 0xa45c - 0xa460 */
6968 volatile unsigned int BB_tx_gain_tab_25; /* 0xa460 - 0xa464 */
6969 volatile unsigned int BB_tx_gain_tab_26; /* 0xa464 - 0xa468 */
6970 volatile unsigned int BB_tx_gain_tab_27; /* 0xa468 - 0xa46c */
6971 volatile unsigned int BB_tx_gain_tab_28; /* 0xa46c - 0xa470 */
6972 volatile unsigned int BB_tx_gain_tab_29; /* 0xa470 - 0xa474 */
6973 volatile unsigned int BB_tx_gain_tab_30; /* 0xa474 - 0xa478 */
6974 volatile unsigned int BB_tx_gain_tab_31; /* 0xa478 - 0xa47c */
6975 volatile unsigned int BB_tx_gain_tab_32; /* 0xa47c - 0xa480 */
6976 volatile unsigned int BB_tx_gain_tab_pal_1; /* 0xa480 - 0xa484 */
6977 volatile unsigned int BB_tx_gain_tab_pal_2; /* 0xa484 - 0xa488 */
6978 volatile unsigned int BB_tx_gain_tab_pal_3; /* 0xa488 - 0xa48c */
6979 volatile unsigned int BB_tx_gain_tab_pal_4; /* 0xa48c - 0xa490 */
6980 volatile unsigned int BB_tx_gain_tab_pal_5; /* 0xa490 - 0xa494 */
6981 volatile unsigned int BB_tx_gain_tab_pal_6; /* 0xa494 - 0xa498 */
6982 volatile unsigned int BB_tx_gain_tab_pal_7; /* 0xa498 - 0xa49c */
6983 volatile unsigned int BB_tx_gain_tab_pal_8; /* 0xa49c - 0xa4a0 */
6984 volatile unsigned int BB_tx_gain_tab_pal_9; /* 0xa4a0 - 0xa4a4 */
6985 volatile unsigned int BB_tx_gain_tab_pal_10; /* 0xa4a4 - 0xa4a8 */
6986 volatile unsigned int BB_tx_gain_tab_pal_11; /* 0xa4a8 - 0xa4ac */
6987 volatile unsigned int BB_tx_gain_tab_pal_12; /* 0xa4ac - 0xa4b0 */
6988 volatile unsigned int BB_tx_gain_tab_pal_13; /* 0xa4b0 - 0xa4b4 */
6989 volatile unsigned int BB_tx_gain_tab_pal_14; /* 0xa4b4 - 0xa4b8 */
6990 volatile unsigned int BB_tx_gain_tab_pal_15; /* 0xa4b8 - 0xa4bc */
6991 volatile unsigned int BB_tx_gain_tab_pal_16; /* 0xa4bc - 0xa4c0 */
6992 volatile unsigned int BB_tx_gain_tab_pal_17; /* 0xa4c0 - 0xa4c4 */
6993 volatile unsigned int BB_tx_gain_tab_pal_18; /* 0xa4c4 - 0xa4c8 */
6994 volatile unsigned int BB_tx_gain_tab_pal_19; /* 0xa4c8 - 0xa4cc */
6995 volatile unsigned int BB_tx_gain_tab_pal_20; /* 0xa4cc - 0xa4d0 */
6996 volatile unsigned int BB_tx_gain_tab_pal_21; /* 0xa4d0 - 0xa4d4 */
6997 volatile unsigned int BB_tx_gain_tab_pal_22; /* 0xa4d4 - 0xa4d8 */
6998 volatile unsigned int BB_tx_gain_tab_pal_23; /* 0xa4d8 - 0xa4dc */
6999 volatile unsigned int BB_tx_gain_tab_pal_24; /* 0xa4dc - 0xa4e0 */
7000 volatile unsigned int BB_tx_gain_tab_pal_25; /* 0xa4e0 - 0xa4e4 */
7001 volatile unsigned int BB_tx_gain_tab_pal_26; /* 0xa4e4 - 0xa4e8 */
7002 volatile unsigned int BB_tx_gain_tab_pal_27; /* 0xa4e8 - 0xa4ec */
7003 volatile unsigned int BB_tx_gain_tab_pal_28; /* 0xa4ec - 0xa4f0 */
7004 volatile unsigned int BB_tx_gain_tab_pal_29; /* 0xa4f0 - 0xa4f4 */
7005 volatile unsigned int BB_tx_gain_tab_pal_30; /* 0xa4f4 - 0xa4f8 */
7006 volatile unsigned int BB_tx_gain_tab_pal_31; /* 0xa4f8 - 0xa4fc */
7007 volatile unsigned int BB_tx_gain_tab_pal_32; /* 0xa4fc - 0xa500 */
7008 volatile char pad__20[0x18]; /* 0xa500 - 0xa518 */
7009 volatile unsigned int BB_caltx_gain_set_0; /* 0xa518 - 0xa51c */
7010 volatile unsigned int BB_caltx_gain_set_2; /* 0xa51c - 0xa520 */
7011 volatile unsigned int BB_caltx_gain_set_4; /* 0xa520 - 0xa524 */
7012 volatile unsigned int BB_caltx_gain_set_6; /* 0xa524 - 0xa528 */
7013 volatile unsigned int BB_caltx_gain_set_8; /* 0xa528 - 0xa52c */
7014 volatile unsigned int BB_caltx_gain_set_10; /* 0xa52c - 0xa530 */
7015 volatile unsigned int BB_caltx_gain_set_12; /* 0xa530 - 0xa534 */
7016 volatile unsigned int BB_caltx_gain_set_14; /* 0xa534 - 0xa538 */
7017 volatile unsigned int BB_caltx_gain_set_16; /* 0xa538 - 0xa53c */
7018 volatile unsigned int BB_caltx_gain_set_18; /* 0xa53c - 0xa540 */
7019 volatile unsigned int BB_caltx_gain_set_20; /* 0xa540 - 0xa544 */
7020 volatile unsigned int BB_caltx_gain_set_22; /* 0xa544 - 0xa548 */
7021 volatile unsigned int BB_caltx_gain_set_24; /* 0xa548 - 0xa54c */
7022 volatile unsigned int BB_caltx_gain_set_26; /* 0xa54c - 0xa550 */
7023 volatile unsigned int BB_caltx_gain_set_28; /* 0xa550 - 0xa554 */
7024 volatile unsigned int BB_caltx_gain_set_30; /* 0xa554 - 0xa558 */
7025 volatile unsigned int BB_txiqcal_meas_b0[96]; /* 0xa558 - 0xa6d8 */
7026 volatile unsigned int BB_txiqcal_start; /* 0xa6d8 - 0xa6dc */
7027 volatile unsigned int BB_txiqcal_control_0; /* 0xa6dc - 0xa6e0 */
7028 volatile unsigned int BB_txiqcal_control_1; /* 0xa6e0 - 0xa6e4 */
7029 volatile unsigned int BB_txiqcal_control_2; /* 0xa6e4 - 0xa6e8 */
7030 volatile unsigned int BB_txiqcal_control_3; /* 0xa6e8 - 0xa6ec */
7031 volatile unsigned int BB_txiq_corr_coeff_01_b0; /* 0xa6ec - 0xa6f0 */
7032 volatile unsigned int BB_txiq_corr_coeff_23_b0; /* 0xa6f0 - 0xa6f4 */
7033 volatile unsigned int BB_txiq_corr_coeff_45_b0; /* 0xa6f4 - 0xa6f8 */
7034 volatile unsigned int BB_txiq_corr_coeff_67_b0; /* 0xa6f8 - 0xa6fc */
7035 volatile unsigned int BB_txiq_corr_coeff_89_b0; /* 0xa6fc - 0xa700 */
7036 volatile unsigned int BB_txiq_corr_coeff_ab_b0; /* 0xa700 - 0xa704 */
7037 volatile unsigned int BB_txiq_corr_coeff_cd_b0; /* 0xa704 - 0xa708 */
7038 volatile unsigned int BB_txiq_corr_coeff_ef_b0; /* 0xa708 - 0xa70c */
7039 volatile unsigned int BB_cal_rxbb_gain_tbl_0; /* 0xa70c - 0xa710 */
7040 volatile unsigned int BB_cal_rxbb_gain_tbl_4; /* 0xa710 - 0xa714 */
7041 volatile unsigned int BB_cal_rxbb_gain_tbl_8; /* 0xa714 - 0xa718 */
7042 volatile unsigned int BB_cal_rxbb_gain_tbl_12; /* 0xa718 - 0xa71c */
7043 volatile unsigned int BB_cal_rxbb_gain_tbl_16; /* 0xa71c - 0xa720 */
7044 volatile unsigned int BB_cal_rxbb_gain_tbl_20; /* 0xa720 - 0xa724 */
7045 volatile unsigned int BB_cal_rxbb_gain_tbl_24; /* 0xa724 - 0xa728 */
7046 volatile unsigned int BB_txiqcal_status_b0; /* 0xa728 - 0xa72c */
7047 volatile unsigned int BB_paprd_trainer_cntl1; /* 0xa72c - 0xa730 */
7048 volatile unsigned int BB_paprd_trainer_cntl2; /* 0xa730 - 0xa734 */
7049 volatile unsigned int BB_paprd_trainer_cntl3; /* 0xa734 - 0xa738 */
7050 volatile unsigned int BB_paprd_trainer_cntl4; /* 0xa738 - 0xa73c */
7051 volatile unsigned int BB_paprd_trainer_stat1; /* 0xa73c - 0xa740 */
7052 volatile unsigned int BB_paprd_trainer_stat2; /* 0xa740 - 0xa744 */
7053 volatile unsigned int BB_paprd_trainer_stat3; /* 0xa744 - 0xa748 */
7054 volatile char pad__21[0x90]; /* 0xa748 - 0xa7d8 */
7055 volatile unsigned int BB_fcal_1; /* 0xa7d8 - 0xa7dc */
7056 volatile unsigned int BB_fcal_2_b0; /* 0xa7dc - 0xa7e0 */
7057 volatile unsigned int BB_radar_bw_filter; /* 0xa7e0 - 0xa7e4 */
7058 volatile unsigned int BB_dft_tone_ctrl_b0; /* 0xa7e4 - 0xa7e8 */
7059 volatile unsigned int BB_therm_adc_1; /* 0xa7e8 - 0xa7ec */
7060 volatile unsigned int BB_therm_adc_2; /* 0xa7ec - 0xa7f0 */
7061 volatile unsigned int BB_therm_adc_3; /* 0xa7f0 - 0xa7f4 */
7062 volatile unsigned int BB_therm_adc_4; /* 0xa7f4 - 0xa7f8 */
7063 volatile unsigned int BB_tx_forced_gain; /* 0xa7f8 - 0xa7fc */
7064 volatile unsigned int BB_eco_ctrl; /* 0xa7fc - 0xa800 */
7065 volatile char pad__22[0x48]; /* 0xa800 - 0xa848 */
7066 volatile unsigned int BB_gain_force_max_gains_b1; /* 0xa848 - 0xa84c */
7067 volatile unsigned int BB_gains_min_offsets_b1; /* 0xa84c - 0xa850 */
7068 volatile char pad__23[0x1b0]; /* 0xa850 - 0xaa00 */
7069 volatile unsigned int BB_rx_ocgain2[128]; /* 0xaa00 - 0xac00 */
7070 volatile char pad__24[0x60c]; /* 0xac00 - 0xb20c */
7071 volatile unsigned int BB_ext_atten_switch_ctl_b1; /* 0xb20c - 0xb210 */
7074 #endif /* __ASSEMBLER__ */
7076 #endif /* _BB_LC_REG_REG_H_ */