1 #ifndef _MBOX_REG_REG_H_
2 #define _MBOX_REG_REG_H_
4 #define MBOX_FIFO_ADDRESS 0x00000000
5 #define MBOX_FIFO_OFFSET 0x00000000
6 #define MBOX_FIFO_DATA_MSB 19
7 #define MBOX_FIFO_DATA_LSB 0
8 #define MBOX_FIFO_DATA_MASK 0x000fffff
9 #define MBOX_FIFO_DATA_GET(x) (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB)
10 #define MBOX_FIFO_DATA_SET(x) (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK)
12 #define MBOX_FIFO_STATUS_ADDRESS 0x00000010
13 #define MBOX_FIFO_STATUS_OFFSET 0x00000010
14 #define MBOX_FIFO_STATUS_EMPTY_MSB 19
15 #define MBOX_FIFO_STATUS_EMPTY_LSB 16
16 #define MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000
17 #define MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB)
18 #define MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK)
19 #define MBOX_FIFO_STATUS_FULL_MSB 15
20 #define MBOX_FIFO_STATUS_FULL_LSB 12
21 #define MBOX_FIFO_STATUS_FULL_MASK 0x0000f000
22 #define MBOX_FIFO_STATUS_FULL_GET(x) (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB)
23 #define MBOX_FIFO_STATUS_FULL_SET(x) (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK)
25 #define MBOX_DMA_POLICY_ADDRESS 0x00000014
26 #define MBOX_DMA_POLICY_OFFSET 0x00000014
27 #define MBOX_DMA_POLICY_TX_QUANTUM_MSB 3
28 #define MBOX_DMA_POLICY_TX_QUANTUM_LSB 3
29 #define MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008
30 #define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB)
31 #define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK)
32 #define MBOX_DMA_POLICY_TX_ORDER_MSB 2
33 #define MBOX_DMA_POLICY_TX_ORDER_LSB 2
34 #define MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004
35 #define MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB)
36 #define MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK)
37 #define MBOX_DMA_POLICY_RX_QUANTUM_MSB 1
38 #define MBOX_DMA_POLICY_RX_QUANTUM_LSB 1
39 #define MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002
40 #define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB)
41 #define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK)
42 #define MBOX_DMA_POLICY_RX_ORDER_MSB 0
43 #define MBOX_DMA_POLICY_RX_ORDER_LSB 0
44 #define MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001
45 #define MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB)
46 #define MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK)
48 #define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018
49 #define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018
50 #define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
51 #define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
52 #define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
53 #define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
54 #define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
56 #define MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c
57 #define MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c
58 #define MBOX0_DMA_RX_CONTROL_RESUME_MSB 2
59 #define MBOX0_DMA_RX_CONTROL_RESUME_LSB 2
60 #define MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
61 #define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB)
62 #define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK)
63 #define MBOX0_DMA_RX_CONTROL_START_MSB 1
64 #define MBOX0_DMA_RX_CONTROL_START_LSB 1
65 #define MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
66 #define MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB)
67 #define MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK)
68 #define MBOX0_DMA_RX_CONTROL_STOP_MSB 0
69 #define MBOX0_DMA_RX_CONTROL_STOP_LSB 0
70 #define MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
71 #define MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB)
72 #define MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK)
74 #define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020
75 #define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020
76 #define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
77 #define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
78 #define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
79 #define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
80 #define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
82 #define MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024
83 #define MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024
84 #define MBOX0_DMA_TX_CONTROL_RESUME_MSB 2
85 #define MBOX0_DMA_TX_CONTROL_RESUME_LSB 2
86 #define MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
87 #define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB)
88 #define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK)
89 #define MBOX0_DMA_TX_CONTROL_START_MSB 1
90 #define MBOX0_DMA_TX_CONTROL_START_LSB 1
91 #define MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
92 #define MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB)
93 #define MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK)
94 #define MBOX0_DMA_TX_CONTROL_STOP_MSB 0
95 #define MBOX0_DMA_TX_CONTROL_STOP_LSB 0
96 #define MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
97 #define MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB)
98 #define MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK)
100 #define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028
101 #define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028
102 #define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
103 #define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
104 #define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
105 #define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
106 #define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
108 #define MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c
109 #define MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c
110 #define MBOX1_DMA_RX_CONTROL_RESUME_MSB 2
111 #define MBOX1_DMA_RX_CONTROL_RESUME_LSB 2
112 #define MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004
113 #define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB)
114 #define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK)
115 #define MBOX1_DMA_RX_CONTROL_START_MSB 1
116 #define MBOX1_DMA_RX_CONTROL_START_LSB 1
117 #define MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002
118 #define MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB)
119 #define MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK)
120 #define MBOX1_DMA_RX_CONTROL_STOP_MSB 0
121 #define MBOX1_DMA_RX_CONTROL_STOP_LSB 0
122 #define MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001
123 #define MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB)
124 #define MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK)
126 #define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030
127 #define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030
128 #define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
129 #define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
130 #define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
131 #define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
132 #define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
134 #define MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034
135 #define MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034
136 #define MBOX1_DMA_TX_CONTROL_RESUME_MSB 2
137 #define MBOX1_DMA_TX_CONTROL_RESUME_LSB 2
138 #define MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004
139 #define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB)
140 #define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK)
141 #define MBOX1_DMA_TX_CONTROL_START_MSB 1
142 #define MBOX1_DMA_TX_CONTROL_START_LSB 1
143 #define MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002
144 #define MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB)
145 #define MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK)
146 #define MBOX1_DMA_TX_CONTROL_STOP_MSB 0
147 #define MBOX1_DMA_TX_CONTROL_STOP_LSB 0
148 #define MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001
149 #define MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB)
150 #define MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK)
152 #define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038
153 #define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038
154 #define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
155 #define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
156 #define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
157 #define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
158 #define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
160 #define MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c
161 #define MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c
162 #define MBOX2_DMA_RX_CONTROL_RESUME_MSB 2
163 #define MBOX2_DMA_RX_CONTROL_RESUME_LSB 2
164 #define MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004
165 #define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB)
166 #define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK)
167 #define MBOX2_DMA_RX_CONTROL_START_MSB 1
168 #define MBOX2_DMA_RX_CONTROL_START_LSB 1
169 #define MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002
170 #define MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB)
171 #define MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK)
172 #define MBOX2_DMA_RX_CONTROL_STOP_MSB 0
173 #define MBOX2_DMA_RX_CONTROL_STOP_LSB 0
174 #define MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001
175 #define MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB)
176 #define MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK)
178 #define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040
179 #define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040
180 #define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
181 #define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
182 #define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
183 #define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
184 #define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
186 #define MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044
187 #define MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044
188 #define MBOX2_DMA_TX_CONTROL_RESUME_MSB 2
189 #define MBOX2_DMA_TX_CONTROL_RESUME_LSB 2
190 #define MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004
191 #define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB)
192 #define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK)
193 #define MBOX2_DMA_TX_CONTROL_START_MSB 1
194 #define MBOX2_DMA_TX_CONTROL_START_LSB 1
195 #define MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002
196 #define MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB)
197 #define MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK)
198 #define MBOX2_DMA_TX_CONTROL_STOP_MSB 0
199 #define MBOX2_DMA_TX_CONTROL_STOP_LSB 0
200 #define MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001
201 #define MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB)
202 #define MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK)
204 #define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048
205 #define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048
206 #define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
207 #define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
208 #define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
209 #define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
210 #define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
212 #define MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c
213 #define MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c
214 #define MBOX3_DMA_RX_CONTROL_RESUME_MSB 2
215 #define MBOX3_DMA_RX_CONTROL_RESUME_LSB 2
216 #define MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004
217 #define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB)
218 #define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK)
219 #define MBOX3_DMA_RX_CONTROL_START_MSB 1
220 #define MBOX3_DMA_RX_CONTROL_START_LSB 1
221 #define MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002
222 #define MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB)
223 #define MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK)
224 #define MBOX3_DMA_RX_CONTROL_STOP_MSB 0
225 #define MBOX3_DMA_RX_CONTROL_STOP_LSB 0
226 #define MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001
227 #define MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB)
228 #define MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK)
230 #define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050
231 #define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050
232 #define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
233 #define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
234 #define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
235 #define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
236 #define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
238 #define MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054
239 #define MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054
240 #define MBOX3_DMA_TX_CONTROL_RESUME_MSB 2
241 #define MBOX3_DMA_TX_CONTROL_RESUME_LSB 2
242 #define MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004
243 #define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB)
244 #define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK)
245 #define MBOX3_DMA_TX_CONTROL_START_MSB 1
246 #define MBOX3_DMA_TX_CONTROL_START_LSB 1
247 #define MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002
248 #define MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB)
249 #define MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK)
250 #define MBOX3_DMA_TX_CONTROL_STOP_MSB 0
251 #define MBOX3_DMA_TX_CONTROL_STOP_LSB 0
252 #define MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001
253 #define MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB)
254 #define MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK)
256 #define MBOX_INT_STATUS_ADDRESS 0x00000058
257 #define MBOX_INT_STATUS_OFFSET 0x00000058
258 #define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31
259 #define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28
260 #define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000
261 #define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
262 #define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
263 #define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27
264 #define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24
265 #define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
266 #define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
267 #define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
268 #define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23
269 #define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20
270 #define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000
271 #define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
272 #define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
273 #define MBOX_INT_STATUS_TX_OVERFLOW_MSB 17
274 #define MBOX_INT_STATUS_TX_OVERFLOW_LSB 17
275 #define MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000
276 #define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB)
277 #define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK)
278 #define MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16
279 #define MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16
280 #define MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000
281 #define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB)
282 #define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK)
283 #define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15
284 #define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12
285 #define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000
286 #define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
287 #define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
288 #define MBOX_INT_STATUS_RX_NOT_FULL_MSB 11
289 #define MBOX_INT_STATUS_RX_NOT_FULL_LSB 8
290 #define MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00
291 #define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB)
292 #define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK)
293 #define MBOX_INT_STATUS_HOST_MSB 7
294 #define MBOX_INT_STATUS_HOST_LSB 0
295 #define MBOX_INT_STATUS_HOST_MASK 0x000000ff
296 #define MBOX_INT_STATUS_HOST_GET(x) (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB)
297 #define MBOX_INT_STATUS_HOST_SET(x) (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK)
299 #define MBOX_INT_ENABLE_ADDRESS 0x0000005c
300 #define MBOX_INT_ENABLE_OFFSET 0x0000005c
301 #define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31
302 #define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28
303 #define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000
304 #define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
305 #define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
306 #define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27
307 #define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24
308 #define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
309 #define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
310 #define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
311 #define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23
312 #define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20
313 #define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000
314 #define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
315 #define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
316 #define MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17
317 #define MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17
318 #define MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000
319 #define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB)
320 #define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK)
321 #define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16
322 #define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16
323 #define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000
324 #define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
325 #define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
326 #define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15
327 #define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12
328 #define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000
329 #define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
330 #define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
331 #define MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11
332 #define MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8
333 #define MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00
334 #define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB)
335 #define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK)
336 #define MBOX_INT_ENABLE_HOST_MSB 7
337 #define MBOX_INT_ENABLE_HOST_LSB 0
338 #define MBOX_INT_ENABLE_HOST_MASK 0x000000ff
339 #define MBOX_INT_ENABLE_HOST_GET(x) (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB)
340 #define MBOX_INT_ENABLE_HOST_SET(x) (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK)
342 #define INT_HOST_ADDRESS 0x00000060
343 #define INT_HOST_OFFSET 0x00000060
344 #define INT_HOST_VECTOR_MSB 7
345 #define INT_HOST_VECTOR_LSB 0
346 #define INT_HOST_VECTOR_MASK 0x000000ff
347 #define INT_HOST_VECTOR_GET(x) (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB)
348 #define INT_HOST_VECTOR_SET(x) (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK)
350 #define LOCAL_COUNT_ADDRESS 0x00000080
351 #define LOCAL_COUNT_OFFSET 0x00000080
352 #define LOCAL_COUNT_VALUE_MSB 7
353 #define LOCAL_COUNT_VALUE_LSB 0
354 #define LOCAL_COUNT_VALUE_MASK 0x000000ff
355 #define LOCAL_COUNT_VALUE_GET(x) (((x) & LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB)
356 #define LOCAL_COUNT_VALUE_SET(x) (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK)
358 #define COUNT_INC_ADDRESS 0x000000a0
359 #define COUNT_INC_OFFSET 0x000000a0
360 #define COUNT_INC_VALUE_MSB 7
361 #define COUNT_INC_VALUE_LSB 0
362 #define COUNT_INC_VALUE_MASK 0x000000ff
363 #define COUNT_INC_VALUE_GET(x) (((x) & COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB)
364 #define COUNT_INC_VALUE_SET(x) (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK)
366 #define LOCAL_SCRATCH_ADDRESS 0x000000c0
367 #define LOCAL_SCRATCH_OFFSET 0x000000c0
368 #define LOCAL_SCRATCH_VALUE_MSB 7
369 #define LOCAL_SCRATCH_VALUE_LSB 0
370 #define LOCAL_SCRATCH_VALUE_MASK 0x000000ff
371 #define LOCAL_SCRATCH_VALUE_GET(x) (((x) & LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB)
372 #define LOCAL_SCRATCH_VALUE_SET(x) (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK)
374 #define USE_LOCAL_BUS_ADDRESS 0x000000e0
375 #define USE_LOCAL_BUS_OFFSET 0x000000e0
376 #define USE_LOCAL_BUS_PIN_INIT_MSB 0
377 #define USE_LOCAL_BUS_PIN_INIT_LSB 0
378 #define USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001
379 #define USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB)
380 #define USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK)
382 #define SDIO_CONFIG_ADDRESS 0x000000e4
383 #define SDIO_CONFIG_OFFSET 0x000000e4
384 #define SDIO_CONFIG_CCCR_IOR1_MSB 0
385 #define SDIO_CONFIG_CCCR_IOR1_LSB 0
386 #define SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001
387 #define SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB)
388 #define SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK)
390 #define MBOX_DEBUG_ADDRESS 0x000000e8
391 #define MBOX_DEBUG_OFFSET 0x000000e8
392 #define MBOX_DEBUG_SEL_MSB 2
393 #define MBOX_DEBUG_SEL_LSB 0
394 #define MBOX_DEBUG_SEL_MASK 0x00000007
395 #define MBOX_DEBUG_SEL_GET(x) (((x) & MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB)
396 #define MBOX_DEBUG_SEL_SET(x) (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK)
398 #define MBOX_FIFO_RESET_ADDRESS 0x000000ec
399 #define MBOX_FIFO_RESET_OFFSET 0x000000ec
400 #define MBOX_FIFO_RESET_INIT_MSB 0
401 #define MBOX_FIFO_RESET_INIT_LSB 0
402 #define MBOX_FIFO_RESET_INIT_MASK 0x00000001
403 #define MBOX_FIFO_RESET_INIT_GET(x) (((x) & MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB)
404 #define MBOX_FIFO_RESET_INIT_SET(x) (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK)
406 #define MBOX_TXFIFO_POP_ADDRESS 0x000000f0
407 #define MBOX_TXFIFO_POP_OFFSET 0x000000f0
408 #define MBOX_TXFIFO_POP_DATA_MSB 0
409 #define MBOX_TXFIFO_POP_DATA_LSB 0
410 #define MBOX_TXFIFO_POP_DATA_MASK 0x00000001
411 #define MBOX_TXFIFO_POP_DATA_GET(x) (((x) & MBOX_TXFIFO_POP_DATA_MASK) >> MBOX_TXFIFO_POP_DATA_LSB)
412 #define MBOX_TXFIFO_POP_DATA_SET(x) (((x) << MBOX_TXFIFO_POP_DATA_LSB) & MBOX_TXFIFO_POP_DATA_MASK)
414 #define MBOX_RXFIFO_POP_ADDRESS 0x00000100
415 #define MBOX_RXFIFO_POP_OFFSET 0x00000100
416 #define MBOX_RXFIFO_POP_DATA_MSB 0
417 #define MBOX_RXFIFO_POP_DATA_LSB 0
418 #define MBOX_RXFIFO_POP_DATA_MASK 0x00000001
419 #define MBOX_RXFIFO_POP_DATA_GET(x) (((x) & MBOX_RXFIFO_POP_DATA_MASK) >> MBOX_RXFIFO_POP_DATA_LSB)
420 #define MBOX_RXFIFO_POP_DATA_SET(x) (((x) << MBOX_RXFIFO_POP_DATA_LSB) & MBOX_RXFIFO_POP_DATA_MASK)
422 #define SDIO_DEBUG_ADDRESS 0x00000110
423 #define SDIO_DEBUG_OFFSET 0x00000110
424 #define SDIO_DEBUG_SEL_MSB 3
425 #define SDIO_DEBUG_SEL_LSB 0
426 #define SDIO_DEBUG_SEL_MASK 0x0000000f
427 #define SDIO_DEBUG_SEL_GET(x) (((x) & SDIO_DEBUG_SEL_MASK) >> SDIO_DEBUG_SEL_LSB)
428 #define SDIO_DEBUG_SEL_SET(x) (((x) << SDIO_DEBUG_SEL_LSB) & SDIO_DEBUG_SEL_MASK)
430 #define HOST_IF_WINDOW_ADDRESS 0x00002000
431 #define HOST_IF_WINDOW_OFFSET 0x00002000
432 #define HOST_IF_WINDOW_DATA_MSB 7
433 #define HOST_IF_WINDOW_DATA_LSB 0
434 #define HOST_IF_WINDOW_DATA_MASK 0x000000ff
435 #define HOST_IF_WINDOW_DATA_GET(x) (((x) & HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB)
436 #define HOST_IF_WINDOW_DATA_SET(x) (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK)
439 #ifndef __ASSEMBLER__
441 typedef struct mbox_reg_reg_s {
442 volatile unsigned int mbox_fifo[4];
443 volatile unsigned int mbox_fifo_status;
444 volatile unsigned int mbox_dma_policy;
445 volatile unsigned int mbox0_dma_rx_descriptor_base;
446 volatile unsigned int mbox0_dma_rx_control;
447 volatile unsigned int mbox0_dma_tx_descriptor_base;
448 volatile unsigned int mbox0_dma_tx_control;
449 volatile unsigned int mbox1_dma_rx_descriptor_base;
450 volatile unsigned int mbox1_dma_rx_control;
451 volatile unsigned int mbox1_dma_tx_descriptor_base;
452 volatile unsigned int mbox1_dma_tx_control;
453 volatile unsigned int mbox2_dma_rx_descriptor_base;
454 volatile unsigned int mbox2_dma_rx_control;
455 volatile unsigned int mbox2_dma_tx_descriptor_base;
456 volatile unsigned int mbox2_dma_tx_control;
457 volatile unsigned int mbox3_dma_rx_descriptor_base;
458 volatile unsigned int mbox3_dma_rx_control;
459 volatile unsigned int mbox3_dma_tx_descriptor_base;
460 volatile unsigned int mbox3_dma_tx_control;
461 volatile unsigned int mbox_int_status;
462 volatile unsigned int mbox_int_enable;
463 volatile unsigned int int_host;
464 unsigned char pad0[28]; /* pad to 0x80 */
465 volatile unsigned int local_count[8];
466 volatile unsigned int count_inc[8];
467 volatile unsigned int local_scratch[8];
468 volatile unsigned int use_local_bus;
469 volatile unsigned int sdio_config;
470 volatile unsigned int mbox_debug;
471 volatile unsigned int mbox_fifo_reset;
472 volatile unsigned int mbox_txfifo_pop[4];
473 volatile unsigned int mbox_rxfifo_pop[4];
474 volatile unsigned int sdio_debug;
475 unsigned char pad1[7916]; /* pad to 0x2000 */
476 volatile unsigned int host_if_window[2048];
479 #endif /* __ASSEMBLER__ */
481 #endif /* _MBOX_REG_H_ */