drivers/spi/spi_s3c64xx.c

   1 /* linux/drivers/spi/spi_s3c64xx.c
   2  *
   3  * Copyright (C) 2009 Samsung Electronics Ltd.
   4  *      Jaswinder Singh <jassi.brar@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/module.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/delay.h>
  25 #include <linux/clk.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/spi/spi.h>
  29
  30 #include <mach/dma.h>
  31 #include <plat/s3c64xx-spi.h>
  32
  33 /* Registers and bit-fields */
  34
  35 #define S3C64XX_SPI_CH_CFG              0x00
  36 #define S3C64XX_SPI_CLK_CFG             0x04
  37 #define S3C64XX_SPI_MODE_CFG    0x08
  38 #define S3C64XX_SPI_SLAVE_SEL   0x0C
  39 #define S3C64XX_SPI_INT_EN              0x10
  40 #define S3C64XX_SPI_STATUS              0x14
  41 #define S3C64XX_SPI_TX_DATA             0x18
  42 #define S3C64XX_SPI_RX_DATA             0x1C
  43 #define S3C64XX_SPI_PACKET_CNT  0x20
  44 #define S3C64XX_SPI_PENDING_CLR 0x24
  45 #define S3C64XX_SPI_SWAP_CFG    0x28
  46 #define S3C64XX_SPI_FB_CLK              0x2C
  47
  48 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  49 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
  50 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
  51 #define S3C64XX_SPI_CPOL_L              (1<<3)
  52 #define S3C64XX_SPI_CPHA_B              (1<<2)
  53 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  54 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  55
  56 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  57 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  58 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  59 #define S3C64XX_SPI_PSR_MASK            0xff
  60
  61 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  62 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  63 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  64 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  65 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  66 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  67 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  68 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  69 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  70 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  71 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  72
  73 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
  74 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
  75
  76 #define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL)
  77
  78 #define S3C64XX_SPI_DEACT(c) writel(S3C64XX_SPI_SLAVE_SIG_INACT, \
  79                                         (c)->regs + S3C64XX_SPI_SLAVE_SEL)
  80
  81 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  82 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  83 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  84 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  85 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  86 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  87 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  88
  89 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  90 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
  91 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  92 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
  93 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
  94 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
  95
  96 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
  97
  98 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
  99 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
 100 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
 101 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
 102 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
 103
 104 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
 105 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
 106 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
 107 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
 108 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
 109 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 110 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 111 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 112
 113 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
 114
 115 #define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \
 116                                         (((i)->fifo_lvl_mask + 1))) \
 117                                         ? 1 : 0)
 118
 119 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
 120 #define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
 121 #define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
 122
 123 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 124 #define S3C64XX_SPI_TRAILCNT_OFF        19
 125
 126 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 127
 128 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 129
 130 #define SUSPND    (1<<0)
 131 #define SPIBUSY   (1<<1)
 132 #define RXBUSY    (1<<2)
 133 #define TXBUSY    (1<<3)
 134
 135 /**
 136  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 137  * @clk: Pointer to the spi clock.
 138  * @src_clk: Pointer to the clock used to generate SPI signals.
 139  * @master: Pointer to the SPI Protocol master.
 140  * @workqueue: Work queue for the SPI xfer requests.
 141  * @cntrlr_info: Platform specific data for the controller this driver manages.
 142  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
 143  * @work: Work
 144  * @queue: To log SPI xfer requests.
 145  * @lock: Controller specific lock.
 146  * @state: Set of FLAGS to indicate status.
 147  * @rx_dmach: Controller's DMA channel for Rx.
 148  * @tx_dmach: Controller's DMA channel for Tx.
 149  * @sfr_start: BUS address of SPI controller regs.
 150  * @regs: Pointer to ioremap'ed controller registers.
 151  * @xfer_completion: To indicate completion of xfer task.
 152  * @cur_mode: Stores the active configuration of the controller.
 153  * @cur_bpw: Stores the active bits per word settings.
 154  * @cur_speed: Stores the active xfer clock speed.
 155  */
 156 struct s3c64xx_spi_driver_data {
 157         void __iomem                    *regs;
 158         struct clk                      *clk;
 159         struct clk                      *src_clk;
 160         struct platform_device          *pdev;
 161         struct spi_master               *master;
 162         struct workqueue_struct         *workqueue;
 163         struct s3c64xx_spi_info  *cntrlr_info;
 164         struct spi_device               *tgl_spi;
 165         struct work_struct              work;
 166         struct list_head                queue;
 167         spinlock_t                      lock;
 168         enum dma_ch                     rx_dmach;
 169         enum dma_ch                     tx_dmach;
 170         unsigned long                   sfr_start;
 171         struct completion               xfer_completion;
 172         unsigned                        state;
 173         unsigned                        cur_mode, cur_bpw;
 174         unsigned                        cur_speed;
 175 };
 176
 177 static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
 178         .name = "samsung-spi-dma",
 179 };
 180
 181 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 182 {
 183         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 184         void __iomem *regs = sdd->regs;
 185         unsigned long loops;
 186         u32 val;
 187
 188         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 189
 190         val = readl(regs + S3C64XX_SPI_CH_CFG);
 191         val |= S3C64XX_SPI_CH_SW_RST;
 192         val &= ~S3C64XX_SPI_CH_HS_EN;
 193         writel(val, regs + S3C64XX_SPI_CH_CFG);
 194
 195         /* Flush TxFIFO*/
 196         loops = msecs_to_loops(1);
 197         do {
 198                 val = readl(regs + S3C64XX_SPI_STATUS);
 199         } while (TX_FIFO_LVL(val, sci) && loops--);
 200
 201         if (loops == 0)
 202                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 203
 204         /* Flush RxFIFO*/
 205         loops = msecs_to_loops(1);
 206         do {
 207                 val = readl(regs + S3C64XX_SPI_STATUS);
 208                 if (RX_FIFO_LVL(val, sci))
 209                         readl(regs + S3C64XX_SPI_RX_DATA);
 210                 else
 211                         break;
 212         } while (loops--);
 213
 214         if (loops == 0)
 215                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 216
 217         val = readl(regs + S3C64XX_SPI_CH_CFG);
 218         val &= ~S3C64XX_SPI_CH_SW_RST;
 219         writel(val, regs + S3C64XX_SPI_CH_CFG);
 220
 221         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 222         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 223         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 224
 225         val = readl(regs + S3C64XX_SPI_CH_CFG);
 226         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 227         writel(val, regs + S3C64XX_SPI_CH_CFG);
 228 }
 229
 230 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 231                                 struct spi_device *spi,
 232                                 struct spi_transfer *xfer, int dma_mode)
 233 {
 234         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 235         void __iomem *regs = sdd->regs;
 236         u32 modecfg, chcfg;
 237
 238         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 239         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 240
 241         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 242         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 243
 244         if (dma_mode) {
 245                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 246         } else {
 247                 /* Always shift in data in FIFO, even if xfer is Tx only,
 248                  * this helps setting PCKT_CNT value for generating clocks
 249                  * as exactly needed.
 250                  */
 251                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 252                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 253                                         | S3C64XX_SPI_PACKET_CNT_EN,
 254                                         regs + S3C64XX_SPI_PACKET_CNT);
 255         }
 256
 257         if (xfer->tx_buf != NULL) {
 258                 sdd->state |= TXBUSY;
 259                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 260                 if (dma_mode) {
 261                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 262                         s3c2410_dma_config(sdd->tx_dmach, sdd->cur_bpw / 8);
 263                         s3c2410_dma_enqueue(sdd->tx_dmach, (void *)sdd,
 264                                                 xfer->tx_dma, xfer->len);
 265                         s3c2410_dma_ctrl(sdd->tx_dmach, S3C2410_DMAOP_START);
 266                 } else {
 267                         switch (sdd->cur_bpw) {
 268                         case 32:
 269                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 270                                         xfer->tx_buf, xfer->len / 4);
 271                                 break;
 272                         case 16:
 273                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 274                                         xfer->tx_buf, xfer->len / 2);
 275                                 break;
 276                         default:
 277                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 278                                         xfer->tx_buf, xfer->len);
 279                                 break;
 280                         }
 281                 }
 282         }
 283
 284         if (xfer->rx_buf != NULL) {
 285                 sdd->state |= RXBUSY;
 286
 287                 if (sci->high_speed && sdd->cur_speed >= 30000000UL
 288                                         && !(sdd->cur_mode & SPI_CPHA))
 289                         chcfg |= S3C64XX_SPI_CH_HS_EN;
 290
 291                 if (dma_mode) {
 292                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 293                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 294                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 295                                         | S3C64XX_SPI_PACKET_CNT_EN,
 296                                         regs + S3C64XX_SPI_PACKET_CNT);
 297                         s3c2410_dma_config(sdd->rx_dmach, sdd->cur_bpw / 8);
 298                         s3c2410_dma_enqueue(sdd->rx_dmach, (void *)sdd,
 299                                                 xfer->rx_dma, xfer->len);
 300                         s3c2410_dma_ctrl(sdd->rx_dmach, S3C2410_DMAOP_START);
 301                 }
 302         }
 303
 304         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 305         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 306 }
 307
 308 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
 309                                                 struct spi_device *spi)
 310 {
 311         struct s3c64xx_spi_csinfo *cs;
 312
 313         if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
 314                 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
 315                         /* Deselect the last toggled device */
 316                         cs = sdd->tgl_spi->controller_data;
 317                         cs->set_level(cs->line,
 318                                         spi->mode & SPI_CS_HIGH ? 0 : 1);
 319                 }
 320                 sdd->tgl_spi = NULL;
 321         }
 322
 323         cs = spi->controller_data;
 324         cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
 325 }
 326
 327 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
 328                                 struct spi_transfer *xfer, int dma_mode)
 329 {
 330         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 331         void __iomem *regs = sdd->regs;
 332         unsigned long val;
 333         int ms;
 334
 335         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 336         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 337         ms += 10; /* some tolerance */
 338
 339         if (dma_mode) {
 340                 val = msecs_to_jiffies(ms) + 10;
 341                 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 342         } else {
 343                 u32 status;
 344                 val = msecs_to_loops(ms);
 345                 do {
 346                         status = readl(regs + S3C64XX_SPI_STATUS);
 347                 } while (RX_FIFO_LVL(status, sci) < xfer->len && --val);
 348         }
 349
 350         if (!val)
 351                 return -EIO;
 352
 353         if (dma_mode) {
 354                 u32 status;
 355
 356                 /*
 357                  * DmaTx returns after simply writing data in the FIFO,
 358                  * w/o waiting for real transmission on the bus to finish.
 359                  * DmaRx returns only after Dma read data from FIFO which
 360                  * needs bus transmission to finish, so we don't worry if
 361                  * Xfer involved Rx(with or without Tx).
 362                  */
 363                 if (xfer->rx_buf == NULL) {
 364                         val = msecs_to_loops(10);
 365                         status = readl(regs + S3C64XX_SPI_STATUS);
 366                         while ((TX_FIFO_LVL(status, sci)
 367                                 || !S3C64XX_SPI_ST_TX_DONE(status, sci))
 368                                         && --val) {
 369                                 cpu_relax();
 370                                 status = readl(regs + S3C64XX_SPI_STATUS);
 371                         }
 372
 373                         if (!val)
 374                                 return -EIO;
 375                 }
 376         } else {
 377                 /* If it was only Tx */
 378                 if (xfer->rx_buf == NULL) {
 379                         sdd->state &= ~TXBUSY;
 380                         return 0;
 381                 }
 382
 383                 switch (sdd->cur_bpw) {
 384                 case 32:
 385                         ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 386                                 xfer->rx_buf, xfer->len / 4);
 387                         break;
 388                 case 16:
 389                         ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 390                                 xfer->rx_buf, xfer->len / 2);
 391                         break;
 392                 default:
 393                         ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 394                                 xfer->rx_buf, xfer->len);
 395                         break;
 396                 }
 397                 sdd->state &= ~RXBUSY;
 398         }
 399
 400         return 0;
 401 }
 402
 403 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
 404                                                 struct spi_device *spi)
 405 {
 406         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 407
 408         if (sdd->tgl_spi == spi)
 409                 sdd->tgl_spi = NULL;
 410
 411         cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
 412 }
 413
 414 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 415 {
 416         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 417         void __iomem *regs = sdd->regs;
 418         u32 val;
 419
 420         /* Disable Clock */
 421         if (sci->clk_from_cmu) {
 422                 clk_disable(sdd->src_clk);
 423         } else {
 424                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 425                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 426                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 427         }
 428
 429         /* Set Polarity and Phase */
 430         val = readl(regs + S3C64XX_SPI_CH_CFG);
 431         val &= ~(S3C64XX_SPI_CH_SLAVE |
 432                         S3C64XX_SPI_CPOL_L |
 433                         S3C64XX_SPI_CPHA_B);
 434
 435         if (sdd->cur_mode & SPI_CPOL)
 436                 val |= S3C64XX_SPI_CPOL_L;
 437
 438         if (sdd->cur_mode & SPI_CPHA)
 439                 val |= S3C64XX_SPI_CPHA_B;
 440
 441         writel(val, regs + S3C64XX_SPI_CH_CFG);
 442
 443         /* Set Channel & DMA Mode */
 444         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 445         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 446                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 447
 448         switch (sdd->cur_bpw) {
 449         case 32:
 450                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 451                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 452                 break;
 453         case 16:
 454                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 455                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 456                 break;
 457         default:
 458                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 459                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 460                 break;
 461         }
 462
 463         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 464
 465         if (sci->clk_from_cmu) {
 466                 /* Configure Clock */
 467                 /* There is half-multiplier before the SPI */
 468                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 469                 /* Enable Clock */
 470                 clk_enable(sdd->src_clk);
 471         } else {
 472                 /* Configure Clock */
 473                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 474                 val &= ~S3C64XX_SPI_PSR_MASK;
 475                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 476                                 & S3C64XX_SPI_PSR_MASK);
 477                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 478
 479                 /* Enable Clock */
 480                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 481                 val |= S3C64XX_SPI_ENCLK_ENABLE;
 482                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 483         }
 484 }
 485
 486 static void s3c64xx_spi_dma_rxcb(struct s3c2410_dma_chan *chan, void *buf_id,
 487                                  int size, enum s3c2410_dma_buffresult res)
 488 {
 489         struct s3c64xx_spi_driver_data *sdd = buf_id;
 490         unsigned long flags;
 491
 492         spin_lock_irqsave(&sdd->lock, flags);
 493
 494         if (res == S3C2410_RES_OK)
 495                 sdd->state &= ~RXBUSY;
 496         else
 497                 dev_err(&sdd->pdev->dev, "DmaAbrtRx-%d\n", size);
 498
 499         /* If the other done */
 500         if (!(sdd->state & TXBUSY))
 501                 complete(&sdd->xfer_completion);
 502
 503         spin_unlock_irqrestore(&sdd->lock, flags);
 504 }
 505
 506 static void s3c64xx_spi_dma_txcb(struct s3c2410_dma_chan *chan, void *buf_id,
 507                                  int size, enum s3c2410_dma_buffresult res)
 508 {
 509         struct s3c64xx_spi_driver_data *sdd = buf_id;
 510         unsigned long flags;
 511
 512         spin_lock_irqsave(&sdd->lock, flags);
 513
 514         if (res == S3C2410_RES_OK)
 515                 sdd->state &= ~TXBUSY;
 516         else
 517                 dev_err(&sdd->pdev->dev, "DmaAbrtTx-%d \n", size);
 518
 519         /* If the other done */
 520         if (!(sdd->state & RXBUSY))
 521                 complete(&sdd->xfer_completion);
 522
 523         spin_unlock_irqrestore(&sdd->lock, flags);
 524 }
 525
 526 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 527
 528 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
 529                                                 struct spi_message *msg)
 530 {
 531         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 532         struct device *dev = &sdd->pdev->dev;
 533         struct spi_transfer *xfer;
 534
 535         if (msg->is_dma_mapped)
 536                 return 0;
 537
 538         /* First mark all xfer unmapped */
 539         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 540                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 541                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 542         }
 543
 544         /* Map until end or first fail */
 545         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 546
 547                 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
 548                         continue;
 549
 550                 if (xfer->tx_buf != NULL) {
 551                         xfer->tx_dma = dma_map_single(dev,
 552                                         (void *)xfer->tx_buf, xfer->len,
 553                                         DMA_TO_DEVICE);
 554                         if (dma_mapping_error(dev, xfer->tx_dma)) {
 555                                 dev_err(dev, "dma_map_single Tx failed\n");
 556                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 557                                 return -ENOMEM;
 558                         }
 559                 }
 560
 561                 if (xfer->rx_buf != NULL) {
 562                         xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
 563                                                 xfer->len, DMA_FROM_DEVICE);
 564                         if (dma_mapping_error(dev, xfer->rx_dma)) {
 565                                 dev_err(dev, "dma_map_single Rx failed\n");
 566                                 dma_unmap_single(dev, xfer->tx_dma,
 567                                                 xfer->len, DMA_TO_DEVICE);
 568                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 569                                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 570                                 return -ENOMEM;
 571                         }
 572                 }
 573         }
 574
 575         return 0;
 576 }
 577
 578 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
 579                                                 struct spi_message *msg)
 580 {
 581         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 582         struct device *dev = &sdd->pdev->dev;
 583         struct spi_transfer *xfer;
 584
 585         if (msg->is_dma_mapped)
 586                 return;
 587
 588         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 589
 590                 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
 591                         continue;
 592
 593                 if (xfer->rx_buf != NULL
 594                                 && xfer->rx_dma != XFER_DMAADDR_INVALID)
 595                         dma_unmap_single(dev, xfer->rx_dma,
 596                                                 xfer->len, DMA_FROM_DEVICE);
 597
 598                 if (xfer->tx_buf != NULL
 599                                 && xfer->tx_dma != XFER_DMAADDR_INVALID)
 600                         dma_unmap_single(dev, xfer->tx_dma,
 601                                                 xfer->len, DMA_TO_DEVICE);
 602         }
 603 }
 604
 605 static void handle_msg(struct s3c64xx_spi_driver_data *sdd,
 606                                         struct spi_message *msg)
 607 {
 608         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 609         struct spi_device *spi = msg->spi;
 610         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 611         struct spi_transfer *xfer;
 612         int status = 0, cs_toggle = 0;
 613         u32 speed;
 614         u8 bpw;
 615
 616         /* If Master's(controller) state differs from that needed by Slave */
 617         if (sdd->cur_speed != spi->max_speed_hz
 618                         || sdd->cur_mode != spi->mode
 619                         || sdd->cur_bpw != spi->bits_per_word) {
 620                 sdd->cur_bpw = spi->bits_per_word;
 621                 sdd->cur_speed = spi->max_speed_hz;
 622                 sdd->cur_mode = spi->mode;
 623                 s3c64xx_spi_config(sdd);
 624         }
 625
 626         /* Map all the transfers if needed */
 627         if (s3c64xx_spi_map_mssg(sdd, msg)) {
 628                 dev_err(&spi->dev,
 629                         "Xfer: Unable to map message buffers!\n");
 630                 status = -ENOMEM;
 631                 goto out;
 632         }
 633
 634         /* Configure feedback delay */
 635         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 636
 637         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 638
 639                 unsigned long flags;
 640                 int use_dma;
 641
 642                 INIT_COMPLETION(sdd->xfer_completion);
 643
 644                 /* Only BPW and Speed may change across transfers */
 645                 bpw = xfer->bits_per_word ? : spi->bits_per_word;
 646                 speed = xfer->speed_hz ? : spi->max_speed_hz;
 647
 648                 if (xfer->len % (bpw / 8)) {
 649                         dev_err(&spi->dev,
 650                                 "Xfer length(%u) not a multiple of word size(%u)\n",
 651                                 xfer->len, bpw / 8);
 652                         status = -EIO;
 653                         goto out;
 654                 }
 655
 656                 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 657                         sdd->cur_bpw = bpw;
 658                         sdd->cur_speed = speed;
 659                         s3c64xx_spi_config(sdd);
 660                 }
 661
 662                 /* Polling method for xfers not bigger than FIFO capacity */
 663                 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
 664                         use_dma = 0;
 665                 else
 666                         use_dma = 1;
 667
 668                 spin_lock_irqsave(&sdd->lock, flags);
 669
 670                 /* Pending only which is to be done */
 671                 sdd->state &= ~RXBUSY;
 672                 sdd->state &= ~TXBUSY;
 673
 674                 enable_datapath(sdd, spi, xfer, use_dma);
 675
 676                 /* Slave Select */
 677                 enable_cs(sdd, spi);
 678
 679                 /* Start the signals */
 680                 S3C64XX_SPI_ACT(sdd);
 681
 682                 spin_unlock_irqrestore(&sdd->lock, flags);
 683
 684                 status = wait_for_xfer(sdd, xfer, use_dma);
 685
 686                 /* Quiese the signals */
 687                 S3C64XX_SPI_DEACT(sdd);
 688
 689                 if (status) {
 690                         dev_err(&spi->dev, "I/O Error: "
 691                                 "rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 692                                 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 693                                 (sdd->state & RXBUSY) ? 'f' : 'p',
 694                                 (sdd->state & TXBUSY) ? 'f' : 'p',
 695                                 xfer->len);
 696
 697                         if (use_dma) {
 698                                 if (xfer->tx_buf != NULL
 699                                                 && (sdd->state & TXBUSY))
 700                                         s3c2410_dma_ctrl(sdd->tx_dmach,
 701                                                         S3C2410_DMAOP_FLUSH);
 702                                 if (xfer->rx_buf != NULL
 703                                                 && (sdd->state & RXBUSY))
 704                                         s3c2410_dma_ctrl(sdd->rx_dmach,
 705                                                         S3C2410_DMAOP_FLUSH);
 706                         }
 707
 708                         goto out;
 709                 }
 710
 711                 if (xfer->delay_usecs)
 712                         udelay(xfer->delay_usecs);
 713
 714                 if (xfer->cs_change) {
 715                         /* Hint that the next mssg is gonna be
 716                            for the same device */
 717                         if (list_is_last(&xfer->transfer_list,
 718                                                 &msg->transfers))
 719                                 cs_toggle = 1;
 720                         else
 721                                 disable_cs(sdd, spi);
 722                 }
 723
 724                 msg->actual_length += xfer->len;
 725
 726                 flush_fifo(sdd);
 727         }
 728
 729 out:
 730         if (!cs_toggle || status)
 731                 disable_cs(sdd, spi);
 732         else
 733                 sdd->tgl_spi = spi;
 734
 735         s3c64xx_spi_unmap_mssg(sdd, msg);
 736
 737         msg->status = status;
 738
 739         if (msg->complete)
 740                 msg->complete(msg->context);
 741 }
 742
 743 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
 744 {
 745         if (s3c2410_dma_request(sdd->rx_dmach,
 746                                         &s3c64xx_spi_dma_client, NULL) < 0) {
 747                 dev_err(&sdd->pdev->dev, "cannot get RxDMA\n");
 748                 return 0;
 749         }
 750         s3c2410_dma_set_buffdone_fn(sdd->rx_dmach, s3c64xx_spi_dma_rxcb);
 751         s3c2410_dma_devconfig(sdd->rx_dmach, S3C2410_DMASRC_HW,
 752                                         sdd->sfr_start + S3C64XX_SPI_RX_DATA);
 753
 754         if (s3c2410_dma_request(sdd->tx_dmach,
 755                                         &s3c64xx_spi_dma_client, NULL) < 0) {
 756                 dev_err(&sdd->pdev->dev, "cannot get TxDMA\n");
 757                 s3c2410_dma_free(sdd->rx_dmach, &s3c64xx_spi_dma_client);
 758                 return 0;
 759         }
 760         s3c2410_dma_set_buffdone_fn(sdd->tx_dmach, s3c64xx_spi_dma_txcb);
 761         s3c2410_dma_devconfig(sdd->tx_dmach, S3C2410_DMASRC_MEM,
 762                                         sdd->sfr_start + S3C64XX_SPI_TX_DATA);
 763
 764         return 1;
 765 }
 766
 767 static void s3c64xx_spi_work(struct work_struct *work)
 768 {
 769         struct s3c64xx_spi_driver_data *sdd = container_of(work,
 770                                         struct s3c64xx_spi_driver_data, work);
 771         unsigned long flags;
 772
 773         /* Acquire DMA channels */
 774         while (!acquire_dma(sdd))
 775                 msleep(10);
 776
 777         spin_lock_irqsave(&sdd->lock, flags);
 778
 779         while (!list_empty(&sdd->queue)
 780                                 && !(sdd->state & SUSPND)) {
 781
 782                 struct spi_message *msg;
 783
 784                 msg = container_of(sdd->queue.next, struct spi_message, queue);
 785
 786                 list_del_init(&msg->queue);
 787
 788                 /* Set Xfer busy flag */
 789                 sdd->state |= SPIBUSY;
 790
 791                 spin_unlock_irqrestore(&sdd->lock, flags);
 792
 793                 handle_msg(sdd, msg);
 794
 795                 spin_lock_irqsave(&sdd->lock, flags);
 796
 797                 sdd->state &= ~SPIBUSY;
 798         }
 799
 800         spin_unlock_irqrestore(&sdd->lock, flags);
 801
 802         /* Free DMA channels */
 803         s3c2410_dma_free(sdd->tx_dmach, &s3c64xx_spi_dma_client);
 804         s3c2410_dma_free(sdd->rx_dmach, &s3c64xx_spi_dma_client);
 805 }
 806
 807 static int s3c64xx_spi_transfer(struct spi_device *spi,
 808                                                 struct spi_message *msg)
 809 {
 810         struct s3c64xx_spi_driver_data *sdd;
 811         unsigned long flags;
 812
 813         sdd = spi_master_get_devdata(spi->master);
 814
 815         spin_lock_irqsave(&sdd->lock, flags);
 816
 817         if (sdd->state & SUSPND) {
 818                 spin_unlock_irqrestore(&sdd->lock, flags);
 819                 return -ESHUTDOWN;
 820         }
 821
 822         msg->status = -EINPROGRESS;
 823         msg->actual_length = 0;
 824
 825         list_add_tail(&msg->queue, &sdd->queue);
 826
 827         queue_work(sdd->workqueue, &sdd->work);
 828
 829         spin_unlock_irqrestore(&sdd->lock, flags);
 830
 831         return 0;
 832 }
 833
 834 /*
 835  * Here we only check the validity of requested configuration
 836  * and save the configuration in a local data-structure.
 837  * The controller is actually configured only just before we
 838  * get a message to transfer.
 839  */
 840 static int s3c64xx_spi_setup(struct spi_device *spi)
 841 {
 842         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 843         struct s3c64xx_spi_driver_data *sdd;
 844         struct s3c64xx_spi_info *sci;
 845         struct spi_message *msg;
 846         unsigned long flags;
 847         int err = 0;
 848
 849         if (cs == NULL || cs->set_level == NULL) {
 850                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
 851                 return -ENODEV;
 852         }
 853
 854         sdd = spi_master_get_devdata(spi->master);
 855         sci = sdd->cntrlr_info;
 856
 857         spin_lock_irqsave(&sdd->lock, flags);
 858
 859         list_for_each_entry(msg, &sdd->queue, queue) {
 860                 /* Is some mssg is already queued for this device */
 861                 if (msg->spi == spi) {
 862                         dev_err(&spi->dev,
 863                                 "setup: attempt while mssg in queue!\n");
 864                         spin_unlock_irqrestore(&sdd->lock, flags);
 865                         return -EBUSY;
 866                 }
 867         }
 868
 869         if (sdd->state & SUSPND) {
 870                 spin_unlock_irqrestore(&sdd->lock, flags);
 871                 dev_err(&spi->dev,
 872                         "setup: SPI-%d not active!\n", spi->master->bus_num);
 873                 return -ESHUTDOWN;
 874         }
 875
 876         spin_unlock_irqrestore(&sdd->lock, flags);
 877
 878         if (spi->bits_per_word != 8
 879                         && spi->bits_per_word != 16
 880                         && spi->bits_per_word != 32) {
 881                 dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n",
 882                                                         spi->bits_per_word);
 883                 err = -EINVAL;
 884                 goto setup_exit;
 885         }
 886
 887         /* Check if we can provide the requested rate */
 888         if (!sci->clk_from_cmu) {
 889                 u32 psr, speed;
 890
 891                 /* Max possible */
 892                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
 893
 894                 if (spi->max_speed_hz > speed)
 895                         spi->max_speed_hz = speed;
 896
 897                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
 898                 psr &= S3C64XX_SPI_PSR_MASK;
 899                 if (psr == S3C64XX_SPI_PSR_MASK)
 900                         psr--;
 901
 902                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 903                 if (spi->max_speed_hz < speed) {
 904                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
 905                                 psr++;
 906                         } else {
 907                                 err = -EINVAL;
 908                                 goto setup_exit;
 909                         }
 910                 }
 911
 912                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 913                 if (spi->max_speed_hz >= speed)
 914                         spi->max_speed_hz = speed;
 915                 else
 916                         err = -EINVAL;
 917         }
 918
 919 setup_exit:
 920
 921         /* setup() returns with device de-selected */
 922         disable_cs(sdd, spi);
 923
 924         return err;
 925 }
 926
 927 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
 928 {
 929         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 930         void __iomem *regs = sdd->regs;
 931         unsigned int val;
 932
 933         sdd->cur_speed = 0;
 934
 935         S3C64XX_SPI_DEACT(sdd);
 936
 937         /* Disable Interrupts - we use Polling if not DMA mode */
 938         writel(0, regs + S3C64XX_SPI_INT_EN);
 939
 940         if (!sci->clk_from_cmu)
 941                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
 942                                 regs + S3C64XX_SPI_CLK_CFG);
 943         writel(0, regs + S3C64XX_SPI_MODE_CFG);
 944         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 945
 946         /* Clear any irq pending bits */
 947         writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
 948                                 regs + S3C64XX_SPI_PENDING_CLR);
 949
 950         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
 951
 952         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 953         val &= ~S3C64XX_SPI_MODE_4BURST;
 954         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
 955         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
 956         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 957
 958         flush_fifo(sdd);
 959 }
 960
 961 static int __init s3c64xx_spi_probe(struct platform_device *pdev)
 962 {
 963         struct resource *mem_res, *dmatx_res, *dmarx_res;
 964         struct s3c64xx_spi_driver_data *sdd;
 965         struct s3c64xx_spi_info *sci;
 966         struct spi_master *master;
 967         int ret;
 968
 969         if (pdev->id < 0) {
 970                 dev_err(&pdev->dev,
 971                                 "Invalid platform device id-%d\n", pdev->id);
 972                 return -ENODEV;
 973         }
 974
 975         if (pdev->dev.platform_data == NULL) {
 976                 dev_err(&pdev->dev, "platform_data missing!\n");
 977                 return -ENODEV;
 978         }
 979
 980         sci = pdev->dev.platform_data;
 981         if (!sci->src_clk_name) {
 982                 dev_err(&pdev->dev,
 983                         "Board init must call s3c64xx_spi_set_info()\n");
 984                 return -EINVAL;
 985         }
 986
 987         /* Check for availability of necessary resource */
 988
 989         dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 990         if (dmatx_res == NULL) {
 991                 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");
 992                 return -ENXIO;
 993         }
 994
 995         dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
 996         if (dmarx_res == NULL) {
 997                 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");
 998                 return -ENXIO;
 999         }
1000
1001         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1002         if (mem_res == NULL) {
1003                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1004                 return -ENXIO;
1005         }
1006
1007         master = spi_alloc_master(&pdev->dev,
1008                                 sizeof(struct s3c64xx_spi_driver_data));
1009         if (master == NULL) {
1010                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1011                 return -ENOMEM;
1012         }
1013
1014         platform_set_drvdata(pdev, master);
1015
1016         sdd = spi_master_get_devdata(master);
1017         sdd->master = master;
1018         sdd->cntrlr_info = sci;
1019         sdd->pdev = pdev;
1020         sdd->sfr_start = mem_res->start;
1021         sdd->tx_dmach = dmatx_res->start;
1022         sdd->rx_dmach = dmarx_res->start;
1023
1024         sdd->cur_bpw = 8;
1025
1026         master->bus_num = pdev->id;
1027         master->setup = s3c64xx_spi_setup;
1028         master->transfer = s3c64xx_spi_transfer;
1029         master->num_chipselect = sci->num_cs;
1030         master->dma_alignment = 8;
1031         /* the spi->mode bits understood by this driver: */
1032         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1033
1034         if (request_mem_region(mem_res->start,
1035                         resource_size(mem_res), pdev->name) == NULL) {
1036                 dev_err(&pdev->dev, "Req mem region failed\n");
1037                 ret = -ENXIO;
1038                 goto err0;
1039         }
1040
1041         sdd->regs = ioremap(mem_res->start, resource_size(mem_res));
1042         if (sdd->regs == NULL) {
1043                 dev_err(&pdev->dev, "Unable to remap IO\n");
1044                 ret = -ENXIO;
1045                 goto err1;
1046         }
1047
1048         if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) {
1049                 dev_err(&pdev->dev, "Unable to config gpio\n");
1050                 ret = -EBUSY;
1051                 goto err2;
1052         }
1053
1054         /* Setup clocks */
1055         sdd->clk = clk_get(&pdev->dev, "spi");
1056         if (IS_ERR(sdd->clk)) {
1057                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1058                 ret = PTR_ERR(sdd->clk);
1059                 goto err3;
1060         }
1061
1062         if (clk_enable(sdd->clk)) {
1063                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1064                 ret = -EBUSY;
1065                 goto err4;
1066         }
1067
1068         sdd->src_clk = clk_get(&pdev->dev, sci->src_clk_name);
1069         if (IS_ERR(sdd->src_clk)) {
1070                 dev_err(&pdev->dev,
1071                         "Unable to acquire clock '%s'\n", sci->src_clk_name);
1072                 ret = PTR_ERR(sdd->src_clk);
1073                 goto err5;
1074         }
1075
1076         if (clk_enable(sdd->src_clk)) {
1077                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n",
1078                                                         sci->src_clk_name);
1079                 ret = -EBUSY;
1080                 goto err6;
1081         }
1082
1083         sdd->workqueue = create_singlethread_workqueue(
1084                                                 dev_name(master->dev.parent));
1085         if (sdd->workqueue == NULL) {
1086                 dev_err(&pdev->dev, "Unable to create workqueue\n");
1087                 ret = -ENOMEM;
1088                 goto err7;
1089         }
1090
1091         /* Setup Deufult Mode */
1092         s3c64xx_spi_hwinit(sdd, pdev->id);
1093
1094         spin_lock_init(&sdd->lock);
1095         init_completion(&sdd->xfer_completion);
1096         INIT_WORK(&sdd->work, s3c64xx_spi_work);
1097         INIT_LIST_HEAD(&sdd->queue);
1098
1099         if (spi_register_master(master)) {
1100                 dev_err(&pdev->dev, "cannot register SPI master\n");
1101                 ret = -EBUSY;
1102                 goto err8;
1103         }
1104
1105         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
1106                                         "with %d Slaves attached\n",
1107                                         pdev->id, master->num_chipselect);
1108         dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
1109                                         mem_res->end, mem_res->start,
1110                                         sdd->rx_dmach, sdd->tx_dmach);
1111
1112         return 0;
1113
1114 err8:
1115         destroy_workqueue(sdd->workqueue);
1116 err7:
1117         clk_disable(sdd->src_clk);
1118 err6:
1119         clk_put(sdd->src_clk);
1120 err5:
1121         clk_disable(sdd->clk);
1122 err4:
1123         clk_put(sdd->clk);
1124 err3:
1125 err2:
1126         iounmap((void *) sdd->regs);
1127 err1:
1128         release_mem_region(mem_res->start, resource_size(mem_res));
1129 err0:
1130         platform_set_drvdata(pdev, NULL);
1131         spi_master_put(master);
1132
1133         return ret;
1134 }
1135
1136 static int s3c64xx_spi_remove(struct platform_device *pdev)
1137 {
1138         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1139         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1140         struct resource *mem_res;
1141         unsigned long flags;
1142
1143         spin_lock_irqsave(&sdd->lock, flags);
1144         sdd->state |= SUSPND;
1145         spin_unlock_irqrestore(&sdd->lock, flags);
1146
1147         while (sdd->state & SPIBUSY)
1148                 msleep(10);
1149
1150         spi_unregister_master(master);
1151
1152         destroy_workqueue(sdd->workqueue);
1153
1154         clk_disable(sdd->src_clk);
1155         clk_put(sdd->src_clk);
1156
1157         clk_disable(sdd->clk);
1158         clk_put(sdd->clk);
1159
1160         iounmap((void *) sdd->regs);
1161
1162         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1163         if (mem_res != NULL)
1164                 release_mem_region(mem_res->start, resource_size(mem_res));
1165
1166         platform_set_drvdata(pdev, NULL);
1167         spi_master_put(master);
1168
1169         return 0;
1170 }
1171
1172 #ifdef CONFIG_PM
1173 static int s3c64xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1174 {
1175         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1176         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1177         unsigned long flags;
1178
1179         spin_lock_irqsave(&sdd->lock, flags);
1180         sdd->state |= SUSPND;
1181         spin_unlock_irqrestore(&sdd->lock, flags);
1182
1183         while (sdd->state & SPIBUSY)
1184                 msleep(10);
1185
1186         /* Disable the clock */
1187         clk_disable(sdd->src_clk);
1188         clk_disable(sdd->clk);
1189
1190         sdd->cur_speed = 0; /* Output Clock is stopped */
1191
1192         return 0;
1193 }
1194
1195 static int s3c64xx_spi_resume(struct platform_device *pdev)
1196 {
1197         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1198         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1199         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1200         unsigned long flags;
1201
1202         sci->cfg_gpio(pdev);
1203
1204         /* Enable the clock */
1205         clk_enable(sdd->src_clk);
1206         clk_enable(sdd->clk);
1207
1208         s3c64xx_spi_hwinit(sdd, pdev->id);
1209
1210         spin_lock_irqsave(&sdd->lock, flags);
1211         sdd->state &= ~SUSPND;
1212         spin_unlock_irqrestore(&sdd->lock, flags);
1213
1214         return 0;
1215 }
1216 #else
1217 #define s3c64xx_spi_suspend     NULL
1218 #define s3c64xx_spi_resume      NULL
1219 #endif /* CONFIG_PM */
1220
1221 static struct platform_driver s3c64xx_spi_driver = {
1222         .driver = {
1223                 .name   = "s3c64xx-spi",
1224                 .owner = THIS_MODULE,
1225         },
1226         .remove = s3c64xx_spi_remove,
1227         .suspend = s3c64xx_spi_suspend,
1228         .resume = s3c64xx_spi_resume,
1229 };
1230 MODULE_ALIAS("platform:s3c64xx-spi");
1231
1232 static int __init s3c64xx_spi_init(void)
1233 {
1234         return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1235 }
1236 subsys_initcall(s3c64xx_spi_init);
1237
1238 static void __exit s3c64xx_spi_exit(void)
1239 {
1240         platform_driver_unregister(&s3c64xx_spi_driver);
1241 }
1242 module_exit(s3c64xx_spi_exit);
1243
1244 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1245 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1246 MODULE_LICENSE("GPL");